* [PATCH 1/4] ARM: sun8i: v3s: restore the usage of CCU definitions
@ 2017-05-15 8:39 ` Icenowy Zheng
0 siblings, 0 replies; 10+ messages in thread
From: Icenowy Zheng @ 2017-05-15 8:39 UTC (permalink / raw)
To: Rob Herring, Maxime Ripard, Chen-Yu Tsai
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng
All the used CCU definitions are stripped from the V3s DTSI file when
it's merged, as the DTSI file and the CCU device tree binding headers
went to different trees.
As they're all in Linus's tree now, restore the usage of the
definitions.
Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 64 +++++++++++++++++++++-------------------
1 file changed, 33 insertions(+), 31 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 71075969e5e6..3b50fa580261 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -41,6 +41,8 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/sun8i-v3s-ccu.h>
+#include <dt-bindings/reset/sun8i-v3s-ccu.h>
/ {
#address-cells = <1>;
@@ -55,7 +57,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
- clocks = <&ccu 14>;
+ clocks = <&ccu CLK_CPU>;
};
};
@@ -96,15 +98,15 @@
mmc0: mmc@01c0f000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c0f000 0x1000>;
- clocks = <&ccu 22>,
- <&ccu 45>,
- <&ccu 47>,
- <&ccu 46>;
+ clocks = <&ccu CLK_BUS_MMC0>,
+ <&ccu CLK_MMC0>,
+ <&ccu CLK_MMC0_OUTPUT>,
+ <&ccu CLK_MMC0_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
"sample";
- resets = <&ccu 7>;
+ resets = <&ccu RST_BUS_MMC0>;
reset-names = "ahb";
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -115,15 +117,15 @@
mmc1: mmc@01c10000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c10000 0x1000>;
- clocks = <&ccu 23>,
- <&ccu 48>,
- <&ccu 50>,
- <&ccu 49>;
+ clocks = <&ccu CLK_BUS_MMC1>,
+ <&ccu CLK_MMC1>,
+ <&ccu CLK_MMC1_OUTPUT>,
+ <&ccu CLK_MMC1_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
"sample";
- resets = <&ccu 8>;
+ resets = <&ccu RST_BUS_MMC1>;
reset-names = "ahb";
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -134,15 +136,15 @@
mmc2: mmc@01c11000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c11000 0x1000>;
- clocks = <&ccu 24>,
- <&ccu 51>,
- <&ccu 53>,
- <&ccu 52>;
+ clocks = <&ccu CLK_BUS_MMC2>,
+ <&ccu CLK_MMC2>,
+ <&ccu CLK_MMC2_OUTPUT>,
+ <&ccu CLK_MMC2_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
"sample";
- resets = <&ccu 9>;
+ resets = <&ccu RST_BUS_MMC2>;
reset-names = "ahb";
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -153,8 +155,8 @@
usb_otg: usb@01c19000 {
compatible = "allwinner,sun8i-h3-musb";
reg = <0x01c19000 0x0400>;
- clocks = <&ccu 29>;
- resets = <&ccu 17>;
+ clocks = <&ccu CLK_BUS_OTG>;
+ resets = <&ccu RST_BUS_OTG>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mc";
phys = <&usbphy 0>;
@@ -169,9 +171,9 @@
<0x01c1a800 0x4>;
reg-names = "phy_ctrl",
"pmu0";
- clocks = <&ccu 56>;
+ clocks = <&ccu CLK_USB_PHY0>;
clock-names = "usb0_phy";
- resets = <&ccu 0>;
+ resets = <&ccu RST_USB_PHY0>;
reset-names = "usb0_reset";
status = "disabled";
#phy-cells = <1>;
@@ -198,7 +200,7 @@
reg = <0x01c20800 0x400>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu 37>, <&osc24M>, <&osc32k>;
+ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
@@ -244,8 +246,8 @@
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&ccu 40>;
- resets = <&ccu 49>;
+ clocks = <&ccu CLK_BUS_UART0>;
+ resets = <&ccu RST_BUS_UART0>;
status = "disabled";
};
@@ -255,8 +257,8 @@
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&ccu 41>;
- resets = <&ccu 50>;
+ clocks = <&ccu CLK_BUS_UART1>;
+ resets = <&ccu RST_BUS_UART1>;
status = "disabled";
};
@@ -266,8 +268,8 @@
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&ccu 42>;
- resets = <&ccu 51>;
+ clocks = <&ccu CLK_BUS_UART2>;
+ resets = <&ccu RST_BUS_UART2>;
status = "disabled";
};
@@ -275,8 +277,8 @@
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2ac00 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu 38>;
- resets = <&ccu 46>;
+ clocks = <&ccu CLK_BUS_I2C0>;
+ resets = <&ccu RST_BUS_I2C0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "disabled";
@@ -288,8 +290,8 @@
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b000 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu 39>;
- resets = <&ccu 47>;
+ clocks = <&ccu CLK_BUS_I2C1>;
+ resets = <&ccu RST_BUS_I2C1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
--
2.12.2
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 1/4] ARM: sun8i: v3s: restore the usage of CCU definitions
@ 2017-05-15 8:39 ` Icenowy Zheng
0 siblings, 0 replies; 10+ messages in thread
From: Icenowy Zheng @ 2017-05-15 8:39 UTC (permalink / raw)
To: linux-arm-kernel
All the used CCU definitions are stripped from the V3s DTSI file when
it's merged, as the DTSI file and the CCU device tree binding headers
went to different trees.
As they're all in Linus's tree now, restore the usage of the
definitions.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 64 +++++++++++++++++++++-------------------
1 file changed, 33 insertions(+), 31 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 71075969e5e6..3b50fa580261 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -41,6 +41,8 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/sun8i-v3s-ccu.h>
+#include <dt-bindings/reset/sun8i-v3s-ccu.h>
/ {
#address-cells = <1>;
@@ -55,7 +57,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
- clocks = <&ccu 14>;
+ clocks = <&ccu CLK_CPU>;
};
};
@@ -96,15 +98,15 @@
mmc0: mmc at 01c0f000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c0f000 0x1000>;
- clocks = <&ccu 22>,
- <&ccu 45>,
- <&ccu 47>,
- <&ccu 46>;
+ clocks = <&ccu CLK_BUS_MMC0>,
+ <&ccu CLK_MMC0>,
+ <&ccu CLK_MMC0_OUTPUT>,
+ <&ccu CLK_MMC0_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
"sample";
- resets = <&ccu 7>;
+ resets = <&ccu RST_BUS_MMC0>;
reset-names = "ahb";
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -115,15 +117,15 @@
mmc1: mmc at 01c10000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c10000 0x1000>;
- clocks = <&ccu 23>,
- <&ccu 48>,
- <&ccu 50>,
- <&ccu 49>;
+ clocks = <&ccu CLK_BUS_MMC1>,
+ <&ccu CLK_MMC1>,
+ <&ccu CLK_MMC1_OUTPUT>,
+ <&ccu CLK_MMC1_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
"sample";
- resets = <&ccu 8>;
+ resets = <&ccu RST_BUS_MMC1>;
reset-names = "ahb";
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -134,15 +136,15 @@
mmc2: mmc at 01c11000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c11000 0x1000>;
- clocks = <&ccu 24>,
- <&ccu 51>,
- <&ccu 53>,
- <&ccu 52>;
+ clocks = <&ccu CLK_BUS_MMC2>,
+ <&ccu CLK_MMC2>,
+ <&ccu CLK_MMC2_OUTPUT>,
+ <&ccu CLK_MMC2_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
"sample";
- resets = <&ccu 9>;
+ resets = <&ccu RST_BUS_MMC2>;
reset-names = "ahb";
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -153,8 +155,8 @@
usb_otg: usb at 01c19000 {
compatible = "allwinner,sun8i-h3-musb";
reg = <0x01c19000 0x0400>;
- clocks = <&ccu 29>;
- resets = <&ccu 17>;
+ clocks = <&ccu CLK_BUS_OTG>;
+ resets = <&ccu RST_BUS_OTG>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mc";
phys = <&usbphy 0>;
@@ -169,9 +171,9 @@
<0x01c1a800 0x4>;
reg-names = "phy_ctrl",
"pmu0";
- clocks = <&ccu 56>;
+ clocks = <&ccu CLK_USB_PHY0>;
clock-names = "usb0_phy";
- resets = <&ccu 0>;
+ resets = <&ccu RST_USB_PHY0>;
reset-names = "usb0_reset";
status = "disabled";
#phy-cells = <1>;
@@ -198,7 +200,7 @@
reg = <0x01c20800 0x400>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu 37>, <&osc24M>, <&osc32k>;
+ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
@@ -244,8 +246,8 @@
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&ccu 40>;
- resets = <&ccu 49>;
+ clocks = <&ccu CLK_BUS_UART0>;
+ resets = <&ccu RST_BUS_UART0>;
status = "disabled";
};
@@ -255,8 +257,8 @@
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&ccu 41>;
- resets = <&ccu 50>;
+ clocks = <&ccu CLK_BUS_UART1>;
+ resets = <&ccu RST_BUS_UART1>;
status = "disabled";
};
@@ -266,8 +268,8 @@
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&ccu 42>;
- resets = <&ccu 51>;
+ clocks = <&ccu CLK_BUS_UART2>;
+ resets = <&ccu RST_BUS_UART2>;
status = "disabled";
};
@@ -275,8 +277,8 @@
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2ac00 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu 38>;
- resets = <&ccu 46>;
+ clocks = <&ccu CLK_BUS_I2C0>;
+ resets = <&ccu RST_BUS_I2C0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "disabled";
@@ -288,8 +290,8 @@
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b000 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu 39>;
- resets = <&ccu 47>;
+ clocks = <&ccu CLK_BUS_I2C1>;
+ resets = <&ccu RST_BUS_I2C1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
--
2.12.2
^ permalink raw reply related [flat|nested] 10+ messages in thread[parent not found: <20170515084001.63123-1-icenowy-h8G6r0blFSE@public.gmane.org>]
* [PATCH 2/4] ARM: sun8i: v3s: add LRADC device node
2017-05-15 8:39 ` Icenowy Zheng
@ 2017-05-15 8:39 ` Icenowy Zheng
-1 siblings, 0 replies; 10+ messages in thread
From: Icenowy Zheng @ 2017-05-15 8:39 UTC (permalink / raw)
To: Rob Herring, Maxime Ripard, Chen-Yu Tsai
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng
Allwinner V3s features a LRADC like the ones in older SoCs.
Add a device tree node for it.
Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 3b50fa580261..b9a3df941fb4 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -240,6 +240,13 @@
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
};
+ lradc: lradc@1c22800 {
+ compatible = "allwinner,sun4i-a10-lradc-keys";
+ reg = <0x01c22800 0x400>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
uart0: serial@01c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
--
2.12.2
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 2/4] ARM: sun8i: v3s: add LRADC device node
@ 2017-05-15 8:39 ` Icenowy Zheng
0 siblings, 0 replies; 10+ messages in thread
From: Icenowy Zheng @ 2017-05-15 8:39 UTC (permalink / raw)
To: linux-arm-kernel
Allwinner V3s features a LRADC like the ones in older SoCs.
Add a device tree node for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 3b50fa580261..b9a3df941fb4 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -240,6 +240,13 @@
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
};
+ lradc: lradc at 1c22800 {
+ compatible = "allwinner,sun4i-a10-lradc-keys";
+ reg = <0x01c22800 0x400>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
uart0: serial at 01c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
--
2.12.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 3/4] ARM: sun8i: v3s: add pinmux for mmc1
2017-05-15 8:39 ` Icenowy Zheng
@ 2017-05-15 8:40 ` Icenowy Zheng
-1 siblings, 0 replies; 10+ messages in thread
From: Icenowy Zheng @ 2017-05-15 8:40 UTC (permalink / raw)
To: Rob Herring, Maxime Ripard, Chen-Yu Tsai
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng
The dock board of Lichee Pi Zero features a MicroSD slot on MMC1, which
can be used with a MicroSD card or the MicroSD-slot Wi-Fi card provided
by Lichee Pi Zero.
Add pinmux for the mmc1 controller, and specify it in the mmc1 device
node as it's the only pinmux for mmc1.
Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index b9a3df941fb4..6ff50665e5e6 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -128,6 +128,8 @@
resets = <&ccu RST_BUS_MMC1>;
reset-names = "ahb";
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -224,6 +226,14 @@
drive-strength = <30>;
bias-pull-up;
};
+
+ mmc1_pins: mmc1 {
+ pins = "PG0", "PG1", "PG2", "PG3",
+ "PG4", "PG5";
+ function = "mmc1";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
};
timer@01c20c00 {
--
2.12.2
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 3/4] ARM: sun8i: v3s: add pinmux for mmc1
@ 2017-05-15 8:40 ` Icenowy Zheng
0 siblings, 0 replies; 10+ messages in thread
From: Icenowy Zheng @ 2017-05-15 8:40 UTC (permalink / raw)
To: linux-arm-kernel
The dock board of Lichee Pi Zero features a MicroSD slot on MMC1, which
can be used with a MicroSD card or the MicroSD-slot Wi-Fi card provided
by Lichee Pi Zero.
Add pinmux for the mmc1 controller, and specify it in the mmc1 device
node as it's the only pinmux for mmc1.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index b9a3df941fb4..6ff50665e5e6 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -128,6 +128,8 @@
resets = <&ccu RST_BUS_MMC1>;
reset-names = "ahb";
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -224,6 +226,14 @@
drive-strength = <30>;
bias-pull-up;
};
+
+ mmc1_pins: mmc1 {
+ pins = "PG0", "PG1", "PG2", "PG3",
+ "PG4", "PG5";
+ function = "mmc1";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
};
timer at 01c20c00 {
--
2.12.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 4/4] ARM: sun8i: v3s: add support for Lichee Pi Zero w/ dock board
2017-05-15 8:39 ` Icenowy Zheng
@ 2017-05-15 8:40 ` Icenowy Zheng
-1 siblings, 0 replies; 10+ messages in thread
From: Icenowy Zheng @ 2017-05-15 8:40 UTC (permalink / raw)
To: Rob Herring, Maxime Ripard, Chen-Yu Tsai
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng
The Lichee Pi Zero board has a "dock board" which needs to be soldered
with the 1.27mm stamp holes on a Lichee Pi Zero board.
It features:
- Onboard MIC and headphone jack (not supported yet)
- Ethernet port (not supported yet)
- An extra MicroSD slot connected to MMC1 controller
- four keys connected to the LRADC.
As it needs to be soldered with the main board to use, add a stand-alone
device tree for it.
Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
---
arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts | 94 ++++++++++++++++++++++
1 file changed, 94 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts
diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts
new file mode 100644
index 000000000000..d2bfccf47149
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sun8i-v3s-licheepi-zero.dts"
+
+/ {
+ model = "Lichee Pi Zero with Dock";
+ compatible = "licheepi,licheepi-zero-dock", "licheepi,licheepi-zero",
+ "allwinner,sun8i-v3s";
+
+ leds {
+ /* The LEDs use PG0~2 pins, which conflict with MMC1 */
+ status = "disbaled";
+ };
+};
+
+&mmc1 {
+ broken-cd;
+ bus-width = <4>;
+ vmmc-supply = <®_vcc3v3>;
+ status = "okay";
+};
+
+&lradc {
+ vref-supply = <®_vcc3v0>;
+ status = "okay";
+
+ button@200 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <200000>;
+ };
+
+ button@400 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <400000>;
+ };
+
+ button@600 {
+ label = "Select";
+ linux,code = <KEY_SELECT>;
+ channel = <0>;
+ voltage = <600000>;
+ };
+
+ button@800 {
+ label = "Start";
+ linux,code = <KEY_OK>;
+ channel = <0>;
+ voltage = <800000>;
+ };
+};
--
2.12.2
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 4/4] ARM: sun8i: v3s: add support for Lichee Pi Zero w/ dock board
@ 2017-05-15 8:40 ` Icenowy Zheng
0 siblings, 0 replies; 10+ messages in thread
From: Icenowy Zheng @ 2017-05-15 8:40 UTC (permalink / raw)
To: linux-arm-kernel
The Lichee Pi Zero board has a "dock board" which needs to be soldered
with the 1.27mm stamp holes on a Lichee Pi Zero board.
It features:
- Onboard MIC and headphone jack (not supported yet)
- Ethernet port (not supported yet)
- An extra MicroSD slot connected to MMC1 controller
- four keys connected to the LRADC.
As it needs to be soldered with the main board to use, add a stand-alone
device tree for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts | 94 ++++++++++++++++++++++
1 file changed, 94 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts
diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts
new file mode 100644
index 000000000000..d2bfccf47149
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sun8i-v3s-licheepi-zero.dts"
+
+/ {
+ model = "Lichee Pi Zero with Dock";
+ compatible = "licheepi,licheepi-zero-dock", "licheepi,licheepi-zero",
+ "allwinner,sun8i-v3s";
+
+ leds {
+ /* The LEDs use PG0~2 pins, which conflict with MMC1 */
+ status = "disbaled";
+ };
+};
+
+&mmc1 {
+ broken-cd;
+ bus-width = <4>;
+ vmmc-supply = <®_vcc3v3>;
+ status = "okay";
+};
+
+&lradc {
+ vref-supply = <®_vcc3v0>;
+ status = "okay";
+
+ button at 200 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <200000>;
+ };
+
+ button at 400 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <400000>;
+ };
+
+ button at 600 {
+ label = "Select";
+ linux,code = <KEY_SELECT>;
+ channel = <0>;
+ voltage = <600000>;
+ };
+
+ button at 800 {
+ label = "Start";
+ linux,code = <KEY_OK>;
+ channel = <0>;
+ voltage = <800000>;
+ };
+};
--
2.12.2
^ permalink raw reply related [flat|nested] 10+ messages in thread[parent not found: <20170515084001.63123-4-icenowy-h8G6r0blFSE@public.gmane.org>]
* Re: [PATCH 4/4] ARM: sun8i: v3s: add support for Lichee Pi Zero w/ dock board
2017-05-15 8:40 ` Icenowy Zheng
@ 2017-05-15 8:59 ` Maxime Ripard
-1 siblings, 0 replies; 10+ messages in thread
From: Maxime Ripard @ 2017-05-15 8:59 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Rob Herring, Chen-Yu Tsai, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
[-- Attachment #1: Type: text/plain, Size: 699 bytes --]
On Mon, May 15, 2017 at 04:40:01PM +0800, Icenowy Zheng wrote:
> The Lichee Pi Zero board has a "dock board" which needs to be soldered
> with the 1.27mm stamp holes on a Lichee Pi Zero board.
>
> It features:
> - Onboard MIC and headphone jack (not supported yet)
> - Ethernet port (not supported yet)
> - An extra MicroSD slot connected to MMC1 controller
> - four keys connected to the LRADC.
>
> As it needs to be soldered with the main board to use, add a stand-alone
> device tree for it.
>
> Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
Applied all 4, thanks
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 4/4] ARM: sun8i: v3s: add support for Lichee Pi Zero w/ dock board
@ 2017-05-15 8:59 ` Maxime Ripard
0 siblings, 0 replies; 10+ messages in thread
From: Maxime Ripard @ 2017-05-15 8:59 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, May 15, 2017 at 04:40:01PM +0800, Icenowy Zheng wrote:
> The Lichee Pi Zero board has a "dock board" which needs to be soldered
> with the 1.27mm stamp holes on a Lichee Pi Zero board.
>
> It features:
> - Onboard MIC and headphone jack (not supported yet)
> - Ethernet port (not supported yet)
> - An extra MicroSD slot connected to MMC1 controller
> - four keys connected to the LRADC.
>
> As it needs to be soldered with the main board to use, add a stand-alone
> device tree for it.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Applied all 4, thanks
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2017-05-15 8:59 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-05-15 8:39 [PATCH 1/4] ARM: sun8i: v3s: restore the usage of CCU definitions Icenowy Zheng
2017-05-15 8:39 ` Icenowy Zheng
[not found] ` <20170515084001.63123-1-icenowy-h8G6r0blFSE@public.gmane.org>
2017-05-15 8:39 ` [PATCH 2/4] ARM: sun8i: v3s: add LRADC device node Icenowy Zheng
2017-05-15 8:39 ` Icenowy Zheng
2017-05-15 8:40 ` [PATCH 3/4] ARM: sun8i: v3s: add pinmux for mmc1 Icenowy Zheng
2017-05-15 8:40 ` Icenowy Zheng
2017-05-15 8:40 ` [PATCH 4/4] ARM: sun8i: v3s: add support for Lichee Pi Zero w/ dock board Icenowy Zheng
2017-05-15 8:40 ` Icenowy Zheng
[not found] ` <20170515084001.63123-4-icenowy-h8G6r0blFSE@public.gmane.org>
2017-05-15 8:59 ` Maxime Ripard
2017-05-15 8:59 ` Maxime Ripard
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