* [v5,4/5] EDAC, sb_edac: Place the ECC enabled check where at least one DIMM present
@ 2017-05-17 13:05 Borislav Petkov
0 siblings, 0 replies; 3+ messages in thread
From: Borislav Petkov @ 2017-05-17 13:05 UTC (permalink / raw)
To: Qiuxu Zhuo; +Cc: mchehab, arozansk, patrickg, tony.luck, linux-edac
On Wed, Apr 26, 2017 at 09:35:21AM +0800, Qiuxu Zhuo wrote:
> This code is based on Patrick previous work from https://lkml.kernel.org/r/57884350.1030401@supermicro.com
> with some code clean:
> - Remove the code to read MCMTR from pci_ha1_ta and CHN_TO_HA macro,
> since the patch "Assign EDAC memory controller per h/w controller"
> unifies TA0 and TA1.
> - Remove the function get_pdev_same_bus(), since in get_dimm_config()
> the variable "pvt->pci_ta" for KNL is also ready, we can simply use
> pci_read_config_dword(pvt->pci_ta, KNL_MCMTR, &pvt->info.mcmtr) to
> read MCMTR.
>
> Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
> ---
> drivers/edac/sb_edac.c | 92 +++++++-------------------------------------------
> 1 file changed, 13 insertions(+), 79 deletions(-)
...
> @@ -1658,6 +1585,7 @@ static int get_dimm_config(struct mem_ctl_info *mci)
>
> if (knl_get_dimm_capacity(pvt, knl_mc_sizes) != 0)
> return -1;
> + pci_read_config_dword(pvt->pci_ta, KNL_MCMTR, &pvt->info.mcmtr);
> } else {
> pci_read_config_dword(pvt->pci_ras, RASENABLES, ®);
> if (IS_MIRROR_ENABLED(reg)) {
> @@ -1727,6 +1655,13 @@ static int get_dimm_config(struct mem_ctl_info *mci)
> }
> edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr);
> if (IS_DIMM_PRESENT(mtr)) {
> + if (!IS_ECC_ENABLED(pvt->info.mcmtr)) {
> + sbridge_printk(KERN_ERR,
> + "CPU SrcID #%d, Ha #%d, Channel #%d has dimms, but ecc is disabled\n",
s/ecc/ECC/g
> + pvt->sbridge_dev->source_id,
> + pvt->sbridge_dev->dom, i);
> + return -ENODEV;
> + }
> pvt->channel[i].dimms++;
>
> ranks = numrank(pvt->info.type, mtr);
^ permalink raw reply [flat|nested] 3+ messages in thread
* [v5,4/5] EDAC, sb_edac: Place the ECC enabled check where at least one DIMM present
@ 2017-05-18 15:26 Qiuxu Zhuo
0 siblings, 0 replies; 3+ messages in thread
From: Qiuxu Zhuo @ 2017-05-18 15:26 UTC (permalink / raw)
To: Borislav Petkov; +Cc: mchehab, arozansk, patrickg, Luck, Tony, linux-edac
> From: Borislav Petkov [mailto:bp@alien8.de]
>
>> + "CPU SrcID #%d, Ha #%d, Channel #%d has dimms, but ecc is disabled\n",
> s/ecc/ECC/g
OK, will correct them (DIMMs, ECC) in next version.
^ permalink raw reply [flat|nested] 3+ messages in thread
* [v5,4/5] EDAC, sb_edac: Place the ECC enabled check where at least one DIMM present
@ 2017-04-26 1:35 Qiuxu Zhuo
0 siblings, 0 replies; 3+ messages in thread
From: Qiuxu Zhuo @ 2017-04-26 1:35 UTC (permalink / raw)
To: bp, mchehab; +Cc: arozansk, patrickg, tony.luck, linux-edac, Qiuxu Zhuo
This code is based on Patrick previous work from https://lkml.kernel.org/r/57884350.1030401@supermicro.com
with some code clean:
- Remove the code to read MCMTR from pci_ha1_ta and CHN_TO_HA macro,
since the patch "Assign EDAC memory controller per h/w controller"
unifies TA0 and TA1.
- Remove the function get_pdev_same_bus(), since in get_dimm_config()
the variable "pvt->pci_ta" for KNL is also ready, we can simply use
pci_read_config_dword(pvt->pci_ta, KNL_MCMTR, &pvt->info.mcmtr) to
read MCMTR.
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
---
drivers/edac/sb_edac.c | 92 +++++++-------------------------------------------
1 file changed, 13 insertions(+), 79 deletions(-)
diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c
index 209491c..c253c41 100644
--- a/drivers/edac/sb_edac.c
+++ b/drivers/edac/sb_edac.c
@@ -1066,79 +1066,6 @@ static int haswell_chan_hash(int idx, u64 addr)
return idx;
}
-/****************************************************************************
- Memory check routines
- ****************************************************************************/
-static struct pci_dev *get_pdev_same_bus(u8 bus, u32 id)
-{
- struct pci_dev *pdev = NULL;
-
- do {
- pdev = pci_get_device(PCI_VENDOR_ID_INTEL, id, pdev);
- if (pdev && pdev->bus->number == bus)
- break;
- } while (pdev);
-
- return pdev;
-}
-
-/**
- * check_if_ecc_is_active() - Checks if ECC is active
- * @bus: Device bus
- * @type: Memory controller type
- * returns: 0 in case ECC is active, -ENODEV if it can't be determined or
- * disabled
- */
-static int check_if_ecc_is_active(const u8 bus, enum type type)
-{
- struct pci_dev *pdev = NULL;
- u32 mcmtr, id;
-
- switch (type) {
- case IVY_BRIDGE:
- id = PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA;
- break;
- case HASWELL:
- id = PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA;
- break;
- case SANDY_BRIDGE:
- id = PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA;
- break;
- case BROADWELL:
- id = PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA;
- break;
- case KNIGHTS_LANDING:
- /*
- * KNL doesn't group things by bus the same way
- * SB/IB/Haswell does.
- */
- id = PCI_DEVICE_ID_INTEL_KNL_IMC_TA;
- break;
- default:
- return -ENODEV;
- }
-
- if (type != KNIGHTS_LANDING)
- pdev = get_pdev_same_bus(bus, id);
- else
- pdev = pci_get_device(PCI_VENDOR_ID_INTEL, id, 0);
-
- if (!pdev) {
- sbridge_printk(KERN_ERR, "Couldn't find PCI device "
- "%04x:%04x! on bus %02d\n",
- PCI_VENDOR_ID_INTEL, id, bus);
- return -ENODEV;
- }
-
- pci_read_config_dword(pdev,
- type == KNIGHTS_LANDING ? KNL_MCMTR : MCMTR, &mcmtr);
- if (!IS_ECC_ENABLED(mcmtr)) {
- sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n");
- return -ENODEV;
- }
- return 0;
-}
-
/* Low bits of TAD limit, and some metadata. */
static const u32 knl_tad_dram_limit_lo[] = {
0x400, 0x500, 0x600, 0x700,
@@ -1658,6 +1585,7 @@ static int get_dimm_config(struct mem_ctl_info *mci)
if (knl_get_dimm_capacity(pvt, knl_mc_sizes) != 0)
return -1;
+ pci_read_config_dword(pvt->pci_ta, KNL_MCMTR, &pvt->info.mcmtr);
} else {
pci_read_config_dword(pvt->pci_ras, RASENABLES, ®);
if (IS_MIRROR_ENABLED(reg)) {
@@ -1727,6 +1655,13 @@ static int get_dimm_config(struct mem_ctl_info *mci)
}
edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr);
if (IS_DIMM_PRESENT(mtr)) {
+ if (!IS_ECC_ENABLED(pvt->info.mcmtr)) {
+ sbridge_printk(KERN_ERR,
+ "CPU SrcID #%d, Ha #%d, Channel #%d has dimms, but ecc is disabled\n",
+ pvt->sbridge_dev->source_id,
+ pvt->sbridge_dev->dom, i);
+ return -ENODEV;
+ }
pvt->channel[i].dimms++;
ranks = numrank(pvt->info.type, mtr);
@@ -3174,11 +3109,6 @@ static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
struct pci_dev *pdev = sbridge_dev->pdev[0];
int rc;
- /* Check the number of active and not disabled channels */
- rc = check_if_ecc_is_active(sbridge_dev->bus, type);
- if (unlikely(rc < 0))
- return rc;
-
/* allocate a new MC control structure */
layers[0].type = EDAC_MC_LAYER_CHANNEL;
layers[0].size = type == KNIGHTS_LANDING ?
@@ -3341,7 +3271,11 @@ static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
}
/* Get dimm basic config and the memory layout */
- get_dimm_config(mci);
+ rc = get_dimm_config(mci);
+ if (rc < 0) {
+ edac_dbg(0, "MC: failed to get_dimm_config()\n");
+ goto fail;
+ }
get_memory_layout(mci);
/* record ptr to the generic device */
^ permalink raw reply related [flat|nested] 3+ messages in thread
end of thread, other threads:[~2017-05-18 15:26 UTC | newest]
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2017-05-17 13:05 [v5,4/5] EDAC, sb_edac: Place the ECC enabled check where at least one DIMM present Borislav Petkov
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2017-05-18 15:26 Qiuxu Zhuo
2017-04-26 1:35 Qiuxu Zhuo
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