* [PATCH v2 0/5] Add minimal boot support for IPQ8074
@ 2017-05-04 11:53 ` Varadarajan Narayanan
0 siblings, 0 replies; 49+ messages in thread
From: Varadarajan Narayanan @ 2017-05-04 11:53 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
mturquette-rdvid1DuHRBWk0Htik3J/w, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
andy.gross-QSEj5FYQhm4dnm+yROfE0A,
david.brown-QSEj5FYQhm4dnm+yROfE0A, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-soc-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: absahu-sgV2jX0FEOL9JmXXK+q4OQ, sjaganat-sgV2jX0FEOL9JmXXK+q4OQ,
sricharan-sgV2jX0FEOL9JmXXK+q4OQ, Varadarajan Narayanan
v2:
* Addressed review feedback from Stephen
- Removed cpu-map entries
- Added mmio-timer nodes
* Fix sparse warnings in the gcc-ipq8074.c
* Updated pinctrl documentation
v1:
https://www.spinics.net/lists/kernel/msg2498734.html
This series adds minimal board boot support for ipq8074-hk01
board.
Abhishek Sahu (2):
clk: qcom: ipq8074: Add Global Clock Controller support
arm64: defconfig: Enable QCOM IPQ8074 clock and pinctrl
Varadarajan Narayanan (3):
pinctrl: qcom: Add ipq8074 pinctrl driver
dt-bindings: qcom: Add IPQ8074 bindings
arm64: dts: Add ipq8074 SoC and HK01 board support
Documentation/devicetree/bindings/arm/qcom.txt | 2 +
.../devicetree/bindings/clock/qcom,gcc.txt | 1 +
.../bindings/pinctrl/qcom,ipq8074-pinctrl.txt | 187 +++
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 53 +
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 194 ++++
arch/arm64/configs/defconfig | 2 +
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-ipq8074.c | 1032 +++++++++++++++++
drivers/pinctrl/qcom/Kconfig | 10 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-ipq8074.c | 1217 ++++++++++++++++++++
include/dt-bindings/clock/qcom,gcc-ipq8074.h | 152 +++
14 files changed, 2862 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
create mode 100644 arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
create mode 100644 arch/arm64/boot/dts/qcom/ipq8074.dtsi
create mode 100644 drivers/clk/qcom/gcc-ipq8074.c
create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq8074.c
create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq8074.h
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
--
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^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 0/5] Add minimal boot support for IPQ8074
@ 2017-05-04 11:53 ` Varadarajan Narayanan
0 siblings, 0 replies; 49+ messages in thread
From: Varadarajan Narayanan @ 2017-05-04 11:53 UTC (permalink / raw)
To: robh+dt, mark.rutland, mturquette, sboyd, linus.walleij,
andy.gross, david.brown, catalin.marinas, will.deacon,
devicetree, linux-kernel, linux-clk, linux-gpio, linux-arm-msm,
linux-soc, linux-arm-kernel
Cc: absahu, sjaganat, sricharan, Varadarajan Narayanan
v2:
* Addressed review feedback from Stephen
- Removed cpu-map entries
- Added mmio-timer nodes
* Fix sparse warnings in the gcc-ipq8074.c
* Updated pinctrl documentation
v1:
https://www.spinics.net/lists/kernel/msg2498734.html
This series adds minimal board boot support for ipq8074-hk01
board.
Abhishek Sahu (2):
clk: qcom: ipq8074: Add Global Clock Controller support
arm64: defconfig: Enable QCOM IPQ8074 clock and pinctrl
Varadarajan Narayanan (3):
pinctrl: qcom: Add ipq8074 pinctrl driver
dt-bindings: qcom: Add IPQ8074 bindings
arm64: dts: Add ipq8074 SoC and HK01 board support
Documentation/devicetree/bindings/arm/qcom.txt | 2 +
.../devicetree/bindings/clock/qcom,gcc.txt | 1 +
.../bindings/pinctrl/qcom,ipq8074-pinctrl.txt | 187 +++
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 53 +
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 194 ++++
arch/arm64/configs/defconfig | 2 +
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-ipq8074.c | 1032 +++++++++++++++++
drivers/pinctrl/qcom/Kconfig | 10 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-ipq8074.c | 1217 ++++++++++++++++++++
include/dt-bindings/clock/qcom,gcc-ipq8074.h | 152 +++
14 files changed, 2862 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
create mode 100644 arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
create mode 100644 arch/arm64/boot/dts/qcom/ipq8074.dtsi
create mode 100644 drivers/clk/qcom/gcc-ipq8074.c
create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq8074.c
create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq8074.h
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 0/5] Add minimal boot support for IPQ8074
@ 2017-05-04 11:53 ` Varadarajan Narayanan
0 siblings, 0 replies; 49+ messages in thread
From: Varadarajan Narayanan @ 2017-05-04 11:53 UTC (permalink / raw)
To: linux-arm-kernel
v2:
* Addressed review feedback from Stephen
- Removed cpu-map entries
- Added mmio-timer nodes
* Fix sparse warnings in the gcc-ipq8074.c
* Updated pinctrl documentation
v1:
https://www.spinics.net/lists/kernel/msg2498734.html
This series adds minimal board boot support for ipq8074-hk01
board.
Abhishek Sahu (2):
clk: qcom: ipq8074: Add Global Clock Controller support
arm64: defconfig: Enable QCOM IPQ8074 clock and pinctrl
Varadarajan Narayanan (3):
pinctrl: qcom: Add ipq8074 pinctrl driver
dt-bindings: qcom: Add IPQ8074 bindings
arm64: dts: Add ipq8074 SoC and HK01 board support
Documentation/devicetree/bindings/arm/qcom.txt | 2 +
.../devicetree/bindings/clock/qcom,gcc.txt | 1 +
.../bindings/pinctrl/qcom,ipq8074-pinctrl.txt | 187 +++
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 53 +
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 194 ++++
arch/arm64/configs/defconfig | 2 +
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-ipq8074.c | 1032 +++++++++++++++++
drivers/pinctrl/qcom/Kconfig | 10 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-ipq8074.c | 1217 ++++++++++++++++++++
include/dt-bindings/clock/qcom,gcc-ipq8074.h | 152 +++
14 files changed, 2862 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
create mode 100644 arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
create mode 100644 arch/arm64/boot/dts/qcom/ipq8074.dtsi
create mode 100644 drivers/clk/qcom/gcc-ipq8074.c
create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq8074.c
create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq8074.h
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
2017-05-04 11:53 ` Varadarajan Narayanan
@ 2017-05-04 11:53 ` Varadarajan Narayanan
-1 siblings, 0 replies; 49+ messages in thread
From: Varadarajan Narayanan @ 2017-05-04 11:53 UTC (permalink / raw)
To: robh+dt, mark.rutland, mturquette, sboyd, linus.walleij,
andy.gross, david.brown, catalin.marinas, will.deacon,
devicetree, linux-kernel, linux-clk, linux-gpio, linux-arm-msm,
linux-soc, linux-arm-kernel
Cc: absahu, sjaganat, sricharan, Varadarajan Narayanan,
Manoharan Vijaya Raghavan
Add initial pinctrl driver to support pin configuration with
pinctrl framework for ipq8074.
Signed-off-by: Manoharan Vijaya Raghavan <mraghava@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
---
.../bindings/pinctrl/qcom,ipq8074-pinctrl.txt | 187 +++
drivers/pinctrl/qcom/Kconfig | 10 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-ipq8074.c | 1217 ++++++++++++++++++++
4 files changed, 1415 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq8074.c
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
new file mode 100644
index 0000000..7765bca
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
@@ -0,0 +1,187 @@
+Qualcomm Technologies, Inc. IPQ8074 TLMM block
+
+This binding describes the Top Level Mode Multiplexer block found in the
+IPQ8074 platform.
+
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be "qcom,ipq8074-pinctrl"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: the base address and size of the TLMM register space.
+
+- interrupts:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: should specify the TLMM summary IRQ.
+
+- interrupt-controller:
+ Usage: required
+ Value type: <none>
+ Definition: identifies this node as an interrupt controller
+
+- #interrupt-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: must be 2. Specifying the pin number and flags, as defined
+ in <dt-bindings/interrupt-controller/irq.h>
+
+- gpio-controller:
+ Usage: required
+ Value type: <none>
+ Definition: identifies this node as a gpio controller
+
+- #gpio-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: must be 2. Specifying the pin number and flags, as defined
+ in <dt-bindings/gpio/gpio.h>
+
+Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
+a general description of GPIO and interrupt bindings.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+The pin configuration nodes act as a container for an arbitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, drive strength, etc.
+
+
+PIN CONFIGURATION NODES:
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pin configuration subnode:
+
+- pins:
+ Usage: required
+ Value type: <string-array>
+ Definition: List of gpio pins affected by the properties specified in
+ this subnode. Valid pins are:
+ gpio0-gpio121,
+ sdc1_clk,
+ sdc1_cmd,
+ sdc1_data
+ sdc2_clk,
+ sdc2_cmd,
+ sdc2_data,
+ qdsd_cmd,
+ qdsd_data0,
+ qdsd_data1,
+ qdsd_data2,
+ qdsd_data3
+
+- function:
+ Usage: required
+ Value type: <string>
+ Definition: Specify the alternative function to be configured for the
+ specified pins. Functions are only valid for gpio pins.
+ Valid values are:
+ gpio, qpic_pad, blsp5_i2c, blsp5_spi, wci20, blsp3_spi3,
+ burn0, pcm_zsi0, blsp5_uart, mac12, blsp3_spi0, burn1, mac01,
+ qdss_cti_trig_out_b0, qdss_cti_trig_in_b0, qpic_pad4,
+ blsp4_uart0, blsp4_i2c0, blsp4_spi0, mac21,
+ qdss_cti_trig_out_b1, qpic_pad5, qdss_cti_trig_in_b1,
+ qpic_pad6, qpic_pad7, cxc0, mac13, qdss_cti_trig_in_a1,
+ qdss_cti_trig_out_a1, wci22, qdss_cti_trig_in_a0, qpic_pad1,
+ qdss_cti_trig_out_a0, qpic_pad2, qpic_pad3, qdss_traceclk_b,
+ qpic_pad0, qdss_tracectl_b, qpic_pad8, pcm_zsi1,
+ qdss_tracedata_b, led0, pwm04, led1, pwm14, led2, pwm24,
+ pwm00, blsp4_uart1, blsp4_i2c1, blsp4_spi1, wci23, mac11,
+ blsp3_spi2, pwm10, pwm20, pwm30, audio_txmclk, pwm02,
+ audio_txbclk, pwm12, audio_txfsync, pwm22, audio_txd, pwm32,
+ audio_rxmclk, pwm03, atest_char0, audio_rxbclk, pwm13,
+ atest_char1, audio_rxfsync, pwm23, atest_char2, audio_rxd,
+ pwm33, atest_char3, pcm_drx, mac10, mac00, pcm_dtx, pcm_fsync,
+ mac20, qdss_traceclk_a, pcm_pclk, qdss_tracectl_a, atest_char,
+ qdss_tracedata_a, blsp0_uart, blsp0_i2c, blsp0_spi,
+ blsp1_uart, blsp1_i2c, blsp1_spi, blsp2_uart, blsp2_i2c,
+ blsp2_spi, blsp3_uart, blsp3_i2c, blsp3_spi, pta2_0, wci21,
+ cxc1, blsp3_spi1, pta2_1, pta2_2, pcie0_clk, dbg_out,
+ cri_trng0, pcie0_rst, cri_trng1, pcie0_wake, cri_trng,
+ pcie1_clk, rx2, ldo_update, pcie1_rst, ldo_en, pcie1_wake,
+ gcc_plltest, sd_card, pwm01, pta1_1, pwm11, rx1, pta1_2,
+ gcc_tlmm, pta1_0, pwm21, prng_rosc, sd_write, pwm31, rx0,
+ tsens_max, mdc, mdio, NA
+
+- bias-disable:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configued as no pull.
+
+- bias-pull-down:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configued as pull down.
+
+- bias-pull-up:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configued as pull up.
+
+- output-high:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins are configured in output mode, driven
+ high.
+ Not valid for sdc pins.
+
+- output-low:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins are configured in output mode, driven
+ low.
+ Not valid for sdc pins.
+
+- drive-strength:
+ Usage: optional
+ Value type: <u32>
+ Definition: Selects the drive strength for the specified pins, in mA.
+ Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
+
+Example:
+
+ tlmm: pinctrl@1000000 {
+ compatible = "qcom,ipq8074-pinctrl";
+ reg = <0x1000000 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ uart2: uart2-default {
+ mux {
+ pins = "gpio23", "gpio24";
+ function = "blsp4_uart1";
+ };
+
+ rx {
+ pins = "gpio23";
+ drive-strength = <4>;
+ bias-disable;
+ };
+
+ tx {
+ pins = "gpio24";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 3ebdc01..9e504db 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -39,6 +39,16 @@ config PINCTRL_IPQ8064
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm IPQ8064 platform.
+config PINCTRL_IPQ8074
+ tristate "Qualcomm Technologies, Inc. IPQ8074 pin controller driver"
+ depends on GPIOLIB && OF
+ select PINCTRL_MSM
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for
+ the Qualcomm Technologies Inc. TLMM block found on the
+ Qualcomm Technologies Inc. IPQ8074 platform. Select this for
+ IPQ8074.
+
config PINCTRL_MSM8660
tristate "Qualcomm 8660 pin controller driver"
depends on GPIOLIB && OF
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index ab47764..06c8b2a 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o
obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
+obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o
obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o
obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o
obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8074.c b/drivers/pinctrl/qcom/pinctrl-ipq8074.c
new file mode 100644
index 0000000..8bb8071
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-ipq8074.c
@@ -0,0 +1,1217 @@
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-msm.h"
+
+#define FUNCTION(fname) \
+ [msm_mux_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define REG_SIZE 0x1000
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins, \
+ .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ msm_mux_gpio, /* gpio mode */ \
+ msm_mux_##f1, \
+ msm_mux_##f2, \
+ msm_mux_##f3, \
+ msm_mux_##f4, \
+ msm_mux_##f5, \
+ msm_mux_##f6, \
+ msm_mux_##f7, \
+ msm_mux_##f8, \
+ msm_mux_##f9 \
+ }, \
+ .nfuncs = 10, \
+ .ctl_reg = REG_SIZE * id, \
+ .io_reg = 0x4 + REG_SIZE * id, \
+ .intr_cfg_reg = 0x8 + REG_SIZE * id, \
+ .intr_status_reg = 0xc + REG_SIZE * id, \
+ .intr_target_reg = 0x8 + REG_SIZE * id, \
+ .mux_bit = 2, \
+ .pull_bit = 0, \
+ .drv_bit = 6, \
+ .oe_bit = 9, \
+ .in_bit = 0, \
+ .out_bit = 1, \
+ .intr_enable_bit = 0, \
+ .intr_status_bit = 0, \
+ .intr_target_bit = 5, \
+ .intr_raw_status_bit = 4, \
+ .intr_polarity_bit = 1, \
+ .intr_detection_bit = 2, \
+ .intr_detection_width = 2, \
+ }
+
+static const struct pinctrl_pin_desc ipq8074_pins[] = {
+ PINCTRL_PIN(0, "GPIO_0"),
+ PINCTRL_PIN(1, "GPIO_1"),
+ PINCTRL_PIN(2, "GPIO_2"),
+ PINCTRL_PIN(3, "GPIO_3"),
+ PINCTRL_PIN(4, "GPIO_4"),
+ PINCTRL_PIN(5, "GPIO_5"),
+ PINCTRL_PIN(6, "GPIO_6"),
+ PINCTRL_PIN(7, "GPIO_7"),
+ PINCTRL_PIN(8, "GPIO_8"),
+ PINCTRL_PIN(9, "GPIO_9"),
+ PINCTRL_PIN(10, "GPIO_10"),
+ PINCTRL_PIN(11, "GPIO_11"),
+ PINCTRL_PIN(12, "GPIO_12"),
+ PINCTRL_PIN(13, "GPIO_13"),
+ PINCTRL_PIN(14, "GPIO_14"),
+ PINCTRL_PIN(15, "GPIO_15"),
+ PINCTRL_PIN(16, "GPIO_16"),
+ PINCTRL_PIN(17, "GPIO_17"),
+ PINCTRL_PIN(18, "GPIO_18"),
+ PINCTRL_PIN(19, "GPIO_19"),
+ PINCTRL_PIN(20, "GPIO_20"),
+ PINCTRL_PIN(21, "GPIO_21"),
+ PINCTRL_PIN(22, "GPIO_22"),
+ PINCTRL_PIN(23, "GPIO_23"),
+ PINCTRL_PIN(24, "GPIO_24"),
+ PINCTRL_PIN(25, "GPIO_25"),
+ PINCTRL_PIN(26, "GPIO_26"),
+ PINCTRL_PIN(27, "GPIO_27"),
+ PINCTRL_PIN(28, "GPIO_28"),
+ PINCTRL_PIN(29, "GPIO_29"),
+ PINCTRL_PIN(30, "GPIO_30"),
+ PINCTRL_PIN(31, "GPIO_31"),
+ PINCTRL_PIN(32, "GPIO_32"),
+ PINCTRL_PIN(33, "GPIO_33"),
+ PINCTRL_PIN(34, "GPIO_34"),
+ PINCTRL_PIN(35, "GPIO_35"),
+ PINCTRL_PIN(36, "GPIO_36"),
+ PINCTRL_PIN(37, "GPIO_37"),
+ PINCTRL_PIN(38, "GPIO_38"),
+ PINCTRL_PIN(39, "GPIO_39"),
+ PINCTRL_PIN(40, "GPIO_40"),
+ PINCTRL_PIN(41, "GPIO_41"),
+ PINCTRL_PIN(42, "GPIO_42"),
+ PINCTRL_PIN(43, "GPIO_43"),
+ PINCTRL_PIN(44, "GPIO_44"),
+ PINCTRL_PIN(45, "GPIO_45"),
+ PINCTRL_PIN(46, "GPIO_46"),
+ PINCTRL_PIN(47, "GPIO_47"),
+ PINCTRL_PIN(48, "GPIO_48"),
+ PINCTRL_PIN(49, "GPIO_49"),
+ PINCTRL_PIN(50, "GPIO_50"),
+ PINCTRL_PIN(51, "GPIO_51"),
+ PINCTRL_PIN(52, "GPIO_52"),
+ PINCTRL_PIN(53, "GPIO_53"),
+ PINCTRL_PIN(54, "GPIO_54"),
+ PINCTRL_PIN(55, "GPIO_55"),
+ PINCTRL_PIN(56, "GPIO_56"),
+ PINCTRL_PIN(57, "GPIO_57"),
+ PINCTRL_PIN(58, "GPIO_58"),
+ PINCTRL_PIN(59, "GPIO_59"),
+ PINCTRL_PIN(60, "GPIO_60"),
+ PINCTRL_PIN(61, "GPIO_61"),
+ PINCTRL_PIN(62, "GPIO_62"),
+ PINCTRL_PIN(63, "GPIO_63"),
+ PINCTRL_PIN(64, "GPIO_64"),
+ PINCTRL_PIN(65, "GPIO_65"),
+ PINCTRL_PIN(66, "GPIO_66"),
+ PINCTRL_PIN(67, "GPIO_67"),
+ PINCTRL_PIN(68, "GPIO_68"),
+ PINCTRL_PIN(69, "GPIO_69"),
+};
+
+#define DECLARE_MSM_GPIO_PINS(pin) \
+ static const unsigned int gpio##pin##_pins[] = { pin }
+DECLARE_MSM_GPIO_PINS(0);
+DECLARE_MSM_GPIO_PINS(1);
+DECLARE_MSM_GPIO_PINS(2);
+DECLARE_MSM_GPIO_PINS(3);
+DECLARE_MSM_GPIO_PINS(4);
+DECLARE_MSM_GPIO_PINS(5);
+DECLARE_MSM_GPIO_PINS(6);
+DECLARE_MSM_GPIO_PINS(7);
+DECLARE_MSM_GPIO_PINS(8);
+DECLARE_MSM_GPIO_PINS(9);
+DECLARE_MSM_GPIO_PINS(10);
+DECLARE_MSM_GPIO_PINS(11);
+DECLARE_MSM_GPIO_PINS(12);
+DECLARE_MSM_GPIO_PINS(13);
+DECLARE_MSM_GPIO_PINS(14);
+DECLARE_MSM_GPIO_PINS(15);
+DECLARE_MSM_GPIO_PINS(16);
+DECLARE_MSM_GPIO_PINS(17);
+DECLARE_MSM_GPIO_PINS(18);
+DECLARE_MSM_GPIO_PINS(19);
+DECLARE_MSM_GPIO_PINS(20);
+DECLARE_MSM_GPIO_PINS(21);
+DECLARE_MSM_GPIO_PINS(22);
+DECLARE_MSM_GPIO_PINS(23);
+DECLARE_MSM_GPIO_PINS(24);
+DECLARE_MSM_GPIO_PINS(25);
+DECLARE_MSM_GPIO_PINS(26);
+DECLARE_MSM_GPIO_PINS(27);
+DECLARE_MSM_GPIO_PINS(28);
+DECLARE_MSM_GPIO_PINS(29);
+DECLARE_MSM_GPIO_PINS(30);
+DECLARE_MSM_GPIO_PINS(31);
+DECLARE_MSM_GPIO_PINS(32);
+DECLARE_MSM_GPIO_PINS(33);
+DECLARE_MSM_GPIO_PINS(34);
+DECLARE_MSM_GPIO_PINS(35);
+DECLARE_MSM_GPIO_PINS(36);
+DECLARE_MSM_GPIO_PINS(37);
+DECLARE_MSM_GPIO_PINS(38);
+DECLARE_MSM_GPIO_PINS(39);
+DECLARE_MSM_GPIO_PINS(40);
+DECLARE_MSM_GPIO_PINS(41);
+DECLARE_MSM_GPIO_PINS(42);
+DECLARE_MSM_GPIO_PINS(43);
+DECLARE_MSM_GPIO_PINS(44);
+DECLARE_MSM_GPIO_PINS(45);
+DECLARE_MSM_GPIO_PINS(46);
+DECLARE_MSM_GPIO_PINS(47);
+DECLARE_MSM_GPIO_PINS(48);
+DECLARE_MSM_GPIO_PINS(49);
+DECLARE_MSM_GPIO_PINS(50);
+DECLARE_MSM_GPIO_PINS(51);
+DECLARE_MSM_GPIO_PINS(52);
+DECLARE_MSM_GPIO_PINS(53);
+DECLARE_MSM_GPIO_PINS(54);
+DECLARE_MSM_GPIO_PINS(55);
+DECLARE_MSM_GPIO_PINS(56);
+DECLARE_MSM_GPIO_PINS(57);
+DECLARE_MSM_GPIO_PINS(58);
+DECLARE_MSM_GPIO_PINS(59);
+DECLARE_MSM_GPIO_PINS(60);
+DECLARE_MSM_GPIO_PINS(61);
+DECLARE_MSM_GPIO_PINS(62);
+DECLARE_MSM_GPIO_PINS(63);
+DECLARE_MSM_GPIO_PINS(64);
+DECLARE_MSM_GPIO_PINS(65);
+DECLARE_MSM_GPIO_PINS(66);
+DECLARE_MSM_GPIO_PINS(67);
+DECLARE_MSM_GPIO_PINS(68);
+DECLARE_MSM_GPIO_PINS(69);
+
+enum ipq8074_functions {
+ msm_mux_gpio,
+ msm_mux_qpic_pad,
+ msm_mux_blsp5_i2c,
+ msm_mux_blsp5_spi,
+ msm_mux_wci20,
+ msm_mux_blsp3_spi3,
+ msm_mux_burn0,
+ msm_mux_pcm_zsi0,
+ msm_mux_blsp5_uart,
+ msm_mux_mac12,
+ msm_mux_blsp3_spi0,
+ msm_mux_burn1,
+ msm_mux_mac01,
+ msm_mux_qdss_cti_trig_out_b0,
+ msm_mux_qdss_cti_trig_in_b0,
+ msm_mux_qpic_pad4,
+ msm_mux_blsp4_uart0,
+ msm_mux_blsp4_i2c0,
+ msm_mux_blsp4_spi0,
+ msm_mux_mac21,
+ msm_mux_qdss_cti_trig_out_b1,
+ msm_mux_qpic_pad5,
+ msm_mux_qdss_cti_trig_in_b1,
+ msm_mux_qpic_pad6,
+ msm_mux_qpic_pad7,
+ msm_mux_cxc0,
+ msm_mux_mac13,
+ msm_mux_qdss_cti_trig_in_a1,
+ msm_mux_qdss_cti_trig_out_a1,
+ msm_mux_wci22,
+ msm_mux_qdss_cti_trig_in_a0,
+ msm_mux_qpic_pad1,
+ msm_mux_qdss_cti_trig_out_a0,
+ msm_mux_qpic_pad2,
+ msm_mux_qpic_pad3,
+ msm_mux_qdss_traceclk_b,
+ msm_mux_qpic_pad0,
+ msm_mux_qdss_tracectl_b,
+ msm_mux_qpic_pad8,
+ msm_mux_pcm_zsi1,
+ msm_mux_qdss_tracedata_b,
+ msm_mux_led0,
+ msm_mux_pwm04,
+ msm_mux_led1,
+ msm_mux_pwm14,
+ msm_mux_led2,
+ msm_mux_pwm24,
+ msm_mux_pwm00,
+ msm_mux_blsp4_uart1,
+ msm_mux_blsp4_i2c1,
+ msm_mux_blsp4_spi1,
+ msm_mux_wci23,
+ msm_mux_mac11,
+ msm_mux_blsp3_spi2,
+ msm_mux_pwm10,
+ msm_mux_pwm20,
+ msm_mux_pwm30,
+ msm_mux_audio_txmclk,
+ msm_mux_pwm02,
+ msm_mux_audio_txbclk,
+ msm_mux_pwm12,
+ msm_mux_audio_txfsync,
+ msm_mux_pwm22,
+ msm_mux_audio_txd,
+ msm_mux_pwm32,
+ msm_mux_audio_rxmclk,
+ msm_mux_pwm03,
+ msm_mux_atest_char0,
+ msm_mux_audio_rxbclk,
+ msm_mux_pwm13,
+ msm_mux_atest_char1,
+ msm_mux_audio_rxfsync,
+ msm_mux_pwm23,
+ msm_mux_atest_char2,
+ msm_mux_audio_rxd,
+ msm_mux_pwm33,
+ msm_mux_atest_char3,
+ msm_mux_pcm_drx,
+ msm_mux_mac10,
+ msm_mux_mac00,
+ msm_mux_pcm_dtx,
+ msm_mux_pcm_fsync,
+ msm_mux_mac20,
+ msm_mux_qdss_traceclk_a,
+ msm_mux_pcm_pclk,
+ msm_mux_qdss_tracectl_a,
+ msm_mux_atest_char,
+ msm_mux_qdss_tracedata_a,
+ msm_mux_blsp0_uart,
+ msm_mux_blsp0_i2c,
+ msm_mux_blsp0_spi,
+ msm_mux_blsp1_uart,
+ msm_mux_blsp1_i2c,
+ msm_mux_blsp1_spi,
+ msm_mux_blsp2_uart,
+ msm_mux_blsp2_i2c,
+ msm_mux_blsp2_spi,
+ msm_mux_blsp3_uart,
+ msm_mux_blsp3_i2c,
+ msm_mux_blsp3_spi,
+ msm_mux_pta2_0,
+ msm_mux_wci21,
+ msm_mux_cxc1,
+ msm_mux_blsp3_spi1,
+ msm_mux_pta2_1,
+ msm_mux_pta2_2,
+ msm_mux_pcie0_clk,
+ msm_mux_dbg_out,
+ msm_mux_cri_trng0,
+ msm_mux_pcie0_rst,
+ msm_mux_cri_trng1,
+ msm_mux_pcie0_wake,
+ msm_mux_cri_trng,
+ msm_mux_pcie1_clk,
+ msm_mux_rx2,
+ msm_mux_ldo_update,
+ msm_mux_pcie1_rst,
+ msm_mux_ldo_en,
+ msm_mux_pcie1_wake,
+ msm_mux_gcc_plltest,
+ msm_mux_sd_card,
+ msm_mux_pwm01,
+ msm_mux_pta1_1,
+ msm_mux_pwm11,
+ msm_mux_rx1,
+ msm_mux_pta1_2,
+ msm_mux_gcc_tlmm,
+ msm_mux_pta1_0,
+ msm_mux_pwm21,
+ msm_mux_prng_rosc,
+ msm_mux_sd_write,
+ msm_mux_pwm31,
+ msm_mux_rx0,
+ msm_mux_tsens_max,
+ msm_mux_mdc,
+ msm_mux_mdio,
+ msm_mux_NA,
+};
+
+static const char * const qpic_pad_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio9", "gpio10",
+ "gpio11", "gpio17",
+};
+
+static const char * const _groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
+ "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
+ "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
+ "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69",
+};
+
+static const char * const blsp5_i2c_groups[] = {
+ "gpio0", "gpio2",
+};
+
+static const char * const blsp5_spi_groups[] = {
+ "gpio0", "gpio2", "gpio9", "gpio16",
+};
+
+static const char * const wci20_groups[] = {
+ "gpio0", "gpio2",
+};
+
+static const char * const blsp3_spi3_groups[] = {
+ "gpio0", "gpio2", "gpio9",
+};
+
+static const char * const burn0_groups[] = {
+ "gpio0",
+};
+
+static const char * const pcm_zsi0_groups[] = {
+ "gpio1",
+};
+
+static const char * const blsp5_uart_groups[] = {
+ "gpio0", "gpio2", "gpio9", "gpio16",
+};
+
+static const char * const mac12_groups[] = {
+ "gpio1", "gpio11",
+};
+
+static const char * const blsp3_spi0_groups[] = {
+ "gpio1", "gpio3", "gpio4",
+};
+
+static const char * const burn1_groups[] = {
+ "gpio1",
+};
+
+static const char * const mac01_groups[] = {
+ "gpio3", "gpio4",
+};
+
+static const char * const qdss_cti_trig_out_b0_groups[] = {
+ "gpio3",
+};
+
+static const char * const qdss_cti_trig_in_b0_groups[] = {
+ "gpio4",
+};
+
+static const char * const qpic_pad4_groups[] = {
+ "gpio5",
+};
+
+static const char * const blsp4_uart0_groups[] = {
+ "gpio5", "gpio6", "gpio7", "gpio8",
+};
+
+static const char * const blsp4_i2c0_groups[] = {
+ "gpio5", "gpio6",
+};
+
+static const char * const blsp4_spi0_groups[] = {
+ "gpio5", "gpio6", "gpio7", "gpio8",
+};
+
+static const char * const mac21_groups[] = {
+ "gpio5", "gpio6",
+};
+
+static const char * const qdss_cti_trig_out_b1_groups[] = {
+ "gpio5",
+};
+
+static const char * const qpic_pad5_groups[] = {
+ "gpio6",
+};
+
+static const char * const qdss_cti_trig_in_b1_groups[] = {
+ "gpio6",
+};
+
+static const char * const qpic_pad6_groups[] = {
+ "gpio7",
+};
+
+static const char * const qpic_pad7_groups[] = {
+ "gpio8",
+};
+
+static const char * const cxc0_groups[] = {
+ "gpio9", "gpio16",
+};
+
+static const char * const mac13_groups[] = {
+ "gpio9", "gpio16",
+};
+
+static const char * const qdss_cti_trig_in_a1_groups[] = {
+ "gpio9",
+};
+
+static const char * const qdss_cti_trig_out_a1_groups[] = {
+ "gpio10",
+};
+
+static const char * const wci22_groups[] = {
+ "gpio11", "gpio17",
+};
+
+static const char * const qdss_cti_trig_in_a0_groups[] = {
+ "gpio11",
+};
+
+static const char * const qpic_pad1_groups[] = {
+ "gpio12",
+};
+
+static const char * const qdss_cti_trig_out_a0_groups[] = {
+ "gpio12",
+};
+
+static const char * const qpic_pad2_groups[] = {
+ "gpio13",
+};
+
+static const char * const qpic_pad3_groups[] = {
+ "gpio14",
+};
+
+static const char * const qdss_traceclk_b_groups[] = {
+ "gpio14",
+};
+
+static const char * const qpic_pad0_groups[] = {
+ "gpio15",
+};
+
+static const char * const qdss_tracectl_b_groups[] = {
+ "gpio15",
+};
+
+static const char * const qpic_pad8_groups[] = {
+ "gpio16",
+};
+
+static const char * const pcm_zsi1_groups[] = {
+ "gpio16",
+};
+
+static const char * const qdss_tracedata_b_groups[] = {
+ "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
+ "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
+ "gpio30", "gpio31",
+};
+
+static const char * const led0_groups[] = {
+ "gpio18",
+};
+
+static const char * const pwm04_groups[] = {
+ "gpio18",
+};
+
+static const char * const led1_groups[] = {
+ "gpio19",
+};
+
+static const char * const pwm14_groups[] = {
+ "gpio19",
+};
+
+static const char * const led2_groups[] = {
+ "gpio20",
+};
+
+static const char * const pwm24_groups[] = {
+ "gpio20",
+};
+
+static const char * const pwm00_groups[] = {
+ "gpio21",
+};
+
+static const char * const blsp4_uart1_groups[] = {
+ "gpio21", "gpio22", "gpio23", "gpio24",
+};
+
+static const char * const blsp4_i2c1_groups[] = {
+ "gpio21", "gpio22",
+};
+
+static const char * const blsp4_spi1_groups[] = {
+ "gpio21", "gpio22", "gpio23", "gpio24",
+};
+
+static const char * const wci23_groups[] = {
+ "gpio21", "gpio22",
+};
+
+static const char * const mac11_groups[] = {
+ "gpio21", "gpio22",
+};
+
+static const char * const blsp3_spi2_groups[] = {
+ "gpio21", "gpio22", "gpio23",
+};
+
+static const char * const pwm10_groups[] = {
+ "gpio22",
+};
+
+static const char * const pwm20_groups[] = {
+ "gpio23",
+};
+
+static const char * const pwm30_groups[] = {
+ "gpio24",
+};
+
+static const char * const audio_txmclk_groups[] = {
+ "gpio25",
+};
+
+static const char * const pwm02_groups[] = {
+ "gpio25",
+};
+
+static const char * const audio_txbclk_groups[] = {
+ "gpio26",
+};
+
+static const char * const pwm12_groups[] = {
+ "gpio26",
+};
+
+static const char * const audio_txfsync_groups[] = {
+ "gpio27",
+};
+
+static const char * const pwm22_groups[] = {
+ "gpio27",
+};
+
+static const char * const audio_txd_groups[] = {
+ "gpio28",
+};
+
+static const char * const pwm32_groups[] = {
+ "gpio28",
+};
+
+static const char * const audio_rxmclk_groups[] = {
+ "gpio29",
+};
+
+static const char * const pwm03_groups[] = {
+ "gpio29",
+};
+
+static const char * const atest_char0_groups[] = {
+ "gpio29",
+};
+
+static const char * const audio_rxbclk_groups[] = {
+ "gpio30",
+};
+
+static const char * const pwm13_groups[] = {
+ "gpio30",
+};
+
+static const char * const atest_char1_groups[] = {
+ "gpio30",
+};
+
+static const char * const audio_rxfsync_groups[] = {
+ "gpio31",
+};
+
+static const char * const pwm23_groups[] = {
+ "gpio31",
+};
+
+static const char * const atest_char2_groups[] = {
+ "gpio31",
+};
+
+static const char * const audio_rxd_groups[] = {
+ "gpio32",
+};
+
+static const char * const pwm33_groups[] = {
+ "gpio32",
+};
+
+static const char * const atest_char3_groups[] = {
+ "gpio32",
+};
+
+static const char * const pcm_drx_groups[] = {
+ "gpio33",
+};
+
+static const char * const mac10_groups[] = {
+ "gpio33", "gpio34",
+};
+
+static const char * const mac00_groups[] = {
+ "gpio33", "gpio34",
+};
+
+static const char * const pcm_dtx_groups[] = {
+ "gpio34",
+};
+
+static const char * const pcm_fsync_groups[] = {
+ "gpio35",
+};
+
+static const char * const mac20_groups[] = {
+ "gpio35", "gpio36",
+};
+
+static const char * const qdss_traceclk_a_groups[] = {
+ "gpio35",
+};
+
+static const char * const pcm_pclk_groups[] = {
+ "gpio36",
+};
+
+static const char * const qdss_tracectl_a_groups[] = {
+ "gpio36",
+};
+
+static const char * const atest_char_groups[] = {
+ "gpio37",
+};
+
+static const char * const qdss_tracedata_a_groups[] = {
+ "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
+ "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", "gpio50",
+ "gpio51", "gpio52",
+};
+
+static const char * const blsp0_uart_groups[] = {
+ "gpio38", "gpio39", "gpio40", "gpio41",
+};
+
+static const char * const blsp0_i2c_groups[] = {
+ "gpio38", "gpio39",
+};
+
+static const char * const blsp0_spi_groups[] = {
+ "gpio38", "gpio39", "gpio40", "gpio41",
+};
+
+static const char * const blsp1_uart_groups[] = {
+ "gpio42", "gpio43", "gpio44", "gpio45",
+};
+
+static const char * const blsp1_i2c_groups[] = {
+ "gpio42", "gpio43",
+};
+
+static const char * const blsp1_spi_groups[] = {
+ "gpio42", "gpio43", "gpio44", "gpio45",
+};
+
+static const char * const blsp2_uart_groups[] = {
+ "gpio46", "gpio47", "gpio48", "gpio49",
+};
+
+static const char * const blsp2_i2c_groups[] = {
+ "gpio46", "gpio47",
+};
+
+static const char * const blsp2_spi_groups[] = {
+ "gpio46", "gpio47", "gpio48", "gpio49",
+};
+
+static const char * const blsp3_uart_groups[] = {
+ "gpio50", "gpio51", "gpio52", "gpio53",
+};
+
+static const char * const blsp3_i2c_groups[] = {
+ "gpio50", "gpio51",
+};
+
+static const char * const blsp3_spi_groups[] = {
+ "gpio50", "gpio51", "gpio52", "gpio53",
+};
+
+static const char * const pta2_0_groups[] = {
+ "gpio54",
+};
+
+static const char * const wci21_groups[] = {
+ "gpio54", "gpio56",
+};
+
+static const char * const cxc1_groups[] = {
+ "gpio54", "gpio56",
+};
+
+static const char * const blsp3_spi1_groups[] = {
+ "gpio54", "gpio55", "gpio56",
+};
+
+static const char * const pta2_1_groups[] = {
+ "gpio55",
+};
+
+static const char * const pta2_2_groups[] = {
+ "gpio56",
+};
+
+static const char * const pcie0_clk_groups[] = {
+ "gpio57",
+};
+
+static const char * const dbg_out_groups[] = {
+ "gpio57",
+};
+
+static const char * const cri_trng0_groups[] = {
+ "gpio57",
+};
+
+static const char * const pcie0_rst_groups[] = {
+ "gpio58",
+};
+
+static const char * const cri_trng1_groups[] = {
+ "gpio58",
+};
+
+static const char * const pcie0_wake_groups[] = {
+ "gpio59",
+};
+
+static const char * const cri_trng_groups[] = {
+ "gpio59",
+};
+
+static const char * const pcie1_clk_groups[] = {
+ "gpio60",
+};
+
+static const char * const rx2_groups[] = {
+ "gpio60",
+};
+
+static const char * const ldo_update_groups[] = {
+ "gpio60",
+};
+
+static const char * const pcie1_rst_groups[] = {
+ "gpio61",
+};
+
+static const char * const ldo_en_groups[] = {
+ "gpio61",
+};
+
+static const char * const pcie1_wake_groups[] = {
+ "gpio62",
+};
+
+static const char * const gcc_plltest_groups[] = {
+ "gpio62", "gpio63",
+};
+
+static const char * const sd_card_groups[] = {
+ "gpio63",
+};
+
+static const char * const pwm01_groups[] = {
+ "gpio63",
+};
+
+static const char * const pta1_1_groups[] = {
+ "gpio64",
+};
+
+static const char * const pwm11_groups[] = {
+ "gpio64",
+};
+
+static const char * const rx1_groups[] = {
+ "gpio64",
+};
+
+static const char * const pta1_2_groups[] = {
+ "gpio65",
+};
+
+static const char * const gcc_tlmm_groups[] = {
+ "gpio65",
+};
+
+static const char * const pta1_0_groups[] = {
+ "gpio66",
+};
+
+static const char * const pwm21_groups[] = {
+ "gpio66",
+};
+
+static const char * const prng_rosc_groups[] = {
+ "gpio66",
+};
+
+static const char * const sd_write_groups[] = {
+ "gpio67",
+};
+
+static const char * const pwm31_groups[] = {
+ "gpio67",
+};
+
+static const char * const rx0_groups[] = {
+ "gpio67",
+};
+
+static const char * const tsens_max_groups[] = {
+ "gpio67",
+};
+
+static const char * const mdc_groups[] = {
+ "gpio68",
+};
+
+static const char * const mdio_groups[] = {
+ "gpio69",
+};
+
+static const char * const gpio_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
+ "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
+ "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
+ "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69",
+};
+
+static const struct msm_function ipq8074_functions[] = {
+ FUNCTION(gpio),
+ FUNCTION(qpic_pad),
+ FUNCTION(blsp5_i2c),
+ FUNCTION(blsp5_spi),
+ FUNCTION(wci20),
+ FUNCTION(blsp3_spi3),
+ FUNCTION(burn0),
+ FUNCTION(pcm_zsi0),
+ FUNCTION(blsp5_uart),
+ FUNCTION(mac12),
+ FUNCTION(blsp3_spi0),
+ FUNCTION(burn1),
+ FUNCTION(mac01),
+ FUNCTION(qdss_cti_trig_out_b0),
+ FUNCTION(qdss_cti_trig_in_b0),
+ FUNCTION(qpic_pad4),
+ FUNCTION(blsp4_uart0),
+ FUNCTION(blsp4_i2c0),
+ FUNCTION(blsp4_spi0),
+ FUNCTION(mac21),
+ FUNCTION(qdss_cti_trig_out_b1),
+ FUNCTION(qpic_pad5),
+ FUNCTION(qdss_cti_trig_in_b1),
+ FUNCTION(qpic_pad6),
+ FUNCTION(qpic_pad7),
+ FUNCTION(cxc0),
+ FUNCTION(mac13),
+ FUNCTION(qdss_cti_trig_in_a1),
+ FUNCTION(qdss_cti_trig_out_a1),
+ FUNCTION(wci22),
+ FUNCTION(qdss_cti_trig_in_a0),
+ FUNCTION(qpic_pad1),
+ FUNCTION(qdss_cti_trig_out_a0),
+ FUNCTION(qpic_pad2),
+ FUNCTION(qpic_pad3),
+ FUNCTION(qdss_traceclk_b),
+ FUNCTION(qpic_pad0),
+ FUNCTION(qdss_tracectl_b),
+ FUNCTION(qpic_pad8),
+ FUNCTION(pcm_zsi1),
+ FUNCTION(qdss_tracedata_b),
+ FUNCTION(led0),
+ FUNCTION(pwm04),
+ FUNCTION(led1),
+ FUNCTION(pwm14),
+ FUNCTION(led2),
+ FUNCTION(pwm24),
+ FUNCTION(pwm00),
+ FUNCTION(blsp4_uart1),
+ FUNCTION(blsp4_i2c1),
+ FUNCTION(blsp4_spi1),
+ FUNCTION(wci23),
+ FUNCTION(mac11),
+ FUNCTION(blsp3_spi2),
+ FUNCTION(pwm10),
+ FUNCTION(pwm20),
+ FUNCTION(pwm30),
+ FUNCTION(audio_txmclk),
+ FUNCTION(pwm02),
+ FUNCTION(audio_txbclk),
+ FUNCTION(pwm12),
+ FUNCTION(audio_txfsync),
+ FUNCTION(pwm22),
+ FUNCTION(audio_txd),
+ FUNCTION(pwm32),
+ FUNCTION(audio_rxmclk),
+ FUNCTION(pwm03),
+ FUNCTION(atest_char0),
+ FUNCTION(audio_rxbclk),
+ FUNCTION(pwm13),
+ FUNCTION(atest_char1),
+ FUNCTION(audio_rxfsync),
+ FUNCTION(pwm23),
+ FUNCTION(atest_char2),
+ FUNCTION(audio_rxd),
+ FUNCTION(pwm33),
+ FUNCTION(atest_char3),
+ FUNCTION(pcm_drx),
+ FUNCTION(mac10),
+ FUNCTION(mac00),
+ FUNCTION(pcm_dtx),
+ FUNCTION(pcm_fsync),
+ FUNCTION(mac20),
+ FUNCTION(qdss_traceclk_a),
+ FUNCTION(pcm_pclk),
+ FUNCTION(qdss_tracectl_a),
+ FUNCTION(atest_char),
+ FUNCTION(qdss_tracedata_a),
+ FUNCTION(blsp0_uart),
+ FUNCTION(blsp0_i2c),
+ FUNCTION(blsp0_spi),
+ FUNCTION(blsp1_uart),
+ FUNCTION(blsp1_i2c),
+ FUNCTION(blsp1_spi),
+ FUNCTION(blsp2_uart),
+ FUNCTION(blsp2_i2c),
+ FUNCTION(blsp2_spi),
+ FUNCTION(blsp3_uart),
+ FUNCTION(blsp3_i2c),
+ FUNCTION(blsp3_spi),
+ FUNCTION(pta2_0),
+ FUNCTION(wci21),
+ FUNCTION(cxc1),
+ FUNCTION(blsp3_spi1),
+ FUNCTION(pta2_1),
+ FUNCTION(pta2_2),
+ FUNCTION(pcie0_clk),
+ FUNCTION(dbg_out),
+ FUNCTION(cri_trng0),
+ FUNCTION(pcie0_rst),
+ FUNCTION(cri_trng1),
+ FUNCTION(pcie0_wake),
+ FUNCTION(cri_trng),
+ FUNCTION(pcie1_clk),
+ FUNCTION(rx2),
+ FUNCTION(ldo_update),
+ FUNCTION(pcie1_rst),
+ FUNCTION(ldo_en),
+ FUNCTION(pcie1_wake),
+ FUNCTION(gcc_plltest),
+ FUNCTION(sd_card),
+ FUNCTION(pwm01),
+ FUNCTION(pta1_1),
+ FUNCTION(pwm11),
+ FUNCTION(rx1),
+ FUNCTION(pta1_2),
+ FUNCTION(gcc_tlmm),
+ FUNCTION(pta1_0),
+ FUNCTION(pwm21),
+ FUNCTION(prng_rosc),
+ FUNCTION(sd_write),
+ FUNCTION(pwm31),
+ FUNCTION(rx0),
+ FUNCTION(tsens_max),
+ FUNCTION(mdc),
+ FUNCTION(mdio),
+};
+
+static const struct msm_pingroup ipq8074_groups[] = {
+ PINGROUP(0, qpic_pad, blsp5_uart, blsp5_i2c, blsp5_spi, wci20,
+ blsp3_spi3, NA, burn0, NA),
+ PINGROUP(1, qpic_pad, pcm_zsi0, mac12, blsp3_spi0, NA, burn1, NA, NA,
+ NA),
+ PINGROUP(2, qpic_pad, blsp5_uart, blsp5_i2c, blsp5_spi, wci20,
+ blsp3_spi3, NA, NA, NA),
+ PINGROUP(3, qpic_pad, mac01, blsp3_spi0, qdss_cti_trig_out_b0, NA, NA,
+ NA, NA, NA),
+ PINGROUP(4, qpic_pad, mac01, blsp3_spi0, qdss_cti_trig_in_b0, NA, NA,
+ NA, NA, NA),
+ PINGROUP(5, qpic_pad4, blsp4_uart0, blsp4_i2c0, blsp4_spi0, mac21,
+ qdss_cti_trig_out_b1, NA, NA, NA),
+ PINGROUP(6, qpic_pad5, blsp4_uart0, blsp4_i2c0, blsp4_spi0, mac21,
+ qdss_cti_trig_in_b1, NA, NA, NA),
+ PINGROUP(7, qpic_pad6, blsp4_uart0, blsp4_spi0, NA, NA, NA, NA, NA, NA),
+ PINGROUP(8, qpic_pad7, blsp4_uart0, blsp4_spi0, NA, NA, NA, NA, NA, NA),
+ PINGROUP(9, qpic_pad, blsp5_uart, blsp5_spi, cxc0, mac13, blsp3_spi3,
+ qdss_cti_trig_in_a1, NA, NA),
+ PINGROUP(10, qpic_pad, qdss_cti_trig_out_a1, NA, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(11, qpic_pad, wci22, mac12, qdss_cti_trig_in_a0, NA, NA, NA,
+ NA, NA),
+ PINGROUP(12, qpic_pad1, qdss_cti_trig_out_a0, NA, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(13, qpic_pad2, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(14, qpic_pad3, qdss_traceclk_b, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(15, qpic_pad0, qdss_tracectl_b, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(16, qpic_pad8, blsp5_uart, pcm_zsi1, blsp5_spi, cxc0, mac13,
+ qdss_tracedata_b, NA, NA),
+ PINGROUP(17, qpic_pad, wci22, qdss_tracedata_b, NA, NA, NA, NA, NA, NA),
+ PINGROUP(18, led0, pwm04, qdss_tracedata_b, NA, NA, NA, NA, NA, NA),
+ PINGROUP(19, led1, pwm14, NA, qdss_tracedata_b, NA, NA, NA, NA, NA),
+ PINGROUP(20, led2, pwm24, NA, qdss_tracedata_b, NA, NA, NA, NA, NA),
+ PINGROUP(21, pwm00, blsp4_uart1, blsp4_i2c1, blsp4_spi1, wci23, mac11,
+ blsp3_spi2, NA, qdss_tracedata_b),
+ PINGROUP(22, pwm10, blsp4_uart1, blsp4_i2c1, blsp4_spi1, wci23, mac11,
+ blsp3_spi2, NA, qdss_tracedata_b),
+ PINGROUP(23, pwm20, blsp4_uart1, blsp4_spi1, blsp3_spi2, NA,
+ qdss_tracedata_b, NA, NA, NA),
+ PINGROUP(24, pwm30, blsp4_uart1, blsp4_spi1, NA, qdss_tracedata_b, NA,
+ NA, NA, NA),
+ PINGROUP(25, audio_txmclk, pwm02, NA, qdss_tracedata_b, NA, NA, NA, NA,
+ NA),
+ PINGROUP(26, audio_txbclk, pwm12, NA, qdss_tracedata_b, NA, NA, NA, NA,
+ NA),
+ PINGROUP(27, audio_txfsync, pwm22, NA, qdss_tracedata_b, NA, NA, NA,
+ NA, NA),
+ PINGROUP(28, audio_txd, pwm32, NA, qdss_tracedata_b, NA, NA, NA, NA,
+ NA),
+ PINGROUP(29, audio_rxmclk, pwm03, atest_char0, NA, qdss_tracedata_b,
+ NA, NA, NA, NA),
+ PINGROUP(30, audio_rxbclk, pwm13, atest_char1, NA, qdss_tracedata_b,
+ NA, NA, NA, NA),
+ PINGROUP(31, audio_rxfsync, pwm23, atest_char2, NA, qdss_tracedata_b,
+ NA, NA, NA, NA),
+ PINGROUP(32, audio_rxd, pwm33, atest_char3, NA, NA, NA, NA, NA, NA),
+ PINGROUP(33, pcm_drx, mac10, mac00, NA, NA, NA, NA, NA, NA),
+ PINGROUP(34, pcm_dtx, mac10, mac00, NA, NA, NA, NA, NA, NA),
+ PINGROUP(35, pcm_fsync, mac20, qdss_traceclk_a, NA, NA, NA, NA, NA, NA),
+ PINGROUP(36, pcm_pclk, mac20, NA, qdss_tracectl_a, NA, NA, NA, NA, NA),
+ PINGROUP(37, atest_char, NA, qdss_tracedata_a, NA, NA, NA, NA, NA, NA),
+ PINGROUP(38, blsp0_uart, blsp0_i2c, blsp0_spi, NA, qdss_tracedata_a,
+ NA, NA, NA, NA),
+ PINGROUP(39, blsp0_uart, blsp0_i2c, blsp0_spi, NA, qdss_tracedata_a,
+ NA, NA, NA, NA),
+ PINGROUP(40, blsp0_uart, blsp0_spi, NA, qdss_tracedata_a, NA, NA, NA,
+ NA, NA),
+ PINGROUP(41, blsp0_uart, blsp0_spi, NA, qdss_tracedata_a, NA, NA, NA,
+ NA, NA),
+ PINGROUP(42, blsp1_uart, blsp1_i2c, blsp1_spi, NA, qdss_tracedata_a,
+ NA, NA, NA, NA),
+ PINGROUP(43, blsp1_uart, blsp1_i2c, blsp1_spi, NA, qdss_tracedata_a,
+ NA, NA, NA, NA),
+ PINGROUP(44, blsp1_uart, blsp1_spi, NA, qdss_tracedata_a, NA, NA, NA,
+ NA, NA),
+ PINGROUP(45, blsp1_uart, blsp1_spi, qdss_tracedata_a, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(46, blsp2_uart, blsp2_i2c, blsp2_spi, qdss_tracedata_a, NA,
+ NA, NA, NA, NA),
+ PINGROUP(47, blsp2_uart, blsp2_i2c, blsp2_spi, NA, qdss_tracedata_a,
+ NA, NA, NA, NA),
+ PINGROUP(48, blsp2_uart, blsp2_spi, NA, qdss_tracedata_a, NA, NA, NA,
+ NA, NA),
+ PINGROUP(49, blsp2_uart, blsp2_spi, NA, qdss_tracedata_a, NA, NA, NA,
+ NA, NA),
+ PINGROUP(50, blsp3_uart, blsp3_i2c, blsp3_spi, NA, qdss_tracedata_a,
+ NA, NA, NA, NA),
+ PINGROUP(51, blsp3_uart, blsp3_i2c, blsp3_spi, NA, qdss_tracedata_a,
+ NA, NA, NA, NA),
+ PINGROUP(52, blsp3_uart, blsp3_spi, NA, qdss_tracedata_a, NA, NA, NA,
+ NA, NA),
+ PINGROUP(53, blsp3_uart, blsp3_spi, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(54, pta2_0, wci21, cxc1, blsp3_spi1, NA, NA, NA, NA, NA),
+ PINGROUP(55, pta2_1, blsp3_spi1, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(56, pta2_2, wci21, cxc1, blsp3_spi1, NA, NA, NA, NA, NA),
+ PINGROUP(57, pcie0_clk, NA, dbg_out, cri_trng0, NA, NA, NA, NA, NA),
+ PINGROUP(58, pcie0_rst, NA, cri_trng1, NA, NA, NA, NA, NA, NA),
+ PINGROUP(59, pcie0_wake, NA, cri_trng, NA, NA, NA, NA, NA, NA),
+ PINGROUP(60, pcie1_clk, rx2, ldo_update, NA, NA, NA, NA, NA, NA),
+ PINGROUP(61, pcie1_rst, ldo_en, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(62, pcie1_wake, gcc_plltest, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(63, sd_card, pwm01, NA, gcc_plltest, NA, NA, NA, NA, NA),
+ PINGROUP(64, pta1_1, pwm11, NA, rx1, NA, NA, NA, NA, NA),
+ PINGROUP(65, pta1_2, NA, gcc_tlmm, NA, NA, NA, NA, NA, NA),
+ PINGROUP(66, pta1_0, pwm21, prng_rosc, NA, NA, NA, NA, NA, NA),
+ PINGROUP(67, sd_write, pwm31, rx0, tsens_max, NA, NA, NA, NA, NA),
+ PINGROUP(68, mdc, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(69, mdio, NA, NA, NA, NA, NA, NA, NA, NA),
+};
+
+static const struct msm_pinctrl_soc_data ipq8074_pinctrl = {
+ .pins = ipq8074_pins,
+ .npins = ARRAY_SIZE(ipq8074_pins),
+ .functions = ipq8074_functions,
+ .nfunctions = ARRAY_SIZE(ipq8074_functions),
+ .groups = ipq8074_groups,
+ .ngroups = ARRAY_SIZE(ipq8074_groups),
+ .ngpios = 70,
+};
+
+static int ipq8074_pinctrl_probe(struct platform_device *pdev)
+{
+ return msm_pinctrl_probe(pdev, &ipq8074_pinctrl);
+}
+
+static const struct of_device_id ipq8074_pinctrl_of_match[] = {
+ { .compatible = "qcom,ipq8074-pinctrl", },
+ { },
+};
+
+static struct platform_driver ipq8074_pinctrl_driver = {
+ .driver = {
+ .name = "ipq8074-pinctrl",
+ .of_match_table = ipq8074_pinctrl_of_match,
+ },
+ .probe = ipq8074_pinctrl_probe,
+ .remove = msm_pinctrl_remove,
+};
+
+static int __init ipq8074_pinctrl_init(void)
+{
+ return platform_driver_register(&ipq8074_pinctrl_driver);
+}
+arch_initcall(ipq8074_pinctrl_init);
+
+static void __exit ipq8074_pinctrl_exit(void)
+{
+ platform_driver_unregister(&ipq8074_pinctrl_driver);
+}
+module_exit(ipq8074_pinctrl_exit);
+
+MODULE_DESCRIPTION("Qualcomm ipq8074 pinctrl driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, ipq8074_pinctrl_of_match);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
@ 2017-05-04 11:53 ` Varadarajan Narayanan
0 siblings, 0 replies; 49+ messages in thread
From: Varadarajan Narayanan @ 2017-05-04 11:53 UTC (permalink / raw)
To: linux-arm-kernel
Add initial pinctrl driver to support pin configuration with
pinctrl framework for ipq8074.
Signed-off-by: Manoharan Vijaya Raghavan <mraghava@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
---
.../bindings/pinctrl/qcom,ipq8074-pinctrl.txt | 187 +++
drivers/pinctrl/qcom/Kconfig | 10 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-ipq8074.c | 1217 ++++++++++++++++++++
4 files changed, 1415 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq8074.c
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
new file mode 100644
index 0000000..7765bca
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
@@ -0,0 +1,187 @@
+Qualcomm Technologies, Inc. IPQ8074 TLMM block
+
+This binding describes the Top Level Mode Multiplexer block found in the
+IPQ8074 platform.
+
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be "qcom,ipq8074-pinctrl"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: the base address and size of the TLMM register space.
+
+- interrupts:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: should specify the TLMM summary IRQ.
+
+- interrupt-controller:
+ Usage: required
+ Value type: <none>
+ Definition: identifies this node as an interrupt controller
+
+- #interrupt-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: must be 2. Specifying the pin number and flags, as defined
+ in <dt-bindings/interrupt-controller/irq.h>
+
+- gpio-controller:
+ Usage: required
+ Value type: <none>
+ Definition: identifies this node as a gpio controller
+
+- #gpio-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: must be 2. Specifying the pin number and flags, as defined
+ in <dt-bindings/gpio/gpio.h>
+
+Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
+a general description of GPIO and interrupt bindings.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+The pin configuration nodes act as a container for an arbitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, drive strength, etc.
+
+
+PIN CONFIGURATION NODES:
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pin configuration subnode:
+
+- pins:
+ Usage: required
+ Value type: <string-array>
+ Definition: List of gpio pins affected by the properties specified in
+ this subnode. Valid pins are:
+ gpio0-gpio121,
+ sdc1_clk,
+ sdc1_cmd,
+ sdc1_data
+ sdc2_clk,
+ sdc2_cmd,
+ sdc2_data,
+ qdsd_cmd,
+ qdsd_data0,
+ qdsd_data1,
+ qdsd_data2,
+ qdsd_data3
+
+- function:
+ Usage: required
+ Value type: <string>
+ Definition: Specify the alternative function to be configured for the
+ specified pins. Functions are only valid for gpio pins.
+ Valid values are:
+ gpio, qpic_pad, blsp5_i2c, blsp5_spi, wci20, blsp3_spi3,
+ burn0, pcm_zsi0, blsp5_uart, mac12, blsp3_spi0, burn1, mac01,
+ qdss_cti_trig_out_b0, qdss_cti_trig_in_b0, qpic_pad4,
+ blsp4_uart0, blsp4_i2c0, blsp4_spi0, mac21,
+ qdss_cti_trig_out_b1, qpic_pad5, qdss_cti_trig_in_b1,
+ qpic_pad6, qpic_pad7, cxc0, mac13, qdss_cti_trig_in_a1,
+ qdss_cti_trig_out_a1, wci22, qdss_cti_trig_in_a0, qpic_pad1,
+ qdss_cti_trig_out_a0, qpic_pad2, qpic_pad3, qdss_traceclk_b,
+ qpic_pad0, qdss_tracectl_b, qpic_pad8, pcm_zsi1,
+ qdss_tracedata_b, led0, pwm04, led1, pwm14, led2, pwm24,
+ pwm00, blsp4_uart1, blsp4_i2c1, blsp4_spi1, wci23, mac11,
+ blsp3_spi2, pwm10, pwm20, pwm30, audio_txmclk, pwm02,
+ audio_txbclk, pwm12, audio_txfsync, pwm22, audio_txd, pwm32,
+ audio_rxmclk, pwm03, atest_char0, audio_rxbclk, pwm13,
+ atest_char1, audio_rxfsync, pwm23, atest_char2, audio_rxd,
+ pwm33, atest_char3, pcm_drx, mac10, mac00, pcm_dtx, pcm_fsync,
+ mac20, qdss_traceclk_a, pcm_pclk, qdss_tracectl_a, atest_char,
+ qdss_tracedata_a, blsp0_uart, blsp0_i2c, blsp0_spi,
+ blsp1_uart, blsp1_i2c, blsp1_spi, blsp2_uart, blsp2_i2c,
+ blsp2_spi, blsp3_uart, blsp3_i2c, blsp3_spi, pta2_0, wci21,
+ cxc1, blsp3_spi1, pta2_1, pta2_2, pcie0_clk, dbg_out,
+ cri_trng0, pcie0_rst, cri_trng1, pcie0_wake, cri_trng,
+ pcie1_clk, rx2, ldo_update, pcie1_rst, ldo_en, pcie1_wake,
+ gcc_plltest, sd_card, pwm01, pta1_1, pwm11, rx1, pta1_2,
+ gcc_tlmm, pta1_0, pwm21, prng_rosc, sd_write, pwm31, rx0,
+ tsens_max, mdc, mdio, NA
+
+- bias-disable:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configued as no pull.
+
+- bias-pull-down:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configued as pull down.
+
+- bias-pull-up:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configued as pull up.
+
+- output-high:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins are configured in output mode, driven
+ high.
+ Not valid for sdc pins.
+
+- output-low:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins are configured in output mode, driven
+ low.
+ Not valid for sdc pins.
+
+- drive-strength:
+ Usage: optional
+ Value type: <u32>
+ Definition: Selects the drive strength for the specified pins, in mA.
+ Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
+
+Example:
+
+ tlmm: pinctrl at 1000000 {
+ compatible = "qcom,ipq8074-pinctrl";
+ reg = <0x1000000 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ uart2: uart2-default {
+ mux {
+ pins = "gpio23", "gpio24";
+ function = "blsp4_uart1";
+ };
+
+ rx {
+ pins = "gpio23";
+ drive-strength = <4>;
+ bias-disable;
+ };
+
+ tx {
+ pins = "gpio24";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 3ebdc01..9e504db 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -39,6 +39,16 @@ config PINCTRL_IPQ8064
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm IPQ8064 platform.
+config PINCTRL_IPQ8074
+ tristate "Qualcomm Technologies, Inc. IPQ8074 pin controller driver"
+ depends on GPIOLIB && OF
+ select PINCTRL_MSM
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for
+ the Qualcomm Technologies Inc. TLMM block found on the
+ Qualcomm Technologies Inc. IPQ8074 platform. Select this for
+ IPQ8074.
+
config PINCTRL_MSM8660
tristate "Qualcomm 8660 pin controller driver"
depends on GPIOLIB && OF
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index ab47764..06c8b2a 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o
obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
+obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o
obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o
obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o
obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8074.c b/drivers/pinctrl/qcom/pinctrl-ipq8074.c
new file mode 100644
index 0000000..8bb8071
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-ipq8074.c
@@ -0,0 +1,1217 @@
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-msm.h"
+
+#define FUNCTION(fname) \
+ [msm_mux_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define REG_SIZE 0x1000
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins, \
+ .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ msm_mux_gpio, /* gpio mode */ \
+ msm_mux_##f1, \
+ msm_mux_##f2, \
+ msm_mux_##f3, \
+ msm_mux_##f4, \
+ msm_mux_##f5, \
+ msm_mux_##f6, \
+ msm_mux_##f7, \
+ msm_mux_##f8, \
+ msm_mux_##f9 \
+ }, \
+ .nfuncs = 10, \
+ .ctl_reg = REG_SIZE * id, \
+ .io_reg = 0x4 + REG_SIZE * id, \
+ .intr_cfg_reg = 0x8 + REG_SIZE * id, \
+ .intr_status_reg = 0xc + REG_SIZE * id, \
+ .intr_target_reg = 0x8 + REG_SIZE * id, \
+ .mux_bit = 2, \
+ .pull_bit = 0, \
+ .drv_bit = 6, \
+ .oe_bit = 9, \
+ .in_bit = 0, \
+ .out_bit = 1, \
+ .intr_enable_bit = 0, \
+ .intr_status_bit = 0, \
+ .intr_target_bit = 5, \
+ .intr_raw_status_bit = 4, \
+ .intr_polarity_bit = 1, \
+ .intr_detection_bit = 2, \
+ .intr_detection_width = 2, \
+ }
+
+static const struct pinctrl_pin_desc ipq8074_pins[] = {
+ PINCTRL_PIN(0, "GPIO_0"),
+ PINCTRL_PIN(1, "GPIO_1"),
+ PINCTRL_PIN(2, "GPIO_2"),
+ PINCTRL_PIN(3, "GPIO_3"),
+ PINCTRL_PIN(4, "GPIO_4"),
+ PINCTRL_PIN(5, "GPIO_5"),
+ PINCTRL_PIN(6, "GPIO_6"),
+ PINCTRL_PIN(7, "GPIO_7"),
+ PINCTRL_PIN(8, "GPIO_8"),
+ PINCTRL_PIN(9, "GPIO_9"),
+ PINCTRL_PIN(10, "GPIO_10"),
+ PINCTRL_PIN(11, "GPIO_11"),
+ PINCTRL_PIN(12, "GPIO_12"),
+ PINCTRL_PIN(13, "GPIO_13"),
+ PINCTRL_PIN(14, "GPIO_14"),
+ PINCTRL_PIN(15, "GPIO_15"),
+ PINCTRL_PIN(16, "GPIO_16"),
+ PINCTRL_PIN(17, "GPIO_17"),
+ PINCTRL_PIN(18, "GPIO_18"),
+ PINCTRL_PIN(19, "GPIO_19"),
+ PINCTRL_PIN(20, "GPIO_20"),
+ PINCTRL_PIN(21, "GPIO_21"),
+ PINCTRL_PIN(22, "GPIO_22"),
+ PINCTRL_PIN(23, "GPIO_23"),
+ PINCTRL_PIN(24, "GPIO_24"),
+ PINCTRL_PIN(25, "GPIO_25"),
+ PINCTRL_PIN(26, "GPIO_26"),
+ PINCTRL_PIN(27, "GPIO_27"),
+ PINCTRL_PIN(28, "GPIO_28"),
+ PINCTRL_PIN(29, "GPIO_29"),
+ PINCTRL_PIN(30, "GPIO_30"),
+ PINCTRL_PIN(31, "GPIO_31"),
+ PINCTRL_PIN(32, "GPIO_32"),
+ PINCTRL_PIN(33, "GPIO_33"),
+ PINCTRL_PIN(34, "GPIO_34"),
+ PINCTRL_PIN(35, "GPIO_35"),
+ PINCTRL_PIN(36, "GPIO_36"),
+ PINCTRL_PIN(37, "GPIO_37"),
+ PINCTRL_PIN(38, "GPIO_38"),
+ PINCTRL_PIN(39, "GPIO_39"),
+ PINCTRL_PIN(40, "GPIO_40"),
+ PINCTRL_PIN(41, "GPIO_41"),
+ PINCTRL_PIN(42, "GPIO_42"),
+ PINCTRL_PIN(43, "GPIO_43"),
+ PINCTRL_PIN(44, "GPIO_44"),
+ PINCTRL_PIN(45, "GPIO_45"),
+ PINCTRL_PIN(46, "GPIO_46"),
+ PINCTRL_PIN(47, "GPIO_47"),
+ PINCTRL_PIN(48, "GPIO_48"),
+ PINCTRL_PIN(49, "GPIO_49"),
+ PINCTRL_PIN(50, "GPIO_50"),
+ PINCTRL_PIN(51, "GPIO_51"),
+ PINCTRL_PIN(52, "GPIO_52"),
+ PINCTRL_PIN(53, "GPIO_53"),
+ PINCTRL_PIN(54, "GPIO_54"),
+ PINCTRL_PIN(55, "GPIO_55"),
+ PINCTRL_PIN(56, "GPIO_56"),
+ PINCTRL_PIN(57, "GPIO_57"),
+ PINCTRL_PIN(58, "GPIO_58"),
+ PINCTRL_PIN(59, "GPIO_59"),
+ PINCTRL_PIN(60, "GPIO_60"),
+ PINCTRL_PIN(61, "GPIO_61"),
+ PINCTRL_PIN(62, "GPIO_62"),
+ PINCTRL_PIN(63, "GPIO_63"),
+ PINCTRL_PIN(64, "GPIO_64"),
+ PINCTRL_PIN(65, "GPIO_65"),
+ PINCTRL_PIN(66, "GPIO_66"),
+ PINCTRL_PIN(67, "GPIO_67"),
+ PINCTRL_PIN(68, "GPIO_68"),
+ PINCTRL_PIN(69, "GPIO_69"),
+};
+
+#define DECLARE_MSM_GPIO_PINS(pin) \
+ static const unsigned int gpio##pin##_pins[] = { pin }
+DECLARE_MSM_GPIO_PINS(0);
+DECLARE_MSM_GPIO_PINS(1);
+DECLARE_MSM_GPIO_PINS(2);
+DECLARE_MSM_GPIO_PINS(3);
+DECLARE_MSM_GPIO_PINS(4);
+DECLARE_MSM_GPIO_PINS(5);
+DECLARE_MSM_GPIO_PINS(6);
+DECLARE_MSM_GPIO_PINS(7);
+DECLARE_MSM_GPIO_PINS(8);
+DECLARE_MSM_GPIO_PINS(9);
+DECLARE_MSM_GPIO_PINS(10);
+DECLARE_MSM_GPIO_PINS(11);
+DECLARE_MSM_GPIO_PINS(12);
+DECLARE_MSM_GPIO_PINS(13);
+DECLARE_MSM_GPIO_PINS(14);
+DECLARE_MSM_GPIO_PINS(15);
+DECLARE_MSM_GPIO_PINS(16);
+DECLARE_MSM_GPIO_PINS(17);
+DECLARE_MSM_GPIO_PINS(18);
+DECLARE_MSM_GPIO_PINS(19);
+DECLARE_MSM_GPIO_PINS(20);
+DECLARE_MSM_GPIO_PINS(21);
+DECLARE_MSM_GPIO_PINS(22);
+DECLARE_MSM_GPIO_PINS(23);
+DECLARE_MSM_GPIO_PINS(24);
+DECLARE_MSM_GPIO_PINS(25);
+DECLARE_MSM_GPIO_PINS(26);
+DECLARE_MSM_GPIO_PINS(27);
+DECLARE_MSM_GPIO_PINS(28);
+DECLARE_MSM_GPIO_PINS(29);
+DECLARE_MSM_GPIO_PINS(30);
+DECLARE_MSM_GPIO_PINS(31);
+DECLARE_MSM_GPIO_PINS(32);
+DECLARE_MSM_GPIO_PINS(33);
+DECLARE_MSM_GPIO_PINS(34);
+DECLARE_MSM_GPIO_PINS(35);
+DECLARE_MSM_GPIO_PINS(36);
+DECLARE_MSM_GPIO_PINS(37);
+DECLARE_MSM_GPIO_PINS(38);
+DECLARE_MSM_GPIO_PINS(39);
+DECLARE_MSM_GPIO_PINS(40);
+DECLARE_MSM_GPIO_PINS(41);
+DECLARE_MSM_GPIO_PINS(42);
+DECLARE_MSM_GPIO_PINS(43);
+DECLARE_MSM_GPIO_PINS(44);
+DECLARE_MSM_GPIO_PINS(45);
+DECLARE_MSM_GPIO_PINS(46);
+DECLARE_MSM_GPIO_PINS(47);
+DECLARE_MSM_GPIO_PINS(48);
+DECLARE_MSM_GPIO_PINS(49);
+DECLARE_MSM_GPIO_PINS(50);
+DECLARE_MSM_GPIO_PINS(51);
+DECLARE_MSM_GPIO_PINS(52);
+DECLARE_MSM_GPIO_PINS(53);
+DECLARE_MSM_GPIO_PINS(54);
+DECLARE_MSM_GPIO_PINS(55);
+DECLARE_MSM_GPIO_PINS(56);
+DECLARE_MSM_GPIO_PINS(57);
+DECLARE_MSM_GPIO_PINS(58);
+DECLARE_MSM_GPIO_PINS(59);
+DECLARE_MSM_GPIO_PINS(60);
+DECLARE_MSM_GPIO_PINS(61);
+DECLARE_MSM_GPIO_PINS(62);
+DECLARE_MSM_GPIO_PINS(63);
+DECLARE_MSM_GPIO_PINS(64);
+DECLARE_MSM_GPIO_PINS(65);
+DECLARE_MSM_GPIO_PINS(66);
+DECLARE_MSM_GPIO_PINS(67);
+DECLARE_MSM_GPIO_PINS(68);
+DECLARE_MSM_GPIO_PINS(69);
+
+enum ipq8074_functions {
+ msm_mux_gpio,
+ msm_mux_qpic_pad,
+ msm_mux_blsp5_i2c,
+ msm_mux_blsp5_spi,
+ msm_mux_wci20,
+ msm_mux_blsp3_spi3,
+ msm_mux_burn0,
+ msm_mux_pcm_zsi0,
+ msm_mux_blsp5_uart,
+ msm_mux_mac12,
+ msm_mux_blsp3_spi0,
+ msm_mux_burn1,
+ msm_mux_mac01,
+ msm_mux_qdss_cti_trig_out_b0,
+ msm_mux_qdss_cti_trig_in_b0,
+ msm_mux_qpic_pad4,
+ msm_mux_blsp4_uart0,
+ msm_mux_blsp4_i2c0,
+ msm_mux_blsp4_spi0,
+ msm_mux_mac21,
+ msm_mux_qdss_cti_trig_out_b1,
+ msm_mux_qpic_pad5,
+ msm_mux_qdss_cti_trig_in_b1,
+ msm_mux_qpic_pad6,
+ msm_mux_qpic_pad7,
+ msm_mux_cxc0,
+ msm_mux_mac13,
+ msm_mux_qdss_cti_trig_in_a1,
+ msm_mux_qdss_cti_trig_out_a1,
+ msm_mux_wci22,
+ msm_mux_qdss_cti_trig_in_a0,
+ msm_mux_qpic_pad1,
+ msm_mux_qdss_cti_trig_out_a0,
+ msm_mux_qpic_pad2,
+ msm_mux_qpic_pad3,
+ msm_mux_qdss_traceclk_b,
+ msm_mux_qpic_pad0,
+ msm_mux_qdss_tracectl_b,
+ msm_mux_qpic_pad8,
+ msm_mux_pcm_zsi1,
+ msm_mux_qdss_tracedata_b,
+ msm_mux_led0,
+ msm_mux_pwm04,
+ msm_mux_led1,
+ msm_mux_pwm14,
+ msm_mux_led2,
+ msm_mux_pwm24,
+ msm_mux_pwm00,
+ msm_mux_blsp4_uart1,
+ msm_mux_blsp4_i2c1,
+ msm_mux_blsp4_spi1,
+ msm_mux_wci23,
+ msm_mux_mac11,
+ msm_mux_blsp3_spi2,
+ msm_mux_pwm10,
+ msm_mux_pwm20,
+ msm_mux_pwm30,
+ msm_mux_audio_txmclk,
+ msm_mux_pwm02,
+ msm_mux_audio_txbclk,
+ msm_mux_pwm12,
+ msm_mux_audio_txfsync,
+ msm_mux_pwm22,
+ msm_mux_audio_txd,
+ msm_mux_pwm32,
+ msm_mux_audio_rxmclk,
+ msm_mux_pwm03,
+ msm_mux_atest_char0,
+ msm_mux_audio_rxbclk,
+ msm_mux_pwm13,
+ msm_mux_atest_char1,
+ msm_mux_audio_rxfsync,
+ msm_mux_pwm23,
+ msm_mux_atest_char2,
+ msm_mux_audio_rxd,
+ msm_mux_pwm33,
+ msm_mux_atest_char3,
+ msm_mux_pcm_drx,
+ msm_mux_mac10,
+ msm_mux_mac00,
+ msm_mux_pcm_dtx,
+ msm_mux_pcm_fsync,
+ msm_mux_mac20,
+ msm_mux_qdss_traceclk_a,
+ msm_mux_pcm_pclk,
+ msm_mux_qdss_tracectl_a,
+ msm_mux_atest_char,
+ msm_mux_qdss_tracedata_a,
+ msm_mux_blsp0_uart,
+ msm_mux_blsp0_i2c,
+ msm_mux_blsp0_spi,
+ msm_mux_blsp1_uart,
+ msm_mux_blsp1_i2c,
+ msm_mux_blsp1_spi,
+ msm_mux_blsp2_uart,
+ msm_mux_blsp2_i2c,
+ msm_mux_blsp2_spi,
+ msm_mux_blsp3_uart,
+ msm_mux_blsp3_i2c,
+ msm_mux_blsp3_spi,
+ msm_mux_pta2_0,
+ msm_mux_wci21,
+ msm_mux_cxc1,
+ msm_mux_blsp3_spi1,
+ msm_mux_pta2_1,
+ msm_mux_pta2_2,
+ msm_mux_pcie0_clk,
+ msm_mux_dbg_out,
+ msm_mux_cri_trng0,
+ msm_mux_pcie0_rst,
+ msm_mux_cri_trng1,
+ msm_mux_pcie0_wake,
+ msm_mux_cri_trng,
+ msm_mux_pcie1_clk,
+ msm_mux_rx2,
+ msm_mux_ldo_update,
+ msm_mux_pcie1_rst,
+ msm_mux_ldo_en,
+ msm_mux_pcie1_wake,
+ msm_mux_gcc_plltest,
+ msm_mux_sd_card,
+ msm_mux_pwm01,
+ msm_mux_pta1_1,
+ msm_mux_pwm11,
+ msm_mux_rx1,
+ msm_mux_pta1_2,
+ msm_mux_gcc_tlmm,
+ msm_mux_pta1_0,
+ msm_mux_pwm21,
+ msm_mux_prng_rosc,
+ msm_mux_sd_write,
+ msm_mux_pwm31,
+ msm_mux_rx0,
+ msm_mux_tsens_max,
+ msm_mux_mdc,
+ msm_mux_mdio,
+ msm_mux_NA,
+};
+
+static const char * const qpic_pad_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio9", "gpio10",
+ "gpio11", "gpio17",
+};
+
+static const char * const _groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
+ "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
+ "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
+ "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69",
+};
+
+static const char * const blsp5_i2c_groups[] = {
+ "gpio0", "gpio2",
+};
+
+static const char * const blsp5_spi_groups[] = {
+ "gpio0", "gpio2", "gpio9", "gpio16",
+};
+
+static const char * const wci20_groups[] = {
+ "gpio0", "gpio2",
+};
+
+static const char * const blsp3_spi3_groups[] = {
+ "gpio0", "gpio2", "gpio9",
+};
+
+static const char * const burn0_groups[] = {
+ "gpio0",
+};
+
+static const char * const pcm_zsi0_groups[] = {
+ "gpio1",
+};
+
+static const char * const blsp5_uart_groups[] = {
+ "gpio0", "gpio2", "gpio9", "gpio16",
+};
+
+static const char * const mac12_groups[] = {
+ "gpio1", "gpio11",
+};
+
+static const char * const blsp3_spi0_groups[] = {
+ "gpio1", "gpio3", "gpio4",
+};
+
+static const char * const burn1_groups[] = {
+ "gpio1",
+};
+
+static const char * const mac01_groups[] = {
+ "gpio3", "gpio4",
+};
+
+static const char * const qdss_cti_trig_out_b0_groups[] = {
+ "gpio3",
+};
+
+static const char * const qdss_cti_trig_in_b0_groups[] = {
+ "gpio4",
+};
+
+static const char * const qpic_pad4_groups[] = {
+ "gpio5",
+};
+
+static const char * const blsp4_uart0_groups[] = {
+ "gpio5", "gpio6", "gpio7", "gpio8",
+};
+
+static const char * const blsp4_i2c0_groups[] = {
+ "gpio5", "gpio6",
+};
+
+static const char * const blsp4_spi0_groups[] = {
+ "gpio5", "gpio6", "gpio7", "gpio8",
+};
+
+static const char * const mac21_groups[] = {
+ "gpio5", "gpio6",
+};
+
+static const char * const qdss_cti_trig_out_b1_groups[] = {
+ "gpio5",
+};
+
+static const char * const qpic_pad5_groups[] = {
+ "gpio6",
+};
+
+static const char * const qdss_cti_trig_in_b1_groups[] = {
+ "gpio6",
+};
+
+static const char * const qpic_pad6_groups[] = {
+ "gpio7",
+};
+
+static const char * const qpic_pad7_groups[] = {
+ "gpio8",
+};
+
+static const char * const cxc0_groups[] = {
+ "gpio9", "gpio16",
+};
+
+static const char * const mac13_groups[] = {
+ "gpio9", "gpio16",
+};
+
+static const char * const qdss_cti_trig_in_a1_groups[] = {
+ "gpio9",
+};
+
+static const char * const qdss_cti_trig_out_a1_groups[] = {
+ "gpio10",
+};
+
+static const char * const wci22_groups[] = {
+ "gpio11", "gpio17",
+};
+
+static const char * const qdss_cti_trig_in_a0_groups[] = {
+ "gpio11",
+};
+
+static const char * const qpic_pad1_groups[] = {
+ "gpio12",
+};
+
+static const char * const qdss_cti_trig_out_a0_groups[] = {
+ "gpio12",
+};
+
+static const char * const qpic_pad2_groups[] = {
+ "gpio13",
+};
+
+static const char * const qpic_pad3_groups[] = {
+ "gpio14",
+};
+
+static const char * const qdss_traceclk_b_groups[] = {
+ "gpio14",
+};
+
+static const char * const qpic_pad0_groups[] = {
+ "gpio15",
+};
+
+static const char * const qdss_tracectl_b_groups[] = {
+ "gpio15",
+};
+
+static const char * const qpic_pad8_groups[] = {
+ "gpio16",
+};
+
+static const char * const pcm_zsi1_groups[] = {
+ "gpio16",
+};
+
+static const char * const qdss_tracedata_b_groups[] = {
+ "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
+ "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
+ "gpio30", "gpio31",
+};
+
+static const char * const led0_groups[] = {
+ "gpio18",
+};
+
+static const char * const pwm04_groups[] = {
+ "gpio18",
+};
+
+static const char * const led1_groups[] = {
+ "gpio19",
+};
+
+static const char * const pwm14_groups[] = {
+ "gpio19",
+};
+
+static const char * const led2_groups[] = {
+ "gpio20",
+};
+
+static const char * const pwm24_groups[] = {
+ "gpio20",
+};
+
+static const char * const pwm00_groups[] = {
+ "gpio21",
+};
+
+static const char * const blsp4_uart1_groups[] = {
+ "gpio21", "gpio22", "gpio23", "gpio24",
+};
+
+static const char * const blsp4_i2c1_groups[] = {
+ "gpio21", "gpio22",
+};
+
+static const char * const blsp4_spi1_groups[] = {
+ "gpio21", "gpio22", "gpio23", "gpio24",
+};
+
+static const char * const wci23_groups[] = {
+ "gpio21", "gpio22",
+};
+
+static const char * const mac11_groups[] = {
+ "gpio21", "gpio22",
+};
+
+static const char * const blsp3_spi2_groups[] = {
+ "gpio21", "gpio22", "gpio23",
+};
+
+static const char * const pwm10_groups[] = {
+ "gpio22",
+};
+
+static const char * const pwm20_groups[] = {
+ "gpio23",
+};
+
+static const char * const pwm30_groups[] = {
+ "gpio24",
+};
+
+static const char * const audio_txmclk_groups[] = {
+ "gpio25",
+};
+
+static const char * const pwm02_groups[] = {
+ "gpio25",
+};
+
+static const char * const audio_txbclk_groups[] = {
+ "gpio26",
+};
+
+static const char * const pwm12_groups[] = {
+ "gpio26",
+};
+
+static const char * const audio_txfsync_groups[] = {
+ "gpio27",
+};
+
+static const char * const pwm22_groups[] = {
+ "gpio27",
+};
+
+static const char * const audio_txd_groups[] = {
+ "gpio28",
+};
+
+static const char * const pwm32_groups[] = {
+ "gpio28",
+};
+
+static const char * const audio_rxmclk_groups[] = {
+ "gpio29",
+};
+
+static const char * const pwm03_groups[] = {
+ "gpio29",
+};
+
+static const char * const atest_char0_groups[] = {
+ "gpio29",
+};
+
+static const char * const audio_rxbclk_groups[] = {
+ "gpio30",
+};
+
+static const char * const pwm13_groups[] = {
+ "gpio30",
+};
+
+static const char * const atest_char1_groups[] = {
+ "gpio30",
+};
+
+static const char * const audio_rxfsync_groups[] = {
+ "gpio31",
+};
+
+static const char * const pwm23_groups[] = {
+ "gpio31",
+};
+
+static const char * const atest_char2_groups[] = {
+ "gpio31",
+};
+
+static const char * const audio_rxd_groups[] = {
+ "gpio32",
+};
+
+static const char * const pwm33_groups[] = {
+ "gpio32",
+};
+
+static const char * const atest_char3_groups[] = {
+ "gpio32",
+};
+
+static const char * const pcm_drx_groups[] = {
+ "gpio33",
+};
+
+static const char * const mac10_groups[] = {
+ "gpio33", "gpio34",
+};
+
+static const char * const mac00_groups[] = {
+ "gpio33", "gpio34",
+};
+
+static const char * const pcm_dtx_groups[] = {
+ "gpio34",
+};
+
+static const char * const pcm_fsync_groups[] = {
+ "gpio35",
+};
+
+static const char * const mac20_groups[] = {
+ "gpio35", "gpio36",
+};
+
+static const char * const qdss_traceclk_a_groups[] = {
+ "gpio35",
+};
+
+static const char * const pcm_pclk_groups[] = {
+ "gpio36",
+};
+
+static const char * const qdss_tracectl_a_groups[] = {
+ "gpio36",
+};
+
+static const char * const atest_char_groups[] = {
+ "gpio37",
+};
+
+static const char * const qdss_tracedata_a_groups[] = {
+ "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
+ "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", "gpio50",
+ "gpio51", "gpio52",
+};
+
+static const char * const blsp0_uart_groups[] = {
+ "gpio38", "gpio39", "gpio40", "gpio41",
+};
+
+static const char * const blsp0_i2c_groups[] = {
+ "gpio38", "gpio39",
+};
+
+static const char * const blsp0_spi_groups[] = {
+ "gpio38", "gpio39", "gpio40", "gpio41",
+};
+
+static const char * const blsp1_uart_groups[] = {
+ "gpio42", "gpio43", "gpio44", "gpio45",
+};
+
+static const char * const blsp1_i2c_groups[] = {
+ "gpio42", "gpio43",
+};
+
+static const char * const blsp1_spi_groups[] = {
+ "gpio42", "gpio43", "gpio44", "gpio45",
+};
+
+static const char * const blsp2_uart_groups[] = {
+ "gpio46", "gpio47", "gpio48", "gpio49",
+};
+
+static const char * const blsp2_i2c_groups[] = {
+ "gpio46", "gpio47",
+};
+
+static const char * const blsp2_spi_groups[] = {
+ "gpio46", "gpio47", "gpio48", "gpio49",
+};
+
+static const char * const blsp3_uart_groups[] = {
+ "gpio50", "gpio51", "gpio52", "gpio53",
+};
+
+static const char * const blsp3_i2c_groups[] = {
+ "gpio50", "gpio51",
+};
+
+static const char * const blsp3_spi_groups[] = {
+ "gpio50", "gpio51", "gpio52", "gpio53",
+};
+
+static const char * const pta2_0_groups[] = {
+ "gpio54",
+};
+
+static const char * const wci21_groups[] = {
+ "gpio54", "gpio56",
+};
+
+static const char * const cxc1_groups[] = {
+ "gpio54", "gpio56",
+};
+
+static const char * const blsp3_spi1_groups[] = {
+ "gpio54", "gpio55", "gpio56",
+};
+
+static const char * const pta2_1_groups[] = {
+ "gpio55",
+};
+
+static const char * const pta2_2_groups[] = {
+ "gpio56",
+};
+
+static const char * const pcie0_clk_groups[] = {
+ "gpio57",
+};
+
+static const char * const dbg_out_groups[] = {
+ "gpio57",
+};
+
+static const char * const cri_trng0_groups[] = {
+ "gpio57",
+};
+
+static const char * const pcie0_rst_groups[] = {
+ "gpio58",
+};
+
+static const char * const cri_trng1_groups[] = {
+ "gpio58",
+};
+
+static const char * const pcie0_wake_groups[] = {
+ "gpio59",
+};
+
+static const char * const cri_trng_groups[] = {
+ "gpio59",
+};
+
+static const char * const pcie1_clk_groups[] = {
+ "gpio60",
+};
+
+static const char * const rx2_groups[] = {
+ "gpio60",
+};
+
+static const char * const ldo_update_groups[] = {
+ "gpio60",
+};
+
+static const char * const pcie1_rst_groups[] = {
+ "gpio61",
+};
+
+static const char * const ldo_en_groups[] = {
+ "gpio61",
+};
+
+static const char * const pcie1_wake_groups[] = {
+ "gpio62",
+};
+
+static const char * const gcc_plltest_groups[] = {
+ "gpio62", "gpio63",
+};
+
+static const char * const sd_card_groups[] = {
+ "gpio63",
+};
+
+static const char * const pwm01_groups[] = {
+ "gpio63",
+};
+
+static const char * const pta1_1_groups[] = {
+ "gpio64",
+};
+
+static const char * const pwm11_groups[] = {
+ "gpio64",
+};
+
+static const char * const rx1_groups[] = {
+ "gpio64",
+};
+
+static const char * const pta1_2_groups[] = {
+ "gpio65",
+};
+
+static const char * const gcc_tlmm_groups[] = {
+ "gpio65",
+};
+
+static const char * const pta1_0_groups[] = {
+ "gpio66",
+};
+
+static const char * const pwm21_groups[] = {
+ "gpio66",
+};
+
+static const char * const prng_rosc_groups[] = {
+ "gpio66",
+};
+
+static const char * const sd_write_groups[] = {
+ "gpio67",
+};
+
+static const char * const pwm31_groups[] = {
+ "gpio67",
+};
+
+static const char * const rx0_groups[] = {
+ "gpio67",
+};
+
+static const char * const tsens_max_groups[] = {
+ "gpio67",
+};
+
+static const char * const mdc_groups[] = {
+ "gpio68",
+};
+
+static const char * const mdio_groups[] = {
+ "gpio69",
+};
+
+static const char * const gpio_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
+ "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
+ "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
+ "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69",
+};
+
+static const struct msm_function ipq8074_functions[] = {
+ FUNCTION(gpio),
+ FUNCTION(qpic_pad),
+ FUNCTION(blsp5_i2c),
+ FUNCTION(blsp5_spi),
+ FUNCTION(wci20),
+ FUNCTION(blsp3_spi3),
+ FUNCTION(burn0),
+ FUNCTION(pcm_zsi0),
+ FUNCTION(blsp5_uart),
+ FUNCTION(mac12),
+ FUNCTION(blsp3_spi0),
+ FUNCTION(burn1),
+ FUNCTION(mac01),
+ FUNCTION(qdss_cti_trig_out_b0),
+ FUNCTION(qdss_cti_trig_in_b0),
+ FUNCTION(qpic_pad4),
+ FUNCTION(blsp4_uart0),
+ FUNCTION(blsp4_i2c0),
+ FUNCTION(blsp4_spi0),
+ FUNCTION(mac21),
+ FUNCTION(qdss_cti_trig_out_b1),
+ FUNCTION(qpic_pad5),
+ FUNCTION(qdss_cti_trig_in_b1),
+ FUNCTION(qpic_pad6),
+ FUNCTION(qpic_pad7),
+ FUNCTION(cxc0),
+ FUNCTION(mac13),
+ FUNCTION(qdss_cti_trig_in_a1),
+ FUNCTION(qdss_cti_trig_out_a1),
+ FUNCTION(wci22),
+ FUNCTION(qdss_cti_trig_in_a0),
+ FUNCTION(qpic_pad1),
+ FUNCTION(qdss_cti_trig_out_a0),
+ FUNCTION(qpic_pad2),
+ FUNCTION(qpic_pad3),
+ FUNCTION(qdss_traceclk_b),
+ FUNCTION(qpic_pad0),
+ FUNCTION(qdss_tracectl_b),
+ FUNCTION(qpic_pad8),
+ FUNCTION(pcm_zsi1),
+ FUNCTION(qdss_tracedata_b),
+ FUNCTION(led0),
+ FUNCTION(pwm04),
+ FUNCTION(led1),
+ FUNCTION(pwm14),
+ FUNCTION(led2),
+ FUNCTION(pwm24),
+ FUNCTION(pwm00),
+ FUNCTION(blsp4_uart1),
+ FUNCTION(blsp4_i2c1),
+ FUNCTION(blsp4_spi1),
+ FUNCTION(wci23),
+ FUNCTION(mac11),
+ FUNCTION(blsp3_spi2),
+ FUNCTION(pwm10),
+ FUNCTION(pwm20),
+ FUNCTION(pwm30),
+ FUNCTION(audio_txmclk),
+ FUNCTION(pwm02),
+ FUNCTION(audio_txbclk),
+ FUNCTION(pwm12),
+ FUNCTION(audio_txfsync),
+ FUNCTION(pwm22),
+ FUNCTION(audio_txd),
+ FUNCTION(pwm32),
+ FUNCTION(audio_rxmclk),
+ FUNCTION(pwm03),
+ FUNCTION(atest_char0),
+ FUNCTION(audio_rxbclk),
+ FUNCTION(pwm13),
+ FUNCTION(atest_char1),
+ FUNCTION(audio_rxfsync),
+ FUNCTION(pwm23),
+ FUNCTION(atest_char2),
+ FUNCTION(audio_rxd),
+ FUNCTION(pwm33),
+ FUNCTION(atest_char3),
+ FUNCTION(pcm_drx),
+ FUNCTION(mac10),
+ FUNCTION(mac00),
+ FUNCTION(pcm_dtx),
+ FUNCTION(pcm_fsync),
+ FUNCTION(mac20),
+ FUNCTION(qdss_traceclk_a),
+ FUNCTION(pcm_pclk),
+ FUNCTION(qdss_tracectl_a),
+ FUNCTION(atest_char),
+ FUNCTION(qdss_tracedata_a),
+ FUNCTION(blsp0_uart),
+ FUNCTION(blsp0_i2c),
+ FUNCTION(blsp0_spi),
+ FUNCTION(blsp1_uart),
+ FUNCTION(blsp1_i2c),
+ FUNCTION(blsp1_spi),
+ FUNCTION(blsp2_uart),
+ FUNCTION(blsp2_i2c),
+ FUNCTION(blsp2_spi),
+ FUNCTION(blsp3_uart),
+ FUNCTION(blsp3_i2c),
+ FUNCTION(blsp3_spi),
+ FUNCTION(pta2_0),
+ FUNCTION(wci21),
+ FUNCTION(cxc1),
+ FUNCTION(blsp3_spi1),
+ FUNCTION(pta2_1),
+ FUNCTION(pta2_2),
+ FUNCTION(pcie0_clk),
+ FUNCTION(dbg_out),
+ FUNCTION(cri_trng0),
+ FUNCTION(pcie0_rst),
+ FUNCTION(cri_trng1),
+ FUNCTION(pcie0_wake),
+ FUNCTION(cri_trng),
+ FUNCTION(pcie1_clk),
+ FUNCTION(rx2),
+ FUNCTION(ldo_update),
+ FUNCTION(pcie1_rst),
+ FUNCTION(ldo_en),
+ FUNCTION(pcie1_wake),
+ FUNCTION(gcc_plltest),
+ FUNCTION(sd_card),
+ FUNCTION(pwm01),
+ FUNCTION(pta1_1),
+ FUNCTION(pwm11),
+ FUNCTION(rx1),
+ FUNCTION(pta1_2),
+ FUNCTION(gcc_tlmm),
+ FUNCTION(pta1_0),
+ FUNCTION(pwm21),
+ FUNCTION(prng_rosc),
+ FUNCTION(sd_write),
+ FUNCTION(pwm31),
+ FUNCTION(rx0),
+ FUNCTION(tsens_max),
+ FUNCTION(mdc),
+ FUNCTION(mdio),
+};
+
+static const struct msm_pingroup ipq8074_groups[] = {
+ PINGROUP(0, qpic_pad, blsp5_uart, blsp5_i2c, blsp5_spi, wci20,
+ blsp3_spi3, NA, burn0, NA),
+ PINGROUP(1, qpic_pad, pcm_zsi0, mac12, blsp3_spi0, NA, burn1, NA, NA,
+ NA),
+ PINGROUP(2, qpic_pad, blsp5_uart, blsp5_i2c, blsp5_spi, wci20,
+ blsp3_spi3, NA, NA, NA),
+ PINGROUP(3, qpic_pad, mac01, blsp3_spi0, qdss_cti_trig_out_b0, NA, NA,
+ NA, NA, NA),
+ PINGROUP(4, qpic_pad, mac01, blsp3_spi0, qdss_cti_trig_in_b0, NA, NA,
+ NA, NA, NA),
+ PINGROUP(5, qpic_pad4, blsp4_uart0, blsp4_i2c0, blsp4_spi0, mac21,
+ qdss_cti_trig_out_b1, NA, NA, NA),
+ PINGROUP(6, qpic_pad5, blsp4_uart0, blsp4_i2c0, blsp4_spi0, mac21,
+ qdss_cti_trig_in_b1, NA, NA, NA),
+ PINGROUP(7, qpic_pad6, blsp4_uart0, blsp4_spi0, NA, NA, NA, NA, NA, NA),
+ PINGROUP(8, qpic_pad7, blsp4_uart0, blsp4_spi0, NA, NA, NA, NA, NA, NA),
+ PINGROUP(9, qpic_pad, blsp5_uart, blsp5_spi, cxc0, mac13, blsp3_spi3,
+ qdss_cti_trig_in_a1, NA, NA),
+ PINGROUP(10, qpic_pad, qdss_cti_trig_out_a1, NA, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(11, qpic_pad, wci22, mac12, qdss_cti_trig_in_a0, NA, NA, NA,
+ NA, NA),
+ PINGROUP(12, qpic_pad1, qdss_cti_trig_out_a0, NA, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(13, qpic_pad2, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(14, qpic_pad3, qdss_traceclk_b, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(15, qpic_pad0, qdss_tracectl_b, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(16, qpic_pad8, blsp5_uart, pcm_zsi1, blsp5_spi, cxc0, mac13,
+ qdss_tracedata_b, NA, NA),
+ PINGROUP(17, qpic_pad, wci22, qdss_tracedata_b, NA, NA, NA, NA, NA, NA),
+ PINGROUP(18, led0, pwm04, qdss_tracedata_b, NA, NA, NA, NA, NA, NA),
+ PINGROUP(19, led1, pwm14, NA, qdss_tracedata_b, NA, NA, NA, NA, NA),
+ PINGROUP(20, led2, pwm24, NA, qdss_tracedata_b, NA, NA, NA, NA, NA),
+ PINGROUP(21, pwm00, blsp4_uart1, blsp4_i2c1, blsp4_spi1, wci23, mac11,
+ blsp3_spi2, NA, qdss_tracedata_b),
+ PINGROUP(22, pwm10, blsp4_uart1, blsp4_i2c1, blsp4_spi1, wci23, mac11,
+ blsp3_spi2, NA, qdss_tracedata_b),
+ PINGROUP(23, pwm20, blsp4_uart1, blsp4_spi1, blsp3_spi2, NA,
+ qdss_tracedata_b, NA, NA, NA),
+ PINGROUP(24, pwm30, blsp4_uart1, blsp4_spi1, NA, qdss_tracedata_b, NA,
+ NA, NA, NA),
+ PINGROUP(25, audio_txmclk, pwm02, NA, qdss_tracedata_b, NA, NA, NA, NA,
+ NA),
+ PINGROUP(26, audio_txbclk, pwm12, NA, qdss_tracedata_b, NA, NA, NA, NA,
+ NA),
+ PINGROUP(27, audio_txfsync, pwm22, NA, qdss_tracedata_b, NA, NA, NA,
+ NA, NA),
+ PINGROUP(28, audio_txd, pwm32, NA, qdss_tracedata_b, NA, NA, NA, NA,
+ NA),
+ PINGROUP(29, audio_rxmclk, pwm03, atest_char0, NA, qdss_tracedata_b,
+ NA, NA, NA, NA),
+ PINGROUP(30, audio_rxbclk, pwm13, atest_char1, NA, qdss_tracedata_b,
+ NA, NA, NA, NA),
+ PINGROUP(31, audio_rxfsync, pwm23, atest_char2, NA, qdss_tracedata_b,
+ NA, NA, NA, NA),
+ PINGROUP(32, audio_rxd, pwm33, atest_char3, NA, NA, NA, NA, NA, NA),
+ PINGROUP(33, pcm_drx, mac10, mac00, NA, NA, NA, NA, NA, NA),
+ PINGROUP(34, pcm_dtx, mac10, mac00, NA, NA, NA, NA, NA, NA),
+ PINGROUP(35, pcm_fsync, mac20, qdss_traceclk_a, NA, NA, NA, NA, NA, NA),
+ PINGROUP(36, pcm_pclk, mac20, NA, qdss_tracectl_a, NA, NA, NA, NA, NA),
+ PINGROUP(37, atest_char, NA, qdss_tracedata_a, NA, NA, NA, NA, NA, NA),
+ PINGROUP(38, blsp0_uart, blsp0_i2c, blsp0_spi, NA, qdss_tracedata_a,
+ NA, NA, NA, NA),
+ PINGROUP(39, blsp0_uart, blsp0_i2c, blsp0_spi, NA, qdss_tracedata_a,
+ NA, NA, NA, NA),
+ PINGROUP(40, blsp0_uart, blsp0_spi, NA, qdss_tracedata_a, NA, NA, NA,
+ NA, NA),
+ PINGROUP(41, blsp0_uart, blsp0_spi, NA, qdss_tracedata_a, NA, NA, NA,
+ NA, NA),
+ PINGROUP(42, blsp1_uart, blsp1_i2c, blsp1_spi, NA, qdss_tracedata_a,
+ NA, NA, NA, NA),
+ PINGROUP(43, blsp1_uart, blsp1_i2c, blsp1_spi, NA, qdss_tracedata_a,
+ NA, NA, NA, NA),
+ PINGROUP(44, blsp1_uart, blsp1_spi, NA, qdss_tracedata_a, NA, NA, NA,
+ NA, NA),
+ PINGROUP(45, blsp1_uart, blsp1_spi, qdss_tracedata_a, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(46, blsp2_uart, blsp2_i2c, blsp2_spi, qdss_tracedata_a, NA,
+ NA, NA, NA, NA),
+ PINGROUP(47, blsp2_uart, blsp2_i2c, blsp2_spi, NA, qdss_tracedata_a,
+ NA, NA, NA, NA),
+ PINGROUP(48, blsp2_uart, blsp2_spi, NA, qdss_tracedata_a, NA, NA, NA,
+ NA, NA),
+ PINGROUP(49, blsp2_uart, blsp2_spi, NA, qdss_tracedata_a, NA, NA, NA,
+ NA, NA),
+ PINGROUP(50, blsp3_uart, blsp3_i2c, blsp3_spi, NA, qdss_tracedata_a,
+ NA, NA, NA, NA),
+ PINGROUP(51, blsp3_uart, blsp3_i2c, blsp3_spi, NA, qdss_tracedata_a,
+ NA, NA, NA, NA),
+ PINGROUP(52, blsp3_uart, blsp3_spi, NA, qdss_tracedata_a, NA, NA, NA,
+ NA, NA),
+ PINGROUP(53, blsp3_uart, blsp3_spi, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(54, pta2_0, wci21, cxc1, blsp3_spi1, NA, NA, NA, NA, NA),
+ PINGROUP(55, pta2_1, blsp3_spi1, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(56, pta2_2, wci21, cxc1, blsp3_spi1, NA, NA, NA, NA, NA),
+ PINGROUP(57, pcie0_clk, NA, dbg_out, cri_trng0, NA, NA, NA, NA, NA),
+ PINGROUP(58, pcie0_rst, NA, cri_trng1, NA, NA, NA, NA, NA, NA),
+ PINGROUP(59, pcie0_wake, NA, cri_trng, NA, NA, NA, NA, NA, NA),
+ PINGROUP(60, pcie1_clk, rx2, ldo_update, NA, NA, NA, NA, NA, NA),
+ PINGROUP(61, pcie1_rst, ldo_en, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(62, pcie1_wake, gcc_plltest, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(63, sd_card, pwm01, NA, gcc_plltest, NA, NA, NA, NA, NA),
+ PINGROUP(64, pta1_1, pwm11, NA, rx1, NA, NA, NA, NA, NA),
+ PINGROUP(65, pta1_2, NA, gcc_tlmm, NA, NA, NA, NA, NA, NA),
+ PINGROUP(66, pta1_0, pwm21, prng_rosc, NA, NA, NA, NA, NA, NA),
+ PINGROUP(67, sd_write, pwm31, rx0, tsens_max, NA, NA, NA, NA, NA),
+ PINGROUP(68, mdc, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(69, mdio, NA, NA, NA, NA, NA, NA, NA, NA),
+};
+
+static const struct msm_pinctrl_soc_data ipq8074_pinctrl = {
+ .pins = ipq8074_pins,
+ .npins = ARRAY_SIZE(ipq8074_pins),
+ .functions = ipq8074_functions,
+ .nfunctions = ARRAY_SIZE(ipq8074_functions),
+ .groups = ipq8074_groups,
+ .ngroups = ARRAY_SIZE(ipq8074_groups),
+ .ngpios = 70,
+};
+
+static int ipq8074_pinctrl_probe(struct platform_device *pdev)
+{
+ return msm_pinctrl_probe(pdev, &ipq8074_pinctrl);
+}
+
+static const struct of_device_id ipq8074_pinctrl_of_match[] = {
+ { .compatible = "qcom,ipq8074-pinctrl", },
+ { },
+};
+
+static struct platform_driver ipq8074_pinctrl_driver = {
+ .driver = {
+ .name = "ipq8074-pinctrl",
+ .of_match_table = ipq8074_pinctrl_of_match,
+ },
+ .probe = ipq8074_pinctrl_probe,
+ .remove = msm_pinctrl_remove,
+};
+
+static int __init ipq8074_pinctrl_init(void)
+{
+ return platform_driver_register(&ipq8074_pinctrl_driver);
+}
+arch_initcall(ipq8074_pinctrl_init);
+
+static void __exit ipq8074_pinctrl_exit(void)
+{
+ platform_driver_unregister(&ipq8074_pinctrl_driver);
+}
+module_exit(ipq8074_pinctrl_exit);
+
+MODULE_DESCRIPTION("Qualcomm ipq8074 pinctrl driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, ipq8074_pinctrl_of_match);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 2/5] dt-bindings: qcom: Add IPQ8074 bindings
2017-05-04 11:53 ` Varadarajan Narayanan
@ 2017-05-04 11:53 ` Varadarajan Narayanan
-1 siblings, 0 replies; 49+ messages in thread
From: Varadarajan Narayanan @ 2017-05-04 11:53 UTC (permalink / raw)
To: robh+dt, mark.rutland, mturquette, sboyd, linus.walleij,
andy.gross, david.brown, catalin.marinas, will.deacon,
devicetree, linux-kernel, linux-clk, linux-gpio, linux-arm-msm,
linux-soc, linux-arm-kernel
Cc: absahu, sjaganat, sricharan, Varadarajan Narayanan
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
---
Documentation/devicetree/bindings/arm/qcom.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.txt b/Documentation/devicetree/bindings/arm/qcom.txt
index 028d16e..0ed4d39 100644
--- a/Documentation/devicetree/bindings/arm/qcom.txt
+++ b/Documentation/devicetree/bindings/arm/qcom.txt
@@ -25,6 +25,7 @@ The 'SoC' element must be one of the following strings:
msm8994
msm8996
mdm9615
+ ipq8074
The 'board' element must be one of the following strings:
@@ -33,6 +34,7 @@ The 'board' element must be one of the following strings:
dragonboard
mtp
sbc
+ hk01
The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
where the minor number may be omitted when it's zero, i.e. v1.0 is the same
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 2/5] dt-bindings: qcom: Add IPQ8074 bindings
@ 2017-05-04 11:53 ` Varadarajan Narayanan
0 siblings, 0 replies; 49+ messages in thread
From: Varadarajan Narayanan @ 2017-05-04 11:53 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
---
Documentation/devicetree/bindings/arm/qcom.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.txt b/Documentation/devicetree/bindings/arm/qcom.txt
index 028d16e..0ed4d39 100644
--- a/Documentation/devicetree/bindings/arm/qcom.txt
+++ b/Documentation/devicetree/bindings/arm/qcom.txt
@@ -25,6 +25,7 @@ The 'SoC' element must be one of the following strings:
msm8994
msm8996
mdm9615
+ ipq8074
The 'board' element must be one of the following strings:
@@ -33,6 +34,7 @@ The 'board' element must be one of the following strings:
dragonboard
mtp
sbc
+ hk01
The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
where the minor number may be omitted when it's zero, i.e. v1.0 is the same
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 3/5] clk: qcom: ipq8074: Add Global Clock Controller support
2017-05-04 11:53 ` Varadarajan Narayanan
@ 2017-05-04 11:53 ` Varadarajan Narayanan
-1 siblings, 0 replies; 49+ messages in thread
From: Varadarajan Narayanan @ 2017-05-04 11:53 UTC (permalink / raw)
To: robh+dt, mark.rutland, mturquette, sboyd, linus.walleij,
andy.gross, david.brown, catalin.marinas, will.deacon,
devicetree, linux-kernel, linux-clk, linux-gpio, linux-arm-msm,
linux-soc, linux-arm-kernel
Cc: absahu, sjaganat, sricharan, Varadarajan Narayanan
From: Abhishek Sahu <absahu@codeaurora.org>
This patch adds support for the global clock controller found on
the IPQ8074 based devices. This includes UART, I2C, SPI etc.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
---
.../devicetree/bindings/clock/qcom,gcc.txt | 1 +
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-ipq8074.c | 1032 ++++++++++++++++++++
include/dt-bindings/clock/qcom,gcc-ipq8074.h | 152 +++
5 files changed, 1195 insertions(+)
create mode 100644 drivers/clk/qcom/gcc-ipq8074.c
create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq8074.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 5b4dfc1..551d03b 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -8,6 +8,7 @@ Required properties :
"qcom,gcc-apq8084"
"qcom,gcc-ipq8064"
"qcom,gcc-ipq4019"
+ "qcom,gcc-ipq8074"
"qcom,gcc-msm8660"
"qcom,gcc-msm8916"
"qcom,gcc-msm8960"
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 5fb8d74..9f6c278 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -82,6 +82,15 @@ config IPQ_LCC_806X
Say Y if you want to use audio devices such as i2s, pcm,
S/PDIF, etc.
+config IPQ_GCC_8074
+ tristate "IPQ8074 Global Clock Controller"
+ depends on COMMON_CLK_QCOM
+ help
+ Support for global clock controller on ipq8074 devices.
+ Say Y if you want to use peripheral devices such as UART, SPI,
+ i2c, USB, SD/eMMC, etc. Select this for the root clock
+ of ipq8074.
+
config MSM_GCC_8660
tristate "MSM8660 Global Clock Controller"
depends on COMMON_CLK_QCOM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 1c3e222..3f3aff2 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
+obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
obj-$(CONFIG_MDM_LCC_9615) += lcc-mdm9615.o
diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
new file mode 100644
index 0000000..a598eaf
--- /dev/null
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -0,0 +1,1032 @@
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+#include "clk-alpha-pll.h"
+#include "reset.h"
+
+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
+
+enum {
+ P_XO,
+ P_GPLL0,
+ P_GPLL0_DIV2,
+};
+
+static const char * const gcc_xo_gpll0_gpll0_out_main_div2[] = {
+ "xo",
+ "gpll0",
+ "gpll0_out_main_div2",
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL0_DIV2, 4 },
+};
+
+static struct clk_alpha_pll gpll0_main = {
+ .offset = 0x21000,
+ .clkr = {
+ .enable_reg = 0x0b000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll0_main",
+ .parent_names = (const char *[]){
+ "xo"
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static struct clk_fixed_factor gpll0_out_main_div2 = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll0_out_main_div2",
+ .parent_names = (const char *[]){
+ "gpll0_main"
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll0 = {
+ .offset = 0x21000,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll0",
+ .parent_names = (const char *[]){
+ "gpll0_main"
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(50000000, P_GPLL0, 16, 0, 0),
+ F(100000000, P_GPLL0, 8, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
+ .cmd_rcgr = 0x27000,
+ .freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "pcnoc_bfdcd_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ .flags = CLK_IS_CRITICAL,
+ },
+};
+
+static struct clk_fixed_factor pcnoc_clk_src = {
+ .mult = 1,
+ .div = 1,
+ .hw.init = &(struct clk_init_data){
+ .name = "pcnoc_clk_src",
+ .parent_names = (const char *[]){
+ "pcnoc_bfdcd_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_branch gcc_sleep_clk_src = {
+ .halt_reg = 0x30000,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x30000,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sleep_clk_src",
+ .parent_names = (const char *[]){
+ "sleep_clk"
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(25000000, P_GPLL0_DIV2, 16, 0, 0),
+ F(50000000, P_GPLL0, 16, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x0200c,
+ .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup1_i2c_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
+ F(960000, P_XO, 10, 1, 2),
+ F(4800000, P_XO, 4, 0, 0),
+ F(9600000, P_XO, 2, 0, 0),
+ F(12500000, P_GPLL0_DIV2, 16, 1, 2),
+ F(16000000, P_GPLL0, 10, 1, 5),
+ F(19200000, P_XO, 1, 0, 0),
+ F(25000000, P_GPLL0, 16, 1, 2),
+ F(50000000, P_GPLL0, 16, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
+ .cmd_rcgr = 0x02024,
+ .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup1_spi_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x03000,
+ .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup2_i2c_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
+ .cmd_rcgr = 0x03014,
+ .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup2_spi_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x04000,
+ .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup3_i2c_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
+ .cmd_rcgr = 0x04014,
+ .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup3_spi_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x05000,
+ .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup4_i2c_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
+ .cmd_rcgr = 0x05014,
+ .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup4_spi_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x06000,
+ .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup5_i2c_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
+ .cmd_rcgr = 0x06014,
+ .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup5_spi_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x07000,
+ .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup6_i2c_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
+ .cmd_rcgr = 0x07014,
+ .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup6_spi_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
+ F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
+ F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
+ F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
+ F(16000000, P_GPLL0_DIV2, 5, 1, 5),
+ F(19200000, P_XO, 1, 0, 0),
+ F(24000000, P_GPLL0, 1, 3, 100),
+ F(25000000, P_GPLL0, 16, 1, 2),
+ F(32000000, P_GPLL0, 1, 1, 25),
+ F(40000000, P_GPLL0, 1, 1, 20),
+ F(46400000, P_GPLL0, 1, 29, 500),
+ F(48000000, P_GPLL0, 1, 3, 50),
+ F(51200000, P_GPLL0, 1, 8, 125),
+ F(56000000, P_GPLL0, 1, 7, 100),
+ F(58982400, P_GPLL0, 1, 1152, 15625),
+ F(60000000, P_GPLL0, 1, 3, 40),
+ F(64000000, P_GPLL0, 12.5, 1, 1),
+ { }
+};
+
+static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
+ .cmd_rcgr = 0x02044,
+ .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_uart1_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
+ .cmd_rcgr = 0x03034,
+ .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_uart2_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
+ .cmd_rcgr = 0x04034,
+ .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_uart3_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
+ .cmd_rcgr = 0x05034,
+ .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_uart4_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
+ .cmd_rcgr = 0x06034,
+ .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_uart5_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
+ .cmd_rcgr = 0x07034,
+ .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_uart6_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_branch gcc_blsp1_ahb_clk = {
+ .halt_reg = 0x01008,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x01008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_ahb_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
+ .halt_reg = 0x02008,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x02008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup1_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup1_i2c_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
+ .halt_reg = 0x02004,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x02004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup1_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup1_spi_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
+ .halt_reg = 0x03010,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x03010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup2_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup2_i2c_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
+ .halt_reg = 0x0300c,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x0300c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup2_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup2_spi_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
+ .halt_reg = 0x04010,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x04010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup3_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup3_i2c_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
+ .halt_reg = 0x0400c,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x0400c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup3_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup3_spi_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
+ .halt_reg = 0x05010,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x05010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup4_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup4_i2c_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
+ .halt_reg = 0x0500c,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x0500c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup4_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup4_spi_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
+ .halt_reg = 0x06010,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x06010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup5_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup5_i2c_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
+ .halt_reg = 0x0600c,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x0600c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup5_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup5_spi_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
+ .halt_reg = 0x07010,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x07010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup6_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup6_i2c_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
+ .halt_reg = 0x0700c,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x0700c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup6_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup6_spi_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart1_apps_clk = {
+ .halt_reg = 0x0203c,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x0203c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_uart1_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_uart1_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart2_apps_clk = {
+ .halt_reg = 0x0302c,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x0302c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_uart2_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_uart2_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart3_apps_clk = {
+ .halt_reg = 0x0402c,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x0402c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_uart3_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_uart3_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart4_apps_clk = {
+ .halt_reg = 0x0502c,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x0502c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_uart4_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_uart4_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart5_apps_clk = {
+ .halt_reg = 0x0602c,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x0602c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_uart5_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_uart5_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart6_apps_clk = {
+ .halt_reg = 0x0702c,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x0702c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_uart6_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_uart6_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_prng_ahb_clk = {
+ .halt_reg = 0x13004,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x13004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_prng_ahb_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qpic_ahb_clk = {
+ .halt_reg = 0x57024,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x57024,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qpic_ahb_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qpic_clk = {
+ .halt_reg = 0x57020,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x57020,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qpic_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_hw *gcc_ipq8074_hws[] = {
+ &gpll0_out_main_div2.hw,
+ &pcnoc_clk_src.hw,
+};
+
+static struct clk_regmap *gcc_ipq8074_clks[] = {
+ [GPLL0_MAIN] = &gpll0_main.clkr,
+ [GPLL0] = &gpll0.clkr,
+ [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
+ [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
+ [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
+ [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
+ [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
+ [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
+ [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
+ [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
+ [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
+ [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
+ [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
+ [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
+ [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
+ [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
+ [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
+ [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
+ [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
+ [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
+ [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
+ [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
+ [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
+ [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
+ [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
+ [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
+ [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
+};
+
+static const struct qcom_reset_map gcc_ipq8074_resets[] = {
+ [GCC_BLSP1_BCR] = { 0x01000, 0 },
+ [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
+ [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
+ [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
+ [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
+ [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
+ [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
+ [GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 },
+ [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
+ [GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 },
+ [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
+ [GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 },
+ [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
+ [GCC_IMEM_BCR] = { 0x0e000, 0 },
+ [GCC_SMMU_BCR] = { 0x12000, 0 },
+ [GCC_APSS_TCU_BCR] = { 0x12050, 0 },
+ [GCC_SMMU_XPU_BCR] = { 0x12054, 0 },
+ [GCC_PCNOC_TBU_BCR] = { 0x12058, 0 },
+ [GCC_SMMU_CFG_BCR] = { 0x1208c, 0 },
+ [GCC_PRNG_BCR] = { 0x13000, 0 },
+ [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
+ [GCC_CRYPTO_BCR] = { 0x16000, 0 },
+ [GCC_WCSS_BCR] = { 0x18000, 0 },
+ [GCC_WCSS_Q6_BCR] = { 0x18100, 0 },
+ [GCC_NSS_BCR] = { 0x19000, 0 },
+ [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
+ [GCC_ADSS_BCR] = { 0x1c000, 0 },
+ [GCC_DDRSS_BCR] = { 0x1e000, 0 },
+ [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
+ [GCC_PCNOC_BCR] = { 0x27018, 0 },
+ [GCC_TCSR_BCR] = { 0x28000, 0 },
+ [GCC_QDSS_BCR] = { 0x29000, 0 },
+ [GCC_DCD_BCR] = { 0x2a000, 0 },
+ [GCC_MSG_RAM_BCR] = { 0x2b000, 0 },
+ [GCC_MPM_BCR] = { 0x2c000, 0 },
+ [GCC_SPMI_BCR] = { 0x2e000, 0 },
+ [GCC_SPDM_BCR] = { 0x2f000, 0 },
+ [GCC_RBCPR_BCR] = { 0x33000, 0 },
+ [GCC_RBCPR_MX_BCR] = { 0x33014, 0 },
+ [GCC_TLMM_BCR] = { 0x34000, 0 },
+ [GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 },
+ [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
+ [GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 },
+ [GCC_USB0_BCR] = { 0x3e070, 0 },
+ [GCC_USB1_PHY_BCR] = { 0x3f034, 0 },
+ [GCC_USB3PHY_1_PHY_BCR] = { 0x3f03c, 0 },
+ [GCC_USB1_BCR] = { 0x3f070, 0 },
+ [GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 },
+ [GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 },
+ [GCC_SDCC1_BCR] = { 0x42000, 0 },
+ [GCC_SDCC2_BCR] = { 0x43000, 0 },
+ [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 },
+ [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47008, 0 },
+ [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x47010, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
+ [GCC_UNIPHY0_BCR] = { 0x56000, 0 },
+ [GCC_UNIPHY1_BCR] = { 0x56100, 0 },
+ [GCC_UNIPHY2_BCR] = { 0x56200, 0 },
+ [GCC_CMN_12GPLL_BCR] = { 0x56300, 0 },
+ [GCC_QPIC_BCR] = { 0x57018, 0 },
+ [GCC_MDIO_BCR] = { 0x58000, 0 },
+ [GCC_PCIE1_TBU_BCR] = { 0x65000, 0 },
+ [GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 },
+ [GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 },
+ [GCC_USB0_TBU_BCR] = { 0x6a000, 0 },
+ [GCC_USB1_TBU_BCR] = { 0x6a004, 0 },
+ [GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 },
+ [GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 },
+ [GCC_PCIE0_BCR] = { 0x75004, 0 },
+ [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
+ [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
+ [GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 },
+ [GCC_PCIE1_BCR] = { 0x76004, 0 },
+ [GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },
+ [GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },
+ [GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },
+ [GCC_DCC_BCR] = { 0x77000, 0 },
+ [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
+ [GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x79000, 0 },
+ [GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
+};
+
+static const struct of_device_id gcc_ipq8074_match_table[] = {
+ { .compatible = "qcom,gcc-ipq8074" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, gcc_ipq8074_match_table);
+
+static const struct regmap_config gcc_ipq8074_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x7fffc,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_desc gcc_ipq8074_desc = {
+ .config = &gcc_ipq8074_regmap_config,
+ .clks = gcc_ipq8074_clks,
+ .num_clks = ARRAY_SIZE(gcc_ipq8074_clks),
+ .resets = gcc_ipq8074_resets,
+ .num_resets = ARRAY_SIZE(gcc_ipq8074_resets),
+};
+
+static int gcc_ipq8074_probe(struct platform_device *pdev)
+{
+ int ret, i;
+ struct clk *clk;
+
+ for (i = 0; i < ARRAY_SIZE(gcc_ipq8074_hws); i++) {
+ clk = devm_clk_register(&pdev->dev, gcc_ipq8074_hws[i]);
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+ }
+
+ ret = qcom_cc_probe(pdev, &gcc_ipq8074_desc);
+
+ return ret;
+}
+
+static struct platform_driver gcc_ipq8074_driver = {
+ .probe = gcc_ipq8074_probe,
+ .driver = {
+ .name = "qcom,gcc-ipq8074",
+ .of_match_table = gcc_ipq8074_match_table,
+ },
+};
+
+static int __init gcc_ipq8074_init(void)
+{
+ return platform_driver_register(&gcc_ipq8074_driver);
+}
+core_initcall(gcc_ipq8074_init);
+
+static void __exit gcc_ipq8074_exit(void)
+{
+ platform_driver_unregister(&gcc_ipq8074_driver);
+}
+module_exit(gcc_ipq8074_exit);
+
+MODULE_DESCRIPTION("QCOM GCC IPQ8074 Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:gcc-ipq8074");
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
new file mode 100644
index 0000000..370c83c
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H
+#define _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H
+
+#define GPLL0 0
+#define GPLL0_MAIN 1
+#define GCC_SLEEP_CLK_SRC 2
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC 3
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC 4
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC 5
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC 6
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC 7
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC 8
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC 9
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC 10
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC 11
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC 12
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC 13
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC 14
+#define BLSP1_UART1_APPS_CLK_SRC 15
+#define BLSP1_UART2_APPS_CLK_SRC 16
+#define BLSP1_UART3_APPS_CLK_SRC 17
+#define BLSP1_UART4_APPS_CLK_SRC 18
+#define BLSP1_UART5_APPS_CLK_SRC 19
+#define BLSP1_UART6_APPS_CLK_SRC 20
+#define GCC_BLSP1_AHB_CLK 21
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK 22
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK 23
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK 24
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK 25
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK 26
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK 27
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK 28
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK 29
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK 30
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK 31
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK 32
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK 33
+#define GCC_BLSP1_UART1_APPS_CLK 34
+#define GCC_BLSP1_UART2_APPS_CLK 35
+#define GCC_BLSP1_UART3_APPS_CLK 36
+#define GCC_BLSP1_UART4_APPS_CLK 37
+#define GCC_BLSP1_UART5_APPS_CLK 38
+#define GCC_BLSP1_UART6_APPS_CLK 39
+#define GCC_PRNG_AHB_CLK 40
+#define GCC_QPIC_AHB_CLK 41
+#define GCC_QPIC_CLK 42
+#define PCNOC_BFDCD_CLK_SRC 43
+
+#define GCC_BLSP1_BCR 0
+#define GCC_BLSP1_QUP1_BCR 1
+#define GCC_BLSP1_UART1_BCR 2
+#define GCC_BLSP1_QUP2_BCR 3
+#define GCC_BLSP1_UART2_BCR 4
+#define GCC_BLSP1_QUP3_BCR 5
+#define GCC_BLSP1_UART3_BCR 6
+#define GCC_BLSP1_QUP4_BCR 7
+#define GCC_BLSP1_UART4_BCR 8
+#define GCC_BLSP1_QUP5_BCR 9
+#define GCC_BLSP1_UART5_BCR 10
+#define GCC_BLSP1_QUP6_BCR 11
+#define GCC_BLSP1_UART6_BCR 12
+#define GCC_IMEM_BCR 13
+#define GCC_SMMU_BCR 14
+#define GCC_APSS_TCU_BCR 15
+#define GCC_SMMU_XPU_BCR 16
+#define GCC_PCNOC_TBU_BCR 17
+#define GCC_SMMU_CFG_BCR 18
+#define GCC_PRNG_BCR 19
+#define GCC_BOOT_ROM_BCR 20
+#define GCC_CRYPTO_BCR 21
+#define GCC_WCSS_BCR 22
+#define GCC_WCSS_Q6_BCR 23
+#define GCC_NSS_BCR 24
+#define GCC_SEC_CTRL_BCR 25
+#define GCC_ADSS_BCR 26
+#define GCC_DDRSS_BCR 27
+#define GCC_SYSTEM_NOC_BCR 28
+#define GCC_PCNOC_BCR 29
+#define GCC_TCSR_BCR 30
+#define GCC_QDSS_BCR 31
+#define GCC_DCD_BCR 32
+#define GCC_MSG_RAM_BCR 33
+#define GCC_MPM_BCR 34
+#define GCC_SPMI_BCR 35
+#define GCC_SPDM_BCR 36
+#define GCC_RBCPR_BCR 37
+#define GCC_RBCPR_MX_BCR 38
+#define GCC_TLMM_BCR 39
+#define GCC_RBCPR_WCSS_BCR 40
+#define GCC_USB0_PHY_BCR 41
+#define GCC_USB3PHY_0_PHY_BCR 42
+#define GCC_USB0_BCR 43
+#define GCC_USB1_PHY_BCR 44
+#define GCC_USB3PHY_1_PHY_BCR 45
+#define GCC_USB1_BCR 46
+#define GCC_QUSB2_0_PHY_BCR 47
+#define GCC_QUSB2_1_PHY_BCR 48
+#define GCC_SDCC1_BCR 49
+#define GCC_SDCC2_BCR 50
+#define GCC_SNOC_BUS_TIMEOUT0_BCR 51
+#define GCC_SNOC_BUS_TIMEOUT2_BCR 52
+#define GCC_SNOC_BUS_TIMEOUT3_BCR 53
+#define GCC_PCNOC_BUS_TIMEOUT0_BCR 54
+#define GCC_PCNOC_BUS_TIMEOUT1_BCR 55
+#define GCC_PCNOC_BUS_TIMEOUT2_BCR 56
+#define GCC_PCNOC_BUS_TIMEOUT3_BCR 57
+#define GCC_PCNOC_BUS_TIMEOUT4_BCR 58
+#define GCC_PCNOC_BUS_TIMEOUT5_BCR 59
+#define GCC_PCNOC_BUS_TIMEOUT6_BCR 60
+#define GCC_PCNOC_BUS_TIMEOUT7_BCR 61
+#define GCC_PCNOC_BUS_TIMEOUT8_BCR 62
+#define GCC_PCNOC_BUS_TIMEOUT9_BCR 63
+#define GCC_UNIPHY0_BCR 64
+#define GCC_UNIPHY1_BCR 65
+#define GCC_UNIPHY2_BCR 66
+#define GCC_CMN_12GPLL_BCR 67
+#define GCC_QPIC_BCR 68
+#define GCC_MDIO_BCR 69
+#define GCC_PCIE1_TBU_BCR 70
+#define GCC_WCSS_CORE_TBU_BCR 71
+#define GCC_WCSS_Q6_TBU_BCR 72
+#define GCC_USB0_TBU_BCR 73
+#define GCC_USB1_TBU_BCR 74
+#define GCC_PCIE0_TBU_BCR 75
+#define GCC_NSS_NOC_TBU_BCR 76
+#define GCC_PCIE0_BCR 77
+#define GCC_PCIE0_PHY_BCR 78
+#define GCC_PCIE0PHY_PHY_BCR 79
+#define GCC_PCIE0_LINK_DOWN_BCR 80
+#define GCC_PCIE1_BCR 81
+#define GCC_PCIE1_PHY_BCR 82
+#define GCC_PCIE1PHY_PHY_BCR 83
+#define GCC_PCIE1_LINK_DOWN_BCR 84
+#define GCC_DCC_BCR 85
+#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 86
+#define GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR 87
+#define GCC_SMMU_CATS_BCR 88
+
+#endif
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 3/5] clk: qcom: ipq8074: Add Global Clock Controller support
@ 2017-05-04 11:53 ` Varadarajan Narayanan
0 siblings, 0 replies; 49+ messages in thread
From: Varadarajan Narayanan @ 2017-05-04 11:53 UTC (permalink / raw)
To: linux-arm-kernel
From: Abhishek Sahu <absahu@codeaurora.org>
This patch adds support for the global clock controller found on
the IPQ8074 based devices. This includes UART, I2C, SPI etc.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
---
.../devicetree/bindings/clock/qcom,gcc.txt | 1 +
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-ipq8074.c | 1032 ++++++++++++++++++++
include/dt-bindings/clock/qcom,gcc-ipq8074.h | 152 +++
5 files changed, 1195 insertions(+)
create mode 100644 drivers/clk/qcom/gcc-ipq8074.c
create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq8074.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 5b4dfc1..551d03b 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -8,6 +8,7 @@ Required properties :
"qcom,gcc-apq8084"
"qcom,gcc-ipq8064"
"qcom,gcc-ipq4019"
+ "qcom,gcc-ipq8074"
"qcom,gcc-msm8660"
"qcom,gcc-msm8916"
"qcom,gcc-msm8960"
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 5fb8d74..9f6c278 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -82,6 +82,15 @@ config IPQ_LCC_806X
Say Y if you want to use audio devices such as i2s, pcm,
S/PDIF, etc.
+config IPQ_GCC_8074
+ tristate "IPQ8074 Global Clock Controller"
+ depends on COMMON_CLK_QCOM
+ help
+ Support for global clock controller on ipq8074 devices.
+ Say Y if you want to use peripheral devices such as UART, SPI,
+ i2c, USB, SD/eMMC, etc. Select this for the root clock
+ of ipq8074.
+
config MSM_GCC_8660
tristate "MSM8660 Global Clock Controller"
depends on COMMON_CLK_QCOM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 1c3e222..3f3aff2 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
+obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
obj-$(CONFIG_MDM_LCC_9615) += lcc-mdm9615.o
diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
new file mode 100644
index 0000000..a598eaf
--- /dev/null
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -0,0 +1,1032 @@
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+#include "clk-alpha-pll.h"
+#include "reset.h"
+
+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
+
+enum {
+ P_XO,
+ P_GPLL0,
+ P_GPLL0_DIV2,
+};
+
+static const char * const gcc_xo_gpll0_gpll0_out_main_div2[] = {
+ "xo",
+ "gpll0",
+ "gpll0_out_main_div2",
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL0_DIV2, 4 },
+};
+
+static struct clk_alpha_pll gpll0_main = {
+ .offset = 0x21000,
+ .clkr = {
+ .enable_reg = 0x0b000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll0_main",
+ .parent_names = (const char *[]){
+ "xo"
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static struct clk_fixed_factor gpll0_out_main_div2 = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll0_out_main_div2",
+ .parent_names = (const char *[]){
+ "gpll0_main"
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll0 = {
+ .offset = 0x21000,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll0",
+ .parent_names = (const char *[]){
+ "gpll0_main"
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(50000000, P_GPLL0, 16, 0, 0),
+ F(100000000, P_GPLL0, 8, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
+ .cmd_rcgr = 0x27000,
+ .freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "pcnoc_bfdcd_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ .flags = CLK_IS_CRITICAL,
+ },
+};
+
+static struct clk_fixed_factor pcnoc_clk_src = {
+ .mult = 1,
+ .div = 1,
+ .hw.init = &(struct clk_init_data){
+ .name = "pcnoc_clk_src",
+ .parent_names = (const char *[]){
+ "pcnoc_bfdcd_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_branch gcc_sleep_clk_src = {
+ .halt_reg = 0x30000,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x30000,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sleep_clk_src",
+ .parent_names = (const char *[]){
+ "sleep_clk"
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(25000000, P_GPLL0_DIV2, 16, 0, 0),
+ F(50000000, P_GPLL0, 16, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x0200c,
+ .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup1_i2c_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
+ F(960000, P_XO, 10, 1, 2),
+ F(4800000, P_XO, 4, 0, 0),
+ F(9600000, P_XO, 2, 0, 0),
+ F(12500000, P_GPLL0_DIV2, 16, 1, 2),
+ F(16000000, P_GPLL0, 10, 1, 5),
+ F(19200000, P_XO, 1, 0, 0),
+ F(25000000, P_GPLL0, 16, 1, 2),
+ F(50000000, P_GPLL0, 16, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
+ .cmd_rcgr = 0x02024,
+ .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup1_spi_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x03000,
+ .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup2_i2c_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
+ .cmd_rcgr = 0x03014,
+ .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup2_spi_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x04000,
+ .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup3_i2c_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
+ .cmd_rcgr = 0x04014,
+ .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup3_spi_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x05000,
+ .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup4_i2c_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
+ .cmd_rcgr = 0x05014,
+ .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup4_spi_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x06000,
+ .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup5_i2c_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
+ .cmd_rcgr = 0x06014,
+ .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup5_spi_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x07000,
+ .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup6_i2c_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
+ .cmd_rcgr = 0x07014,
+ .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup6_spi_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
+ F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
+ F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
+ F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
+ F(16000000, P_GPLL0_DIV2, 5, 1, 5),
+ F(19200000, P_XO, 1, 0, 0),
+ F(24000000, P_GPLL0, 1, 3, 100),
+ F(25000000, P_GPLL0, 16, 1, 2),
+ F(32000000, P_GPLL0, 1, 1, 25),
+ F(40000000, P_GPLL0, 1, 1, 20),
+ F(46400000, P_GPLL0, 1, 29, 500),
+ F(48000000, P_GPLL0, 1, 3, 50),
+ F(51200000, P_GPLL0, 1, 8, 125),
+ F(56000000, P_GPLL0, 1, 7, 100),
+ F(58982400, P_GPLL0, 1, 1152, 15625),
+ F(60000000, P_GPLL0, 1, 3, 40),
+ F(64000000, P_GPLL0, 12.5, 1, 1),
+ { }
+};
+
+static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
+ .cmd_rcgr = 0x02044,
+ .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_uart1_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
+ .cmd_rcgr = 0x03034,
+ .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_uart2_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
+ .cmd_rcgr = 0x04034,
+ .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_uart3_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
+ .cmd_rcgr = 0x05034,
+ .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_uart4_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
+ .cmd_rcgr = 0x06034,
+ .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_uart5_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
+ .cmd_rcgr = 0x07034,
+ .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_uart6_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_branch gcc_blsp1_ahb_clk = {
+ .halt_reg = 0x01008,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x01008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_ahb_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
+ .halt_reg = 0x02008,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x02008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup1_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup1_i2c_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
+ .halt_reg = 0x02004,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x02004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup1_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup1_spi_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
+ .halt_reg = 0x03010,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x03010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup2_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup2_i2c_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
+ .halt_reg = 0x0300c,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x0300c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup2_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup2_spi_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
+ .halt_reg = 0x04010,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x04010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup3_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup3_i2c_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
+ .halt_reg = 0x0400c,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x0400c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup3_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup3_spi_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
+ .halt_reg = 0x05010,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x05010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup4_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup4_i2c_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
+ .halt_reg = 0x0500c,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x0500c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup4_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup4_spi_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
+ .halt_reg = 0x06010,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x06010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup5_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup5_i2c_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
+ .halt_reg = 0x0600c,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x0600c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup5_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup5_spi_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
+ .halt_reg = 0x07010,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x07010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup6_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup6_i2c_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
+ .halt_reg = 0x0700c,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x0700c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup6_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup6_spi_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart1_apps_clk = {
+ .halt_reg = 0x0203c,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x0203c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_uart1_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_uart1_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart2_apps_clk = {
+ .halt_reg = 0x0302c,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x0302c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_uart2_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_uart2_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart3_apps_clk = {
+ .halt_reg = 0x0402c,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x0402c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_uart3_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_uart3_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart4_apps_clk = {
+ .halt_reg = 0x0502c,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x0502c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_uart4_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_uart4_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart5_apps_clk = {
+ .halt_reg = 0x0602c,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x0602c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_uart5_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_uart5_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart6_apps_clk = {
+ .halt_reg = 0x0702c,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x0702c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_uart6_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_uart6_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_prng_ahb_clk = {
+ .halt_reg = 0x13004,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x13004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_prng_ahb_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qpic_ahb_clk = {
+ .halt_reg = 0x57024,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x57024,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qpic_ahb_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qpic_clk = {
+ .halt_reg = 0x57020,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x57020,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qpic_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_hw *gcc_ipq8074_hws[] = {
+ &gpll0_out_main_div2.hw,
+ &pcnoc_clk_src.hw,
+};
+
+static struct clk_regmap *gcc_ipq8074_clks[] = {
+ [GPLL0_MAIN] = &gpll0_main.clkr,
+ [GPLL0] = &gpll0.clkr,
+ [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
+ [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
+ [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
+ [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
+ [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
+ [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
+ [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
+ [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
+ [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
+ [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
+ [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
+ [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
+ [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
+ [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
+ [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
+ [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
+ [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
+ [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
+ [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
+ [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
+ [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
+ [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
+ [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
+ [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
+ [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
+};
+
+static const struct qcom_reset_map gcc_ipq8074_resets[] = {
+ [GCC_BLSP1_BCR] = { 0x01000, 0 },
+ [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
+ [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
+ [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
+ [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
+ [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
+ [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
+ [GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 },
+ [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
+ [GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 },
+ [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
+ [GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 },
+ [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
+ [GCC_IMEM_BCR] = { 0x0e000, 0 },
+ [GCC_SMMU_BCR] = { 0x12000, 0 },
+ [GCC_APSS_TCU_BCR] = { 0x12050, 0 },
+ [GCC_SMMU_XPU_BCR] = { 0x12054, 0 },
+ [GCC_PCNOC_TBU_BCR] = { 0x12058, 0 },
+ [GCC_SMMU_CFG_BCR] = { 0x1208c, 0 },
+ [GCC_PRNG_BCR] = { 0x13000, 0 },
+ [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
+ [GCC_CRYPTO_BCR] = { 0x16000, 0 },
+ [GCC_WCSS_BCR] = { 0x18000, 0 },
+ [GCC_WCSS_Q6_BCR] = { 0x18100, 0 },
+ [GCC_NSS_BCR] = { 0x19000, 0 },
+ [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
+ [GCC_ADSS_BCR] = { 0x1c000, 0 },
+ [GCC_DDRSS_BCR] = { 0x1e000, 0 },
+ [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
+ [GCC_PCNOC_BCR] = { 0x27018, 0 },
+ [GCC_TCSR_BCR] = { 0x28000, 0 },
+ [GCC_QDSS_BCR] = { 0x29000, 0 },
+ [GCC_DCD_BCR] = { 0x2a000, 0 },
+ [GCC_MSG_RAM_BCR] = { 0x2b000, 0 },
+ [GCC_MPM_BCR] = { 0x2c000, 0 },
+ [GCC_SPMI_BCR] = { 0x2e000, 0 },
+ [GCC_SPDM_BCR] = { 0x2f000, 0 },
+ [GCC_RBCPR_BCR] = { 0x33000, 0 },
+ [GCC_RBCPR_MX_BCR] = { 0x33014, 0 },
+ [GCC_TLMM_BCR] = { 0x34000, 0 },
+ [GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 },
+ [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
+ [GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 },
+ [GCC_USB0_BCR] = { 0x3e070, 0 },
+ [GCC_USB1_PHY_BCR] = { 0x3f034, 0 },
+ [GCC_USB3PHY_1_PHY_BCR] = { 0x3f03c, 0 },
+ [GCC_USB1_BCR] = { 0x3f070, 0 },
+ [GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 },
+ [GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 },
+ [GCC_SDCC1_BCR] = { 0x42000, 0 },
+ [GCC_SDCC2_BCR] = { 0x43000, 0 },
+ [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 },
+ [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47008, 0 },
+ [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x47010, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
+ [GCC_UNIPHY0_BCR] = { 0x56000, 0 },
+ [GCC_UNIPHY1_BCR] = { 0x56100, 0 },
+ [GCC_UNIPHY2_BCR] = { 0x56200, 0 },
+ [GCC_CMN_12GPLL_BCR] = { 0x56300, 0 },
+ [GCC_QPIC_BCR] = { 0x57018, 0 },
+ [GCC_MDIO_BCR] = { 0x58000, 0 },
+ [GCC_PCIE1_TBU_BCR] = { 0x65000, 0 },
+ [GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 },
+ [GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 },
+ [GCC_USB0_TBU_BCR] = { 0x6a000, 0 },
+ [GCC_USB1_TBU_BCR] = { 0x6a004, 0 },
+ [GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 },
+ [GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 },
+ [GCC_PCIE0_BCR] = { 0x75004, 0 },
+ [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
+ [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
+ [GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 },
+ [GCC_PCIE1_BCR] = { 0x76004, 0 },
+ [GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },
+ [GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },
+ [GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },
+ [GCC_DCC_BCR] = { 0x77000, 0 },
+ [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
+ [GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x79000, 0 },
+ [GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
+};
+
+static const struct of_device_id gcc_ipq8074_match_table[] = {
+ { .compatible = "qcom,gcc-ipq8074" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, gcc_ipq8074_match_table);
+
+static const struct regmap_config gcc_ipq8074_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x7fffc,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_desc gcc_ipq8074_desc = {
+ .config = &gcc_ipq8074_regmap_config,
+ .clks = gcc_ipq8074_clks,
+ .num_clks = ARRAY_SIZE(gcc_ipq8074_clks),
+ .resets = gcc_ipq8074_resets,
+ .num_resets = ARRAY_SIZE(gcc_ipq8074_resets),
+};
+
+static int gcc_ipq8074_probe(struct platform_device *pdev)
+{
+ int ret, i;
+ struct clk *clk;
+
+ for (i = 0; i < ARRAY_SIZE(gcc_ipq8074_hws); i++) {
+ clk = devm_clk_register(&pdev->dev, gcc_ipq8074_hws[i]);
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+ }
+
+ ret = qcom_cc_probe(pdev, &gcc_ipq8074_desc);
+
+ return ret;
+}
+
+static struct platform_driver gcc_ipq8074_driver = {
+ .probe = gcc_ipq8074_probe,
+ .driver = {
+ .name = "qcom,gcc-ipq8074",
+ .of_match_table = gcc_ipq8074_match_table,
+ },
+};
+
+static int __init gcc_ipq8074_init(void)
+{
+ return platform_driver_register(&gcc_ipq8074_driver);
+}
+core_initcall(gcc_ipq8074_init);
+
+static void __exit gcc_ipq8074_exit(void)
+{
+ platform_driver_unregister(&gcc_ipq8074_driver);
+}
+module_exit(gcc_ipq8074_exit);
+
+MODULE_DESCRIPTION("QCOM GCC IPQ8074 Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:gcc-ipq8074");
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
new file mode 100644
index 0000000..370c83c
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H
+#define _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H
+
+#define GPLL0 0
+#define GPLL0_MAIN 1
+#define GCC_SLEEP_CLK_SRC 2
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC 3
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC 4
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC 5
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC 6
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC 7
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC 8
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC 9
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC 10
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC 11
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC 12
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC 13
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC 14
+#define BLSP1_UART1_APPS_CLK_SRC 15
+#define BLSP1_UART2_APPS_CLK_SRC 16
+#define BLSP1_UART3_APPS_CLK_SRC 17
+#define BLSP1_UART4_APPS_CLK_SRC 18
+#define BLSP1_UART5_APPS_CLK_SRC 19
+#define BLSP1_UART6_APPS_CLK_SRC 20
+#define GCC_BLSP1_AHB_CLK 21
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK 22
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK 23
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK 24
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK 25
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK 26
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK 27
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK 28
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK 29
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK 30
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK 31
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK 32
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK 33
+#define GCC_BLSP1_UART1_APPS_CLK 34
+#define GCC_BLSP1_UART2_APPS_CLK 35
+#define GCC_BLSP1_UART3_APPS_CLK 36
+#define GCC_BLSP1_UART4_APPS_CLK 37
+#define GCC_BLSP1_UART5_APPS_CLK 38
+#define GCC_BLSP1_UART6_APPS_CLK 39
+#define GCC_PRNG_AHB_CLK 40
+#define GCC_QPIC_AHB_CLK 41
+#define GCC_QPIC_CLK 42
+#define PCNOC_BFDCD_CLK_SRC 43
+
+#define GCC_BLSP1_BCR 0
+#define GCC_BLSP1_QUP1_BCR 1
+#define GCC_BLSP1_UART1_BCR 2
+#define GCC_BLSP1_QUP2_BCR 3
+#define GCC_BLSP1_UART2_BCR 4
+#define GCC_BLSP1_QUP3_BCR 5
+#define GCC_BLSP1_UART3_BCR 6
+#define GCC_BLSP1_QUP4_BCR 7
+#define GCC_BLSP1_UART4_BCR 8
+#define GCC_BLSP1_QUP5_BCR 9
+#define GCC_BLSP1_UART5_BCR 10
+#define GCC_BLSP1_QUP6_BCR 11
+#define GCC_BLSP1_UART6_BCR 12
+#define GCC_IMEM_BCR 13
+#define GCC_SMMU_BCR 14
+#define GCC_APSS_TCU_BCR 15
+#define GCC_SMMU_XPU_BCR 16
+#define GCC_PCNOC_TBU_BCR 17
+#define GCC_SMMU_CFG_BCR 18
+#define GCC_PRNG_BCR 19
+#define GCC_BOOT_ROM_BCR 20
+#define GCC_CRYPTO_BCR 21
+#define GCC_WCSS_BCR 22
+#define GCC_WCSS_Q6_BCR 23
+#define GCC_NSS_BCR 24
+#define GCC_SEC_CTRL_BCR 25
+#define GCC_ADSS_BCR 26
+#define GCC_DDRSS_BCR 27
+#define GCC_SYSTEM_NOC_BCR 28
+#define GCC_PCNOC_BCR 29
+#define GCC_TCSR_BCR 30
+#define GCC_QDSS_BCR 31
+#define GCC_DCD_BCR 32
+#define GCC_MSG_RAM_BCR 33
+#define GCC_MPM_BCR 34
+#define GCC_SPMI_BCR 35
+#define GCC_SPDM_BCR 36
+#define GCC_RBCPR_BCR 37
+#define GCC_RBCPR_MX_BCR 38
+#define GCC_TLMM_BCR 39
+#define GCC_RBCPR_WCSS_BCR 40
+#define GCC_USB0_PHY_BCR 41
+#define GCC_USB3PHY_0_PHY_BCR 42
+#define GCC_USB0_BCR 43
+#define GCC_USB1_PHY_BCR 44
+#define GCC_USB3PHY_1_PHY_BCR 45
+#define GCC_USB1_BCR 46
+#define GCC_QUSB2_0_PHY_BCR 47
+#define GCC_QUSB2_1_PHY_BCR 48
+#define GCC_SDCC1_BCR 49
+#define GCC_SDCC2_BCR 50
+#define GCC_SNOC_BUS_TIMEOUT0_BCR 51
+#define GCC_SNOC_BUS_TIMEOUT2_BCR 52
+#define GCC_SNOC_BUS_TIMEOUT3_BCR 53
+#define GCC_PCNOC_BUS_TIMEOUT0_BCR 54
+#define GCC_PCNOC_BUS_TIMEOUT1_BCR 55
+#define GCC_PCNOC_BUS_TIMEOUT2_BCR 56
+#define GCC_PCNOC_BUS_TIMEOUT3_BCR 57
+#define GCC_PCNOC_BUS_TIMEOUT4_BCR 58
+#define GCC_PCNOC_BUS_TIMEOUT5_BCR 59
+#define GCC_PCNOC_BUS_TIMEOUT6_BCR 60
+#define GCC_PCNOC_BUS_TIMEOUT7_BCR 61
+#define GCC_PCNOC_BUS_TIMEOUT8_BCR 62
+#define GCC_PCNOC_BUS_TIMEOUT9_BCR 63
+#define GCC_UNIPHY0_BCR 64
+#define GCC_UNIPHY1_BCR 65
+#define GCC_UNIPHY2_BCR 66
+#define GCC_CMN_12GPLL_BCR 67
+#define GCC_QPIC_BCR 68
+#define GCC_MDIO_BCR 69
+#define GCC_PCIE1_TBU_BCR 70
+#define GCC_WCSS_CORE_TBU_BCR 71
+#define GCC_WCSS_Q6_TBU_BCR 72
+#define GCC_USB0_TBU_BCR 73
+#define GCC_USB1_TBU_BCR 74
+#define GCC_PCIE0_TBU_BCR 75
+#define GCC_NSS_NOC_TBU_BCR 76
+#define GCC_PCIE0_BCR 77
+#define GCC_PCIE0_PHY_BCR 78
+#define GCC_PCIE0PHY_PHY_BCR 79
+#define GCC_PCIE0_LINK_DOWN_BCR 80
+#define GCC_PCIE1_BCR 81
+#define GCC_PCIE1_PHY_BCR 82
+#define GCC_PCIE1PHY_PHY_BCR 83
+#define GCC_PCIE1_LINK_DOWN_BCR 84
+#define GCC_DCC_BCR 85
+#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 86
+#define GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR 87
+#define GCC_SMMU_CATS_BCR 88
+
+#endif
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 4/5] arm64: dts: Add ipq8074 SoC and HK01 board support
2017-05-04 11:53 ` Varadarajan Narayanan
@ 2017-05-04 11:54 ` Varadarajan Narayanan
-1 siblings, 0 replies; 49+ messages in thread
From: Varadarajan Narayanan @ 2017-05-04 11:54 UTC (permalink / raw)
To: robh+dt, mark.rutland, mturquette, sboyd, linus.walleij,
andy.gross, david.brown, catalin.marinas, will.deacon,
devicetree, linux-kernel, linux-clk, linux-gpio, linux-arm-msm,
linux-soc, linux-arm-kernel
Cc: absahu, sjaganat, sricharan, Varadarajan Narayanan,
Manoharan Vijaya Raghavan
Add initial device tree support for the Qualcomm IPQ8074 SoC and
HK01 evaluation board.
Signed-off-by: Manoharan Vijaya Raghavan <mraghava@codeaurora.org>
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 53 ++++++++
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 194 ++++++++++++++++++++++++++++++
3 files changed, 248 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
create mode 100644 arch/arm64/boot/dts/qcom/ipq8074.dtsi
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index cc0f02d..ff81d7e 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -1,5 +1,6 @@
dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
+dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
new file mode 100644
index 0000000..7d44be9
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -0,0 +1,53 @@
+/dts-v1/;
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include "ipq8074.dtsi"
+
+/ {
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
+ compatible = "qcom,ipq8074-hk01", "qcom,ipq8074";
+ interrupt-parent = <&intc>;
+
+ aliases {
+ serial0 = &blsp1_uart5;
+ };
+
+ chosen {
+ bootargs = "root=/dev/ram0 rw init=/init";
+ stdout-path = "serial0";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0x0 0x20000000>;
+ };
+
+ soc {
+ pinctrl@1000000 {
+ serial_4_pins: serial4_pinmux {
+ mux {
+ pins = "gpio23", "gpio24";
+ function = "blsp4_uart1";
+ bias-disable;
+ };
+ };
+ };
+
+ serial@78b3000 {
+ pinctrl-0 = <&serial_4_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
new file mode 100644
index 0000000..2bc5dec
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ8074";
+ compatible = "qcom,ipq8074";
+
+ soc: soc {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ ranges = <0 0 0 0xffffffff>;
+ compatible = "simple-bus";
+
+ pinctrl@1000000 {
+ compatible = "qcom,ipq8074-pinctrl";
+ reg = <0x1000000 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <0x2>;
+ interrupt-controller;
+ #interrupt-cells = <0x2>;
+ };
+
+ intc: interrupt-controller@b000000 {
+ compatible = "qcom,msm-qgic2";
+ interrupt-controller;
+ #interrupt-cells = <0x3>;
+ reg = <0xb000000 0x1000>, <0xb002000 0x1000>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ timer@b120000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "arm,armv7-timer-mem";
+ reg = <0xb120000 0x1000>;
+ clock-frequency = <19200000>;
+
+ frame@b120000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb121000 0x1000>,
+ <0xb122000 0x1000>;
+ };
+
+ frame@b123000 {
+ frame-number = <1>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb123000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b124000 {
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb124000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b125000 {
+ frame-number = <3>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb125000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b126000 {
+ frame-number = <4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb126000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b127000 {
+ frame-number = <5>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb127000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b128000 {
+ frame-number = <6>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb128000 0x1000>;
+ status = "disabled";
+ };
+ };
+
+ gcc: gcc@1800000 {
+ compatible = "qcom,gcc-ipq8074";
+ reg = <0x1800000 0x80000>;
+ #clock-cells = <0x1>;
+ #reset-cells = <0x1>;
+ };
+
+ blsp1_uart5: serial@78b3000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x78b3000 0x200>;
+ interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+ };
+
+ cpus {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ enable-method = "psci";
+ reg = <0x1>;
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ enable-method = "psci";
+ reg = <0x2>;
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ enable-method = "psci";
+ reg = <0x3>;
+ next-level-cache = <&L2_0>;
+ };
+
+ L2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <0x2>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
+ };
+
+ clocks {
+ sleep_clk: sleep_clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ #clock-cells = <0>;
+ };
+
+ xo: xo {
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+ #clock-cells = <0>;
+ };
+ };
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 4/5] arm64: dts: Add ipq8074 SoC and HK01 board support
@ 2017-05-04 11:54 ` Varadarajan Narayanan
0 siblings, 0 replies; 49+ messages in thread
From: Varadarajan Narayanan @ 2017-05-04 11:54 UTC (permalink / raw)
To: linux-arm-kernel
Add initial device tree support for the Qualcomm IPQ8074 SoC and
HK01 evaluation board.
Signed-off-by: Manoharan Vijaya Raghavan <mraghava@codeaurora.org>
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 53 ++++++++
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 194 ++++++++++++++++++++++++++++++
3 files changed, 248 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
create mode 100644 arch/arm64/boot/dts/qcom/ipq8074.dtsi
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index cc0f02d..ff81d7e 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -1,5 +1,6 @@
dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
+dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
new file mode 100644
index 0000000..7d44be9
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -0,0 +1,53 @@
+/dts-v1/;
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include "ipq8074.dtsi"
+
+/ {
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
+ compatible = "qcom,ipq8074-hk01", "qcom,ipq8074";
+ interrupt-parent = <&intc>;
+
+ aliases {
+ serial0 = &blsp1_uart5;
+ };
+
+ chosen {
+ bootargs = "root=/dev/ram0 rw init=/init";
+ stdout-path = "serial0";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0x0 0x20000000>;
+ };
+
+ soc {
+ pinctrl at 1000000 {
+ serial_4_pins: serial4_pinmux {
+ mux {
+ pins = "gpio23", "gpio24";
+ function = "blsp4_uart1";
+ bias-disable;
+ };
+ };
+ };
+
+ serial at 78b3000 {
+ pinctrl-0 = <&serial_4_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
new file mode 100644
index 0000000..2bc5dec
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ8074";
+ compatible = "qcom,ipq8074";
+
+ soc: soc {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ ranges = <0 0 0 0xffffffff>;
+ compatible = "simple-bus";
+
+ pinctrl at 1000000 {
+ compatible = "qcom,ipq8074-pinctrl";
+ reg = <0x1000000 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <0x2>;
+ interrupt-controller;
+ #interrupt-cells = <0x2>;
+ };
+
+ intc: interrupt-controller at b000000 {
+ compatible = "qcom,msm-qgic2";
+ interrupt-controller;
+ #interrupt-cells = <0x3>;
+ reg = <0xb000000 0x1000>, <0xb002000 0x1000>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ timer at b120000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "arm,armv7-timer-mem";
+ reg = <0xb120000 0x1000>;
+ clock-frequency = <19200000>;
+
+ frame at b120000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb121000 0x1000>,
+ <0xb122000 0x1000>;
+ };
+
+ frame at b123000 {
+ frame-number = <1>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb123000 0x1000>;
+ status = "disabled";
+ };
+
+ frame at b124000 {
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb124000 0x1000>;
+ status = "disabled";
+ };
+
+ frame at b125000 {
+ frame-number = <3>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb125000 0x1000>;
+ status = "disabled";
+ };
+
+ frame at b126000 {
+ frame-number = <4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb126000 0x1000>;
+ status = "disabled";
+ };
+
+ frame at b127000 {
+ frame-number = <5>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb127000 0x1000>;
+ status = "disabled";
+ };
+
+ frame at b128000 {
+ frame-number = <6>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb128000 0x1000>;
+ status = "disabled";
+ };
+ };
+
+ gcc: gcc at 1800000 {
+ compatible = "qcom,gcc-ipq8074";
+ reg = <0x1800000 0x80000>;
+ #clock-cells = <0x1>;
+ #reset-cells = <0x1>;
+ };
+
+ blsp1_uart5: serial at 78b3000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x78b3000 0x200>;
+ interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+ };
+
+ cpus {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+
+ CPU0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CPU1: cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ enable-method = "psci";
+ reg = <0x1>;
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU2: cpu at 2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ enable-method = "psci";
+ reg = <0x2>;
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU3: cpu at 3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ enable-method = "psci";
+ reg = <0x3>;
+ next-level-cache = <&L2_0>;
+ };
+
+ L2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <0x2>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
+ };
+
+ clocks {
+ sleep_clk: sleep_clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ #clock-cells = <0>;
+ };
+
+ xo: xo {
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+ #clock-cells = <0>;
+ };
+ };
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 5/5] arm64: defconfig: Enable QCOM IPQ8074 clock and pinctrl
2017-05-04 11:53 ` Varadarajan Narayanan
(?)
@ 2017-05-04 11:54 ` Varadarajan Narayanan
-1 siblings, 0 replies; 49+ messages in thread
From: Varadarajan Narayanan @ 2017-05-04 11:54 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
mturquette-rdvid1DuHRBWk0Htik3J/w, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
andy.gross-QSEj5FYQhm4dnm+yROfE0A,
david.brown-QSEj5FYQhm4dnm+yROfE0A, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-soc-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: absahu-sgV2jX0FEOL9JmXXK+q4OQ, sjaganat-sgV2jX0FEOL9JmXXK+q4OQ,
sricharan-sgV2jX0FEOL9JmXXK+q4OQ, Varadarajan Narayanan
From: Abhishek Sahu <absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
These configs are required for booting kernel in QCOM
IPQ8074 boards.
Signed-off-by: Abhishek Sahu <absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Signed-off-by: Varadarajan Narayanan <varada-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
---
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 7c48028..e6aeb69 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -266,6 +266,7 @@ CONFIG_SPI_SPIDEV=m
CONFIG_SPI_S3C64XX=y
CONFIG_SPMI=y
CONFIG_PINCTRL_SINGLE=y
+CONFIG_PINCTRL_IPQ8074=y
CONFIG_PINCTRL_MAX77620=y
CONFIG_PINCTRL_MSM8916=y
CONFIG_PINCTRL_MSM8994=y
@@ -439,6 +440,7 @@ CONFIG_COMMON_CLK_PWM=y
CONFIG_COMMON_CLK_RK808=y
CONFIG_CLK_QORIQ=y
CONFIG_COMMON_CLK_QCOM=y
+CONFIG_IPQ_GCC_8074=y
CONFIG_MSM_GCC_8916=y
CONFIG_MSM_GCC_8994=y
CONFIG_MSM_MMCC_8996=y
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 5/5] arm64: defconfig: Enable QCOM IPQ8074 clock and pinctrl
@ 2017-05-04 11:54 ` Varadarajan Narayanan
0 siblings, 0 replies; 49+ messages in thread
From: Varadarajan Narayanan @ 2017-05-04 11:54 UTC (permalink / raw)
To: robh+dt, mark.rutland, mturquette, sboyd, linus.walleij,
andy.gross, david.brown, catalin.marinas, will.deacon,
devicetree, linux-kernel, linux-clk, linux-gpio, linux-arm-msm,
linux-soc, linux-arm-kernel
Cc: absahu, sjaganat, sricharan, Varadarajan Narayanan
From: Abhishek Sahu <absahu@codeaurora.org>
These configs are required for booting kernel in QCOM
IPQ8074 boards.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
---
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 7c48028..e6aeb69 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -266,6 +266,7 @@ CONFIG_SPI_SPIDEV=m
CONFIG_SPI_S3C64XX=y
CONFIG_SPMI=y
CONFIG_PINCTRL_SINGLE=y
+CONFIG_PINCTRL_IPQ8074=y
CONFIG_PINCTRL_MAX77620=y
CONFIG_PINCTRL_MSM8916=y
CONFIG_PINCTRL_MSM8994=y
@@ -439,6 +440,7 @@ CONFIG_COMMON_CLK_PWM=y
CONFIG_COMMON_CLK_RK808=y
CONFIG_CLK_QORIQ=y
CONFIG_COMMON_CLK_QCOM=y
+CONFIG_IPQ_GCC_8074=y
CONFIG_MSM_GCC_8916=y
CONFIG_MSM_GCC_8994=y
CONFIG_MSM_MMCC_8996=y
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 5/5] arm64: defconfig: Enable QCOM IPQ8074 clock and pinctrl
@ 2017-05-04 11:54 ` Varadarajan Narayanan
0 siblings, 0 replies; 49+ messages in thread
From: Varadarajan Narayanan @ 2017-05-04 11:54 UTC (permalink / raw)
To: linux-arm-kernel
From: Abhishek Sahu <absahu@codeaurora.org>
These configs are required for booting kernel in QCOM
IPQ8074 boards.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
---
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 7c48028..e6aeb69 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -266,6 +266,7 @@ CONFIG_SPI_SPIDEV=m
CONFIG_SPI_S3C64XX=y
CONFIG_SPMI=y
CONFIG_PINCTRL_SINGLE=y
+CONFIG_PINCTRL_IPQ8074=y
CONFIG_PINCTRL_MAX77620=y
CONFIG_PINCTRL_MSM8916=y
CONFIG_PINCTRL_MSM8994=y
@@ -439,6 +440,7 @@ CONFIG_COMMON_CLK_PWM=y
CONFIG_COMMON_CLK_RK808=y
CONFIG_CLK_QORIQ=y
CONFIG_COMMON_CLK_QCOM=y
+CONFIG_IPQ_GCC_8074=y
CONFIG_MSM_GCC_8916=y
CONFIG_MSM_GCC_8994=y
CONFIG_MSM_MMCC_8996=y
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 49+ messages in thread
* Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
2017-05-04 11:53 ` Varadarajan Narayanan
@ 2017-05-08 5:49 ` Varadarajan Narayanan
-1 siblings, 0 replies; 49+ messages in thread
From: Varadarajan Narayanan @ 2017-05-08 5:49 UTC (permalink / raw)
To: robh+dt, mark.rutland, mturquette, sboyd, linus.walleij,
andy.gross, david.brown, catalin.marinas, will.deacon,
devicetree, linux-kernel, linux-clk, linux-gpio, linux-arm-msm,
linux-soc, linux-arm-kernel, bjorn.andersson
Cc: absahu, sjaganat, sricharan, Manoharan Vijaya Raghavan
+ Bjorn Andersson
On 5/4/2017 5:23 PM, Varadarajan Narayanan wrote:
> Add initial pinctrl driver to support pin configuration with
> pinctrl framework for ipq8074.
>
> Signed-off-by: Manoharan Vijaya Raghavan <mraghava@codeaurora.org>
> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
> ---
> .../bindings/pinctrl/qcom,ipq8074-pinctrl.txt | 187 +++
> drivers/pinctrl/qcom/Kconfig | 10 +
> drivers/pinctrl/qcom/Makefile | 1 +
> drivers/pinctrl/qcom/pinctrl-ipq8074.c | 1217 ++++++++++++++++++++
> 4 files changed, 1415 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
> create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq8074.c
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
> new file mode 100644
> index 0000000..7765bca
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
> @@ -0,0 +1,187 @@
> +Qualcomm Technologies, Inc. IPQ8074 TLMM block
> +
> +This binding describes the Top Level Mode Multiplexer block found in the
> +IPQ8074 platform.
> +
> +- compatible:
> + Usage: required
> + Value type: <string>
> + Definition: must be "qcom,ipq8074-pinctrl"
> +
> +- reg:
> + Usage: required
> + Value type: <prop-encoded-array>
> + Definition: the base address and size of the TLMM register space.
> +
> +- interrupts:
> + Usage: required
> + Value type: <prop-encoded-array>
> + Definition: should specify the TLMM summary IRQ.
> +
> +- interrupt-controller:
> + Usage: required
> + Value type: <none>
> + Definition: identifies this node as an interrupt controller
> +
> +- #interrupt-cells:
> + Usage: required
> + Value type: <u32>
> + Definition: must be 2. Specifying the pin number and flags, as defined
> + in <dt-bindings/interrupt-controller/irq.h>
> +
> +- gpio-controller:
> + Usage: required
> + Value type: <none>
> + Definition: identifies this node as a gpio controller
> +
> +- #gpio-cells:
> + Usage: required
> + Value type: <u32>
> + Definition: must be 2. Specifying the pin number and flags, as defined
> + in <dt-bindings/gpio/gpio.h>
> +
> +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
> +a general description of GPIO and interrupt bindings.
> +
> +Please refer to pinctrl-bindings.txt in this directory for details of the
> +common pinctrl bindings used by client devices, including the meaning of the
> +phrase "pin configuration node".
> +
> +The pin configuration nodes act as a container for an arbitrary number of
> +subnodes. Each of these subnodes represents some desired configuration for a
> +pin, a group, or a list of pins or groups. This configuration can include the
> +mux function to select on those pin(s)/group(s), and various pin configuration
> +parameters, such as pull-up, drive strength, etc.
> +
> +
> +PIN CONFIGURATION NODES:
> +
> +The name of each subnode is not important; all subnodes should be enumerated
> +and processed purely based on their content.
> +
> +Each subnode only affects those parameters that are explicitly listed. In
> +other words, a subnode that lists a mux function but no pin configuration
> +parameters implies no information about any pin configuration parameters.
> +Similarly, a pin subnode that describes a pullup parameter implies no
> +information about e.g. the mux function.
> +
> +
> +The following generic properties as defined in pinctrl-bindings.txt are valid
> +to specify in a pin configuration subnode:
> +
> +- pins:
> + Usage: required
> + Value type: <string-array>
> + Definition: List of gpio pins affected by the properties specified in
> + this subnode. Valid pins are:
> + gpio0-gpio121,
> + sdc1_clk,
> + sdc1_cmd,
> + sdc1_data
> + sdc2_clk,
> + sdc2_cmd,
> + sdc2_data,
> + qdsd_cmd,
> + qdsd_data0,
> + qdsd_data1,
> + qdsd_data2,
> + qdsd_data3
> +
> +- function:
> + Usage: required
> + Value type: <string>
> + Definition: Specify the alternative function to be configured for the
> + specified pins. Functions are only valid for gpio pins.
> + Valid values are:
> + gpio, qpic_pad, blsp5_i2c, blsp5_spi, wci20, blsp3_spi3,
> + burn0, pcm_zsi0, blsp5_uart, mac12, blsp3_spi0, burn1, mac01,
> + qdss_cti_trig_out_b0, qdss_cti_trig_in_b0, qpic_pad4,
> + blsp4_uart0, blsp4_i2c0, blsp4_spi0, mac21,
> + qdss_cti_trig_out_b1, qpic_pad5, qdss_cti_trig_in_b1,
> + qpic_pad6, qpic_pad7, cxc0, mac13, qdss_cti_trig_in_a1,
> + qdss_cti_trig_out_a1, wci22, qdss_cti_trig_in_a0, qpic_pad1,
> + qdss_cti_trig_out_a0, qpic_pad2, qpic_pad3, qdss_traceclk_b,
> + qpic_pad0, qdss_tracectl_b, qpic_pad8, pcm_zsi1,
> + qdss_tracedata_b, led0, pwm04, led1, pwm14, led2, pwm24,
> + pwm00, blsp4_uart1, blsp4_i2c1, blsp4_spi1, wci23, mac11,
> + blsp3_spi2, pwm10, pwm20, pwm30, audio_txmclk, pwm02,
> + audio_txbclk, pwm12, audio_txfsync, pwm22, audio_txd, pwm32,
> + audio_rxmclk, pwm03, atest_char0, audio_rxbclk, pwm13,
> + atest_char1, audio_rxfsync, pwm23, atest_char2, audio_rxd,
> + pwm33, atest_char3, pcm_drx, mac10, mac00, pcm_dtx, pcm_fsync,
> + mac20, qdss_traceclk_a, pcm_pclk, qdss_tracectl_a, atest_char,
> + qdss_tracedata_a, blsp0_uart, blsp0_i2c, blsp0_spi,
> + blsp1_uart, blsp1_i2c, blsp1_spi, blsp2_uart, blsp2_i2c,
> + blsp2_spi, blsp3_uart, blsp3_i2c, blsp3_spi, pta2_0, wci21,
> + cxc1, blsp3_spi1, pta2_1, pta2_2, pcie0_clk, dbg_out,
> + cri_trng0, pcie0_rst, cri_trng1, pcie0_wake, cri_trng,
> + pcie1_clk, rx2, ldo_update, pcie1_rst, ldo_en, pcie1_wake,
> + gcc_plltest, sd_card, pwm01, pta1_1, pwm11, rx1, pta1_2,
> + gcc_tlmm, pta1_0, pwm21, prng_rosc, sd_write, pwm31, rx0,
> + tsens_max, mdc, mdio, NA
> +
> +- bias-disable:
> + Usage: optional
> + Value type: <none>
> + Definition: The specified pins should be configued as no pull.
> +
> +- bias-pull-down:
> + Usage: optional
> + Value type: <none>
> + Definition: The specified pins should be configued as pull down.
> +
> +- bias-pull-up:
> + Usage: optional
> + Value type: <none>
> + Definition: The specified pins should be configued as pull up.
> +
> +- output-high:
> + Usage: optional
> + Value type: <none>
> + Definition: The specified pins are configured in output mode, driven
> + high.
> + Not valid for sdc pins.
> +
> +- output-low:
> + Usage: optional
> + Value type: <none>
> + Definition: The specified pins are configured in output mode, driven
> + low.
> + Not valid for sdc pins.
> +
> +- drive-strength:
> + Usage: optional
> + Value type: <u32>
> + Definition: Selects the drive strength for the specified pins, in mA.
> + Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
> +
> +Example:
> +
> + tlmm: pinctrl@1000000 {
> + compatible = "qcom,ipq8074-pinctrl";
> + reg = <0x1000000 0x300000>;
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + uart2: uart2-default {
> + mux {
> + pins = "gpio23", "gpio24";
> + function = "blsp4_uart1";
> + };
> +
> + rx {
> + pins = "gpio23";
> + drive-strength = <4>;
> + bias-disable;
> + };
> +
> + tx {
> + pins = "gpio24";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> + };
> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
> index 3ebdc01..9e504db 100644
> --- a/drivers/pinctrl/qcom/Kconfig
> +++ b/drivers/pinctrl/qcom/Kconfig
> @@ -39,6 +39,16 @@ config PINCTRL_IPQ8064
> This is the pinctrl, pinmux, pinconf and gpiolib driver for the
> Qualcomm TLMM block found in the Qualcomm IPQ8064 platform.
>
> +config PINCTRL_IPQ8074
> + tristate "Qualcomm Technologies, Inc. IPQ8074 pin controller driver"
> + depends on GPIOLIB && OF
> + select PINCTRL_MSM
> + help
> + This is the pinctrl, pinmux, pinconf and gpiolib driver for
> + the Qualcomm Technologies Inc. TLMM block found on the
> + Qualcomm Technologies Inc. IPQ8074 platform. Select this for
> + IPQ8074.
> +
> config PINCTRL_MSM8660
> tristate "Qualcomm 8660 pin controller driver"
> depends on GPIOLIB && OF
> diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
> index ab47764..06c8b2a 100644
> --- a/drivers/pinctrl/qcom/Makefile
> +++ b/drivers/pinctrl/qcom/Makefile
> @@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
> obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
> obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o
> obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
> +obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o
> obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o
> obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o
> obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
> diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8074.c b/drivers/pinctrl/qcom/pinctrl-ipq8074.c
> new file mode 100644
> index 0000000..8bb8071
> --- /dev/null
> +++ b/drivers/pinctrl/qcom/pinctrl-ipq8074.c
> @@ -0,0 +1,1217 @@
> +/*
> + * Copyright (c) 2017, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/pinctrl/pinctrl.h>
> +
> +#include "pinctrl-msm.h"
> +
> +#define FUNCTION(fname) \
> + [msm_mux_##fname] = { \
> + .name = #fname, \
> + .groups = fname##_groups, \
> + .ngroups = ARRAY_SIZE(fname##_groups), \
> + }
> +
> +#define REG_SIZE 0x1000
> +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
> + { \
> + .name = "gpio" #id, \
> + .pins = gpio##id##_pins, \
> + .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
> + .funcs = (int[]){ \
> + msm_mux_gpio, /* gpio mode */ \
> + msm_mux_##f1, \
> + msm_mux_##f2, \
> + msm_mux_##f3, \
> + msm_mux_##f4, \
> + msm_mux_##f5, \
> + msm_mux_##f6, \
> + msm_mux_##f7, \
> + msm_mux_##f8, \
> + msm_mux_##f9 \
> + }, \
> + .nfuncs = 10, \
> + .ctl_reg = REG_SIZE * id, \
> + .io_reg = 0x4 + REG_SIZE * id, \
> + .intr_cfg_reg = 0x8 + REG_SIZE * id, \
> + .intr_status_reg = 0xc + REG_SIZE * id, \
> + .intr_target_reg = 0x8 + REG_SIZE * id, \
> + .mux_bit = 2, \
> + .pull_bit = 0, \
> + .drv_bit = 6, \
> + .oe_bit = 9, \
> + .in_bit = 0, \
> + .out_bit = 1, \
> + .intr_enable_bit = 0, \
> + .intr_status_bit = 0, \
> + .intr_target_bit = 5, \
> + .intr_raw_status_bit = 4, \
> + .intr_polarity_bit = 1, \
> + .intr_detection_bit = 2, \
> + .intr_detection_width = 2, \
> + }
> +
> +static const struct pinctrl_pin_desc ipq8074_pins[] = {
> + PINCTRL_PIN(0, "GPIO_0"),
> + PINCTRL_PIN(1, "GPIO_1"),
> + PINCTRL_PIN(2, "GPIO_2"),
> + PINCTRL_PIN(3, "GPIO_3"),
> + PINCTRL_PIN(4, "GPIO_4"),
> + PINCTRL_PIN(5, "GPIO_5"),
> + PINCTRL_PIN(6, "GPIO_6"),
> + PINCTRL_PIN(7, "GPIO_7"),
> + PINCTRL_PIN(8, "GPIO_8"),
> + PINCTRL_PIN(9, "GPIO_9"),
> + PINCTRL_PIN(10, "GPIO_10"),
> + PINCTRL_PIN(11, "GPIO_11"),
> + PINCTRL_PIN(12, "GPIO_12"),
> + PINCTRL_PIN(13, "GPIO_13"),
> + PINCTRL_PIN(14, "GPIO_14"),
> + PINCTRL_PIN(15, "GPIO_15"),
> + PINCTRL_PIN(16, "GPIO_16"),
> + PINCTRL_PIN(17, "GPIO_17"),
> + PINCTRL_PIN(18, "GPIO_18"),
> + PINCTRL_PIN(19, "GPIO_19"),
> + PINCTRL_PIN(20, "GPIO_20"),
> + PINCTRL_PIN(21, "GPIO_21"),
> + PINCTRL_PIN(22, "GPIO_22"),
> + PINCTRL_PIN(23, "GPIO_23"),
> + PINCTRL_PIN(24, "GPIO_24"),
> + PINCTRL_PIN(25, "GPIO_25"),
> + PINCTRL_PIN(26, "GPIO_26"),
> + PINCTRL_PIN(27, "GPIO_27"),
> + PINCTRL_PIN(28, "GPIO_28"),
> + PINCTRL_PIN(29, "GPIO_29"),
> + PINCTRL_PIN(30, "GPIO_30"),
> + PINCTRL_PIN(31, "GPIO_31"),
> + PINCTRL_PIN(32, "GPIO_32"),
> + PINCTRL_PIN(33, "GPIO_33"),
> + PINCTRL_PIN(34, "GPIO_34"),
> + PINCTRL_PIN(35, "GPIO_35"),
> + PINCTRL_PIN(36, "GPIO_36"),
> + PINCTRL_PIN(37, "GPIO_37"),
> + PINCTRL_PIN(38, "GPIO_38"),
> + PINCTRL_PIN(39, "GPIO_39"),
> + PINCTRL_PIN(40, "GPIO_40"),
> + PINCTRL_PIN(41, "GPIO_41"),
> + PINCTRL_PIN(42, "GPIO_42"),
> + PINCTRL_PIN(43, "GPIO_43"),
> + PINCTRL_PIN(44, "GPIO_44"),
> + PINCTRL_PIN(45, "GPIO_45"),
> + PINCTRL_PIN(46, "GPIO_46"),
> + PINCTRL_PIN(47, "GPIO_47"),
> + PINCTRL_PIN(48, "GPIO_48"),
> + PINCTRL_PIN(49, "GPIO_49"),
> + PINCTRL_PIN(50, "GPIO_50"),
> + PINCTRL_PIN(51, "GPIO_51"),
> + PINCTRL_PIN(52, "GPIO_52"),
> + PINCTRL_PIN(53, "GPIO_53"),
> + PINCTRL_PIN(54, "GPIO_54"),
> + PINCTRL_PIN(55, "GPIO_55"),
> + PINCTRL_PIN(56, "GPIO_56"),
> + PINCTRL_PIN(57, "GPIO_57"),
> + PINCTRL_PIN(58, "GPIO_58"),
> + PINCTRL_PIN(59, "GPIO_59"),
> + PINCTRL_PIN(60, "GPIO_60"),
> + PINCTRL_PIN(61, "GPIO_61"),
> + PINCTRL_PIN(62, "GPIO_62"),
> + PINCTRL_PIN(63, "GPIO_63"),
> + PINCTRL_PIN(64, "GPIO_64"),
> + PINCTRL_PIN(65, "GPIO_65"),
> + PINCTRL_PIN(66, "GPIO_66"),
> + PINCTRL_PIN(67, "GPIO_67"),
> + PINCTRL_PIN(68, "GPIO_68"),
> + PINCTRL_PIN(69, "GPIO_69"),
> +};
> +
> +#define DECLARE_MSM_GPIO_PINS(pin) \
> + static const unsigned int gpio##pin##_pins[] = { pin }
> +DECLARE_MSM_GPIO_PINS(0);
> +DECLARE_MSM_GPIO_PINS(1);
> +DECLARE_MSM_GPIO_PINS(2);
> +DECLARE_MSM_GPIO_PINS(3);
> +DECLARE_MSM_GPIO_PINS(4);
> +DECLARE_MSM_GPIO_PINS(5);
> +DECLARE_MSM_GPIO_PINS(6);
> +DECLARE_MSM_GPIO_PINS(7);
> +DECLARE_MSM_GPIO_PINS(8);
> +DECLARE_MSM_GPIO_PINS(9);
> +DECLARE_MSM_GPIO_PINS(10);
> +DECLARE_MSM_GPIO_PINS(11);
> +DECLARE_MSM_GPIO_PINS(12);
> +DECLARE_MSM_GPIO_PINS(13);
> +DECLARE_MSM_GPIO_PINS(14);
> +DECLARE_MSM_GPIO_PINS(15);
> +DECLARE_MSM_GPIO_PINS(16);
> +DECLARE_MSM_GPIO_PINS(17);
> +DECLARE_MSM_GPIO_PINS(18);
> +DECLARE_MSM_GPIO_PINS(19);
> +DECLARE_MSM_GPIO_PINS(20);
> +DECLARE_MSM_GPIO_PINS(21);
> +DECLARE_MSM_GPIO_PINS(22);
> +DECLARE_MSM_GPIO_PINS(23);
> +DECLARE_MSM_GPIO_PINS(24);
> +DECLARE_MSM_GPIO_PINS(25);
> +DECLARE_MSM_GPIO_PINS(26);
> +DECLARE_MSM_GPIO_PINS(27);
> +DECLARE_MSM_GPIO_PINS(28);
> +DECLARE_MSM_GPIO_PINS(29);
> +DECLARE_MSM_GPIO_PINS(30);
> +DECLARE_MSM_GPIO_PINS(31);
> +DECLARE_MSM_GPIO_PINS(32);
> +DECLARE_MSM_GPIO_PINS(33);
> +DECLARE_MSM_GPIO_PINS(34);
> +DECLARE_MSM_GPIO_PINS(35);
> +DECLARE_MSM_GPIO_PINS(36);
> +DECLARE_MSM_GPIO_PINS(37);
> +DECLARE_MSM_GPIO_PINS(38);
> +DECLARE_MSM_GPIO_PINS(39);
> +DECLARE_MSM_GPIO_PINS(40);
> +DECLARE_MSM_GPIO_PINS(41);
> +DECLARE_MSM_GPIO_PINS(42);
> +DECLARE_MSM_GPIO_PINS(43);
> +DECLARE_MSM_GPIO_PINS(44);
> +DECLARE_MSM_GPIO_PINS(45);
> +DECLARE_MSM_GPIO_PINS(46);
> +DECLARE_MSM_GPIO_PINS(47);
> +DECLARE_MSM_GPIO_PINS(48);
> +DECLARE_MSM_GPIO_PINS(49);
> +DECLARE_MSM_GPIO_PINS(50);
> +DECLARE_MSM_GPIO_PINS(51);
> +DECLARE_MSM_GPIO_PINS(52);
> +DECLARE_MSM_GPIO_PINS(53);
> +DECLARE_MSM_GPIO_PINS(54);
> +DECLARE_MSM_GPIO_PINS(55);
> +DECLARE_MSM_GPIO_PINS(56);
> +DECLARE_MSM_GPIO_PINS(57);
> +DECLARE_MSM_GPIO_PINS(58);
> +DECLARE_MSM_GPIO_PINS(59);
> +DECLARE_MSM_GPIO_PINS(60);
> +DECLARE_MSM_GPIO_PINS(61);
> +DECLARE_MSM_GPIO_PINS(62);
> +DECLARE_MSM_GPIO_PINS(63);
> +DECLARE_MSM_GPIO_PINS(64);
> +DECLARE_MSM_GPIO_PINS(65);
> +DECLARE_MSM_GPIO_PINS(66);
> +DECLARE_MSM_GPIO_PINS(67);
> +DECLARE_MSM_GPIO_PINS(68);
> +DECLARE_MSM_GPIO_PINS(69);
> +
> +enum ipq8074_functions {
> + msm_mux_gpio,
> + msm_mux_qpic_pad,
> + msm_mux_blsp5_i2c,
> + msm_mux_blsp5_spi,
> + msm_mux_wci20,
> + msm_mux_blsp3_spi3,
> + msm_mux_burn0,
> + msm_mux_pcm_zsi0,
> + msm_mux_blsp5_uart,
> + msm_mux_mac12,
> + msm_mux_blsp3_spi0,
> + msm_mux_burn1,
> + msm_mux_mac01,
> + msm_mux_qdss_cti_trig_out_b0,
> + msm_mux_qdss_cti_trig_in_b0,
> + msm_mux_qpic_pad4,
> + msm_mux_blsp4_uart0,
> + msm_mux_blsp4_i2c0,
> + msm_mux_blsp4_spi0,
> + msm_mux_mac21,
> + msm_mux_qdss_cti_trig_out_b1,
> + msm_mux_qpic_pad5,
> + msm_mux_qdss_cti_trig_in_b1,
> + msm_mux_qpic_pad6,
> + msm_mux_qpic_pad7,
> + msm_mux_cxc0,
> + msm_mux_mac13,
> + msm_mux_qdss_cti_trig_in_a1,
> + msm_mux_qdss_cti_trig_out_a1,
> + msm_mux_wci22,
> + msm_mux_qdss_cti_trig_in_a0,
> + msm_mux_qpic_pad1,
> + msm_mux_qdss_cti_trig_out_a0,
> + msm_mux_qpic_pad2,
> + msm_mux_qpic_pad3,
> + msm_mux_qdss_traceclk_b,
> + msm_mux_qpic_pad0,
> + msm_mux_qdss_tracectl_b,
> + msm_mux_qpic_pad8,
> + msm_mux_pcm_zsi1,
> + msm_mux_qdss_tracedata_b,
> + msm_mux_led0,
> + msm_mux_pwm04,
> + msm_mux_led1,
> + msm_mux_pwm14,
> + msm_mux_led2,
> + msm_mux_pwm24,
> + msm_mux_pwm00,
> + msm_mux_blsp4_uart1,
> + msm_mux_blsp4_i2c1,
> + msm_mux_blsp4_spi1,
> + msm_mux_wci23,
> + msm_mux_mac11,
> + msm_mux_blsp3_spi2,
> + msm_mux_pwm10,
> + msm_mux_pwm20,
> + msm_mux_pwm30,
> + msm_mux_audio_txmclk,
> + msm_mux_pwm02,
> + msm_mux_audio_txbclk,
> + msm_mux_pwm12,
> + msm_mux_audio_txfsync,
> + msm_mux_pwm22,
> + msm_mux_audio_txd,
> + msm_mux_pwm32,
> + msm_mux_audio_rxmclk,
> + msm_mux_pwm03,
> + msm_mux_atest_char0,
> + msm_mux_audio_rxbclk,
> + msm_mux_pwm13,
> + msm_mux_atest_char1,
> + msm_mux_audio_rxfsync,
> + msm_mux_pwm23,
> + msm_mux_atest_char2,
> + msm_mux_audio_rxd,
> + msm_mux_pwm33,
> + msm_mux_atest_char3,
> + msm_mux_pcm_drx,
> + msm_mux_mac10,
> + msm_mux_mac00,
> + msm_mux_pcm_dtx,
> + msm_mux_pcm_fsync,
> + msm_mux_mac20,
> + msm_mux_qdss_traceclk_a,
> + msm_mux_pcm_pclk,
> + msm_mux_qdss_tracectl_a,
> + msm_mux_atest_char,
> + msm_mux_qdss_tracedata_a,
> + msm_mux_blsp0_uart,
> + msm_mux_blsp0_i2c,
> + msm_mux_blsp0_spi,
> + msm_mux_blsp1_uart,
> + msm_mux_blsp1_i2c,
> + msm_mux_blsp1_spi,
> + msm_mux_blsp2_uart,
> + msm_mux_blsp2_i2c,
> + msm_mux_blsp2_spi,
> + msm_mux_blsp3_uart,
> + msm_mux_blsp3_i2c,
> + msm_mux_blsp3_spi,
> + msm_mux_pta2_0,
> + msm_mux_wci21,
> + msm_mux_cxc1,
> + msm_mux_blsp3_spi1,
> + msm_mux_pta2_1,
> + msm_mux_pta2_2,
> + msm_mux_pcie0_clk,
> + msm_mux_dbg_out,
> + msm_mux_cri_trng0,
> + msm_mux_pcie0_rst,
> + msm_mux_cri_trng1,
> + msm_mux_pcie0_wake,
> + msm_mux_cri_trng,
> + msm_mux_pcie1_clk,
> + msm_mux_rx2,
> + msm_mux_ldo_update,
> + msm_mux_pcie1_rst,
> + msm_mux_ldo_en,
> + msm_mux_pcie1_wake,
> + msm_mux_gcc_plltest,
> + msm_mux_sd_card,
> + msm_mux_pwm01,
> + msm_mux_pta1_1,
> + msm_mux_pwm11,
> + msm_mux_rx1,
> + msm_mux_pta1_2,
> + msm_mux_gcc_tlmm,
> + msm_mux_pta1_0,
> + msm_mux_pwm21,
> + msm_mux_prng_rosc,
> + msm_mux_sd_write,
> + msm_mux_pwm31,
> + msm_mux_rx0,
> + msm_mux_tsens_max,
> + msm_mux_mdc,
> + msm_mux_mdio,
> + msm_mux_NA,
> +};
> +
> +static const char * const qpic_pad_groups[] = {
> + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio9", "gpio10",
> + "gpio11", "gpio17",
> +};
> +
> +static const char * const _groups[] = {
> + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
> + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
> + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
> + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
> + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
> + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
> + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
> + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
> + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
> + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69",
> +};
> +
> +static const char * const blsp5_i2c_groups[] = {
> + "gpio0", "gpio2",
> +};
> +
> +static const char * const blsp5_spi_groups[] = {
> + "gpio0", "gpio2", "gpio9", "gpio16",
> +};
> +
> +static const char * const wci20_groups[] = {
> + "gpio0", "gpio2",
> +};
> +
> +static const char * const blsp3_spi3_groups[] = {
> + "gpio0", "gpio2", "gpio9",
> +};
> +
> +static const char * const burn0_groups[] = {
> + "gpio0",
> +};
> +
> +static const char * const pcm_zsi0_groups[] = {
> + "gpio1",
> +};
> +
> +static const char * const blsp5_uart_groups[] = {
> + "gpio0", "gpio2", "gpio9", "gpio16",
> +};
> +
> +static const char * const mac12_groups[] = {
> + "gpio1", "gpio11",
> +};
> +
> +static const char * const blsp3_spi0_groups[] = {
> + "gpio1", "gpio3", "gpio4",
> +};
> +
> +static const char * const burn1_groups[] = {
> + "gpio1",
> +};
> +
> +static const char * const mac01_groups[] = {
> + "gpio3", "gpio4",
> +};
> +
> +static const char * const qdss_cti_trig_out_b0_groups[] = {
> + "gpio3",
> +};
> +
> +static const char * const qdss_cti_trig_in_b0_groups[] = {
> + "gpio4",
> +};
> +
> +static const char * const qpic_pad4_groups[] = {
> + "gpio5",
> +};
> +
> +static const char * const blsp4_uart0_groups[] = {
> + "gpio5", "gpio6", "gpio7", "gpio8",
> +};
> +
> +static const char * const blsp4_i2c0_groups[] = {
> + "gpio5", "gpio6",
> +};
> +
> +static const char * const blsp4_spi0_groups[] = {
> + "gpio5", "gpio6", "gpio7", "gpio8",
> +};
> +
> +static const char * const mac21_groups[] = {
> + "gpio5", "gpio6",
> +};
> +
> +static const char * const qdss_cti_trig_out_b1_groups[] = {
> + "gpio5",
> +};
> +
> +static const char * const qpic_pad5_groups[] = {
> + "gpio6",
> +};
> +
> +static const char * const qdss_cti_trig_in_b1_groups[] = {
> + "gpio6",
> +};
> +
> +static const char * const qpic_pad6_groups[] = {
> + "gpio7",
> +};
> +
> +static const char * const qpic_pad7_groups[] = {
> + "gpio8",
> +};
> +
> +static const char * const cxc0_groups[] = {
> + "gpio9", "gpio16",
> +};
> +
> +static const char * const mac13_groups[] = {
> + "gpio9", "gpio16",
> +};
> +
> +static const char * const qdss_cti_trig_in_a1_groups[] = {
> + "gpio9",
> +};
> +
> +static const char * const qdss_cti_trig_out_a1_groups[] = {
> + "gpio10",
> +};
> +
> +static const char * const wci22_groups[] = {
> + "gpio11", "gpio17",
> +};
> +
> +static const char * const qdss_cti_trig_in_a0_groups[] = {
> + "gpio11",
> +};
> +
> +static const char * const qpic_pad1_groups[] = {
> + "gpio12",
> +};
> +
> +static const char * const qdss_cti_trig_out_a0_groups[] = {
> + "gpio12",
> +};
> +
> +static const char * const qpic_pad2_groups[] = {
> + "gpio13",
> +};
> +
> +static const char * const qpic_pad3_groups[] = {
> + "gpio14",
> +};
> +
> +static const char * const qdss_traceclk_b_groups[] = {
> + "gpio14",
> +};
> +
> +static const char * const qpic_pad0_groups[] = {
> + "gpio15",
> +};
> +
> +static const char * const qdss_tracectl_b_groups[] = {
> + "gpio15",
> +};
> +
> +static const char * const qpic_pad8_groups[] = {
> + "gpio16",
> +};
> +
> +static const char * const pcm_zsi1_groups[] = {
> + "gpio16",
> +};
> +
> +static const char * const qdss_tracedata_b_groups[] = {
> + "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
> + "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
> + "gpio30", "gpio31",
> +};
> +
> +static const char * const led0_groups[] = {
> + "gpio18",
> +};
> +
> +static const char * const pwm04_groups[] = {
> + "gpio18",
> +};
> +
> +static const char * const led1_groups[] = {
> + "gpio19",
> +};
> +
> +static const char * const pwm14_groups[] = {
> + "gpio19",
> +};
> +
> +static const char * const led2_groups[] = {
> + "gpio20",
> +};
> +
> +static const char * const pwm24_groups[] = {
> + "gpio20",
> +};
> +
> +static const char * const pwm00_groups[] = {
> + "gpio21",
> +};
> +
> +static const char * const blsp4_uart1_groups[] = {
> + "gpio21", "gpio22", "gpio23", "gpio24",
> +};
> +
> +static const char * const blsp4_i2c1_groups[] = {
> + "gpio21", "gpio22",
> +};
> +
> +static const char * const blsp4_spi1_groups[] = {
> + "gpio21", "gpio22", "gpio23", "gpio24",
> +};
> +
> +static const char * const wci23_groups[] = {
> + "gpio21", "gpio22",
> +};
> +
> +static const char * const mac11_groups[] = {
> + "gpio21", "gpio22",
> +};
> +
> +static const char * const blsp3_spi2_groups[] = {
> + "gpio21", "gpio22", "gpio23",
> +};
> +
> +static const char * const pwm10_groups[] = {
> + "gpio22",
> +};
> +
> +static const char * const pwm20_groups[] = {
> + "gpio23",
> +};
> +
> +static const char * const pwm30_groups[] = {
> + "gpio24",
> +};
> +
> +static const char * const audio_txmclk_groups[] = {
> + "gpio25",
> +};
> +
> +static const char * const pwm02_groups[] = {
> + "gpio25",
> +};
> +
> +static const char * const audio_txbclk_groups[] = {
> + "gpio26",
> +};
> +
> +static const char * const pwm12_groups[] = {
> + "gpio26",
> +};
> +
> +static const char * const audio_txfsync_groups[] = {
> + "gpio27",
> +};
> +
> +static const char * const pwm22_groups[] = {
> + "gpio27",
> +};
> +
> +static const char * const audio_txd_groups[] = {
> + "gpio28",
> +};
> +
> +static const char * const pwm32_groups[] = {
> + "gpio28",
> +};
> +
> +static const char * const audio_rxmclk_groups[] = {
> + "gpio29",
> +};
> +
> +static const char * const pwm03_groups[] = {
> + "gpio29",
> +};
> +
> +static const char * const atest_char0_groups[] = {
> + "gpio29",
> +};
> +
> +static const char * const audio_rxbclk_groups[] = {
> + "gpio30",
> +};
> +
> +static const char * const pwm13_groups[] = {
> + "gpio30",
> +};
> +
> +static const char * const atest_char1_groups[] = {
> + "gpio30",
> +};
> +
> +static const char * const audio_rxfsync_groups[] = {
> + "gpio31",
> +};
> +
> +static const char * const pwm23_groups[] = {
> + "gpio31",
> +};
> +
> +static const char * const atest_char2_groups[] = {
> + "gpio31",
> +};
> +
> +static const char * const audio_rxd_groups[] = {
> + "gpio32",
> +};
> +
> +static const char * const pwm33_groups[] = {
> + "gpio32",
> +};
> +
> +static const char * const atest_char3_groups[] = {
> + "gpio32",
> +};
> +
> +static const char * const pcm_drx_groups[] = {
> + "gpio33",
> +};
> +
> +static const char * const mac10_groups[] = {
> + "gpio33", "gpio34",
> +};
> +
> +static const char * const mac00_groups[] = {
> + "gpio33", "gpio34",
> +};
> +
> +static const char * const pcm_dtx_groups[] = {
> + "gpio34",
> +};
> +
> +static const char * const pcm_fsync_groups[] = {
> + "gpio35",
> +};
> +
> +static const char * const mac20_groups[] = {
> + "gpio35", "gpio36",
> +};
> +
> +static const char * const qdss_traceclk_a_groups[] = {
> + "gpio35",
> +};
> +
> +static const char * const pcm_pclk_groups[] = {
> + "gpio36",
> +};
> +
> +static const char * const qdss_tracectl_a_groups[] = {
> + "gpio36",
> +};
> +
> +static const char * const atest_char_groups[] = {
> + "gpio37",
> +};
> +
> +static const char * const qdss_tracedata_a_groups[] = {
> + "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
> + "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", "gpio50",
> + "gpio51", "gpio52",
> +};
> +
> +static const char * const blsp0_uart_groups[] = {
> + "gpio38", "gpio39", "gpio40", "gpio41",
> +};
> +
> +static const char * const blsp0_i2c_groups[] = {
> + "gpio38", "gpio39",
> +};
> +
> +static const char * const blsp0_spi_groups[] = {
> + "gpio38", "gpio39", "gpio40", "gpio41",
> +};
> +
> +static const char * const blsp1_uart_groups[] = {
> + "gpio42", "gpio43", "gpio44", "gpio45",
> +};
> +
> +static const char * const blsp1_i2c_groups[] = {
> + "gpio42", "gpio43",
> +};
> +
> +static const char * const blsp1_spi_groups[] = {
> + "gpio42", "gpio43", "gpio44", "gpio45",
> +};
> +
> +static const char * const blsp2_uart_groups[] = {
> + "gpio46", "gpio47", "gpio48", "gpio49",
> +};
> +
> +static const char * const blsp2_i2c_groups[] = {
> + "gpio46", "gpio47",
> +};
> +
> +static const char * const blsp2_spi_groups[] = {
> + "gpio46", "gpio47", "gpio48", "gpio49",
> +};
> +
> +static const char * const blsp3_uart_groups[] = {
> + "gpio50", "gpio51", "gpio52", "gpio53",
> +};
> +
> +static const char * const blsp3_i2c_groups[] = {
> + "gpio50", "gpio51",
> +};
> +
> +static const char * const blsp3_spi_groups[] = {
> + "gpio50", "gpio51", "gpio52", "gpio53",
> +};
> +
> +static const char * const pta2_0_groups[] = {
> + "gpio54",
> +};
> +
> +static const char * const wci21_groups[] = {
> + "gpio54", "gpio56",
> +};
> +
> +static const char * const cxc1_groups[] = {
> + "gpio54", "gpio56",
> +};
> +
> +static const char * const blsp3_spi1_groups[] = {
> + "gpio54", "gpio55", "gpio56",
> +};
> +
> +static const char * const pta2_1_groups[] = {
> + "gpio55",
> +};
> +
> +static const char * const pta2_2_groups[] = {
> + "gpio56",
> +};
> +
> +static const char * const pcie0_clk_groups[] = {
> + "gpio57",
> +};
> +
> +static const char * const dbg_out_groups[] = {
> + "gpio57",
> +};
> +
> +static const char * const cri_trng0_groups[] = {
> + "gpio57",
> +};
> +
> +static const char * const pcie0_rst_groups[] = {
> + "gpio58",
> +};
> +
> +static const char * const cri_trng1_groups[] = {
> + "gpio58",
> +};
> +
> +static const char * const pcie0_wake_groups[] = {
> + "gpio59",
> +};
> +
> +static const char * const cri_trng_groups[] = {
> + "gpio59",
> +};
> +
> +static const char * const pcie1_clk_groups[] = {
> + "gpio60",
> +};
> +
> +static const char * const rx2_groups[] = {
> + "gpio60",
> +};
> +
> +static const char * const ldo_update_groups[] = {
> + "gpio60",
> +};
> +
> +static const char * const pcie1_rst_groups[] = {
> + "gpio61",
> +};
> +
> +static const char * const ldo_en_groups[] = {
> + "gpio61",
> +};
> +
> +static const char * const pcie1_wake_groups[] = {
> + "gpio62",
> +};
> +
> +static const char * const gcc_plltest_groups[] = {
> + "gpio62", "gpio63",
> +};
> +
> +static const char * const sd_card_groups[] = {
> + "gpio63",
> +};
> +
> +static const char * const pwm01_groups[] = {
> + "gpio63",
> +};
> +
> +static const char * const pta1_1_groups[] = {
> + "gpio64",
> +};
> +
> +static const char * const pwm11_groups[] = {
> + "gpio64",
> +};
> +
> +static const char * const rx1_groups[] = {
> + "gpio64",
> +};
> +
> +static const char * const pta1_2_groups[] = {
> + "gpio65",
> +};
> +
> +static const char * const gcc_tlmm_groups[] = {
> + "gpio65",
> +};
> +
> +static const char * const pta1_0_groups[] = {
> + "gpio66",
> +};
> +
> +static const char * const pwm21_groups[] = {
> + "gpio66",
> +};
> +
> +static const char * const prng_rosc_groups[] = {
> + "gpio66",
> +};
> +
> +static const char * const sd_write_groups[] = {
> + "gpio67",
> +};
> +
> +static const char * const pwm31_groups[] = {
> + "gpio67",
> +};
> +
> +static const char * const rx0_groups[] = {
> + "gpio67",
> +};
> +
> +static const char * const tsens_max_groups[] = {
> + "gpio67",
> +};
> +
> +static const char * const mdc_groups[] = {
> + "gpio68",
> +};
> +
> +static const char * const mdio_groups[] = {
> + "gpio69",
> +};
> +
> +static const char * const gpio_groups[] = {
> + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
> + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
> + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
> + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
> + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
> + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
> + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
> + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
> + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
> + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69",
> +};
> +
> +static const struct msm_function ipq8074_functions[] = {
> + FUNCTION(gpio),
> + FUNCTION(qpic_pad),
> + FUNCTION(blsp5_i2c),
> + FUNCTION(blsp5_spi),
> + FUNCTION(wci20),
> + FUNCTION(blsp3_spi3),
> + FUNCTION(burn0),
> + FUNCTION(pcm_zsi0),
> + FUNCTION(blsp5_uart),
> + FUNCTION(mac12),
> + FUNCTION(blsp3_spi0),
> + FUNCTION(burn1),
> + FUNCTION(mac01),
> + FUNCTION(qdss_cti_trig_out_b0),
> + FUNCTION(qdss_cti_trig_in_b0),
> + FUNCTION(qpic_pad4),
> + FUNCTION(blsp4_uart0),
> + FUNCTION(blsp4_i2c0),
> + FUNCTION(blsp4_spi0),
> + FUNCTION(mac21),
> + FUNCTION(qdss_cti_trig_out_b1),
> + FUNCTION(qpic_pad5),
> + FUNCTION(qdss_cti_trig_in_b1),
> + FUNCTION(qpic_pad6),
> + FUNCTION(qpic_pad7),
> + FUNCTION(cxc0),
> + FUNCTION(mac13),
> + FUNCTION(qdss_cti_trig_in_a1),
> + FUNCTION(qdss_cti_trig_out_a1),
> + FUNCTION(wci22),
> + FUNCTION(qdss_cti_trig_in_a0),
> + FUNCTION(qpic_pad1),
> + FUNCTION(qdss_cti_trig_out_a0),
> + FUNCTION(qpic_pad2),
> + FUNCTION(qpic_pad3),
> + FUNCTION(qdss_traceclk_b),
> + FUNCTION(qpic_pad0),
> + FUNCTION(qdss_tracectl_b),
> + FUNCTION(qpic_pad8),
> + FUNCTION(pcm_zsi1),
> + FUNCTION(qdss_tracedata_b),
> + FUNCTION(led0),
> + FUNCTION(pwm04),
> + FUNCTION(led1),
> + FUNCTION(pwm14),
> + FUNCTION(led2),
> + FUNCTION(pwm24),
> + FUNCTION(pwm00),
> + FUNCTION(blsp4_uart1),
> + FUNCTION(blsp4_i2c1),
> + FUNCTION(blsp4_spi1),
> + FUNCTION(wci23),
> + FUNCTION(mac11),
> + FUNCTION(blsp3_spi2),
> + FUNCTION(pwm10),
> + FUNCTION(pwm20),
> + FUNCTION(pwm30),
> + FUNCTION(audio_txmclk),
> + FUNCTION(pwm02),
> + FUNCTION(audio_txbclk),
> + FUNCTION(pwm12),
> + FUNCTION(audio_txfsync),
> + FUNCTION(pwm22),
> + FUNCTION(audio_txd),
> + FUNCTION(pwm32),
> + FUNCTION(audio_rxmclk),
> + FUNCTION(pwm03),
> + FUNCTION(atest_char0),
> + FUNCTION(audio_rxbclk),
> + FUNCTION(pwm13),
> + FUNCTION(atest_char1),
> + FUNCTION(audio_rxfsync),
> + FUNCTION(pwm23),
> + FUNCTION(atest_char2),
> + FUNCTION(audio_rxd),
> + FUNCTION(pwm33),
> + FUNCTION(atest_char3),
> + FUNCTION(pcm_drx),
> + FUNCTION(mac10),
> + FUNCTION(mac00),
> + FUNCTION(pcm_dtx),
> + FUNCTION(pcm_fsync),
> + FUNCTION(mac20),
> + FUNCTION(qdss_traceclk_a),
> + FUNCTION(pcm_pclk),
> + FUNCTION(qdss_tracectl_a),
> + FUNCTION(atest_char),
> + FUNCTION(qdss_tracedata_a),
> + FUNCTION(blsp0_uart),
> + FUNCTION(blsp0_i2c),
> + FUNCTION(blsp0_spi),
> + FUNCTION(blsp1_uart),
> + FUNCTION(blsp1_i2c),
> + FUNCTION(blsp1_spi),
> + FUNCTION(blsp2_uart),
> + FUNCTION(blsp2_i2c),
> + FUNCTION(blsp2_spi),
> + FUNCTION(blsp3_uart),
> + FUNCTION(blsp3_i2c),
> + FUNCTION(blsp3_spi),
> + FUNCTION(pta2_0),
> + FUNCTION(wci21),
> + FUNCTION(cxc1),
> + FUNCTION(blsp3_spi1),
> + FUNCTION(pta2_1),
> + FUNCTION(pta2_2),
> + FUNCTION(pcie0_clk),
> + FUNCTION(dbg_out),
> + FUNCTION(cri_trng0),
> + FUNCTION(pcie0_rst),
> + FUNCTION(cri_trng1),
> + FUNCTION(pcie0_wake),
> + FUNCTION(cri_trng),
> + FUNCTION(pcie1_clk),
> + FUNCTION(rx2),
> + FUNCTION(ldo_update),
> + FUNCTION(pcie1_rst),
> + FUNCTION(ldo_en),
> + FUNCTION(pcie1_wake),
> + FUNCTION(gcc_plltest),
> + FUNCTION(sd_card),
> + FUNCTION(pwm01),
> + FUNCTION(pta1_1),
> + FUNCTION(pwm11),
> + FUNCTION(rx1),
> + FUNCTION(pta1_2),
> + FUNCTION(gcc_tlmm),
> + FUNCTION(pta1_0),
> + FUNCTION(pwm21),
> + FUNCTION(prng_rosc),
> + FUNCTION(sd_write),
> + FUNCTION(pwm31),
> + FUNCTION(rx0),
> + FUNCTION(tsens_max),
> + FUNCTION(mdc),
> + FUNCTION(mdio),
> +};
> +
> +static const struct msm_pingroup ipq8074_groups[] = {
> + PINGROUP(0, qpic_pad, blsp5_uart, blsp5_i2c, blsp5_spi, wci20,
> + blsp3_spi3, NA, burn0, NA),
> + PINGROUP(1, qpic_pad, pcm_zsi0, mac12, blsp3_spi0, NA, burn1, NA, NA,
> + NA),
> + PINGROUP(2, qpic_pad, blsp5_uart, blsp5_i2c, blsp5_spi, wci20,
> + blsp3_spi3, NA, NA, NA),
> + PINGROUP(3, qpic_pad, mac01, blsp3_spi0, qdss_cti_trig_out_b0, NA, NA,
> + NA, NA, NA),
> + PINGROUP(4, qpic_pad, mac01, blsp3_spi0, qdss_cti_trig_in_b0, NA, NA,
> + NA, NA, NA),
> + PINGROUP(5, qpic_pad4, blsp4_uart0, blsp4_i2c0, blsp4_spi0, mac21,
> + qdss_cti_trig_out_b1, NA, NA, NA),
> + PINGROUP(6, qpic_pad5, blsp4_uart0, blsp4_i2c0, blsp4_spi0, mac21,
> + qdss_cti_trig_in_b1, NA, NA, NA),
> + PINGROUP(7, qpic_pad6, blsp4_uart0, blsp4_spi0, NA, NA, NA, NA, NA, NA),
> + PINGROUP(8, qpic_pad7, blsp4_uart0, blsp4_spi0, NA, NA, NA, NA, NA, NA),
> + PINGROUP(9, qpic_pad, blsp5_uart, blsp5_spi, cxc0, mac13, blsp3_spi3,
> + qdss_cti_trig_in_a1, NA, NA),
> + PINGROUP(10, qpic_pad, qdss_cti_trig_out_a1, NA, NA, NA, NA, NA, NA,
> + NA),
> + PINGROUP(11, qpic_pad, wci22, mac12, qdss_cti_trig_in_a0, NA, NA, NA,
> + NA, NA),
> + PINGROUP(12, qpic_pad1, qdss_cti_trig_out_a0, NA, NA, NA, NA, NA, NA,
> + NA),
> + PINGROUP(13, qpic_pad2, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(14, qpic_pad3, qdss_traceclk_b, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(15, qpic_pad0, qdss_tracectl_b, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(16, qpic_pad8, blsp5_uart, pcm_zsi1, blsp5_spi, cxc0, mac13,
> + qdss_tracedata_b, NA, NA),
> + PINGROUP(17, qpic_pad, wci22, qdss_tracedata_b, NA, NA, NA, NA, NA, NA),
> + PINGROUP(18, led0, pwm04, qdss_tracedata_b, NA, NA, NA, NA, NA, NA),
> + PINGROUP(19, led1, pwm14, NA, qdss_tracedata_b, NA, NA, NA, NA, NA),
> + PINGROUP(20, led2, pwm24, NA, qdss_tracedata_b, NA, NA, NA, NA, NA),
> + PINGROUP(21, pwm00, blsp4_uart1, blsp4_i2c1, blsp4_spi1, wci23, mac11,
> + blsp3_spi2, NA, qdss_tracedata_b),
> + PINGROUP(22, pwm10, blsp4_uart1, blsp4_i2c1, blsp4_spi1, wci23, mac11,
> + blsp3_spi2, NA, qdss_tracedata_b),
> + PINGROUP(23, pwm20, blsp4_uart1, blsp4_spi1, blsp3_spi2, NA,
> + qdss_tracedata_b, NA, NA, NA),
> + PINGROUP(24, pwm30, blsp4_uart1, blsp4_spi1, NA, qdss_tracedata_b, NA,
> + NA, NA, NA),
> + PINGROUP(25, audio_txmclk, pwm02, NA, qdss_tracedata_b, NA, NA, NA, NA,
> + NA),
> + PINGROUP(26, audio_txbclk, pwm12, NA, qdss_tracedata_b, NA, NA, NA, NA,
> + NA),
> + PINGROUP(27, audio_txfsync, pwm22, NA, qdss_tracedata_b, NA, NA, NA,
> + NA, NA),
> + PINGROUP(28, audio_txd, pwm32, NA, qdss_tracedata_b, NA, NA, NA, NA,
> + NA),
> + PINGROUP(29, audio_rxmclk, pwm03, atest_char0, NA, qdss_tracedata_b,
> + NA, NA, NA, NA),
> + PINGROUP(30, audio_rxbclk, pwm13, atest_char1, NA, qdss_tracedata_b,
> + NA, NA, NA, NA),
> + PINGROUP(31, audio_rxfsync, pwm23, atest_char2, NA, qdss_tracedata_b,
> + NA, NA, NA, NA),
> + PINGROUP(32, audio_rxd, pwm33, atest_char3, NA, NA, NA, NA, NA, NA),
> + PINGROUP(33, pcm_drx, mac10, mac00, NA, NA, NA, NA, NA, NA),
> + PINGROUP(34, pcm_dtx, mac10, mac00, NA, NA, NA, NA, NA, NA),
> + PINGROUP(35, pcm_fsync, mac20, qdss_traceclk_a, NA, NA, NA, NA, NA, NA),
> + PINGROUP(36, pcm_pclk, mac20, NA, qdss_tracectl_a, NA, NA, NA, NA, NA),
> + PINGROUP(37, atest_char, NA, qdss_tracedata_a, NA, NA, NA, NA, NA, NA),
> + PINGROUP(38, blsp0_uart, blsp0_i2c, blsp0_spi, NA, qdss_tracedata_a,
> + NA, NA, NA, NA),
> + PINGROUP(39, blsp0_uart, blsp0_i2c, blsp0_spi, NA, qdss_tracedata_a,
> + NA, NA, NA, NA),
> + PINGROUP(40, blsp0_uart, blsp0_spi, NA, qdss_tracedata_a, NA, NA, NA,
> + NA, NA),
> + PINGROUP(41, blsp0_uart, blsp0_spi, NA, qdss_tracedata_a, NA, NA, NA,
> + NA, NA),
> + PINGROUP(42, blsp1_uart, blsp1_i2c, blsp1_spi, NA, qdss_tracedata_a,
> + NA, NA, NA, NA),
> + PINGROUP(43, blsp1_uart, blsp1_i2c, blsp1_spi, NA, qdss_tracedata_a,
> + NA, NA, NA, NA),
> + PINGROUP(44, blsp1_uart, blsp1_spi, NA, qdss_tracedata_a, NA, NA, NA,
> + NA, NA),
> + PINGROUP(45, blsp1_uart, blsp1_spi, qdss_tracedata_a, NA, NA, NA, NA,
> + NA, NA),
> + PINGROUP(46, blsp2_uart, blsp2_i2c, blsp2_spi, qdss_tracedata_a, NA,
> + NA, NA, NA, NA),
> + PINGROUP(47, blsp2_uart, blsp2_i2c, blsp2_spi, NA, qdss_tracedata_a,
> + NA, NA, NA, NA),
> + PINGROUP(48, blsp2_uart, blsp2_spi, NA, qdss_tracedata_a, NA, NA, NA,
> + NA, NA),
> + PINGROUP(49, blsp2_uart, blsp2_spi, NA, qdss_tracedata_a, NA, NA, NA,
> + NA, NA),
> + PINGROUP(50, blsp3_uart, blsp3_i2c, blsp3_spi, NA, qdss_tracedata_a,
> + NA, NA, NA, NA),
> + PINGROUP(51, blsp3_uart, blsp3_i2c, blsp3_spi, NA, qdss_tracedata_a,
> + NA, NA, NA, NA),
> + PINGROUP(52, blsp3_uart, blsp3_spi, NA, qdss_tracedata_a, NA, NA, NA,
> + NA, NA),
> + PINGROUP(53, blsp3_uart, blsp3_spi, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(54, pta2_0, wci21, cxc1, blsp3_spi1, NA, NA, NA, NA, NA),
> + PINGROUP(55, pta2_1, blsp3_spi1, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(56, pta2_2, wci21, cxc1, blsp3_spi1, NA, NA, NA, NA, NA),
> + PINGROUP(57, pcie0_clk, NA, dbg_out, cri_trng0, NA, NA, NA, NA, NA),
> + PINGROUP(58, pcie0_rst, NA, cri_trng1, NA, NA, NA, NA, NA, NA),
> + PINGROUP(59, pcie0_wake, NA, cri_trng, NA, NA, NA, NA, NA, NA),
> + PINGROUP(60, pcie1_clk, rx2, ldo_update, NA, NA, NA, NA, NA, NA),
> + PINGROUP(61, pcie1_rst, ldo_en, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(62, pcie1_wake, gcc_plltest, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(63, sd_card, pwm01, NA, gcc_plltest, NA, NA, NA, NA, NA),
> + PINGROUP(64, pta1_1, pwm11, NA, rx1, NA, NA, NA, NA, NA),
> + PINGROUP(65, pta1_2, NA, gcc_tlmm, NA, NA, NA, NA, NA, NA),
> + PINGROUP(66, pta1_0, pwm21, prng_rosc, NA, NA, NA, NA, NA, NA),
> + PINGROUP(67, sd_write, pwm31, rx0, tsens_max, NA, NA, NA, NA, NA),
> + PINGROUP(68, mdc, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(69, mdio, NA, NA, NA, NA, NA, NA, NA, NA),
> +};
> +
> +static const struct msm_pinctrl_soc_data ipq8074_pinctrl = {
> + .pins = ipq8074_pins,
> + .npins = ARRAY_SIZE(ipq8074_pins),
> + .functions = ipq8074_functions,
> + .nfunctions = ARRAY_SIZE(ipq8074_functions),
> + .groups = ipq8074_groups,
> + .ngroups = ARRAY_SIZE(ipq8074_groups),
> + .ngpios = 70,
> +};
> +
> +static int ipq8074_pinctrl_probe(struct platform_device *pdev)
> +{
> + return msm_pinctrl_probe(pdev, &ipq8074_pinctrl);
> +}
> +
> +static const struct of_device_id ipq8074_pinctrl_of_match[] = {
> + { .compatible = "qcom,ipq8074-pinctrl", },
> + { },
> +};
> +
> +static struct platform_driver ipq8074_pinctrl_driver = {
> + .driver = {
> + .name = "ipq8074-pinctrl",
> + .of_match_table = ipq8074_pinctrl_of_match,
> + },
> + .probe = ipq8074_pinctrl_probe,
> + .remove = msm_pinctrl_remove,
> +};
> +
> +static int __init ipq8074_pinctrl_init(void)
> +{
> + return platform_driver_register(&ipq8074_pinctrl_driver);
> +}
> +arch_initcall(ipq8074_pinctrl_init);
> +
> +static void __exit ipq8074_pinctrl_exit(void)
> +{
> + platform_driver_unregister(&ipq8074_pinctrl_driver);
> +}
> +module_exit(ipq8074_pinctrl_exit);
> +
> +MODULE_DESCRIPTION("Qualcomm ipq8074 pinctrl driver");
> +MODULE_LICENSE("GPL v2");
> +MODULE_DEVICE_TABLE(of, ipq8074_pinctrl_of_match);
>
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum, a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
@ 2017-05-08 5:49 ` Varadarajan Narayanan
0 siblings, 0 replies; 49+ messages in thread
From: Varadarajan Narayanan @ 2017-05-08 5:49 UTC (permalink / raw)
To: linux-arm-kernel
+ Bjorn Andersson
On 5/4/2017 5:23 PM, Varadarajan Narayanan wrote:
> Add initial pinctrl driver to support pin configuration with
> pinctrl framework for ipq8074.
>
> Signed-off-by: Manoharan Vijaya Raghavan <mraghava@codeaurora.org>
> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
> ---
> .../bindings/pinctrl/qcom,ipq8074-pinctrl.txt | 187 +++
> drivers/pinctrl/qcom/Kconfig | 10 +
> drivers/pinctrl/qcom/Makefile | 1 +
> drivers/pinctrl/qcom/pinctrl-ipq8074.c | 1217 ++++++++++++++++++++
> 4 files changed, 1415 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
> create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq8074.c
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
> new file mode 100644
> index 0000000..7765bca
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
> @@ -0,0 +1,187 @@
> +Qualcomm Technologies, Inc. IPQ8074 TLMM block
> +
> +This binding describes the Top Level Mode Multiplexer block found in the
> +IPQ8074 platform.
> +
> +- compatible:
> + Usage: required
> + Value type: <string>
> + Definition: must be "qcom,ipq8074-pinctrl"
> +
> +- reg:
> + Usage: required
> + Value type: <prop-encoded-array>
> + Definition: the base address and size of the TLMM register space.
> +
> +- interrupts:
> + Usage: required
> + Value type: <prop-encoded-array>
> + Definition: should specify the TLMM summary IRQ.
> +
> +- interrupt-controller:
> + Usage: required
> + Value type: <none>
> + Definition: identifies this node as an interrupt controller
> +
> +- #interrupt-cells:
> + Usage: required
> + Value type: <u32>
> + Definition: must be 2. Specifying the pin number and flags, as defined
> + in <dt-bindings/interrupt-controller/irq.h>
> +
> +- gpio-controller:
> + Usage: required
> + Value type: <none>
> + Definition: identifies this node as a gpio controller
> +
> +- #gpio-cells:
> + Usage: required
> + Value type: <u32>
> + Definition: must be 2. Specifying the pin number and flags, as defined
> + in <dt-bindings/gpio/gpio.h>
> +
> +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
> +a general description of GPIO and interrupt bindings.
> +
> +Please refer to pinctrl-bindings.txt in this directory for details of the
> +common pinctrl bindings used by client devices, including the meaning of the
> +phrase "pin configuration node".
> +
> +The pin configuration nodes act as a container for an arbitrary number of
> +subnodes. Each of these subnodes represents some desired configuration for a
> +pin, a group, or a list of pins or groups. This configuration can include the
> +mux function to select on those pin(s)/group(s), and various pin configuration
> +parameters, such as pull-up, drive strength, etc.
> +
> +
> +PIN CONFIGURATION NODES:
> +
> +The name of each subnode is not important; all subnodes should be enumerated
> +and processed purely based on their content.
> +
> +Each subnode only affects those parameters that are explicitly listed. In
> +other words, a subnode that lists a mux function but no pin configuration
> +parameters implies no information about any pin configuration parameters.
> +Similarly, a pin subnode that describes a pullup parameter implies no
> +information about e.g. the mux function.
> +
> +
> +The following generic properties as defined in pinctrl-bindings.txt are valid
> +to specify in a pin configuration subnode:
> +
> +- pins:
> + Usage: required
> + Value type: <string-array>
> + Definition: List of gpio pins affected by the properties specified in
> + this subnode. Valid pins are:
> + gpio0-gpio121,
> + sdc1_clk,
> + sdc1_cmd,
> + sdc1_data
> + sdc2_clk,
> + sdc2_cmd,
> + sdc2_data,
> + qdsd_cmd,
> + qdsd_data0,
> + qdsd_data1,
> + qdsd_data2,
> + qdsd_data3
> +
> +- function:
> + Usage: required
> + Value type: <string>
> + Definition: Specify the alternative function to be configured for the
> + specified pins. Functions are only valid for gpio pins.
> + Valid values are:
> + gpio, qpic_pad, blsp5_i2c, blsp5_spi, wci20, blsp3_spi3,
> + burn0, pcm_zsi0, blsp5_uart, mac12, blsp3_spi0, burn1, mac01,
> + qdss_cti_trig_out_b0, qdss_cti_trig_in_b0, qpic_pad4,
> + blsp4_uart0, blsp4_i2c0, blsp4_spi0, mac21,
> + qdss_cti_trig_out_b1, qpic_pad5, qdss_cti_trig_in_b1,
> + qpic_pad6, qpic_pad7, cxc0, mac13, qdss_cti_trig_in_a1,
> + qdss_cti_trig_out_a1, wci22, qdss_cti_trig_in_a0, qpic_pad1,
> + qdss_cti_trig_out_a0, qpic_pad2, qpic_pad3, qdss_traceclk_b,
> + qpic_pad0, qdss_tracectl_b, qpic_pad8, pcm_zsi1,
> + qdss_tracedata_b, led0, pwm04, led1, pwm14, led2, pwm24,
> + pwm00, blsp4_uart1, blsp4_i2c1, blsp4_spi1, wci23, mac11,
> + blsp3_spi2, pwm10, pwm20, pwm30, audio_txmclk, pwm02,
> + audio_txbclk, pwm12, audio_txfsync, pwm22, audio_txd, pwm32,
> + audio_rxmclk, pwm03, atest_char0, audio_rxbclk, pwm13,
> + atest_char1, audio_rxfsync, pwm23, atest_char2, audio_rxd,
> + pwm33, atest_char3, pcm_drx, mac10, mac00, pcm_dtx, pcm_fsync,
> + mac20, qdss_traceclk_a, pcm_pclk, qdss_tracectl_a, atest_char,
> + qdss_tracedata_a, blsp0_uart, blsp0_i2c, blsp0_spi,
> + blsp1_uart, blsp1_i2c, blsp1_spi, blsp2_uart, blsp2_i2c,
> + blsp2_spi, blsp3_uart, blsp3_i2c, blsp3_spi, pta2_0, wci21,
> + cxc1, blsp3_spi1, pta2_1, pta2_2, pcie0_clk, dbg_out,
> + cri_trng0, pcie0_rst, cri_trng1, pcie0_wake, cri_trng,
> + pcie1_clk, rx2, ldo_update, pcie1_rst, ldo_en, pcie1_wake,
> + gcc_plltest, sd_card, pwm01, pta1_1, pwm11, rx1, pta1_2,
> + gcc_tlmm, pta1_0, pwm21, prng_rosc, sd_write, pwm31, rx0,
> + tsens_max, mdc, mdio, NA
> +
> +- bias-disable:
> + Usage: optional
> + Value type: <none>
> + Definition: The specified pins should be configued as no pull.
> +
> +- bias-pull-down:
> + Usage: optional
> + Value type: <none>
> + Definition: The specified pins should be configued as pull down.
> +
> +- bias-pull-up:
> + Usage: optional
> + Value type: <none>
> + Definition: The specified pins should be configued as pull up.
> +
> +- output-high:
> + Usage: optional
> + Value type: <none>
> + Definition: The specified pins are configured in output mode, driven
> + high.
> + Not valid for sdc pins.
> +
> +- output-low:
> + Usage: optional
> + Value type: <none>
> + Definition: The specified pins are configured in output mode, driven
> + low.
> + Not valid for sdc pins.
> +
> +- drive-strength:
> + Usage: optional
> + Value type: <u32>
> + Definition: Selects the drive strength for the specified pins, in mA.
> + Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
> +
> +Example:
> +
> + tlmm: pinctrl at 1000000 {
> + compatible = "qcom,ipq8074-pinctrl";
> + reg = <0x1000000 0x300000>;
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + uart2: uart2-default {
> + mux {
> + pins = "gpio23", "gpio24";
> + function = "blsp4_uart1";
> + };
> +
> + rx {
> + pins = "gpio23";
> + drive-strength = <4>;
> + bias-disable;
> + };
> +
> + tx {
> + pins = "gpio24";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> + };
> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
> index 3ebdc01..9e504db 100644
> --- a/drivers/pinctrl/qcom/Kconfig
> +++ b/drivers/pinctrl/qcom/Kconfig
> @@ -39,6 +39,16 @@ config PINCTRL_IPQ8064
> This is the pinctrl, pinmux, pinconf and gpiolib driver for the
> Qualcomm TLMM block found in the Qualcomm IPQ8064 platform.
>
> +config PINCTRL_IPQ8074
> + tristate "Qualcomm Technologies, Inc. IPQ8074 pin controller driver"
> + depends on GPIOLIB && OF
> + select PINCTRL_MSM
> + help
> + This is the pinctrl, pinmux, pinconf and gpiolib driver for
> + the Qualcomm Technologies Inc. TLMM block found on the
> + Qualcomm Technologies Inc. IPQ8074 platform. Select this for
> + IPQ8074.
> +
> config PINCTRL_MSM8660
> tristate "Qualcomm 8660 pin controller driver"
> depends on GPIOLIB && OF
> diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
> index ab47764..06c8b2a 100644
> --- a/drivers/pinctrl/qcom/Makefile
> +++ b/drivers/pinctrl/qcom/Makefile
> @@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
> obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
> obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o
> obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
> +obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o
> obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o
> obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o
> obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
> diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8074.c b/drivers/pinctrl/qcom/pinctrl-ipq8074.c
> new file mode 100644
> index 0000000..8bb8071
> --- /dev/null
> +++ b/drivers/pinctrl/qcom/pinctrl-ipq8074.c
> @@ -0,0 +1,1217 @@
> +/*
> + * Copyright (c) 2017, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/pinctrl/pinctrl.h>
> +
> +#include "pinctrl-msm.h"
> +
> +#define FUNCTION(fname) \
> + [msm_mux_##fname] = { \
> + .name = #fname, \
> + .groups = fname##_groups, \
> + .ngroups = ARRAY_SIZE(fname##_groups), \
> + }
> +
> +#define REG_SIZE 0x1000
> +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
> + { \
> + .name = "gpio" #id, \
> + .pins = gpio##id##_pins, \
> + .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
> + .funcs = (int[]){ \
> + msm_mux_gpio, /* gpio mode */ \
> + msm_mux_##f1, \
> + msm_mux_##f2, \
> + msm_mux_##f3, \
> + msm_mux_##f4, \
> + msm_mux_##f5, \
> + msm_mux_##f6, \
> + msm_mux_##f7, \
> + msm_mux_##f8, \
> + msm_mux_##f9 \
> + }, \
> + .nfuncs = 10, \
> + .ctl_reg = REG_SIZE * id, \
> + .io_reg = 0x4 + REG_SIZE * id, \
> + .intr_cfg_reg = 0x8 + REG_SIZE * id, \
> + .intr_status_reg = 0xc + REG_SIZE * id, \
> + .intr_target_reg = 0x8 + REG_SIZE * id, \
> + .mux_bit = 2, \
> + .pull_bit = 0, \
> + .drv_bit = 6, \
> + .oe_bit = 9, \
> + .in_bit = 0, \
> + .out_bit = 1, \
> + .intr_enable_bit = 0, \
> + .intr_status_bit = 0, \
> + .intr_target_bit = 5, \
> + .intr_raw_status_bit = 4, \
> + .intr_polarity_bit = 1, \
> + .intr_detection_bit = 2, \
> + .intr_detection_width = 2, \
> + }
> +
> +static const struct pinctrl_pin_desc ipq8074_pins[] = {
> + PINCTRL_PIN(0, "GPIO_0"),
> + PINCTRL_PIN(1, "GPIO_1"),
> + PINCTRL_PIN(2, "GPIO_2"),
> + PINCTRL_PIN(3, "GPIO_3"),
> + PINCTRL_PIN(4, "GPIO_4"),
> + PINCTRL_PIN(5, "GPIO_5"),
> + PINCTRL_PIN(6, "GPIO_6"),
> + PINCTRL_PIN(7, "GPIO_7"),
> + PINCTRL_PIN(8, "GPIO_8"),
> + PINCTRL_PIN(9, "GPIO_9"),
> + PINCTRL_PIN(10, "GPIO_10"),
> + PINCTRL_PIN(11, "GPIO_11"),
> + PINCTRL_PIN(12, "GPIO_12"),
> + PINCTRL_PIN(13, "GPIO_13"),
> + PINCTRL_PIN(14, "GPIO_14"),
> + PINCTRL_PIN(15, "GPIO_15"),
> + PINCTRL_PIN(16, "GPIO_16"),
> + PINCTRL_PIN(17, "GPIO_17"),
> + PINCTRL_PIN(18, "GPIO_18"),
> + PINCTRL_PIN(19, "GPIO_19"),
> + PINCTRL_PIN(20, "GPIO_20"),
> + PINCTRL_PIN(21, "GPIO_21"),
> + PINCTRL_PIN(22, "GPIO_22"),
> + PINCTRL_PIN(23, "GPIO_23"),
> + PINCTRL_PIN(24, "GPIO_24"),
> + PINCTRL_PIN(25, "GPIO_25"),
> + PINCTRL_PIN(26, "GPIO_26"),
> + PINCTRL_PIN(27, "GPIO_27"),
> + PINCTRL_PIN(28, "GPIO_28"),
> + PINCTRL_PIN(29, "GPIO_29"),
> + PINCTRL_PIN(30, "GPIO_30"),
> + PINCTRL_PIN(31, "GPIO_31"),
> + PINCTRL_PIN(32, "GPIO_32"),
> + PINCTRL_PIN(33, "GPIO_33"),
> + PINCTRL_PIN(34, "GPIO_34"),
> + PINCTRL_PIN(35, "GPIO_35"),
> + PINCTRL_PIN(36, "GPIO_36"),
> + PINCTRL_PIN(37, "GPIO_37"),
> + PINCTRL_PIN(38, "GPIO_38"),
> + PINCTRL_PIN(39, "GPIO_39"),
> + PINCTRL_PIN(40, "GPIO_40"),
> + PINCTRL_PIN(41, "GPIO_41"),
> + PINCTRL_PIN(42, "GPIO_42"),
> + PINCTRL_PIN(43, "GPIO_43"),
> + PINCTRL_PIN(44, "GPIO_44"),
> + PINCTRL_PIN(45, "GPIO_45"),
> + PINCTRL_PIN(46, "GPIO_46"),
> + PINCTRL_PIN(47, "GPIO_47"),
> + PINCTRL_PIN(48, "GPIO_48"),
> + PINCTRL_PIN(49, "GPIO_49"),
> + PINCTRL_PIN(50, "GPIO_50"),
> + PINCTRL_PIN(51, "GPIO_51"),
> + PINCTRL_PIN(52, "GPIO_52"),
> + PINCTRL_PIN(53, "GPIO_53"),
> + PINCTRL_PIN(54, "GPIO_54"),
> + PINCTRL_PIN(55, "GPIO_55"),
> + PINCTRL_PIN(56, "GPIO_56"),
> + PINCTRL_PIN(57, "GPIO_57"),
> + PINCTRL_PIN(58, "GPIO_58"),
> + PINCTRL_PIN(59, "GPIO_59"),
> + PINCTRL_PIN(60, "GPIO_60"),
> + PINCTRL_PIN(61, "GPIO_61"),
> + PINCTRL_PIN(62, "GPIO_62"),
> + PINCTRL_PIN(63, "GPIO_63"),
> + PINCTRL_PIN(64, "GPIO_64"),
> + PINCTRL_PIN(65, "GPIO_65"),
> + PINCTRL_PIN(66, "GPIO_66"),
> + PINCTRL_PIN(67, "GPIO_67"),
> + PINCTRL_PIN(68, "GPIO_68"),
> + PINCTRL_PIN(69, "GPIO_69"),
> +};
> +
> +#define DECLARE_MSM_GPIO_PINS(pin) \
> + static const unsigned int gpio##pin##_pins[] = { pin }
> +DECLARE_MSM_GPIO_PINS(0);
> +DECLARE_MSM_GPIO_PINS(1);
> +DECLARE_MSM_GPIO_PINS(2);
> +DECLARE_MSM_GPIO_PINS(3);
> +DECLARE_MSM_GPIO_PINS(4);
> +DECLARE_MSM_GPIO_PINS(5);
> +DECLARE_MSM_GPIO_PINS(6);
> +DECLARE_MSM_GPIO_PINS(7);
> +DECLARE_MSM_GPIO_PINS(8);
> +DECLARE_MSM_GPIO_PINS(9);
> +DECLARE_MSM_GPIO_PINS(10);
> +DECLARE_MSM_GPIO_PINS(11);
> +DECLARE_MSM_GPIO_PINS(12);
> +DECLARE_MSM_GPIO_PINS(13);
> +DECLARE_MSM_GPIO_PINS(14);
> +DECLARE_MSM_GPIO_PINS(15);
> +DECLARE_MSM_GPIO_PINS(16);
> +DECLARE_MSM_GPIO_PINS(17);
> +DECLARE_MSM_GPIO_PINS(18);
> +DECLARE_MSM_GPIO_PINS(19);
> +DECLARE_MSM_GPIO_PINS(20);
> +DECLARE_MSM_GPIO_PINS(21);
> +DECLARE_MSM_GPIO_PINS(22);
> +DECLARE_MSM_GPIO_PINS(23);
> +DECLARE_MSM_GPIO_PINS(24);
> +DECLARE_MSM_GPIO_PINS(25);
> +DECLARE_MSM_GPIO_PINS(26);
> +DECLARE_MSM_GPIO_PINS(27);
> +DECLARE_MSM_GPIO_PINS(28);
> +DECLARE_MSM_GPIO_PINS(29);
> +DECLARE_MSM_GPIO_PINS(30);
> +DECLARE_MSM_GPIO_PINS(31);
> +DECLARE_MSM_GPIO_PINS(32);
> +DECLARE_MSM_GPIO_PINS(33);
> +DECLARE_MSM_GPIO_PINS(34);
> +DECLARE_MSM_GPIO_PINS(35);
> +DECLARE_MSM_GPIO_PINS(36);
> +DECLARE_MSM_GPIO_PINS(37);
> +DECLARE_MSM_GPIO_PINS(38);
> +DECLARE_MSM_GPIO_PINS(39);
> +DECLARE_MSM_GPIO_PINS(40);
> +DECLARE_MSM_GPIO_PINS(41);
> +DECLARE_MSM_GPIO_PINS(42);
> +DECLARE_MSM_GPIO_PINS(43);
> +DECLARE_MSM_GPIO_PINS(44);
> +DECLARE_MSM_GPIO_PINS(45);
> +DECLARE_MSM_GPIO_PINS(46);
> +DECLARE_MSM_GPIO_PINS(47);
> +DECLARE_MSM_GPIO_PINS(48);
> +DECLARE_MSM_GPIO_PINS(49);
> +DECLARE_MSM_GPIO_PINS(50);
> +DECLARE_MSM_GPIO_PINS(51);
> +DECLARE_MSM_GPIO_PINS(52);
> +DECLARE_MSM_GPIO_PINS(53);
> +DECLARE_MSM_GPIO_PINS(54);
> +DECLARE_MSM_GPIO_PINS(55);
> +DECLARE_MSM_GPIO_PINS(56);
> +DECLARE_MSM_GPIO_PINS(57);
> +DECLARE_MSM_GPIO_PINS(58);
> +DECLARE_MSM_GPIO_PINS(59);
> +DECLARE_MSM_GPIO_PINS(60);
> +DECLARE_MSM_GPIO_PINS(61);
> +DECLARE_MSM_GPIO_PINS(62);
> +DECLARE_MSM_GPIO_PINS(63);
> +DECLARE_MSM_GPIO_PINS(64);
> +DECLARE_MSM_GPIO_PINS(65);
> +DECLARE_MSM_GPIO_PINS(66);
> +DECLARE_MSM_GPIO_PINS(67);
> +DECLARE_MSM_GPIO_PINS(68);
> +DECLARE_MSM_GPIO_PINS(69);
> +
> +enum ipq8074_functions {
> + msm_mux_gpio,
> + msm_mux_qpic_pad,
> + msm_mux_blsp5_i2c,
> + msm_mux_blsp5_spi,
> + msm_mux_wci20,
> + msm_mux_blsp3_spi3,
> + msm_mux_burn0,
> + msm_mux_pcm_zsi0,
> + msm_mux_blsp5_uart,
> + msm_mux_mac12,
> + msm_mux_blsp3_spi0,
> + msm_mux_burn1,
> + msm_mux_mac01,
> + msm_mux_qdss_cti_trig_out_b0,
> + msm_mux_qdss_cti_trig_in_b0,
> + msm_mux_qpic_pad4,
> + msm_mux_blsp4_uart0,
> + msm_mux_blsp4_i2c0,
> + msm_mux_blsp4_spi0,
> + msm_mux_mac21,
> + msm_mux_qdss_cti_trig_out_b1,
> + msm_mux_qpic_pad5,
> + msm_mux_qdss_cti_trig_in_b1,
> + msm_mux_qpic_pad6,
> + msm_mux_qpic_pad7,
> + msm_mux_cxc0,
> + msm_mux_mac13,
> + msm_mux_qdss_cti_trig_in_a1,
> + msm_mux_qdss_cti_trig_out_a1,
> + msm_mux_wci22,
> + msm_mux_qdss_cti_trig_in_a0,
> + msm_mux_qpic_pad1,
> + msm_mux_qdss_cti_trig_out_a0,
> + msm_mux_qpic_pad2,
> + msm_mux_qpic_pad3,
> + msm_mux_qdss_traceclk_b,
> + msm_mux_qpic_pad0,
> + msm_mux_qdss_tracectl_b,
> + msm_mux_qpic_pad8,
> + msm_mux_pcm_zsi1,
> + msm_mux_qdss_tracedata_b,
> + msm_mux_led0,
> + msm_mux_pwm04,
> + msm_mux_led1,
> + msm_mux_pwm14,
> + msm_mux_led2,
> + msm_mux_pwm24,
> + msm_mux_pwm00,
> + msm_mux_blsp4_uart1,
> + msm_mux_blsp4_i2c1,
> + msm_mux_blsp4_spi1,
> + msm_mux_wci23,
> + msm_mux_mac11,
> + msm_mux_blsp3_spi2,
> + msm_mux_pwm10,
> + msm_mux_pwm20,
> + msm_mux_pwm30,
> + msm_mux_audio_txmclk,
> + msm_mux_pwm02,
> + msm_mux_audio_txbclk,
> + msm_mux_pwm12,
> + msm_mux_audio_txfsync,
> + msm_mux_pwm22,
> + msm_mux_audio_txd,
> + msm_mux_pwm32,
> + msm_mux_audio_rxmclk,
> + msm_mux_pwm03,
> + msm_mux_atest_char0,
> + msm_mux_audio_rxbclk,
> + msm_mux_pwm13,
> + msm_mux_atest_char1,
> + msm_mux_audio_rxfsync,
> + msm_mux_pwm23,
> + msm_mux_atest_char2,
> + msm_mux_audio_rxd,
> + msm_mux_pwm33,
> + msm_mux_atest_char3,
> + msm_mux_pcm_drx,
> + msm_mux_mac10,
> + msm_mux_mac00,
> + msm_mux_pcm_dtx,
> + msm_mux_pcm_fsync,
> + msm_mux_mac20,
> + msm_mux_qdss_traceclk_a,
> + msm_mux_pcm_pclk,
> + msm_mux_qdss_tracectl_a,
> + msm_mux_atest_char,
> + msm_mux_qdss_tracedata_a,
> + msm_mux_blsp0_uart,
> + msm_mux_blsp0_i2c,
> + msm_mux_blsp0_spi,
> + msm_mux_blsp1_uart,
> + msm_mux_blsp1_i2c,
> + msm_mux_blsp1_spi,
> + msm_mux_blsp2_uart,
> + msm_mux_blsp2_i2c,
> + msm_mux_blsp2_spi,
> + msm_mux_blsp3_uart,
> + msm_mux_blsp3_i2c,
> + msm_mux_blsp3_spi,
> + msm_mux_pta2_0,
> + msm_mux_wci21,
> + msm_mux_cxc1,
> + msm_mux_blsp3_spi1,
> + msm_mux_pta2_1,
> + msm_mux_pta2_2,
> + msm_mux_pcie0_clk,
> + msm_mux_dbg_out,
> + msm_mux_cri_trng0,
> + msm_mux_pcie0_rst,
> + msm_mux_cri_trng1,
> + msm_mux_pcie0_wake,
> + msm_mux_cri_trng,
> + msm_mux_pcie1_clk,
> + msm_mux_rx2,
> + msm_mux_ldo_update,
> + msm_mux_pcie1_rst,
> + msm_mux_ldo_en,
> + msm_mux_pcie1_wake,
> + msm_mux_gcc_plltest,
> + msm_mux_sd_card,
> + msm_mux_pwm01,
> + msm_mux_pta1_1,
> + msm_mux_pwm11,
> + msm_mux_rx1,
> + msm_mux_pta1_2,
> + msm_mux_gcc_tlmm,
> + msm_mux_pta1_0,
> + msm_mux_pwm21,
> + msm_mux_prng_rosc,
> + msm_mux_sd_write,
> + msm_mux_pwm31,
> + msm_mux_rx0,
> + msm_mux_tsens_max,
> + msm_mux_mdc,
> + msm_mux_mdio,
> + msm_mux_NA,
> +};
> +
> +static const char * const qpic_pad_groups[] = {
> + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio9", "gpio10",
> + "gpio11", "gpio17",
> +};
> +
> +static const char * const _groups[] = {
> + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
> + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
> + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
> + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
> + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
> + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
> + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
> + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
> + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
> + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69",
> +};
> +
> +static const char * const blsp5_i2c_groups[] = {
> + "gpio0", "gpio2",
> +};
> +
> +static const char * const blsp5_spi_groups[] = {
> + "gpio0", "gpio2", "gpio9", "gpio16",
> +};
> +
> +static const char * const wci20_groups[] = {
> + "gpio0", "gpio2",
> +};
> +
> +static const char * const blsp3_spi3_groups[] = {
> + "gpio0", "gpio2", "gpio9",
> +};
> +
> +static const char * const burn0_groups[] = {
> + "gpio0",
> +};
> +
> +static const char * const pcm_zsi0_groups[] = {
> + "gpio1",
> +};
> +
> +static const char * const blsp5_uart_groups[] = {
> + "gpio0", "gpio2", "gpio9", "gpio16",
> +};
> +
> +static const char * const mac12_groups[] = {
> + "gpio1", "gpio11",
> +};
> +
> +static const char * const blsp3_spi0_groups[] = {
> + "gpio1", "gpio3", "gpio4",
> +};
> +
> +static const char * const burn1_groups[] = {
> + "gpio1",
> +};
> +
> +static const char * const mac01_groups[] = {
> + "gpio3", "gpio4",
> +};
> +
> +static const char * const qdss_cti_trig_out_b0_groups[] = {
> + "gpio3",
> +};
> +
> +static const char * const qdss_cti_trig_in_b0_groups[] = {
> + "gpio4",
> +};
> +
> +static const char * const qpic_pad4_groups[] = {
> + "gpio5",
> +};
> +
> +static const char * const blsp4_uart0_groups[] = {
> + "gpio5", "gpio6", "gpio7", "gpio8",
> +};
> +
> +static const char * const blsp4_i2c0_groups[] = {
> + "gpio5", "gpio6",
> +};
> +
> +static const char * const blsp4_spi0_groups[] = {
> + "gpio5", "gpio6", "gpio7", "gpio8",
> +};
> +
> +static const char * const mac21_groups[] = {
> + "gpio5", "gpio6",
> +};
> +
> +static const char * const qdss_cti_trig_out_b1_groups[] = {
> + "gpio5",
> +};
> +
> +static const char * const qpic_pad5_groups[] = {
> + "gpio6",
> +};
> +
> +static const char * const qdss_cti_trig_in_b1_groups[] = {
> + "gpio6",
> +};
> +
> +static const char * const qpic_pad6_groups[] = {
> + "gpio7",
> +};
> +
> +static const char * const qpic_pad7_groups[] = {
> + "gpio8",
> +};
> +
> +static const char * const cxc0_groups[] = {
> + "gpio9", "gpio16",
> +};
> +
> +static const char * const mac13_groups[] = {
> + "gpio9", "gpio16",
> +};
> +
> +static const char * const qdss_cti_trig_in_a1_groups[] = {
> + "gpio9",
> +};
> +
> +static const char * const qdss_cti_trig_out_a1_groups[] = {
> + "gpio10",
> +};
> +
> +static const char * const wci22_groups[] = {
> + "gpio11", "gpio17",
> +};
> +
> +static const char * const qdss_cti_trig_in_a0_groups[] = {
> + "gpio11",
> +};
> +
> +static const char * const qpic_pad1_groups[] = {
> + "gpio12",
> +};
> +
> +static const char * const qdss_cti_trig_out_a0_groups[] = {
> + "gpio12",
> +};
> +
> +static const char * const qpic_pad2_groups[] = {
> + "gpio13",
> +};
> +
> +static const char * const qpic_pad3_groups[] = {
> + "gpio14",
> +};
> +
> +static const char * const qdss_traceclk_b_groups[] = {
> + "gpio14",
> +};
> +
> +static const char * const qpic_pad0_groups[] = {
> + "gpio15",
> +};
> +
> +static const char * const qdss_tracectl_b_groups[] = {
> + "gpio15",
> +};
> +
> +static const char * const qpic_pad8_groups[] = {
> + "gpio16",
> +};
> +
> +static const char * const pcm_zsi1_groups[] = {
> + "gpio16",
> +};
> +
> +static const char * const qdss_tracedata_b_groups[] = {
> + "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
> + "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
> + "gpio30", "gpio31",
> +};
> +
> +static const char * const led0_groups[] = {
> + "gpio18",
> +};
> +
> +static const char * const pwm04_groups[] = {
> + "gpio18",
> +};
> +
> +static const char * const led1_groups[] = {
> + "gpio19",
> +};
> +
> +static const char * const pwm14_groups[] = {
> + "gpio19",
> +};
> +
> +static const char * const led2_groups[] = {
> + "gpio20",
> +};
> +
> +static const char * const pwm24_groups[] = {
> + "gpio20",
> +};
> +
> +static const char * const pwm00_groups[] = {
> + "gpio21",
> +};
> +
> +static const char * const blsp4_uart1_groups[] = {
> + "gpio21", "gpio22", "gpio23", "gpio24",
> +};
> +
> +static const char * const blsp4_i2c1_groups[] = {
> + "gpio21", "gpio22",
> +};
> +
> +static const char * const blsp4_spi1_groups[] = {
> + "gpio21", "gpio22", "gpio23", "gpio24",
> +};
> +
> +static const char * const wci23_groups[] = {
> + "gpio21", "gpio22",
> +};
> +
> +static const char * const mac11_groups[] = {
> + "gpio21", "gpio22",
> +};
> +
> +static const char * const blsp3_spi2_groups[] = {
> + "gpio21", "gpio22", "gpio23",
> +};
> +
> +static const char * const pwm10_groups[] = {
> + "gpio22",
> +};
> +
> +static const char * const pwm20_groups[] = {
> + "gpio23",
> +};
> +
> +static const char * const pwm30_groups[] = {
> + "gpio24",
> +};
> +
> +static const char * const audio_txmclk_groups[] = {
> + "gpio25",
> +};
> +
> +static const char * const pwm02_groups[] = {
> + "gpio25",
> +};
> +
> +static const char * const audio_txbclk_groups[] = {
> + "gpio26",
> +};
> +
> +static const char * const pwm12_groups[] = {
> + "gpio26",
> +};
> +
> +static const char * const audio_txfsync_groups[] = {
> + "gpio27",
> +};
> +
> +static const char * const pwm22_groups[] = {
> + "gpio27",
> +};
> +
> +static const char * const audio_txd_groups[] = {
> + "gpio28",
> +};
> +
> +static const char * const pwm32_groups[] = {
> + "gpio28",
> +};
> +
> +static const char * const audio_rxmclk_groups[] = {
> + "gpio29",
> +};
> +
> +static const char * const pwm03_groups[] = {
> + "gpio29",
> +};
> +
> +static const char * const atest_char0_groups[] = {
> + "gpio29",
> +};
> +
> +static const char * const audio_rxbclk_groups[] = {
> + "gpio30",
> +};
> +
> +static const char * const pwm13_groups[] = {
> + "gpio30",
> +};
> +
> +static const char * const atest_char1_groups[] = {
> + "gpio30",
> +};
> +
> +static const char * const audio_rxfsync_groups[] = {
> + "gpio31",
> +};
> +
> +static const char * const pwm23_groups[] = {
> + "gpio31",
> +};
> +
> +static const char * const atest_char2_groups[] = {
> + "gpio31",
> +};
> +
> +static const char * const audio_rxd_groups[] = {
> + "gpio32",
> +};
> +
> +static const char * const pwm33_groups[] = {
> + "gpio32",
> +};
> +
> +static const char * const atest_char3_groups[] = {
> + "gpio32",
> +};
> +
> +static const char * const pcm_drx_groups[] = {
> + "gpio33",
> +};
> +
> +static const char * const mac10_groups[] = {
> + "gpio33", "gpio34",
> +};
> +
> +static const char * const mac00_groups[] = {
> + "gpio33", "gpio34",
> +};
> +
> +static const char * const pcm_dtx_groups[] = {
> + "gpio34",
> +};
> +
> +static const char * const pcm_fsync_groups[] = {
> + "gpio35",
> +};
> +
> +static const char * const mac20_groups[] = {
> + "gpio35", "gpio36",
> +};
> +
> +static const char * const qdss_traceclk_a_groups[] = {
> + "gpio35",
> +};
> +
> +static const char * const pcm_pclk_groups[] = {
> + "gpio36",
> +};
> +
> +static const char * const qdss_tracectl_a_groups[] = {
> + "gpio36",
> +};
> +
> +static const char * const atest_char_groups[] = {
> + "gpio37",
> +};
> +
> +static const char * const qdss_tracedata_a_groups[] = {
> + "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
> + "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", "gpio50",
> + "gpio51", "gpio52",
> +};
> +
> +static const char * const blsp0_uart_groups[] = {
> + "gpio38", "gpio39", "gpio40", "gpio41",
> +};
> +
> +static const char * const blsp0_i2c_groups[] = {
> + "gpio38", "gpio39",
> +};
> +
> +static const char * const blsp0_spi_groups[] = {
> + "gpio38", "gpio39", "gpio40", "gpio41",
> +};
> +
> +static const char * const blsp1_uart_groups[] = {
> + "gpio42", "gpio43", "gpio44", "gpio45",
> +};
> +
> +static const char * const blsp1_i2c_groups[] = {
> + "gpio42", "gpio43",
> +};
> +
> +static const char * const blsp1_spi_groups[] = {
> + "gpio42", "gpio43", "gpio44", "gpio45",
> +};
> +
> +static const char * const blsp2_uart_groups[] = {
> + "gpio46", "gpio47", "gpio48", "gpio49",
> +};
> +
> +static const char * const blsp2_i2c_groups[] = {
> + "gpio46", "gpio47",
> +};
> +
> +static const char * const blsp2_spi_groups[] = {
> + "gpio46", "gpio47", "gpio48", "gpio49",
> +};
> +
> +static const char * const blsp3_uart_groups[] = {
> + "gpio50", "gpio51", "gpio52", "gpio53",
> +};
> +
> +static const char * const blsp3_i2c_groups[] = {
> + "gpio50", "gpio51",
> +};
> +
> +static const char * const blsp3_spi_groups[] = {
> + "gpio50", "gpio51", "gpio52", "gpio53",
> +};
> +
> +static const char * const pta2_0_groups[] = {
> + "gpio54",
> +};
> +
> +static const char * const wci21_groups[] = {
> + "gpio54", "gpio56",
> +};
> +
> +static const char * const cxc1_groups[] = {
> + "gpio54", "gpio56",
> +};
> +
> +static const char * const blsp3_spi1_groups[] = {
> + "gpio54", "gpio55", "gpio56",
> +};
> +
> +static const char * const pta2_1_groups[] = {
> + "gpio55",
> +};
> +
> +static const char * const pta2_2_groups[] = {
> + "gpio56",
> +};
> +
> +static const char * const pcie0_clk_groups[] = {
> + "gpio57",
> +};
> +
> +static const char * const dbg_out_groups[] = {
> + "gpio57",
> +};
> +
> +static const char * const cri_trng0_groups[] = {
> + "gpio57",
> +};
> +
> +static const char * const pcie0_rst_groups[] = {
> + "gpio58",
> +};
> +
> +static const char * const cri_trng1_groups[] = {
> + "gpio58",
> +};
> +
> +static const char * const pcie0_wake_groups[] = {
> + "gpio59",
> +};
> +
> +static const char * const cri_trng_groups[] = {
> + "gpio59",
> +};
> +
> +static const char * const pcie1_clk_groups[] = {
> + "gpio60",
> +};
> +
> +static const char * const rx2_groups[] = {
> + "gpio60",
> +};
> +
> +static const char * const ldo_update_groups[] = {
> + "gpio60",
> +};
> +
> +static const char * const pcie1_rst_groups[] = {
> + "gpio61",
> +};
> +
> +static const char * const ldo_en_groups[] = {
> + "gpio61",
> +};
> +
> +static const char * const pcie1_wake_groups[] = {
> + "gpio62",
> +};
> +
> +static const char * const gcc_plltest_groups[] = {
> + "gpio62", "gpio63",
> +};
> +
> +static const char * const sd_card_groups[] = {
> + "gpio63",
> +};
> +
> +static const char * const pwm01_groups[] = {
> + "gpio63",
> +};
> +
> +static const char * const pta1_1_groups[] = {
> + "gpio64",
> +};
> +
> +static const char * const pwm11_groups[] = {
> + "gpio64",
> +};
> +
> +static const char * const rx1_groups[] = {
> + "gpio64",
> +};
> +
> +static const char * const pta1_2_groups[] = {
> + "gpio65",
> +};
> +
> +static const char * const gcc_tlmm_groups[] = {
> + "gpio65",
> +};
> +
> +static const char * const pta1_0_groups[] = {
> + "gpio66",
> +};
> +
> +static const char * const pwm21_groups[] = {
> + "gpio66",
> +};
> +
> +static const char * const prng_rosc_groups[] = {
> + "gpio66",
> +};
> +
> +static const char * const sd_write_groups[] = {
> + "gpio67",
> +};
> +
> +static const char * const pwm31_groups[] = {
> + "gpio67",
> +};
> +
> +static const char * const rx0_groups[] = {
> + "gpio67",
> +};
> +
> +static const char * const tsens_max_groups[] = {
> + "gpio67",
> +};
> +
> +static const char * const mdc_groups[] = {
> + "gpio68",
> +};
> +
> +static const char * const mdio_groups[] = {
> + "gpio69",
> +};
> +
> +static const char * const gpio_groups[] = {
> + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
> + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
> + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
> + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
> + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
> + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
> + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
> + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
> + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
> + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69",
> +};
> +
> +static const struct msm_function ipq8074_functions[] = {
> + FUNCTION(gpio),
> + FUNCTION(qpic_pad),
> + FUNCTION(blsp5_i2c),
> + FUNCTION(blsp5_spi),
> + FUNCTION(wci20),
> + FUNCTION(blsp3_spi3),
> + FUNCTION(burn0),
> + FUNCTION(pcm_zsi0),
> + FUNCTION(blsp5_uart),
> + FUNCTION(mac12),
> + FUNCTION(blsp3_spi0),
> + FUNCTION(burn1),
> + FUNCTION(mac01),
> + FUNCTION(qdss_cti_trig_out_b0),
> + FUNCTION(qdss_cti_trig_in_b0),
> + FUNCTION(qpic_pad4),
> + FUNCTION(blsp4_uart0),
> + FUNCTION(blsp4_i2c0),
> + FUNCTION(blsp4_spi0),
> + FUNCTION(mac21),
> + FUNCTION(qdss_cti_trig_out_b1),
> + FUNCTION(qpic_pad5),
> + FUNCTION(qdss_cti_trig_in_b1),
> + FUNCTION(qpic_pad6),
> + FUNCTION(qpic_pad7),
> + FUNCTION(cxc0),
> + FUNCTION(mac13),
> + FUNCTION(qdss_cti_trig_in_a1),
> + FUNCTION(qdss_cti_trig_out_a1),
> + FUNCTION(wci22),
> + FUNCTION(qdss_cti_trig_in_a0),
> + FUNCTION(qpic_pad1),
> + FUNCTION(qdss_cti_trig_out_a0),
> + FUNCTION(qpic_pad2),
> + FUNCTION(qpic_pad3),
> + FUNCTION(qdss_traceclk_b),
> + FUNCTION(qpic_pad0),
> + FUNCTION(qdss_tracectl_b),
> + FUNCTION(qpic_pad8),
> + FUNCTION(pcm_zsi1),
> + FUNCTION(qdss_tracedata_b),
> + FUNCTION(led0),
> + FUNCTION(pwm04),
> + FUNCTION(led1),
> + FUNCTION(pwm14),
> + FUNCTION(led2),
> + FUNCTION(pwm24),
> + FUNCTION(pwm00),
> + FUNCTION(blsp4_uart1),
> + FUNCTION(blsp4_i2c1),
> + FUNCTION(blsp4_spi1),
> + FUNCTION(wci23),
> + FUNCTION(mac11),
> + FUNCTION(blsp3_spi2),
> + FUNCTION(pwm10),
> + FUNCTION(pwm20),
> + FUNCTION(pwm30),
> + FUNCTION(audio_txmclk),
> + FUNCTION(pwm02),
> + FUNCTION(audio_txbclk),
> + FUNCTION(pwm12),
> + FUNCTION(audio_txfsync),
> + FUNCTION(pwm22),
> + FUNCTION(audio_txd),
> + FUNCTION(pwm32),
> + FUNCTION(audio_rxmclk),
> + FUNCTION(pwm03),
> + FUNCTION(atest_char0),
> + FUNCTION(audio_rxbclk),
> + FUNCTION(pwm13),
> + FUNCTION(atest_char1),
> + FUNCTION(audio_rxfsync),
> + FUNCTION(pwm23),
> + FUNCTION(atest_char2),
> + FUNCTION(audio_rxd),
> + FUNCTION(pwm33),
> + FUNCTION(atest_char3),
> + FUNCTION(pcm_drx),
> + FUNCTION(mac10),
> + FUNCTION(mac00),
> + FUNCTION(pcm_dtx),
> + FUNCTION(pcm_fsync),
> + FUNCTION(mac20),
> + FUNCTION(qdss_traceclk_a),
> + FUNCTION(pcm_pclk),
> + FUNCTION(qdss_tracectl_a),
> + FUNCTION(atest_char),
> + FUNCTION(qdss_tracedata_a),
> + FUNCTION(blsp0_uart),
> + FUNCTION(blsp0_i2c),
> + FUNCTION(blsp0_spi),
> + FUNCTION(blsp1_uart),
> + FUNCTION(blsp1_i2c),
> + FUNCTION(blsp1_spi),
> + FUNCTION(blsp2_uart),
> + FUNCTION(blsp2_i2c),
> + FUNCTION(blsp2_spi),
> + FUNCTION(blsp3_uart),
> + FUNCTION(blsp3_i2c),
> + FUNCTION(blsp3_spi),
> + FUNCTION(pta2_0),
> + FUNCTION(wci21),
> + FUNCTION(cxc1),
> + FUNCTION(blsp3_spi1),
> + FUNCTION(pta2_1),
> + FUNCTION(pta2_2),
> + FUNCTION(pcie0_clk),
> + FUNCTION(dbg_out),
> + FUNCTION(cri_trng0),
> + FUNCTION(pcie0_rst),
> + FUNCTION(cri_trng1),
> + FUNCTION(pcie0_wake),
> + FUNCTION(cri_trng),
> + FUNCTION(pcie1_clk),
> + FUNCTION(rx2),
> + FUNCTION(ldo_update),
> + FUNCTION(pcie1_rst),
> + FUNCTION(ldo_en),
> + FUNCTION(pcie1_wake),
> + FUNCTION(gcc_plltest),
> + FUNCTION(sd_card),
> + FUNCTION(pwm01),
> + FUNCTION(pta1_1),
> + FUNCTION(pwm11),
> + FUNCTION(rx1),
> + FUNCTION(pta1_2),
> + FUNCTION(gcc_tlmm),
> + FUNCTION(pta1_0),
> + FUNCTION(pwm21),
> + FUNCTION(prng_rosc),
> + FUNCTION(sd_write),
> + FUNCTION(pwm31),
> + FUNCTION(rx0),
> + FUNCTION(tsens_max),
> + FUNCTION(mdc),
> + FUNCTION(mdio),
> +};
> +
> +static const struct msm_pingroup ipq8074_groups[] = {
> + PINGROUP(0, qpic_pad, blsp5_uart, blsp5_i2c, blsp5_spi, wci20,
> + blsp3_spi3, NA, burn0, NA),
> + PINGROUP(1, qpic_pad, pcm_zsi0, mac12, blsp3_spi0, NA, burn1, NA, NA,
> + NA),
> + PINGROUP(2, qpic_pad, blsp5_uart, blsp5_i2c, blsp5_spi, wci20,
> + blsp3_spi3, NA, NA, NA),
> + PINGROUP(3, qpic_pad, mac01, blsp3_spi0, qdss_cti_trig_out_b0, NA, NA,
> + NA, NA, NA),
> + PINGROUP(4, qpic_pad, mac01, blsp3_spi0, qdss_cti_trig_in_b0, NA, NA,
> + NA, NA, NA),
> + PINGROUP(5, qpic_pad4, blsp4_uart0, blsp4_i2c0, blsp4_spi0, mac21,
> + qdss_cti_trig_out_b1, NA, NA, NA),
> + PINGROUP(6, qpic_pad5, blsp4_uart0, blsp4_i2c0, blsp4_spi0, mac21,
> + qdss_cti_trig_in_b1, NA, NA, NA),
> + PINGROUP(7, qpic_pad6, blsp4_uart0, blsp4_spi0, NA, NA, NA, NA, NA, NA),
> + PINGROUP(8, qpic_pad7, blsp4_uart0, blsp4_spi0, NA, NA, NA, NA, NA, NA),
> + PINGROUP(9, qpic_pad, blsp5_uart, blsp5_spi, cxc0, mac13, blsp3_spi3,
> + qdss_cti_trig_in_a1, NA, NA),
> + PINGROUP(10, qpic_pad, qdss_cti_trig_out_a1, NA, NA, NA, NA, NA, NA,
> + NA),
> + PINGROUP(11, qpic_pad, wci22, mac12, qdss_cti_trig_in_a0, NA, NA, NA,
> + NA, NA),
> + PINGROUP(12, qpic_pad1, qdss_cti_trig_out_a0, NA, NA, NA, NA, NA, NA,
> + NA),
> + PINGROUP(13, qpic_pad2, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(14, qpic_pad3, qdss_traceclk_b, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(15, qpic_pad0, qdss_tracectl_b, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(16, qpic_pad8, blsp5_uart, pcm_zsi1, blsp5_spi, cxc0, mac13,
> + qdss_tracedata_b, NA, NA),
> + PINGROUP(17, qpic_pad, wci22, qdss_tracedata_b, NA, NA, NA, NA, NA, NA),
> + PINGROUP(18, led0, pwm04, qdss_tracedata_b, NA, NA, NA, NA, NA, NA),
> + PINGROUP(19, led1, pwm14, NA, qdss_tracedata_b, NA, NA, NA, NA, NA),
> + PINGROUP(20, led2, pwm24, NA, qdss_tracedata_b, NA, NA, NA, NA, NA),
> + PINGROUP(21, pwm00, blsp4_uart1, blsp4_i2c1, blsp4_spi1, wci23, mac11,
> + blsp3_spi2, NA, qdss_tracedata_b),
> + PINGROUP(22, pwm10, blsp4_uart1, blsp4_i2c1, blsp4_spi1, wci23, mac11,
> + blsp3_spi2, NA, qdss_tracedata_b),
> + PINGROUP(23, pwm20, blsp4_uart1, blsp4_spi1, blsp3_spi2, NA,
> + qdss_tracedata_b, NA, NA, NA),
> + PINGROUP(24, pwm30, blsp4_uart1, blsp4_spi1, NA, qdss_tracedata_b, NA,
> + NA, NA, NA),
> + PINGROUP(25, audio_txmclk, pwm02, NA, qdss_tracedata_b, NA, NA, NA, NA,
> + NA),
> + PINGROUP(26, audio_txbclk, pwm12, NA, qdss_tracedata_b, NA, NA, NA, NA,
> + NA),
> + PINGROUP(27, audio_txfsync, pwm22, NA, qdss_tracedata_b, NA, NA, NA,
> + NA, NA),
> + PINGROUP(28, audio_txd, pwm32, NA, qdss_tracedata_b, NA, NA, NA, NA,
> + NA),
> + PINGROUP(29, audio_rxmclk, pwm03, atest_char0, NA, qdss_tracedata_b,
> + NA, NA, NA, NA),
> + PINGROUP(30, audio_rxbclk, pwm13, atest_char1, NA, qdss_tracedata_b,
> + NA, NA, NA, NA),
> + PINGROUP(31, audio_rxfsync, pwm23, atest_char2, NA, qdss_tracedata_b,
> + NA, NA, NA, NA),
> + PINGROUP(32, audio_rxd, pwm33, atest_char3, NA, NA, NA, NA, NA, NA),
> + PINGROUP(33, pcm_drx, mac10, mac00, NA, NA, NA, NA, NA, NA),
> + PINGROUP(34, pcm_dtx, mac10, mac00, NA, NA, NA, NA, NA, NA),
> + PINGROUP(35, pcm_fsync, mac20, qdss_traceclk_a, NA, NA, NA, NA, NA, NA),
> + PINGROUP(36, pcm_pclk, mac20, NA, qdss_tracectl_a, NA, NA, NA, NA, NA),
> + PINGROUP(37, atest_char, NA, qdss_tracedata_a, NA, NA, NA, NA, NA, NA),
> + PINGROUP(38, blsp0_uart, blsp0_i2c, blsp0_spi, NA, qdss_tracedata_a,
> + NA, NA, NA, NA),
> + PINGROUP(39, blsp0_uart, blsp0_i2c, blsp0_spi, NA, qdss_tracedata_a,
> + NA, NA, NA, NA),
> + PINGROUP(40, blsp0_uart, blsp0_spi, NA, qdss_tracedata_a, NA, NA, NA,
> + NA, NA),
> + PINGROUP(41, blsp0_uart, blsp0_spi, NA, qdss_tracedata_a, NA, NA, NA,
> + NA, NA),
> + PINGROUP(42, blsp1_uart, blsp1_i2c, blsp1_spi, NA, qdss_tracedata_a,
> + NA, NA, NA, NA),
> + PINGROUP(43, blsp1_uart, blsp1_i2c, blsp1_spi, NA, qdss_tracedata_a,
> + NA, NA, NA, NA),
> + PINGROUP(44, blsp1_uart, blsp1_spi, NA, qdss_tracedata_a, NA, NA, NA,
> + NA, NA),
> + PINGROUP(45, blsp1_uart, blsp1_spi, qdss_tracedata_a, NA, NA, NA, NA,
> + NA, NA),
> + PINGROUP(46, blsp2_uart, blsp2_i2c, blsp2_spi, qdss_tracedata_a, NA,
> + NA, NA, NA, NA),
> + PINGROUP(47, blsp2_uart, blsp2_i2c, blsp2_spi, NA, qdss_tracedata_a,
> + NA, NA, NA, NA),
> + PINGROUP(48, blsp2_uart, blsp2_spi, NA, qdss_tracedata_a, NA, NA, NA,
> + NA, NA),
> + PINGROUP(49, blsp2_uart, blsp2_spi, NA, qdss_tracedata_a, NA, NA, NA,
> + NA, NA),
> + PINGROUP(50, blsp3_uart, blsp3_i2c, blsp3_spi, NA, qdss_tracedata_a,
> + NA, NA, NA, NA),
> + PINGROUP(51, blsp3_uart, blsp3_i2c, blsp3_spi, NA, qdss_tracedata_a,
> + NA, NA, NA, NA),
> + PINGROUP(52, blsp3_uart, blsp3_spi, NA, qdss_tracedata_a, NA, NA, NA,
> + NA, NA),
> + PINGROUP(53, blsp3_uart, blsp3_spi, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(54, pta2_0, wci21, cxc1, blsp3_spi1, NA, NA, NA, NA, NA),
> + PINGROUP(55, pta2_1, blsp3_spi1, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(56, pta2_2, wci21, cxc1, blsp3_spi1, NA, NA, NA, NA, NA),
> + PINGROUP(57, pcie0_clk, NA, dbg_out, cri_trng0, NA, NA, NA, NA, NA),
> + PINGROUP(58, pcie0_rst, NA, cri_trng1, NA, NA, NA, NA, NA, NA),
> + PINGROUP(59, pcie0_wake, NA, cri_trng, NA, NA, NA, NA, NA, NA),
> + PINGROUP(60, pcie1_clk, rx2, ldo_update, NA, NA, NA, NA, NA, NA),
> + PINGROUP(61, pcie1_rst, ldo_en, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(62, pcie1_wake, gcc_plltest, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(63, sd_card, pwm01, NA, gcc_plltest, NA, NA, NA, NA, NA),
> + PINGROUP(64, pta1_1, pwm11, NA, rx1, NA, NA, NA, NA, NA),
> + PINGROUP(65, pta1_2, NA, gcc_tlmm, NA, NA, NA, NA, NA, NA),
> + PINGROUP(66, pta1_0, pwm21, prng_rosc, NA, NA, NA, NA, NA, NA),
> + PINGROUP(67, sd_write, pwm31, rx0, tsens_max, NA, NA, NA, NA, NA),
> + PINGROUP(68, mdc, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(69, mdio, NA, NA, NA, NA, NA, NA, NA, NA),
> +};
> +
> +static const struct msm_pinctrl_soc_data ipq8074_pinctrl = {
> + .pins = ipq8074_pins,
> + .npins = ARRAY_SIZE(ipq8074_pins),
> + .functions = ipq8074_functions,
> + .nfunctions = ARRAY_SIZE(ipq8074_functions),
> + .groups = ipq8074_groups,
> + .ngroups = ARRAY_SIZE(ipq8074_groups),
> + .ngpios = 70,
> +};
> +
> +static int ipq8074_pinctrl_probe(struct platform_device *pdev)
> +{
> + return msm_pinctrl_probe(pdev, &ipq8074_pinctrl);
> +}
> +
> +static const struct of_device_id ipq8074_pinctrl_of_match[] = {
> + { .compatible = "qcom,ipq8074-pinctrl", },
> + { },
> +};
> +
> +static struct platform_driver ipq8074_pinctrl_driver = {
> + .driver = {
> + .name = "ipq8074-pinctrl",
> + .of_match_table = ipq8074_pinctrl_of_match,
> + },
> + .probe = ipq8074_pinctrl_probe,
> + .remove = msm_pinctrl_remove,
> +};
> +
> +static int __init ipq8074_pinctrl_init(void)
> +{
> + return platform_driver_register(&ipq8074_pinctrl_driver);
> +}
> +arch_initcall(ipq8074_pinctrl_init);
> +
> +static void __exit ipq8074_pinctrl_exit(void)
> +{
> + platform_driver_unregister(&ipq8074_pinctrl_driver);
> +}
> +module_exit(ipq8074_pinctrl_exit);
> +
> +MODULE_DESCRIPTION("Qualcomm ipq8074 pinctrl driver");
> +MODULE_LICENSE("GPL v2");
> +MODULE_DEVICE_TABLE(of, ipq8074_pinctrl_of_match);
>
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum, a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
2017-05-04 11:53 ` Varadarajan Narayanan
@ 2017-05-08 16:38 ` Rob Herring
-1 siblings, 0 replies; 49+ messages in thread
From: Rob Herring @ 2017-05-08 16:38 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: mark.rutland, mturquette, sboyd, linus.walleij, andy.gross,
david.brown, catalin.marinas, will.deacon, devicetree,
linux-kernel, linux-clk, linux-gpio, linux-arm-msm, linux-soc,
linux-arm-kernel, absahu, sjaganat, sricharan,
Manoharan Vijaya Raghavan
On Thu, May 04, 2017 at 05:23:57PM +0530, Varadarajan Narayanan wrote:
> Add initial pinctrl driver to support pin configuration with
> pinctrl framework for ipq8074.
>
> Signed-off-by: Manoharan Vijaya Raghavan <mraghava@codeaurora.org>
> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
> ---
> .../bindings/pinctrl/qcom,ipq8074-pinctrl.txt | 187 +++
Acked-by: Rob Herring <robh@kernel.org>
> drivers/pinctrl/qcom/Kconfig | 10 +
> drivers/pinctrl/qcom/Makefile | 1 +
> drivers/pinctrl/qcom/pinctrl-ipq8074.c | 1217 ++++++++++++++++++++
> 4 files changed, 1415 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
> create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq8074.c
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
@ 2017-05-08 16:38 ` Rob Herring
0 siblings, 0 replies; 49+ messages in thread
From: Rob Herring @ 2017-05-08 16:38 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, May 04, 2017 at 05:23:57PM +0530, Varadarajan Narayanan wrote:
> Add initial pinctrl driver to support pin configuration with
> pinctrl framework for ipq8074.
>
> Signed-off-by: Manoharan Vijaya Raghavan <mraghava@codeaurora.org>
> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
> ---
> .../bindings/pinctrl/qcom,ipq8074-pinctrl.txt | 187 +++
Acked-by: Rob Herring <robh@kernel.org>
> drivers/pinctrl/qcom/Kconfig | 10 +
> drivers/pinctrl/qcom/Makefile | 1 +
> drivers/pinctrl/qcom/pinctrl-ipq8074.c | 1217 ++++++++++++++++++++
> 4 files changed, 1415 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
> create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq8074.c
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 2/5] dt-bindings: qcom: Add IPQ8074 bindings
2017-05-04 11:53 ` Varadarajan Narayanan
@ 2017-05-08 16:38 ` Rob Herring
-1 siblings, 0 replies; 49+ messages in thread
From: Rob Herring @ 2017-05-08 16:38 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: mark.rutland, mturquette, sboyd, linus.walleij, andy.gross,
david.brown, catalin.marinas, will.deacon, devicetree,
linux-kernel, linux-clk, linux-gpio, linux-arm-msm, linux-soc,
linux-arm-kernel, absahu, sjaganat, sricharan
On Thu, May 04, 2017 at 05:23:58PM +0530, Varadarajan Narayanan wrote:
> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
> ---
> Documentation/devicetree/bindings/arm/qcom.txt | 2 ++
> 1 file changed, 2 insertions(+)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 2/5] dt-bindings: qcom: Add IPQ8074 bindings
@ 2017-05-08 16:38 ` Rob Herring
0 siblings, 0 replies; 49+ messages in thread
From: Rob Herring @ 2017-05-08 16:38 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, May 04, 2017 at 05:23:58PM +0530, Varadarajan Narayanan wrote:
> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
> ---
> Documentation/devicetree/bindings/arm/qcom.txt | 2 ++
> 1 file changed, 2 insertions(+)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 3/5] clk: qcom: ipq8074: Add Global Clock Controller support
2017-05-04 11:53 ` Varadarajan Narayanan
(?)
@ 2017-05-08 16:40 ` Rob Herring
-1 siblings, 0 replies; 49+ messages in thread
From: Rob Herring @ 2017-05-08 16:40 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: mark.rutland-5wv7dgnIgG8, mturquette-rdvid1DuHRBWk0Htik3J/w,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
andy.gross-QSEj5FYQhm4dnm+yROfE0A,
david.brown-QSEj5FYQhm4dnm+yROfE0A, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-soc-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
absahu-sgV2jX0FEOL9JmXXK+q4OQ, sjaganat-sgV2jX0FEOL9JmXXK+q4OQ,
sricharan-sgV2jX0FEOL9JmXXK+q4OQ
On Thu, May 04, 2017 at 05:23:59PM +0530, Varadarajan Narayanan wrote:
> From: Abhishek Sahu <absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
>
> This patch adds support for the global clock controller found on
> the IPQ8074 based devices. This includes UART, I2C, SPI etc.
>
> Signed-off-by: Abhishek Sahu <absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> Signed-off-by: Varadarajan Narayanan <varada-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> ---
> .../devicetree/bindings/clock/qcom,gcc.txt | 1 +
> drivers/clk/qcom/Kconfig | 9 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/gcc-ipq8074.c | 1032 ++++++++++++++++++++
> include/dt-bindings/clock/qcom,gcc-ipq8074.h | 152 +++
For the binding,
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> 5 files changed, 1195 insertions(+)
> create mode 100644 drivers/clk/qcom/gcc-ipq8074.c
> create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq8074.h
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 3/5] clk: qcom: ipq8074: Add Global Clock Controller support
@ 2017-05-08 16:40 ` Rob Herring
0 siblings, 0 replies; 49+ messages in thread
From: Rob Herring @ 2017-05-08 16:40 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: mark.rutland, mturquette, sboyd, linus.walleij, andy.gross,
david.brown, catalin.marinas, will.deacon, devicetree,
linux-kernel, linux-clk, linux-gpio, linux-arm-msm, linux-soc,
linux-arm-kernel, absahu, sjaganat, sricharan
On Thu, May 04, 2017 at 05:23:59PM +0530, Varadarajan Narayanan wrote:
> From: Abhishek Sahu <absahu@codeaurora.org>
>
> This patch adds support for the global clock controller found on
> the IPQ8074 based devices. This includes UART, I2C, SPI etc.
>
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
> ---
> .../devicetree/bindings/clock/qcom,gcc.txt | 1 +
> drivers/clk/qcom/Kconfig | 9 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/gcc-ipq8074.c | 1032 ++++++++++++++++++++
> include/dt-bindings/clock/qcom,gcc-ipq8074.h | 152 +++
For the binding,
Acked-by: Rob Herring <robh@kernel.org>
> 5 files changed, 1195 insertions(+)
> create mode 100644 drivers/clk/qcom/gcc-ipq8074.c
> create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq8074.h
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 3/5] clk: qcom: ipq8074: Add Global Clock Controller support
@ 2017-05-08 16:40 ` Rob Herring
0 siblings, 0 replies; 49+ messages in thread
From: Rob Herring @ 2017-05-08 16:40 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, May 04, 2017 at 05:23:59PM +0530, Varadarajan Narayanan wrote:
> From: Abhishek Sahu <absahu@codeaurora.org>
>
> This patch adds support for the global clock controller found on
> the IPQ8074 based devices. This includes UART, I2C, SPI etc.
>
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
> ---
> .../devicetree/bindings/clock/qcom,gcc.txt | 1 +
> drivers/clk/qcom/Kconfig | 9 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/gcc-ipq8074.c | 1032 ++++++++++++++++++++
> include/dt-bindings/clock/qcom,gcc-ipq8074.h | 152 +++
For the binding,
Acked-by: Rob Herring <robh@kernel.org>
> 5 files changed, 1195 insertions(+)
> create mode 100644 drivers/clk/qcom/gcc-ipq8074.c
> create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq8074.h
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
2017-05-04 11:53 ` Varadarajan Narayanan
@ 2017-05-10 22:43 ` Bjorn Andersson
-1 siblings, 0 replies; 49+ messages in thread
From: Bjorn Andersson @ 2017-05-10 22:43 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: robh+dt, mark.rutland, mturquette, sboyd, linus.walleij,
andy.gross, david.brown, catalin.marinas, will.deacon,
devicetree, linux-kernel, linux-clk, linux-gpio, linux-arm-msm,
linux-soc, linux-arm-kernel, absahu, sjaganat, sricharan,
Manoharan Vijaya Raghavan
On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
> Add initial pinctrl driver to support pin configuration with
> pinctrl framework for ipq8074.
>
> Signed-off-by: Manoharan Vijaya Raghavan <mraghava@codeaurora.org>
> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
> ---
> .../bindings/pinctrl/qcom,ipq8074-pinctrl.txt | 187 +++
> drivers/pinctrl/qcom/Kconfig | 10 +
> drivers/pinctrl/qcom/Makefile | 1 +
> drivers/pinctrl/qcom/pinctrl-ipq8074.c | 1217 ++++++++++++++++++++
> 4 files changed, 1415 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
> create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq8074.c
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
[..]
> +- pins:
> + Usage: required
> + Value type: <string-array>
> + Definition: List of gpio pins affected by the properties specified in
> + this subnode. Valid pins are:
> + gpio0-gpio121,
> + sdc1_clk,
> + sdc1_cmd,
> + sdc1_data
> + sdc2_clk,
> + sdc2_cmd,
> + sdc2_data,
> + qdsd_cmd,
> + qdsd_data0,
> + qdsd_data1,
> + qdsd_data2,
> + qdsd_data3
These doesn't match the implementation.
> +
> +- function:
> + Usage: required
> + Value type: <string>
> + Definition: Specify the alternative function to be configured for the
> + specified pins. Functions are only valid for gpio pins.
> + Valid values are:
> + gpio, qpic_pad, blsp5_i2c, blsp5_spi, wci20, blsp3_spi3,
> + burn0, pcm_zsi0, blsp5_uart, mac12, blsp3_spi0, burn1, mac01,
> + qdss_cti_trig_out_b0, qdss_cti_trig_in_b0, qpic_pad4,
> + blsp4_uart0, blsp4_i2c0, blsp4_spi0, mac21,
> + qdss_cti_trig_out_b1, qpic_pad5, qdss_cti_trig_in_b1,
> + qpic_pad6, qpic_pad7, cxc0, mac13, qdss_cti_trig_in_a1,
> + qdss_cti_trig_out_a1, wci22, qdss_cti_trig_in_a0, qpic_pad1,
> + qdss_cti_trig_out_a0, qpic_pad2, qpic_pad3, qdss_traceclk_b,
> + qpic_pad0, qdss_tracectl_b, qpic_pad8, pcm_zsi1,
> + qdss_tracedata_b, led0, pwm04, led1, pwm14, led2, pwm24,
> + pwm00, blsp4_uart1, blsp4_i2c1, blsp4_spi1, wci23, mac11,
> + blsp3_spi2, pwm10, pwm20, pwm30, audio_txmclk, pwm02,
> + audio_txbclk, pwm12, audio_txfsync, pwm22, audio_txd, pwm32,
> + audio_rxmclk, pwm03, atest_char0, audio_rxbclk, pwm13,
> + atest_char1, audio_rxfsync, pwm23, atest_char2, audio_rxd,
> + pwm33, atest_char3, pcm_drx, mac10, mac00, pcm_dtx, pcm_fsync,
> + mac20, qdss_traceclk_a, pcm_pclk, qdss_tracectl_a, atest_char,
> + qdss_tracedata_a, blsp0_uart, blsp0_i2c, blsp0_spi,
> + blsp1_uart, blsp1_i2c, blsp1_spi, blsp2_uart, blsp2_i2c,
> + blsp2_spi, blsp3_uart, blsp3_i2c, blsp3_spi, pta2_0, wci21,
> + cxc1, blsp3_spi1, pta2_1, pta2_2, pcie0_clk, dbg_out,
> + cri_trng0, pcie0_rst, cri_trng1, pcie0_wake, cri_trng,
> + pcie1_clk, rx2, ldo_update, pcie1_rst, ldo_en, pcie1_wake,
> + gcc_plltest, sd_card, pwm01, pta1_1, pwm11, rx1, pta1_2,
> + gcc_tlmm, pta1_0, pwm21, prng_rosc, sd_write, pwm31, rx0,
> + tsens_max, mdc, mdio, NA
Please indent these to the same level as the description.
> +
[..]
> +
> +- output-high:
> + Usage: optional
> + Value type: <none>
> + Definition: The specified pins are configured in output mode, driven
> + high.
> + Not valid for sdc pins.
If you don't have any sdc pins, drop this.
> +
> +- output-low:
> + Usage: optional
> + Value type: <none>
> + Definition: The specified pins are configured in output mode, driven
> + low.
> + Not valid for sdc pins.
If you don't have any sdc pins, drop this.
> +
> +- drive-strength:
> + Usage: optional
> + Value type: <u32>
> + Definition: Selects the drive strength for the specified pins, in mA.
> + Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
> +
[..]
> diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8074.c b/drivers/pinctrl/qcom/pinctrl-ipq8074.c
[..]
> +
> +enum ipq8074_functions {
Please keep these sorted alphabetically.
> + msm_mux_gpio,
> + msm_mux_qpic_pad,
> + msm_mux_blsp5_i2c,
> + msm_mux_blsp5_spi,
> + msm_mux_wci20,
What does "20" mean here?
> + msm_mux_blsp3_spi3,
> + msm_mux_burn0,
> + msm_mux_pcm_zsi0,
> + msm_mux_blsp5_uart,
> + msm_mux_mac12,
What does "12" mean here?
> + msm_mux_blsp3_spi0,
> + msm_mux_burn1,
> + msm_mux_mac01,
> + msm_mux_qdss_cti_trig_out_b0,
> + msm_mux_qdss_cti_trig_in_b0,
> + msm_mux_qpic_pad4,
What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
alternative muxings...?
> + msm_mux_blsp4_uart0,
> + msm_mux_blsp4_i2c0,
> + msm_mux_blsp4_spi0,
> + msm_mux_mac21,
> + msm_mux_qdss_cti_trig_out_b1,
> + msm_mux_qpic_pad5,
> + msm_mux_qdss_cti_trig_in_b1,
> + msm_mux_qpic_pad6,
> + msm_mux_qpic_pad7,
> + msm_mux_cxc0,
> + msm_mux_mac13,
> + msm_mux_qdss_cti_trig_in_a1,
> + msm_mux_qdss_cti_trig_out_a1,
> + msm_mux_wci22,
> + msm_mux_qdss_cti_trig_in_a0,
> + msm_mux_qpic_pad1,
> + msm_mux_qdss_cti_trig_out_a0,
> + msm_mux_qpic_pad2,
> + msm_mux_qpic_pad3,
> + msm_mux_qdss_traceclk_b,
> + msm_mux_qpic_pad0,
> + msm_mux_qdss_tracectl_b,
> + msm_mux_qpic_pad8,
> + msm_mux_pcm_zsi1,
> + msm_mux_qdss_tracedata_b,
> + msm_mux_led0,
> + msm_mux_pwm04,
What does "04" mean here?
> + msm_mux_led1,
> + msm_mux_pwm14,
> + msm_mux_led2,
> + msm_mux_pwm24,
> + msm_mux_pwm00,
> + msm_mux_blsp4_uart1,
Are uart0 vs uart1 alternative muxes?
[..]
> +static const struct msm_function ipq8074_functions[] = {
Please keep these sorted alphabetically too.
Regards,
Bjorn
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
@ 2017-05-10 22:43 ` Bjorn Andersson
0 siblings, 0 replies; 49+ messages in thread
From: Bjorn Andersson @ 2017-05-10 22:43 UTC (permalink / raw)
To: linux-arm-kernel
On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
> Add initial pinctrl driver to support pin configuration with
> pinctrl framework for ipq8074.
>
> Signed-off-by: Manoharan Vijaya Raghavan <mraghava@codeaurora.org>
> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
> ---
> .../bindings/pinctrl/qcom,ipq8074-pinctrl.txt | 187 +++
> drivers/pinctrl/qcom/Kconfig | 10 +
> drivers/pinctrl/qcom/Makefile | 1 +
> drivers/pinctrl/qcom/pinctrl-ipq8074.c | 1217 ++++++++++++++++++++
> 4 files changed, 1415 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
> create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq8074.c
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
[..]
> +- pins:
> + Usage: required
> + Value type: <string-array>
> + Definition: List of gpio pins affected by the properties specified in
> + this subnode. Valid pins are:
> + gpio0-gpio121,
> + sdc1_clk,
> + sdc1_cmd,
> + sdc1_data
> + sdc2_clk,
> + sdc2_cmd,
> + sdc2_data,
> + qdsd_cmd,
> + qdsd_data0,
> + qdsd_data1,
> + qdsd_data2,
> + qdsd_data3
These doesn't match the implementation.
> +
> +- function:
> + Usage: required
> + Value type: <string>
> + Definition: Specify the alternative function to be configured for the
> + specified pins. Functions are only valid for gpio pins.
> + Valid values are:
> + gpio, qpic_pad, blsp5_i2c, blsp5_spi, wci20, blsp3_spi3,
> + burn0, pcm_zsi0, blsp5_uart, mac12, blsp3_spi0, burn1, mac01,
> + qdss_cti_trig_out_b0, qdss_cti_trig_in_b0, qpic_pad4,
> + blsp4_uart0, blsp4_i2c0, blsp4_spi0, mac21,
> + qdss_cti_trig_out_b1, qpic_pad5, qdss_cti_trig_in_b1,
> + qpic_pad6, qpic_pad7, cxc0, mac13, qdss_cti_trig_in_a1,
> + qdss_cti_trig_out_a1, wci22, qdss_cti_trig_in_a0, qpic_pad1,
> + qdss_cti_trig_out_a0, qpic_pad2, qpic_pad3, qdss_traceclk_b,
> + qpic_pad0, qdss_tracectl_b, qpic_pad8, pcm_zsi1,
> + qdss_tracedata_b, led0, pwm04, led1, pwm14, led2, pwm24,
> + pwm00, blsp4_uart1, blsp4_i2c1, blsp4_spi1, wci23, mac11,
> + blsp3_spi2, pwm10, pwm20, pwm30, audio_txmclk, pwm02,
> + audio_txbclk, pwm12, audio_txfsync, pwm22, audio_txd, pwm32,
> + audio_rxmclk, pwm03, atest_char0, audio_rxbclk, pwm13,
> + atest_char1, audio_rxfsync, pwm23, atest_char2, audio_rxd,
> + pwm33, atest_char3, pcm_drx, mac10, mac00, pcm_dtx, pcm_fsync,
> + mac20, qdss_traceclk_a, pcm_pclk, qdss_tracectl_a, atest_char,
> + qdss_tracedata_a, blsp0_uart, blsp0_i2c, blsp0_spi,
> + blsp1_uart, blsp1_i2c, blsp1_spi, blsp2_uart, blsp2_i2c,
> + blsp2_spi, blsp3_uart, blsp3_i2c, blsp3_spi, pta2_0, wci21,
> + cxc1, blsp3_spi1, pta2_1, pta2_2, pcie0_clk, dbg_out,
> + cri_trng0, pcie0_rst, cri_trng1, pcie0_wake, cri_trng,
> + pcie1_clk, rx2, ldo_update, pcie1_rst, ldo_en, pcie1_wake,
> + gcc_plltest, sd_card, pwm01, pta1_1, pwm11, rx1, pta1_2,
> + gcc_tlmm, pta1_0, pwm21, prng_rosc, sd_write, pwm31, rx0,
> + tsens_max, mdc, mdio, NA
Please indent these to the same level as the description.
> +
[..]
> +
> +- output-high:
> + Usage: optional
> + Value type: <none>
> + Definition: The specified pins are configured in output mode, driven
> + high.
> + Not valid for sdc pins.
If you don't have any sdc pins, drop this.
> +
> +- output-low:
> + Usage: optional
> + Value type: <none>
> + Definition: The specified pins are configured in output mode, driven
> + low.
> + Not valid for sdc pins.
If you don't have any sdc pins, drop this.
> +
> +- drive-strength:
> + Usage: optional
> + Value type: <u32>
> + Definition: Selects the drive strength for the specified pins, in mA.
> + Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
> +
[..]
> diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8074.c b/drivers/pinctrl/qcom/pinctrl-ipq8074.c
[..]
> +
> +enum ipq8074_functions {
Please keep these sorted alphabetically.
> + msm_mux_gpio,
> + msm_mux_qpic_pad,
> + msm_mux_blsp5_i2c,
> + msm_mux_blsp5_spi,
> + msm_mux_wci20,
What does "20" mean here?
> + msm_mux_blsp3_spi3,
> + msm_mux_burn0,
> + msm_mux_pcm_zsi0,
> + msm_mux_blsp5_uart,
> + msm_mux_mac12,
What does "12" mean here?
> + msm_mux_blsp3_spi0,
> + msm_mux_burn1,
> + msm_mux_mac01,
> + msm_mux_qdss_cti_trig_out_b0,
> + msm_mux_qdss_cti_trig_in_b0,
> + msm_mux_qpic_pad4,
What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
alternative muxings...?
> + msm_mux_blsp4_uart0,
> + msm_mux_blsp4_i2c0,
> + msm_mux_blsp4_spi0,
> + msm_mux_mac21,
> + msm_mux_qdss_cti_trig_out_b1,
> + msm_mux_qpic_pad5,
> + msm_mux_qdss_cti_trig_in_b1,
> + msm_mux_qpic_pad6,
> + msm_mux_qpic_pad7,
> + msm_mux_cxc0,
> + msm_mux_mac13,
> + msm_mux_qdss_cti_trig_in_a1,
> + msm_mux_qdss_cti_trig_out_a1,
> + msm_mux_wci22,
> + msm_mux_qdss_cti_trig_in_a0,
> + msm_mux_qpic_pad1,
> + msm_mux_qdss_cti_trig_out_a0,
> + msm_mux_qpic_pad2,
> + msm_mux_qpic_pad3,
> + msm_mux_qdss_traceclk_b,
> + msm_mux_qpic_pad0,
> + msm_mux_qdss_tracectl_b,
> + msm_mux_qpic_pad8,
> + msm_mux_pcm_zsi1,
> + msm_mux_qdss_tracedata_b,
> + msm_mux_led0,
> + msm_mux_pwm04,
What does "04" mean here?
> + msm_mux_led1,
> + msm_mux_pwm14,
> + msm_mux_led2,
> + msm_mux_pwm24,
> + msm_mux_pwm00,
> + msm_mux_blsp4_uart1,
Are uart0 vs uart1 alternative muxes?
[..]
> +static const struct msm_function ipq8074_functions[] = {
Please keep these sorted alphabetically too.
Regards,
Bjorn
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
2017-05-10 22:43 ` Bjorn Andersson
@ 2017-05-11 10:33 ` Varadarajan Narayanan
-1 siblings, 0 replies; 49+ messages in thread
From: Varadarajan Narayanan @ 2017-05-11 10:33 UTC (permalink / raw)
To: Bjorn Andersson
Cc: robh+dt, mark.rutland, mturquette, sboyd, linus.walleij,
andy.gross, david.brown, catalin.marinas, will.deacon,
devicetree, linux-kernel, linux-clk, linux-gpio, linux-arm-msm,
linux-soc, linux-arm-kernel, absahu, sjaganat, sricharan,
Manoharan Vijaya Raghavan
On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
> On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
>
>> Add initial pinctrl driver to support pin configuration with
>> pinctrl framework for ipq8074.
>>
>> Signed-off-by: Manoharan Vijaya Raghavan <mraghava@codeaurora.org>
>> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
>> ---
>> .../bindings/pinctrl/qcom,ipq8074-pinctrl.txt | 187 +++
>> drivers/pinctrl/qcom/Kconfig | 10 +
>> drivers/pinctrl/qcom/Makefile | 1 +
>> drivers/pinctrl/qcom/pinctrl-ipq8074.c | 1217 ++++++++++++++++++++
>> 4 files changed, 1415 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
>> create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq8074.c
>>
>> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
> [..]
>> +- pins:
>> + Usage: required
>> + Value type: <string-array>
>> + Definition: List of gpio pins affected by the properties specified in
>> + this subnode. Valid pins are:
>> + gpio0-gpio121,
>> + sdc1_clk,
>> + sdc1_cmd,
>> + sdc1_data
>> + sdc2_clk,
>> + sdc2_cmd,
>> + sdc2_data,
>> + qdsd_cmd,
>> + qdsd_data0,
>> + qdsd_data1,
>> + qdsd_data2,
>> + qdsd_data3
>
> These doesn't match the implementation.
Will remove them.
>> +
>> +- function:
>> + Usage: required
>> + Value type: <string>
>> + Definition: Specify the alternative function to be configured for the
>> + specified pins. Functions are only valid for gpio pins.
>> + Valid values are:
>> + gpio, qpic_pad, blsp5_i2c, blsp5_spi, wci20, blsp3_spi3,
>> + burn0, pcm_zsi0, blsp5_uart, mac12, blsp3_spi0, burn1, mac01,
>> + qdss_cti_trig_out_b0, qdss_cti_trig_in_b0, qpic_pad4,
>> + blsp4_uart0, blsp4_i2c0, blsp4_spi0, mac21,
>> + qdss_cti_trig_out_b1, qpic_pad5, qdss_cti_trig_in_b1,
>> + qpic_pad6, qpic_pad7, cxc0, mac13, qdss_cti_trig_in_a1,
>> + qdss_cti_trig_out_a1, wci22, qdss_cti_trig_in_a0, qpic_pad1,
>> + qdss_cti_trig_out_a0, qpic_pad2, qpic_pad3, qdss_traceclk_b,
>> + qpic_pad0, qdss_tracectl_b, qpic_pad8, pcm_zsi1,
>> + qdss_tracedata_b, led0, pwm04, led1, pwm14, led2, pwm24,
>> + pwm00, blsp4_uart1, blsp4_i2c1, blsp4_spi1, wci23, mac11,
>> + blsp3_spi2, pwm10, pwm20, pwm30, audio_txmclk, pwm02,
>> + audio_txbclk, pwm12, audio_txfsync, pwm22, audio_txd, pwm32,
>> + audio_rxmclk, pwm03, atest_char0, audio_rxbclk, pwm13,
>> + atest_char1, audio_rxfsync, pwm23, atest_char2, audio_rxd,
>> + pwm33, atest_char3, pcm_drx, mac10, mac00, pcm_dtx, pcm_fsync,
>> + mac20, qdss_traceclk_a, pcm_pclk, qdss_tracectl_a, atest_char,
>> + qdss_tracedata_a, blsp0_uart, blsp0_i2c, blsp0_spi,
>> + blsp1_uart, blsp1_i2c, blsp1_spi, blsp2_uart, blsp2_i2c,
>> + blsp2_spi, blsp3_uart, blsp3_i2c, blsp3_spi, pta2_0, wci21,
>> + cxc1, blsp3_spi1, pta2_1, pta2_2, pcie0_clk, dbg_out,
>> + cri_trng0, pcie0_rst, cri_trng1, pcie0_wake, cri_trng,
>> + pcie1_clk, rx2, ldo_update, pcie1_rst, ldo_en, pcie1_wake,
>> + gcc_plltest, sd_card, pwm01, pta1_1, pwm11, rx1, pta1_2,
>> + gcc_tlmm, pta1_0, pwm21, prng_rosc, sd_write, pwm31, rx0,
>> + tsens_max, mdc, mdio, NA
>
> Please indent these to the same level as the description.
Ok
>> +
> [..]
>> +
>> +- output-high:
>> + Usage: optional
>> + Value type: <none>
>> + Definition: The specified pins are configured in output mode, driven
>> + high.
>> + Not valid for sdc pins.
>
> If you don't have any sdc pins, drop this.
Ok
>> +
>> +- output-low:
>> + Usage: optional
>> + Value type: <none>
>> + Definition: The specified pins are configured in output mode, driven
>> + low.
>> + Not valid for sdc pins.
>
> If you don't have any sdc pins, drop this.
Ok
>> +
>> +- drive-strength:
>> + Usage: optional
>> + Value type: <u32>
>> + Definition: Selects the drive strength for the specified pins, in mA.
>> + Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
>> +
> [..]
>> diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8074.c b/drivers/pinctrl/qcom/pinctrl-ipq8074.c
> [..]
>> +
>> +enum ipq8074_functions {
>
> Please keep these sorted alphabetically.
Ok
>> + msm_mux_gpio,
>> + msm_mux_qpic_pad,
>> + msm_mux_blsp5_i2c,
>> + msm_mux_blsp5_spi,
>> + msm_mux_wci20,
>
> What does "20" mean here?
This is for Wireless Coex Interface. The same functionality can be muxed
on to different GPIOs. WCI2, is the 2nd edition of the WCI standard and
0, 1 are for the muxing to different GPIOs (alternate muxes).
>> + msm_mux_blsp3_spi3,
>> + msm_mux_burn0,
>> + msm_mux_pcm_zsi0,
>> + msm_mux_blsp5_uart,
>> + msm_mux_mac12,
>
> What does "12" mean here?
The SoC has three MAC cores. Each core has two pins for the smart
antenna feature. macXY indicates the function select for MAC no. X and
smart antenna no. Y.
>> + msm_mux_blsp3_spi0,
>> + msm_mux_burn1,
>> + msm_mux_mac01,
>> + msm_mux_qdss_cti_trig_out_b0,
>> + msm_mux_qdss_cti_trig_in_b0,
>> + msm_mux_qpic_pad4,
>
> What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
> alternative muxings...?
This is for the NAND and LCD display. The pins listed are the 9 data pins.
>> + msm_mux_blsp4_uart0,
>> + msm_mux_blsp4_i2c0,
>> + msm_mux_blsp4_spi0,
>> + msm_mux_mac21,
>> + msm_mux_qdss_cti_trig_out_b1,
>> + msm_mux_qpic_pad5,
>> + msm_mux_qdss_cti_trig_in_b1,
>> + msm_mux_qpic_pad6,
>> + msm_mux_qpic_pad7,
>> + msm_mux_cxc0,
>> + msm_mux_mac13,
>> + msm_mux_qdss_cti_trig_in_a1,
>> + msm_mux_qdss_cti_trig_out_a1,
>> + msm_mux_wci22,
>> + msm_mux_qdss_cti_trig_in_a0,
>> + msm_mux_qpic_pad1,
>> + msm_mux_qdss_cti_trig_out_a0,
>> + msm_mux_qpic_pad2,
>> + msm_mux_qpic_pad3,
>> + msm_mux_qdss_traceclk_b,
>> + msm_mux_qpic_pad0,
>> + msm_mux_qdss_tracectl_b,
>> + msm_mux_qpic_pad8,
>> + msm_mux_pcm_zsi1,
>> + msm_mux_qdss_tracedata_b,
>> + msm_mux_led0,
>> + msm_mux_pwm04,
>
> What does "04" mean here?
There are 4 Pulse Width Modulation channels, pwmXY is pwm channel X and
pin Y.
>
>> + msm_mux_led1,
>> + msm_mux_pwm14,
>> + msm_mux_led2,
>> + msm_mux_pwm24,
>> + msm_mux_pwm00,
>> + msm_mux_blsp4_uart1,
>
> Are uart0 vs uart1 alternative muxes?
These are two different uarts available at two independent pins.
> [..]
>> +static const struct msm_function ipq8074_functions[] = {
>
> Please keep these sorted alphabetically too.
Ok
Thanks
Varada
> Regards,
> Bjorn
>
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum, a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
@ 2017-05-11 10:33 ` Varadarajan Narayanan
0 siblings, 0 replies; 49+ messages in thread
From: Varadarajan Narayanan @ 2017-05-11 10:33 UTC (permalink / raw)
To: linux-arm-kernel
On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
> On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
>
>> Add initial pinctrl driver to support pin configuration with
>> pinctrl framework for ipq8074.
>>
>> Signed-off-by: Manoharan Vijaya Raghavan <mraghava@codeaurora.org>
>> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
>> ---
>> .../bindings/pinctrl/qcom,ipq8074-pinctrl.txt | 187 +++
>> drivers/pinctrl/qcom/Kconfig | 10 +
>> drivers/pinctrl/qcom/Makefile | 1 +
>> drivers/pinctrl/qcom/pinctrl-ipq8074.c | 1217 ++++++++++++++++++++
>> 4 files changed, 1415 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
>> create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq8074.c
>>
>> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
> [..]
>> +- pins:
>> + Usage: required
>> + Value type: <string-array>
>> + Definition: List of gpio pins affected by the properties specified in
>> + this subnode. Valid pins are:
>> + gpio0-gpio121,
>> + sdc1_clk,
>> + sdc1_cmd,
>> + sdc1_data
>> + sdc2_clk,
>> + sdc2_cmd,
>> + sdc2_data,
>> + qdsd_cmd,
>> + qdsd_data0,
>> + qdsd_data1,
>> + qdsd_data2,
>> + qdsd_data3
>
> These doesn't match the implementation.
Will remove them.
>> +
>> +- function:
>> + Usage: required
>> + Value type: <string>
>> + Definition: Specify the alternative function to be configured for the
>> + specified pins. Functions are only valid for gpio pins.
>> + Valid values are:
>> + gpio, qpic_pad, blsp5_i2c, blsp5_spi, wci20, blsp3_spi3,
>> + burn0, pcm_zsi0, blsp5_uart, mac12, blsp3_spi0, burn1, mac01,
>> + qdss_cti_trig_out_b0, qdss_cti_trig_in_b0, qpic_pad4,
>> + blsp4_uart0, blsp4_i2c0, blsp4_spi0, mac21,
>> + qdss_cti_trig_out_b1, qpic_pad5, qdss_cti_trig_in_b1,
>> + qpic_pad6, qpic_pad7, cxc0, mac13, qdss_cti_trig_in_a1,
>> + qdss_cti_trig_out_a1, wci22, qdss_cti_trig_in_a0, qpic_pad1,
>> + qdss_cti_trig_out_a0, qpic_pad2, qpic_pad3, qdss_traceclk_b,
>> + qpic_pad0, qdss_tracectl_b, qpic_pad8, pcm_zsi1,
>> + qdss_tracedata_b, led0, pwm04, led1, pwm14, led2, pwm24,
>> + pwm00, blsp4_uart1, blsp4_i2c1, blsp4_spi1, wci23, mac11,
>> + blsp3_spi2, pwm10, pwm20, pwm30, audio_txmclk, pwm02,
>> + audio_txbclk, pwm12, audio_txfsync, pwm22, audio_txd, pwm32,
>> + audio_rxmclk, pwm03, atest_char0, audio_rxbclk, pwm13,
>> + atest_char1, audio_rxfsync, pwm23, atest_char2, audio_rxd,
>> + pwm33, atest_char3, pcm_drx, mac10, mac00, pcm_dtx, pcm_fsync,
>> + mac20, qdss_traceclk_a, pcm_pclk, qdss_tracectl_a, atest_char,
>> + qdss_tracedata_a, blsp0_uart, blsp0_i2c, blsp0_spi,
>> + blsp1_uart, blsp1_i2c, blsp1_spi, blsp2_uart, blsp2_i2c,
>> + blsp2_spi, blsp3_uart, blsp3_i2c, blsp3_spi, pta2_0, wci21,
>> + cxc1, blsp3_spi1, pta2_1, pta2_2, pcie0_clk, dbg_out,
>> + cri_trng0, pcie0_rst, cri_trng1, pcie0_wake, cri_trng,
>> + pcie1_clk, rx2, ldo_update, pcie1_rst, ldo_en, pcie1_wake,
>> + gcc_plltest, sd_card, pwm01, pta1_1, pwm11, rx1, pta1_2,
>> + gcc_tlmm, pta1_0, pwm21, prng_rosc, sd_write, pwm31, rx0,
>> + tsens_max, mdc, mdio, NA
>
> Please indent these to the same level as the description.
Ok
>> +
> [..]
>> +
>> +- output-high:
>> + Usage: optional
>> + Value type: <none>
>> + Definition: The specified pins are configured in output mode, driven
>> + high.
>> + Not valid for sdc pins.
>
> If you don't have any sdc pins, drop this.
Ok
>> +
>> +- output-low:
>> + Usage: optional
>> + Value type: <none>
>> + Definition: The specified pins are configured in output mode, driven
>> + low.
>> + Not valid for sdc pins.
>
> If you don't have any sdc pins, drop this.
Ok
>> +
>> +- drive-strength:
>> + Usage: optional
>> + Value type: <u32>
>> + Definition: Selects the drive strength for the specified pins, in mA.
>> + Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
>> +
> [..]
>> diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8074.c b/drivers/pinctrl/qcom/pinctrl-ipq8074.c
> [..]
>> +
>> +enum ipq8074_functions {
>
> Please keep these sorted alphabetically.
Ok
>> + msm_mux_gpio,
>> + msm_mux_qpic_pad,
>> + msm_mux_blsp5_i2c,
>> + msm_mux_blsp5_spi,
>> + msm_mux_wci20,
>
> What does "20" mean here?
This is for Wireless Coex Interface. The same functionality can be muxed
on to different GPIOs. WCI2, is the 2nd edition of the WCI standard and
0, 1 are for the muxing to different GPIOs (alternate muxes).
>> + msm_mux_blsp3_spi3,
>> + msm_mux_burn0,
>> + msm_mux_pcm_zsi0,
>> + msm_mux_blsp5_uart,
>> + msm_mux_mac12,
>
> What does "12" mean here?
The SoC has three MAC cores. Each core has two pins for the smart
antenna feature. macXY indicates the function select for MAC no. X and
smart antenna no. Y.
>> + msm_mux_blsp3_spi0,
>> + msm_mux_burn1,
>> + msm_mux_mac01,
>> + msm_mux_qdss_cti_trig_out_b0,
>> + msm_mux_qdss_cti_trig_in_b0,
>> + msm_mux_qpic_pad4,
>
> What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
> alternative muxings...?
This is for the NAND and LCD display. The pins listed are the 9 data pins.
>> + msm_mux_blsp4_uart0,
>> + msm_mux_blsp4_i2c0,
>> + msm_mux_blsp4_spi0,
>> + msm_mux_mac21,
>> + msm_mux_qdss_cti_trig_out_b1,
>> + msm_mux_qpic_pad5,
>> + msm_mux_qdss_cti_trig_in_b1,
>> + msm_mux_qpic_pad6,
>> + msm_mux_qpic_pad7,
>> + msm_mux_cxc0,
>> + msm_mux_mac13,
>> + msm_mux_qdss_cti_trig_in_a1,
>> + msm_mux_qdss_cti_trig_out_a1,
>> + msm_mux_wci22,
>> + msm_mux_qdss_cti_trig_in_a0,
>> + msm_mux_qpic_pad1,
>> + msm_mux_qdss_cti_trig_out_a0,
>> + msm_mux_qpic_pad2,
>> + msm_mux_qpic_pad3,
>> + msm_mux_qdss_traceclk_b,
>> + msm_mux_qpic_pad0,
>> + msm_mux_qdss_tracectl_b,
>> + msm_mux_qpic_pad8,
>> + msm_mux_pcm_zsi1,
>> + msm_mux_qdss_tracedata_b,
>> + msm_mux_led0,
>> + msm_mux_pwm04,
>
> What does "04" mean here?
There are 4 Pulse Width Modulation channels, pwmXY is pwm channel X and
pin Y.
>
>> + msm_mux_led1,
>> + msm_mux_pwm14,
>> + msm_mux_led2,
>> + msm_mux_pwm24,
>> + msm_mux_pwm00,
>> + msm_mux_blsp4_uart1,
>
> Are uart0 vs uart1 alternative muxes?
These are two different uarts available at two independent pins.
> [..]
>> +static const struct msm_function ipq8074_functions[] = {
>
> Please keep these sorted alphabetically too.
Ok
Thanks
Varada
> Regards,
> Bjorn
>
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum, a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
2017-05-11 10:33 ` Varadarajan Narayanan
@ 2017-05-14 4:23 ` Bjorn Andersson
-1 siblings, 0 replies; 49+ messages in thread
From: Bjorn Andersson @ 2017-05-14 4:23 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: robh+dt, mark.rutland, mturquette, sboyd, linus.walleij,
andy.gross, david.brown, catalin.marinas, will.deacon,
devicetree, linux-kernel, linux-clk, linux-gpio, linux-arm-msm,
linux-soc, linux-arm-kernel, absahu, sjaganat, sricharan,
Manoharan Vijaya Raghavan
On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
>
>
> On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
> > On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
> >
[..]
> > > +enum ipq8074_functions {
> >
> > Please keep these sorted alphabetically.
>
> Ok
>
> > > + msm_mux_gpio,
> > > + msm_mux_qpic_pad,
> > > + msm_mux_blsp5_i2c,
> > > + msm_mux_blsp5_spi,
> > > + msm_mux_wci20,
> >
> > What does "20" mean here?
>
> This is for Wireless Coex Interface. The same functionality can be muxed on
> to different GPIOs. WCI2, is the 2nd edition of the WCI standard and 0, 1
> are for the muxing to different GPIOs (alternate muxes).
>
In other Qualcomm platforms the alternative muxes are denoted by letters
(a,b,c...). Would you mind picking up this naming scheme, or do you see
any problems with that? (E.g. wci2a in this case)
Btw, do you need any additional configuration for selecting alternative
muxing or is that automagical these days?
> > > + msm_mux_blsp3_spi3,
> > > + msm_mux_burn0,
> > > + msm_mux_pcm_zsi0,
> > > + msm_mux_blsp5_uart,
> > > + msm_mux_mac12,
> >
> > What does "12" mean here?
>
> The SoC has three MAC cores. Each core has two pins for the smart antenna
> feature. macXY indicates the function select for MAC no. X and smart antenna
> no. Y.
>
Ok
> > > + msm_mux_blsp3_spi0,
> > > + msm_mux_burn1,
> > > + msm_mux_mac01,
> > > + msm_mux_qdss_cti_trig_out_b0,
> > > + msm_mux_qdss_cti_trig_in_b0,
> > > + msm_mux_qpic_pad4,
> >
> > What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
> > alternative muxings...?
>
> This is for the NAND and LCD display. The pins listed are the 9 data pins.
>
Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
possible to reference a partial group in the DTS, if that's necessary)
> > > + msm_mux_blsp4_uart0,
> > > + msm_mux_blsp4_i2c0,
> > > + msm_mux_blsp4_spi0,
> > > + msm_mux_mac21,
> > > + msm_mux_qdss_cti_trig_out_b1,
> > > + msm_mux_qpic_pad5,
> > > + msm_mux_qdss_cti_trig_in_b1,
> > > + msm_mux_qpic_pad6,
> > > + msm_mux_qpic_pad7,
> > > + msm_mux_cxc0,
> > > + msm_mux_mac13,
> > > + msm_mux_qdss_cti_trig_in_a1,
> > > + msm_mux_qdss_cti_trig_out_a1,
> > > + msm_mux_wci22,
> > > + msm_mux_qdss_cti_trig_in_a0,
> > > + msm_mux_qpic_pad1,
> > > + msm_mux_qdss_cti_trig_out_a0,
> > > + msm_mux_qpic_pad2,
> > > + msm_mux_qpic_pad3,
> > > + msm_mux_qdss_traceclk_b,
> > > + msm_mux_qpic_pad0,
> > > + msm_mux_qdss_tracectl_b,
> > > + msm_mux_qpic_pad8,
> > > + msm_mux_pcm_zsi1,
> > > + msm_mux_qdss_tracedata_b,
> > > + msm_mux_led0,
> > > + msm_mux_pwm04,
> >
> > What does "04" mean here?
>
> There are 4 Pulse Width Modulation channels, pwmXY is pwm channel X and pin
> Y.
So Y is alternative mux? Can we use letters for this as well?
> >
> > > + msm_mux_led1,
> > > + msm_mux_pwm14,
> > > + msm_mux_led2,
> > > + msm_mux_pwm24,
> > > + msm_mux_pwm00,
> > > + msm_mux_blsp4_uart1,
> >
> > Are uart0 vs uart1 alternative muxes?
>
> These are two different uarts available at two independent pins.
>
Ok, then I'm happy with the naming of this :)
Thanks,
Bjorn
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
@ 2017-05-14 4:23 ` Bjorn Andersson
0 siblings, 0 replies; 49+ messages in thread
From: Bjorn Andersson @ 2017-05-14 4:23 UTC (permalink / raw)
To: linux-arm-kernel
On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
>
>
> On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
> > On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
> >
[..]
> > > +enum ipq8074_functions {
> >
> > Please keep these sorted alphabetically.
>
> Ok
>
> > > + msm_mux_gpio,
> > > + msm_mux_qpic_pad,
> > > + msm_mux_blsp5_i2c,
> > > + msm_mux_blsp5_spi,
> > > + msm_mux_wci20,
> >
> > What does "20" mean here?
>
> This is for Wireless Coex Interface. The same functionality can be muxed on
> to different GPIOs. WCI2, is the 2nd edition of the WCI standard and 0, 1
> are for the muxing to different GPIOs (alternate muxes).
>
In other Qualcomm platforms the alternative muxes are denoted by letters
(a,b,c...). Would you mind picking up this naming scheme, or do you see
any problems with that? (E.g. wci2a in this case)
Btw, do you need any additional configuration for selecting alternative
muxing or is that automagical these days?
> > > + msm_mux_blsp3_spi3,
> > > + msm_mux_burn0,
> > > + msm_mux_pcm_zsi0,
> > > + msm_mux_blsp5_uart,
> > > + msm_mux_mac12,
> >
> > What does "12" mean here?
>
> The SoC has three MAC cores. Each core has two pins for the smart antenna
> feature. macXY indicates the function select for MAC no. X and smart antenna
> no. Y.
>
Ok
> > > + msm_mux_blsp3_spi0,
> > > + msm_mux_burn1,
> > > + msm_mux_mac01,
> > > + msm_mux_qdss_cti_trig_out_b0,
> > > + msm_mux_qdss_cti_trig_in_b0,
> > > + msm_mux_qpic_pad4,
> >
> > What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
> > alternative muxings...?
>
> This is for the NAND and LCD display. The pins listed are the 9 data pins.
>
Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
possible to reference a partial group in the DTS, if that's necessary)
> > > + msm_mux_blsp4_uart0,
> > > + msm_mux_blsp4_i2c0,
> > > + msm_mux_blsp4_spi0,
> > > + msm_mux_mac21,
> > > + msm_mux_qdss_cti_trig_out_b1,
> > > + msm_mux_qpic_pad5,
> > > + msm_mux_qdss_cti_trig_in_b1,
> > > + msm_mux_qpic_pad6,
> > > + msm_mux_qpic_pad7,
> > > + msm_mux_cxc0,
> > > + msm_mux_mac13,
> > > + msm_mux_qdss_cti_trig_in_a1,
> > > + msm_mux_qdss_cti_trig_out_a1,
> > > + msm_mux_wci22,
> > > + msm_mux_qdss_cti_trig_in_a0,
> > > + msm_mux_qpic_pad1,
> > > + msm_mux_qdss_cti_trig_out_a0,
> > > + msm_mux_qpic_pad2,
> > > + msm_mux_qpic_pad3,
> > > + msm_mux_qdss_traceclk_b,
> > > + msm_mux_qpic_pad0,
> > > + msm_mux_qdss_tracectl_b,
> > > + msm_mux_qpic_pad8,
> > > + msm_mux_pcm_zsi1,
> > > + msm_mux_qdss_tracedata_b,
> > > + msm_mux_led0,
> > > + msm_mux_pwm04,
> >
> > What does "04" mean here?
>
> There are 4 Pulse Width Modulation channels, pwmXY is pwm channel X and pin
> Y.
So Y is alternative mux? Can we use letters for this as well?
> >
> > > + msm_mux_led1,
> > > + msm_mux_pwm14,
> > > + msm_mux_led2,
> > > + msm_mux_pwm24,
> > > + msm_mux_pwm00,
> > > + msm_mux_blsp4_uart1,
> >
> > Are uart0 vs uart1 alternative muxes?
>
> These are two different uarts available at two independent pins.
>
Ok, then I'm happy with the naming of this :)
Thanks,
Bjorn
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
2017-05-14 4:23 ` Bjorn Andersson
@ 2017-05-15 9:05 ` Varadarajan Narayanan
-1 siblings, 0 replies; 49+ messages in thread
From: Varadarajan Narayanan @ 2017-05-15 9:05 UTC (permalink / raw)
To: Bjorn Andersson
Cc: robh+dt, mark.rutland, mturquette, sboyd, linus.walleij,
andy.gross, david.brown, catalin.marinas, will.deacon,
devicetree, linux-kernel, linux-clk, linux-gpio, linux-arm-msm,
linux-soc, linux-arm-kernel, absahu, sjaganat, sricharan,
Manoharan Vijaya Raghavan
On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
> On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
>
>> On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
>>> On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
>>>
> [..]
>>>> +enum ipq8074_functions {
>>>
>>> Please keep these sorted alphabetically.
>>
>> Ok
>>
>>>> + msm_mux_gpio,
>>>> + msm_mux_qpic_pad,
>>>> + msm_mux_blsp5_i2c,
>>>> + msm_mux_blsp5_spi,
>>>> + msm_mux_wci20,
>>>
>>> What does "20" mean here?
>>
>> This is for Wireless Coex Interface. The same functionality can be muxed on
>> to different GPIOs. WCI2, is the 2nd edition of the WCI standard and 0, 1
>> are for the muxing to different GPIOs (alternate muxes).
>>
>
> In other Qualcomm platforms the alternative muxes are denoted by letters
> (a,b,c...). Would you mind picking up this naming scheme, or do you see
> any problems with that? (E.g. wci2a in this case)
Ok
> Btw, do you need any additional configuration for selecting alternative
> muxing or is that automagical these days?
No additional configuration is needed.
>>>> + msm_mux_blsp3_spi3,
>>>> + msm_mux_burn0,
>>>> + msm_mux_pcm_zsi0,
>>>> + msm_mux_blsp5_uart,
>>>> + msm_mux_mac12,
>>>
>>> What does "12" mean here?
>>
>> The SoC has three MAC cores. Each core has two pins for the smart antenna
>> feature. macXY indicates the function select for MAC no. X and smart antenna
>> no. Y.
>>
>
> Ok
>
>>>> + msm_mux_blsp3_spi0,
>>>> + msm_mux_burn1,
>>>> + msm_mux_mac01,
>>>> + msm_mux_qdss_cti_trig_out_b0,
>>>> + msm_mux_qdss_cti_trig_in_b0,
>>>> + msm_mux_qpic_pad4,
>>>
>>> What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
>>> alternative muxings...?
>>
>> This is for the NAND and LCD display. The pins listed are the 9 data pins.
>>
>
> Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
> possible to reference a partial group in the DTS, if that's necessary)
There are two sets of 9 pins, either of which can go to NAND or LCD.
Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
Is that ok?
>>>> + msm_mux_blsp4_uart0,
>>>> + msm_mux_blsp4_i2c0,
>>>> + msm_mux_blsp4_spi0,
>>>> + msm_mux_mac21,
>>>> + msm_mux_qdss_cti_trig_out_b1,
>>>> + msm_mux_qpic_pad5,
>>>> + msm_mux_qdss_cti_trig_in_b1,
>>>> + msm_mux_qpic_pad6,
>>>> + msm_mux_qpic_pad7,
>>>> + msm_mux_cxc0,
>>>> + msm_mux_mac13,
>>>> + msm_mux_qdss_cti_trig_in_a1,
>>>> + msm_mux_qdss_cti_trig_out_a1,
>>>> + msm_mux_wci22,
>>>> + msm_mux_qdss_cti_trig_in_a0,
>>>> + msm_mux_qpic_pad1,
>>>> + msm_mux_qdss_cti_trig_out_a0,
>>>> + msm_mux_qpic_pad2,
>>>> + msm_mux_qpic_pad3,
>>>> + msm_mux_qdss_traceclk_b,
>>>> + msm_mux_qpic_pad0,
>>>> + msm_mux_qdss_tracectl_b,
>>>> + msm_mux_qpic_pad8,
>>>> + msm_mux_pcm_zsi1,
>>>> + msm_mux_qdss_tracedata_b,
>>>> + msm_mux_led0,
>>>> + msm_mux_pwm04,
>>>
>>> What does "04" mean here?
>>
>> There are 4 Pulse Width Modulation channels, pwmXY is pwm channel X and pin
>> Y.
>
> So Y is alternative mux? Can we use letters for this as well?
Ok
>>>> + msm_mux_led1,
>>>> + msm_mux_pwm14,
>>>> + msm_mux_led2,
>>>> + msm_mux_pwm24,
>>>> + msm_mux_pwm00,
>>>> + msm_mux_blsp4_uart1,
>>>
>>> Are uart0 vs uart1 alternative muxes?
>>
>> These are two different uarts available at two independent pins.
>>
>
> Ok, then I'm happy with the naming of this :)
>
> Thanks,
> Bjorn
>
Thanks
Varada
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum, a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
@ 2017-05-15 9:05 ` Varadarajan Narayanan
0 siblings, 0 replies; 49+ messages in thread
From: Varadarajan Narayanan @ 2017-05-15 9:05 UTC (permalink / raw)
To: linux-arm-kernel
On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
> On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
>
>> On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
>>> On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
>>>
> [..]
>>>> +enum ipq8074_functions {
>>>
>>> Please keep these sorted alphabetically.
>>
>> Ok
>>
>>>> + msm_mux_gpio,
>>>> + msm_mux_qpic_pad,
>>>> + msm_mux_blsp5_i2c,
>>>> + msm_mux_blsp5_spi,
>>>> + msm_mux_wci20,
>>>
>>> What does "20" mean here?
>>
>> This is for Wireless Coex Interface. The same functionality can be muxed on
>> to different GPIOs. WCI2, is the 2nd edition of the WCI standard and 0, 1
>> are for the muxing to different GPIOs (alternate muxes).
>>
>
> In other Qualcomm platforms the alternative muxes are denoted by letters
> (a,b,c...). Would you mind picking up this naming scheme, or do you see
> any problems with that? (E.g. wci2a in this case)
Ok
> Btw, do you need any additional configuration for selecting alternative
> muxing or is that automagical these days?
No additional configuration is needed.
>>>> + msm_mux_blsp3_spi3,
>>>> + msm_mux_burn0,
>>>> + msm_mux_pcm_zsi0,
>>>> + msm_mux_blsp5_uart,
>>>> + msm_mux_mac12,
>>>
>>> What does "12" mean here?
>>
>> The SoC has three MAC cores. Each core has two pins for the smart antenna
>> feature. macXY indicates the function select for MAC no. X and smart antenna
>> no. Y.
>>
>
> Ok
>
>>>> + msm_mux_blsp3_spi0,
>>>> + msm_mux_burn1,
>>>> + msm_mux_mac01,
>>>> + msm_mux_qdss_cti_trig_out_b0,
>>>> + msm_mux_qdss_cti_trig_in_b0,
>>>> + msm_mux_qpic_pad4,
>>>
>>> What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
>>> alternative muxings...?
>>
>> This is for the NAND and LCD display. The pins listed are the 9 data pins.
>>
>
> Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
> possible to reference a partial group in the DTS, if that's necessary)
There are two sets of 9 pins, either of which can go to NAND or LCD.
Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
Is that ok?
>>>> + msm_mux_blsp4_uart0,
>>>> + msm_mux_blsp4_i2c0,
>>>> + msm_mux_blsp4_spi0,
>>>> + msm_mux_mac21,
>>>> + msm_mux_qdss_cti_trig_out_b1,
>>>> + msm_mux_qpic_pad5,
>>>> + msm_mux_qdss_cti_trig_in_b1,
>>>> + msm_mux_qpic_pad6,
>>>> + msm_mux_qpic_pad7,
>>>> + msm_mux_cxc0,
>>>> + msm_mux_mac13,
>>>> + msm_mux_qdss_cti_trig_in_a1,
>>>> + msm_mux_qdss_cti_trig_out_a1,
>>>> + msm_mux_wci22,
>>>> + msm_mux_qdss_cti_trig_in_a0,
>>>> + msm_mux_qpic_pad1,
>>>> + msm_mux_qdss_cti_trig_out_a0,
>>>> + msm_mux_qpic_pad2,
>>>> + msm_mux_qpic_pad3,
>>>> + msm_mux_qdss_traceclk_b,
>>>> + msm_mux_qpic_pad0,
>>>> + msm_mux_qdss_tracectl_b,
>>>> + msm_mux_qpic_pad8,
>>>> + msm_mux_pcm_zsi1,
>>>> + msm_mux_qdss_tracedata_b,
>>>> + msm_mux_led0,
>>>> + msm_mux_pwm04,
>>>
>>> What does "04" mean here?
>>
>> There are 4 Pulse Width Modulation channels, pwmXY is pwm channel X and pin
>> Y.
>
> So Y is alternative mux? Can we use letters for this as well?
Ok
>>>> + msm_mux_led1,
>>>> + msm_mux_pwm14,
>>>> + msm_mux_led2,
>>>> + msm_mux_pwm24,
>>>> + msm_mux_pwm00,
>>>> + msm_mux_blsp4_uart1,
>>>
>>> Are uart0 vs uart1 alternative muxes?
>>
>> These are two different uarts available at two independent pins.
>>
>
> Ok, then I'm happy with the naming of this :)
>
> Thanks,
> Bjorn
>
Thanks
Varada
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum, a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
2017-05-15 9:05 ` Varadarajan Narayanan
(?)
@ 2017-05-15 11:24 ` Varadarajan Narayanan
-1 siblings, 0 replies; 49+ messages in thread
From: Varadarajan Narayanan @ 2017-05-15 11:24 UTC (permalink / raw)
To: Bjorn Andersson
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
mturquette-rdvid1DuHRBWk0Htik3J/w, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
andy.gross-QSEj5FYQhm4dnm+yROfE0A,
david.brown-QSEj5FYQhm4dnm+yROfE0A, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-soc-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
absahu-sgV2jX0FEOL9JmXXK+q4OQ, sjaganat-sgV2jX0FEOL9JmXXK+q4OQ,
sricharan-sgV2jX0FEOL9JmXXK+q4OQ, Manoharan Vijaya Raghavan
On 5/15/2017 2:35 PM, Varadarajan Narayanan wrote:
> On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
>> On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
>>
>>> On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
>>>> On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
>>>>
>> [..]
>>>>> +enum ipq8074_functions {
>>>>
>>>> Please keep these sorted alphabetically.
>>>
>>> Ok
>>>
>>>>> + msm_mux_gpio,
>>>>> + msm_mux_qpic_pad,
>>>>> + msm_mux_blsp5_i2c,
>>>>> + msm_mux_blsp5_spi,
>>>>> + msm_mux_wci20,
>>>>
>>>> What does "20" mean here?
>>>
>>> This is for Wireless Coex Interface. The same functionality can be
>>> muxed on
>>> to different GPIOs. WCI2, is the 2nd edition of the WCI standard and
>>> 0, 1
>>> are for the muxing to different GPIOs (alternate muxes).
>>>
>>
>> In other Qualcomm platforms the alternative muxes are denoted by letters
>> (a,b,c...). Would you mind picking up this naming scheme, or do you see
>> any problems with that? (E.g. wci2a in this case)
>
> Ok
>
>> Btw, do you need any additional configuration for selecting alternative
>> muxing or is that automagical these days?
>
> No additional configuration is needed.
>
>>>>> + msm_mux_blsp3_spi3,
>>>>> + msm_mux_burn0,
>>>>> + msm_mux_pcm_zsi0,
>>>>> + msm_mux_blsp5_uart,
>>>>> + msm_mux_mac12,
>>>>
>>>> What does "12" mean here?
>>>
>>> The SoC has three MAC cores. Each core has two pins for the smart
>>> antenna
>>> feature. macXY indicates the function select for MAC no. X and smart
>>> antenna
>>> no. Y.
>>>
>>
>> Ok
>>
>>>>> + msm_mux_blsp3_spi0,
>>>>> + msm_mux_burn1,
>>>>> + msm_mux_mac01,
>>>>> + msm_mux_qdss_cti_trig_out_b0,
>>>>> + msm_mux_qdss_cti_trig_in_b0,
>>>>> + msm_mux_qpic_pad4,
>>>>
>>>> What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
>>>> alternative muxings...?
>>>
>>> This is for the NAND and LCD display. The pins listed are the 9 data
>>> pins.
>>>
>>
>> Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
>> possible to reference a partial group in the DTS, if that's necessary)
>
> There are two sets of 9 pins, either of which can go to NAND or LCD.
> Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
> Is that ok?
>
>>>>> + msm_mux_blsp4_uart0,
>>>>> + msm_mux_blsp4_i2c0,
>>>>> + msm_mux_blsp4_spi0,
>>>>> + msm_mux_mac21,
>>>>> + msm_mux_qdss_cti_trig_out_b1,
>>>>> + msm_mux_qpic_pad5,
>>>>> + msm_mux_qdss_cti_trig_in_b1,
>>>>> + msm_mux_qpic_pad6,
>>>>> + msm_mux_qpic_pad7,
>>>>> + msm_mux_cxc0,
>>>>> + msm_mux_mac13,
>>>>> + msm_mux_qdss_cti_trig_in_a1,
>>>>> + msm_mux_qdss_cti_trig_out_a1,
>>>>> + msm_mux_wci22,
>>>>> + msm_mux_qdss_cti_trig_in_a0,
>>>>> + msm_mux_qpic_pad1,
>>>>> + msm_mux_qdss_cti_trig_out_a0,
>>>>> + msm_mux_qpic_pad2,
>>>>> + msm_mux_qpic_pad3,
>>>>> + msm_mux_qdss_traceclk_b,
>>>>> + msm_mux_qpic_pad0,
>>>>> + msm_mux_qdss_tracectl_b,
>>>>> + msm_mux_qpic_pad8,
>>>>> + msm_mux_pcm_zsi1,
>>>>> + msm_mux_qdss_tracedata_b,
>>>>> + msm_mux_led0,
>>>>> + msm_mux_pwm04,
>>>>
>>>> What does "04" mean here?
>>>
>>> There are 4 Pulse Width Modulation channels, pwmXY is pwm channel X
>>> and pin
>>> Y.
>>
>> So Y is alternative mux? Can we use letters for this as well?
>
> Ok
Sorry, actually they are not alternative muxes. There are 4 different
PWM instances. Each PWM instance can handle 'n' different GPIOs (for
example, that can be connected to LED etc.).
Thanks
Varada
>>>>> + msm_mux_led1,
>>>>> + msm_mux_pwm14,
>>>>> + msm_mux_led2,
>>>>> + msm_mux_pwm24,
>>>>> + msm_mux_pwm00,
>>>>> + msm_mux_blsp4_uart1,
>>>>
>>>> Are uart0 vs uart1 alternative muxes?
>>>
>>> These are two different uarts available at two independent pins.
>>>
>>
>> Ok, then I'm happy with the naming of this :)
>>
>> Thanks,
>> Bjorn
>>
>
> Thanks
> Varada
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum, a Linux Foundation Collaborative Project
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
@ 2017-05-15 11:24 ` Varadarajan Narayanan
0 siblings, 0 replies; 49+ messages in thread
From: Varadarajan Narayanan @ 2017-05-15 11:24 UTC (permalink / raw)
To: Bjorn Andersson
Cc: robh+dt, mark.rutland, mturquette, sboyd, linus.walleij,
andy.gross, david.brown, catalin.marinas, will.deacon,
devicetree, linux-kernel, linux-clk, linux-gpio, linux-arm-msm,
linux-soc, linux-arm-kernel, absahu, sjaganat, sricharan,
Manoharan Vijaya Raghavan
On 5/15/2017 2:35 PM, Varadarajan Narayanan wrote:
> On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
>> On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
>>
>>> On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
>>>> On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
>>>>
>> [..]
>>>>> +enum ipq8074_functions {
>>>>
>>>> Please keep these sorted alphabetically.
>>>
>>> Ok
>>>
>>>>> + msm_mux_gpio,
>>>>> + msm_mux_qpic_pad,
>>>>> + msm_mux_blsp5_i2c,
>>>>> + msm_mux_blsp5_spi,
>>>>> + msm_mux_wci20,
>>>>
>>>> What does "20" mean here?
>>>
>>> This is for Wireless Coex Interface. The same functionality can be
>>> muxed on
>>> to different GPIOs. WCI2, is the 2nd edition of the WCI standard and
>>> 0, 1
>>> are for the muxing to different GPIOs (alternate muxes).
>>>
>>
>> In other Qualcomm platforms the alternative muxes are denoted by letters
>> (a,b,c...). Would you mind picking up this naming scheme, or do you see
>> any problems with that? (E.g. wci2a in this case)
>
> Ok
>
>> Btw, do you need any additional configuration for selecting alternative
>> muxing or is that automagical these days?
>
> No additional configuration is needed.
>
>>>>> + msm_mux_blsp3_spi3,
>>>>> + msm_mux_burn0,
>>>>> + msm_mux_pcm_zsi0,
>>>>> + msm_mux_blsp5_uart,
>>>>> + msm_mux_mac12,
>>>>
>>>> What does "12" mean here?
>>>
>>> The SoC has three MAC cores. Each core has two pins for the smart
>>> antenna
>>> feature. macXY indicates the function select for MAC no. X and smart
>>> antenna
>>> no. Y.
>>>
>>
>> Ok
>>
>>>>> + msm_mux_blsp3_spi0,
>>>>> + msm_mux_burn1,
>>>>> + msm_mux_mac01,
>>>>> + msm_mux_qdss_cti_trig_out_b0,
>>>>> + msm_mux_qdss_cti_trig_in_b0,
>>>>> + msm_mux_qpic_pad4,
>>>>
>>>> What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
>>>> alternative muxings...?
>>>
>>> This is for the NAND and LCD display. The pins listed are the 9 data
>>> pins.
>>>
>>
>> Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
>> possible to reference a partial group in the DTS, if that's necessary)
>
> There are two sets of 9 pins, either of which can go to NAND or LCD.
> Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
> Is that ok?
>
>>>>> + msm_mux_blsp4_uart0,
>>>>> + msm_mux_blsp4_i2c0,
>>>>> + msm_mux_blsp4_spi0,
>>>>> + msm_mux_mac21,
>>>>> + msm_mux_qdss_cti_trig_out_b1,
>>>>> + msm_mux_qpic_pad5,
>>>>> + msm_mux_qdss_cti_trig_in_b1,
>>>>> + msm_mux_qpic_pad6,
>>>>> + msm_mux_qpic_pad7,
>>>>> + msm_mux_cxc0,
>>>>> + msm_mux_mac13,
>>>>> + msm_mux_qdss_cti_trig_in_a1,
>>>>> + msm_mux_qdss_cti_trig_out_a1,
>>>>> + msm_mux_wci22,
>>>>> + msm_mux_qdss_cti_trig_in_a0,
>>>>> + msm_mux_qpic_pad1,
>>>>> + msm_mux_qdss_cti_trig_out_a0,
>>>>> + msm_mux_qpic_pad2,
>>>>> + msm_mux_qpic_pad3,
>>>>> + msm_mux_qdss_traceclk_b,
>>>>> + msm_mux_qpic_pad0,
>>>>> + msm_mux_qdss_tracectl_b,
>>>>> + msm_mux_qpic_pad8,
>>>>> + msm_mux_pcm_zsi1,
>>>>> + msm_mux_qdss_tracedata_b,
>>>>> + msm_mux_led0,
>>>>> + msm_mux_pwm04,
>>>>
>>>> What does "04" mean here?
>>>
>>> There are 4 Pulse Width Modulation channels, pwmXY is pwm channel X
>>> and pin
>>> Y.
>>
>> So Y is alternative mux? Can we use letters for this as well?
>
> Ok
Sorry, actually they are not alternative muxes. There are 4 different
PWM instances. Each PWM instance can handle 'n' different GPIOs (for
example, that can be connected to LED etc.).
Thanks
Varada
>>>>> + msm_mux_led1,
>>>>> + msm_mux_pwm14,
>>>>> + msm_mux_led2,
>>>>> + msm_mux_pwm24,
>>>>> + msm_mux_pwm00,
>>>>> + msm_mux_blsp4_uart1,
>>>>
>>>> Are uart0 vs uart1 alternative muxes?
>>>
>>> These are two different uarts available at two independent pins.
>>>
>>
>> Ok, then I'm happy with the naming of this :)
>>
>> Thanks,
>> Bjorn
>>
>
> Thanks
> Varada
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum, a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
@ 2017-05-15 11:24 ` Varadarajan Narayanan
0 siblings, 0 replies; 49+ messages in thread
From: Varadarajan Narayanan @ 2017-05-15 11:24 UTC (permalink / raw)
To: linux-arm-kernel
On 5/15/2017 2:35 PM, Varadarajan Narayanan wrote:
> On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
>> On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
>>
>>> On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
>>>> On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
>>>>
>> [..]
>>>>> +enum ipq8074_functions {
>>>>
>>>> Please keep these sorted alphabetically.
>>>
>>> Ok
>>>
>>>>> + msm_mux_gpio,
>>>>> + msm_mux_qpic_pad,
>>>>> + msm_mux_blsp5_i2c,
>>>>> + msm_mux_blsp5_spi,
>>>>> + msm_mux_wci20,
>>>>
>>>> What does "20" mean here?
>>>
>>> This is for Wireless Coex Interface. The same functionality can be
>>> muxed on
>>> to different GPIOs. WCI2, is the 2nd edition of the WCI standard and
>>> 0, 1
>>> are for the muxing to different GPIOs (alternate muxes).
>>>
>>
>> In other Qualcomm platforms the alternative muxes are denoted by letters
>> (a,b,c...). Would you mind picking up this naming scheme, or do you see
>> any problems with that? (E.g. wci2a in this case)
>
> Ok
>
>> Btw, do you need any additional configuration for selecting alternative
>> muxing or is that automagical these days?
>
> No additional configuration is needed.
>
>>>>> + msm_mux_blsp3_spi3,
>>>>> + msm_mux_burn0,
>>>>> + msm_mux_pcm_zsi0,
>>>>> + msm_mux_blsp5_uart,
>>>>> + msm_mux_mac12,
>>>>
>>>> What does "12" mean here?
>>>
>>> The SoC has three MAC cores. Each core has two pins for the smart
>>> antenna
>>> feature. macXY indicates the function select for MAC no. X and smart
>>> antenna
>>> no. Y.
>>>
>>
>> Ok
>>
>>>>> + msm_mux_blsp3_spi0,
>>>>> + msm_mux_burn1,
>>>>> + msm_mux_mac01,
>>>>> + msm_mux_qdss_cti_trig_out_b0,
>>>>> + msm_mux_qdss_cti_trig_in_b0,
>>>>> + msm_mux_qpic_pad4,
>>>>
>>>> What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
>>>> alternative muxings...?
>>>
>>> This is for the NAND and LCD display. The pins listed are the 9 data
>>> pins.
>>>
>>
>> Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
>> possible to reference a partial group in the DTS, if that's necessary)
>
> There are two sets of 9 pins, either of which can go to NAND or LCD.
> Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
> Is that ok?
>
>>>>> + msm_mux_blsp4_uart0,
>>>>> + msm_mux_blsp4_i2c0,
>>>>> + msm_mux_blsp4_spi0,
>>>>> + msm_mux_mac21,
>>>>> + msm_mux_qdss_cti_trig_out_b1,
>>>>> + msm_mux_qpic_pad5,
>>>>> + msm_mux_qdss_cti_trig_in_b1,
>>>>> + msm_mux_qpic_pad6,
>>>>> + msm_mux_qpic_pad7,
>>>>> + msm_mux_cxc0,
>>>>> + msm_mux_mac13,
>>>>> + msm_mux_qdss_cti_trig_in_a1,
>>>>> + msm_mux_qdss_cti_trig_out_a1,
>>>>> + msm_mux_wci22,
>>>>> + msm_mux_qdss_cti_trig_in_a0,
>>>>> + msm_mux_qpic_pad1,
>>>>> + msm_mux_qdss_cti_trig_out_a0,
>>>>> + msm_mux_qpic_pad2,
>>>>> + msm_mux_qpic_pad3,
>>>>> + msm_mux_qdss_traceclk_b,
>>>>> + msm_mux_qpic_pad0,
>>>>> + msm_mux_qdss_tracectl_b,
>>>>> + msm_mux_qpic_pad8,
>>>>> + msm_mux_pcm_zsi1,
>>>>> + msm_mux_qdss_tracedata_b,
>>>>> + msm_mux_led0,
>>>>> + msm_mux_pwm04,
>>>>
>>>> What does "04" mean here?
>>>
>>> There are 4 Pulse Width Modulation channels, pwmXY is pwm channel X
>>> and pin
>>> Y.
>>
>> So Y is alternative mux? Can we use letters for this as well?
>
> Ok
Sorry, actually they are not alternative muxes. There are 4 different
PWM instances. Each PWM instance can handle 'n' different GPIOs (for
example, that can be connected to LED etc.).
Thanks
Varada
>>>>> + msm_mux_led1,
>>>>> + msm_mux_pwm14,
>>>>> + msm_mux_led2,
>>>>> + msm_mux_pwm24,
>>>>> + msm_mux_pwm00,
>>>>> + msm_mux_blsp4_uart1,
>>>>
>>>> Are uart0 vs uart1 alternative muxes?
>>>
>>> These are two different uarts available at two independent pins.
>>>
>>
>> Ok, then I'm happy with the naming of this :)
>>
>> Thanks,
>> Bjorn
>>
>
> Thanks
> Varada
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum, a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
2017-05-15 9:05 ` Varadarajan Narayanan
@ 2017-05-17 19:33 ` Bjorn Andersson
-1 siblings, 0 replies; 49+ messages in thread
From: Bjorn Andersson @ 2017-05-17 19:33 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: robh+dt, mark.rutland, mturquette, sboyd, linus.walleij,
andy.gross, david.brown, catalin.marinas, will.deacon,
devicetree, linux-kernel, linux-clk, linux-gpio, linux-arm-msm,
linux-soc, linux-arm-kernel, absahu, sjaganat, sricharan,
Manoharan Vijaya Raghavan
On Mon 15 May 02:05 PDT 2017, Varadarajan Narayanan wrote:
> On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
> > On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
> >
> > > On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
> > > > On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
[..]
> > > > > + msm_mux_qpic_pad4,
> > > >
> > > > What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
> > > > alternative muxings...?
> > >
> > > This is for the NAND and LCD display. The pins listed are the 9 data pins.
> > >
> >
> > Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
> > possible to reference a partial group in the DTS, if that's necessary)
>
> There are two sets of 9 pins, either of which can go to NAND or LCD.
> Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
> Is that ok?
>
So you have NAND and LCD hardware muxed to either "a" or "b" and then
you mux either "a" or "b" out onto actual pins?
How is this first mux configured?
I think the a/b scheme sounds reasonable, if above is how it works.
Regards,
Bjorn
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
@ 2017-05-17 19:33 ` Bjorn Andersson
0 siblings, 0 replies; 49+ messages in thread
From: Bjorn Andersson @ 2017-05-17 19:33 UTC (permalink / raw)
To: linux-arm-kernel
On Mon 15 May 02:05 PDT 2017, Varadarajan Narayanan wrote:
> On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
> > On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
> >
> > > On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
> > > > On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
[..]
> > > > > + msm_mux_qpic_pad4,
> > > >
> > > > What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
> > > > alternative muxings...?
> > >
> > > This is for the NAND and LCD display. The pins listed are the 9 data pins.
> > >
> >
> > Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
> > possible to reference a partial group in the DTS, if that's necessary)
>
> There are two sets of 9 pins, either of which can go to NAND or LCD.
> Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
> Is that ok?
>
So you have NAND and LCD hardware muxed to either "a" or "b" and then
you mux either "a" or "b" out onto actual pins?
How is this first mux configured?
I think the a/b scheme sounds reasonable, if above is how it works.
Regards,
Bjorn
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
2017-05-15 11:24 ` Varadarajan Narayanan
@ 2017-05-17 19:47 ` Bjorn Andersson
-1 siblings, 0 replies; 49+ messages in thread
From: Bjorn Andersson @ 2017-05-17 19:47 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: robh+dt, mark.rutland, mturquette, sboyd, linus.walleij,
andy.gross, david.brown, catalin.marinas, will.deacon,
devicetree, linux-kernel, linux-clk, linux-gpio, linux-arm-msm,
linux-soc, linux-arm-kernel, absahu, sjaganat, sricharan,
Manoharan Vijaya Raghavan
On Mon 15 May 04:24 PDT 2017, Varadarajan Narayanan wrote:
>
>
> On 5/15/2017 2:35 PM, Varadarajan Narayanan wrote:
> > On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
> > > On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
> > >
> > > > On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
> > > > > On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
> > > > >
> > > [..]
> > > > > > +enum ipq8074_functions {
> > > > >
> > > > > Please keep these sorted alphabetically.
> > > >
> > > > Ok
> > > >
> > > > > > + msm_mux_gpio,
> > > > > > + msm_mux_qpic_pad,
> > > > > > + msm_mux_blsp5_i2c,
> > > > > > + msm_mux_blsp5_spi,
> > > > > > + msm_mux_wci20,
> > > > >
> > > > > What does "20" mean here?
> > > >
> > > > This is for Wireless Coex Interface. The same functionality can
> > > > be muxed on
> > > > to different GPIOs. WCI2, is the 2nd edition of the WCI standard
> > > > and 0, 1
> > > > are for the muxing to different GPIOs (alternate muxes).
> > > >
> > >
> > > In other Qualcomm platforms the alternative muxes are denoted by letters
> > > (a,b,c...). Would you mind picking up this naming scheme, or do you see
> > > any problems with that? (E.g. wci2a in this case)
> >
> > Ok
> >
> > > Btw, do you need any additional configuration for selecting alternative
> > > muxing or is that automagical these days?
> >
> > No additional configuration is needed.
> >
> > > > > > + msm_mux_blsp3_spi3,
> > > > > > + msm_mux_burn0,
> > > > > > + msm_mux_pcm_zsi0,
> > > > > > + msm_mux_blsp5_uart,
> > > > > > + msm_mux_mac12,
> > > > >
> > > > > What does "12" mean here?
> > > >
> > > > The SoC has three MAC cores. Each core has two pins for the
> > > > smart antenna
> > > > feature. macXY indicates the function select for MAC no. X and
> > > > smart antenna
> > > > no. Y.
> > > >
> > >
> > > Ok
> > >
> > > > > > + msm_mux_blsp3_spi0,
> > > > > > + msm_mux_burn1,
> > > > > > + msm_mux_mac01,
> > > > > > + msm_mux_qdss_cti_trig_out_b0,
> > > > > > + msm_mux_qdss_cti_trig_in_b0,
> > > > > > + msm_mux_qpic_pad4,
> > > > >
> > > > > What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
> > > > > alternative muxings...?
> > > >
> > > > This is for the NAND and LCD display. The pins listed are the 9
> > > > data pins.
> > > >
> > >
> > > Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
> > > possible to reference a partial group in the DTS, if that's necessary)
> >
> > There are two sets of 9 pins, either of which can go to NAND or LCD.
> > Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
> > Is that ok?
> >
> > > > > > + msm_mux_blsp4_uart0,
> > > > > > + msm_mux_blsp4_i2c0,
> > > > > > + msm_mux_blsp4_spi0,
> > > > > > + msm_mux_mac21,
> > > > > > + msm_mux_qdss_cti_trig_out_b1,
> > > > > > + msm_mux_qpic_pad5,
> > > > > > + msm_mux_qdss_cti_trig_in_b1,
> > > > > > + msm_mux_qpic_pad6,
> > > > > > + msm_mux_qpic_pad7,
> > > > > > + msm_mux_cxc0,
> > > > > > + msm_mux_mac13,
> > > > > > + msm_mux_qdss_cti_trig_in_a1,
> > > > > > + msm_mux_qdss_cti_trig_out_a1,
> > > > > > + msm_mux_wci22,
> > > > > > + msm_mux_qdss_cti_trig_in_a0,
> > > > > > + msm_mux_qpic_pad1,
> > > > > > + msm_mux_qdss_cti_trig_out_a0,
> > > > > > + msm_mux_qpic_pad2,
> > > > > > + msm_mux_qpic_pad3,
> > > > > > + msm_mux_qdss_traceclk_b,
> > > > > > + msm_mux_qpic_pad0,
> > > > > > + msm_mux_qdss_tracectl_b,
> > > > > > + msm_mux_qpic_pad8,
> > > > > > + msm_mux_pcm_zsi1,
> > > > > > + msm_mux_qdss_tracedata_b,
> > > > > > + msm_mux_led0,
> > > > > > + msm_mux_pwm04,
> > > > >
> > > > > What does "04" mean here?
> > > >
> > > > There are 4 Pulse Width Modulation channels, pwmXY is pwm
> > > > channel X and pin
> > > > Y.
> > >
> > > So Y is alternative mux? Can we use letters for this as well?
> >
> > Ok
>
> Sorry, actually they are not alternative muxes. There are 4 different PWM
> instances. Each PWM instance can handle 'n' different GPIOs (for example,
> that can be connected to LED etc.).
>
So we have 4 PWMs and the output from a single PWM can muxed to drive
the output of 4 pins?
Then skip the last digit and just go pwm0, ... pwm3 and include all four
pins that can be part of each instance. As the pingroup configuration is
per pin in the TLMM it's possible to configure subsets of the pins in a
group.
Regards,
Bjorn
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
@ 2017-05-17 19:47 ` Bjorn Andersson
0 siblings, 0 replies; 49+ messages in thread
From: Bjorn Andersson @ 2017-05-17 19:47 UTC (permalink / raw)
To: linux-arm-kernel
On Mon 15 May 04:24 PDT 2017, Varadarajan Narayanan wrote:
>
>
> On 5/15/2017 2:35 PM, Varadarajan Narayanan wrote:
> > On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
> > > On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
> > >
> > > > On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
> > > > > On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
> > > > >
> > > [..]
> > > > > > +enum ipq8074_functions {
> > > > >
> > > > > Please keep these sorted alphabetically.
> > > >
> > > > Ok
> > > >
> > > > > > + msm_mux_gpio,
> > > > > > + msm_mux_qpic_pad,
> > > > > > + msm_mux_blsp5_i2c,
> > > > > > + msm_mux_blsp5_spi,
> > > > > > + msm_mux_wci20,
> > > > >
> > > > > What does "20" mean here?
> > > >
> > > > This is for Wireless Coex Interface. The same functionality can
> > > > be muxed on
> > > > to different GPIOs. WCI2, is the 2nd edition of the WCI standard
> > > > and 0, 1
> > > > are for the muxing to different GPIOs (alternate muxes).
> > > >
> > >
> > > In other Qualcomm platforms the alternative muxes are denoted by letters
> > > (a,b,c...). Would you mind picking up this naming scheme, or do you see
> > > any problems with that? (E.g. wci2a in this case)
> >
> > Ok
> >
> > > Btw, do you need any additional configuration for selecting alternative
> > > muxing or is that automagical these days?
> >
> > No additional configuration is needed.
> >
> > > > > > + msm_mux_blsp3_spi3,
> > > > > > + msm_mux_burn0,
> > > > > > + msm_mux_pcm_zsi0,
> > > > > > + msm_mux_blsp5_uart,
> > > > > > + msm_mux_mac12,
> > > > >
> > > > > What does "12" mean here?
> > > >
> > > > The SoC has three MAC cores. Each core has two pins for the
> > > > smart antenna
> > > > feature. macXY indicates the function select for MAC no. X and
> > > > smart antenna
> > > > no. Y.
> > > >
> > >
> > > Ok
> > >
> > > > > > + msm_mux_blsp3_spi0,
> > > > > > + msm_mux_burn1,
> > > > > > + msm_mux_mac01,
> > > > > > + msm_mux_qdss_cti_trig_out_b0,
> > > > > > + msm_mux_qdss_cti_trig_in_b0,
> > > > > > + msm_mux_qpic_pad4,
> > > > >
> > > > > What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
> > > > > alternative muxings...?
> > > >
> > > > This is for the NAND and LCD display. The pins listed are the 9
> > > > data pins.
> > > >
> > >
> > > Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
> > > possible to reference a partial group in the DTS, if that's necessary)
> >
> > There are two sets of 9 pins, either of which can go to NAND or LCD.
> > Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
> > Is that ok?
> >
> > > > > > + msm_mux_blsp4_uart0,
> > > > > > + msm_mux_blsp4_i2c0,
> > > > > > + msm_mux_blsp4_spi0,
> > > > > > + msm_mux_mac21,
> > > > > > + msm_mux_qdss_cti_trig_out_b1,
> > > > > > + msm_mux_qpic_pad5,
> > > > > > + msm_mux_qdss_cti_trig_in_b1,
> > > > > > + msm_mux_qpic_pad6,
> > > > > > + msm_mux_qpic_pad7,
> > > > > > + msm_mux_cxc0,
> > > > > > + msm_mux_mac13,
> > > > > > + msm_mux_qdss_cti_trig_in_a1,
> > > > > > + msm_mux_qdss_cti_trig_out_a1,
> > > > > > + msm_mux_wci22,
> > > > > > + msm_mux_qdss_cti_trig_in_a0,
> > > > > > + msm_mux_qpic_pad1,
> > > > > > + msm_mux_qdss_cti_trig_out_a0,
> > > > > > + msm_mux_qpic_pad2,
> > > > > > + msm_mux_qpic_pad3,
> > > > > > + msm_mux_qdss_traceclk_b,
> > > > > > + msm_mux_qpic_pad0,
> > > > > > + msm_mux_qdss_tracectl_b,
> > > > > > + msm_mux_qpic_pad8,
> > > > > > + msm_mux_pcm_zsi1,
> > > > > > + msm_mux_qdss_tracedata_b,
> > > > > > + msm_mux_led0,
> > > > > > + msm_mux_pwm04,
> > > > >
> > > > > What does "04" mean here?
> > > >
> > > > There are 4 Pulse Width Modulation channels, pwmXY is pwm
> > > > channel X and pin
> > > > Y.
> > >
> > > So Y is alternative mux? Can we use letters for this as well?
> >
> > Ok
>
> Sorry, actually they are not alternative muxes. There are 4 different PWM
> instances. Each PWM instance can handle 'n' different GPIOs (for example,
> that can be connected to LED etc.).
>
So we have 4 PWMs and the output from a single PWM can muxed to drive
the output of 4 pins?
Then skip the last digit and just go pwm0, ... pwm3 and include all four
pins that can be part of each instance. As the pingroup configuration is
per pin in the TLMM it's possible to configure subsets of the pins in a
group.
Regards,
Bjorn
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
2017-05-17 19:47 ` Bjorn Andersson
(?)
@ 2017-05-18 8:37 ` Varadarajan Narayanan
-1 siblings, 0 replies; 49+ messages in thread
From: Varadarajan Narayanan @ 2017-05-18 8:37 UTC (permalink / raw)
To: Bjorn Andersson
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
mturquette-rdvid1DuHRBWk0Htik3J/w, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
andy.gross-QSEj5FYQhm4dnm+yROfE0A,
david.brown-QSEj5FYQhm4dnm+yROfE0A, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-soc-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
absahu-sgV2jX0FEOL9JmXXK+q4OQ, sjaganat-sgV2jX0FEOL9JmXXK+q4OQ,
sricharan-sgV2jX0FEOL9JmXXK+q4OQ, Manoharan Vijaya Raghavan
On 5/18/2017 1:17 AM, Bjorn Andersson wrote:
> On Mon 15 May 04:24 PDT 2017, Varadarajan Narayanan wrote:
>
>>
>>
>> On 5/15/2017 2:35 PM, Varadarajan Narayanan wrote:
>>> On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
>>>> On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
>>>>
>>>>> On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
>>>>>> On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
>>>>>>
>>>> [..]
>>>>>>> +enum ipq8074_functions {
>>>>>>
>>>>>> Please keep these sorted alphabetically.
>>>>>
>>>>> Ok
>>>>>
>>>>>>> + msm_mux_gpio,
>>>>>>> + msm_mux_qpic_pad,
>>>>>>> + msm_mux_blsp5_i2c,
>>>>>>> + msm_mux_blsp5_spi,
>>>>>>> + msm_mux_wci20,
>>>>>>
>>>>>> What does "20" mean here?
>>>>>
>>>>> This is for Wireless Coex Interface. The same functionality can
>>>>> be muxed on
>>>>> to different GPIOs. WCI2, is the 2nd edition of the WCI standard
>>>>> and 0, 1
>>>>> are for the muxing to different GPIOs (alternate muxes).
>>>>>
>>>>
>>>> In other Qualcomm platforms the alternative muxes are denoted by letters
>>>> (a,b,c...). Would you mind picking up this naming scheme, or do you see
>>>> any problems with that? (E.g. wci2a in this case)
>>>
>>> Ok
>>>
>>>> Btw, do you need any additional configuration for selecting alternative
>>>> muxing or is that automagical these days?
>>>
>>> No additional configuration is needed.
>>>
>>>>>>> + msm_mux_blsp3_spi3,
>>>>>>> + msm_mux_burn0,
>>>>>>> + msm_mux_pcm_zsi0,
>>>>>>> + msm_mux_blsp5_uart,
>>>>>>> + msm_mux_mac12,
>>>>>>
>>>>>> What does "12" mean here?
>>>>>
>>>>> The SoC has three MAC cores. Each core has two pins for the
>>>>> smart antenna
>>>>> feature. macXY indicates the function select for MAC no. X and
>>>>> smart antenna
>>>>> no. Y.
>>>>>
>>>>
>>>> Ok
>>>>
>>>>>>> + msm_mux_blsp3_spi0,
>>>>>>> + msm_mux_burn1,
>>>>>>> + msm_mux_mac01,
>>>>>>> + msm_mux_qdss_cti_trig_out_b0,
>>>>>>> + msm_mux_qdss_cti_trig_in_b0,
>>>>>>> + msm_mux_qpic_pad4,
>>>>>>
>>>>>> What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
>>>>>> alternative muxings...?
>>>>>
>>>>> This is for the NAND and LCD display. The pins listed are the 9
>>>>> data pins.
>>>>>
>>>>
>>>> Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
>>>> possible to reference a partial group in the DTS, if that's necessary)
>>>
>>> There are two sets of 9 pins, either of which can go to NAND or LCD.
>>> Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
>>> Is that ok?
>>>
>>>>>>> + msm_mux_blsp4_uart0,
>>>>>>> + msm_mux_blsp4_i2c0,
>>>>>>> + msm_mux_blsp4_spi0,
>>>>>>> + msm_mux_mac21,
>>>>>>> + msm_mux_qdss_cti_trig_out_b1,
>>>>>>> + msm_mux_qpic_pad5,
>>>>>>> + msm_mux_qdss_cti_trig_in_b1,
>>>>>>> + msm_mux_qpic_pad6,
>>>>>>> + msm_mux_qpic_pad7,
>>>>>>> + msm_mux_cxc0,
>>>>>>> + msm_mux_mac13,
>>>>>>> + msm_mux_qdss_cti_trig_in_a1,
>>>>>>> + msm_mux_qdss_cti_trig_out_a1,
>>>>>>> + msm_mux_wci22,
>>>>>>> + msm_mux_qdss_cti_trig_in_a0,
>>>>>>> + msm_mux_qpic_pad1,
>>>>>>> + msm_mux_qdss_cti_trig_out_a0,
>>>>>>> + msm_mux_qpic_pad2,
>>>>>>> + msm_mux_qpic_pad3,
>>>>>>> + msm_mux_qdss_traceclk_b,
>>>>>>> + msm_mux_qpic_pad0,
>>>>>>> + msm_mux_qdss_tracectl_b,
>>>>>>> + msm_mux_qpic_pad8,
>>>>>>> + msm_mux_pcm_zsi1,
>>>>>>> + msm_mux_qdss_tracedata_b,
>>>>>>> + msm_mux_led0,
>>>>>>> + msm_mux_pwm04,
>>>>>>
>>>>>> What does "04" mean here?
>>>>>
>>>>> There are 4 Pulse Width Modulation channels, pwmXY is pwm
>>>>> channel X and pin
>>>>> Y.
>>>>
>>>> So Y is alternative mux? Can we use letters for this as well?
>>>
>>> Ok
>>
>> Sorry, actually they are not alternative muxes. There are 4 different PWM
>> instances. Each PWM instance can handle 'n' different GPIOs (for example,
>> that can be connected to LED etc.).
>>
>
> So we have 4 PWMs and the output from a single PWM can muxed to drive
> the output of 4 pins?
>
> Then skip the last digit and just go pwm0, ... pwm3 and include all four
> pins that can be part of each instance. As the pingroup configuration is
> per pin in the TLMM it's possible to configure subsets of the pins in a
> group.
Ok
Thanks
Varada
> Regards,
> Bjorn
>
--
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Forum, a Linux Foundation Collaborative Project
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^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
@ 2017-05-18 8:37 ` Varadarajan Narayanan
0 siblings, 0 replies; 49+ messages in thread
From: Varadarajan Narayanan @ 2017-05-18 8:37 UTC (permalink / raw)
To: Bjorn Andersson
Cc: robh+dt, mark.rutland, mturquette, sboyd, linus.walleij,
andy.gross, david.brown, catalin.marinas, will.deacon,
devicetree, linux-kernel, linux-clk, linux-gpio, linux-arm-msm,
linux-soc, linux-arm-kernel, absahu, sjaganat, sricharan,
Manoharan Vijaya Raghavan
On 5/18/2017 1:17 AM, Bjorn Andersson wrote:
> On Mon 15 May 04:24 PDT 2017, Varadarajan Narayanan wrote:
>
>>
>>
>> On 5/15/2017 2:35 PM, Varadarajan Narayanan wrote:
>>> On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
>>>> On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
>>>>
>>>>> On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
>>>>>> On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
>>>>>>
>>>> [..]
>>>>>>> +enum ipq8074_functions {
>>>>>>
>>>>>> Please keep these sorted alphabetically.
>>>>>
>>>>> Ok
>>>>>
>>>>>>> + msm_mux_gpio,
>>>>>>> + msm_mux_qpic_pad,
>>>>>>> + msm_mux_blsp5_i2c,
>>>>>>> + msm_mux_blsp5_spi,
>>>>>>> + msm_mux_wci20,
>>>>>>
>>>>>> What does "20" mean here?
>>>>>
>>>>> This is for Wireless Coex Interface. The same functionality can
>>>>> be muxed on
>>>>> to different GPIOs. WCI2, is the 2nd edition of the WCI standard
>>>>> and 0, 1
>>>>> are for the muxing to different GPIOs (alternate muxes).
>>>>>
>>>>
>>>> In other Qualcomm platforms the alternative muxes are denoted by letters
>>>> (a,b,c...). Would you mind picking up this naming scheme, or do you see
>>>> any problems with that? (E.g. wci2a in this case)
>>>
>>> Ok
>>>
>>>> Btw, do you need any additional configuration for selecting alternative
>>>> muxing or is that automagical these days?
>>>
>>> No additional configuration is needed.
>>>
>>>>>>> + msm_mux_blsp3_spi3,
>>>>>>> + msm_mux_burn0,
>>>>>>> + msm_mux_pcm_zsi0,
>>>>>>> + msm_mux_blsp5_uart,
>>>>>>> + msm_mux_mac12,
>>>>>>
>>>>>> What does "12" mean here?
>>>>>
>>>>> The SoC has three MAC cores. Each core has two pins for the
>>>>> smart antenna
>>>>> feature. macXY indicates the function select for MAC no. X and
>>>>> smart antenna
>>>>> no. Y.
>>>>>
>>>>
>>>> Ok
>>>>
>>>>>>> + msm_mux_blsp3_spi0,
>>>>>>> + msm_mux_burn1,
>>>>>>> + msm_mux_mac01,
>>>>>>> + msm_mux_qdss_cti_trig_out_b0,
>>>>>>> + msm_mux_qdss_cti_trig_in_b0,
>>>>>>> + msm_mux_qpic_pad4,
>>>>>>
>>>>>> What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
>>>>>> alternative muxings...?
>>>>>
>>>>> This is for the NAND and LCD display. The pins listed are the 9
>>>>> data pins.
>>>>>
>>>>
>>>> Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
>>>> possible to reference a partial group in the DTS, if that's necessary)
>>>
>>> There are two sets of 9 pins, either of which can go to NAND or LCD.
>>> Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
>>> Is that ok?
>>>
>>>>>>> + msm_mux_blsp4_uart0,
>>>>>>> + msm_mux_blsp4_i2c0,
>>>>>>> + msm_mux_blsp4_spi0,
>>>>>>> + msm_mux_mac21,
>>>>>>> + msm_mux_qdss_cti_trig_out_b1,
>>>>>>> + msm_mux_qpic_pad5,
>>>>>>> + msm_mux_qdss_cti_trig_in_b1,
>>>>>>> + msm_mux_qpic_pad6,
>>>>>>> + msm_mux_qpic_pad7,
>>>>>>> + msm_mux_cxc0,
>>>>>>> + msm_mux_mac13,
>>>>>>> + msm_mux_qdss_cti_trig_in_a1,
>>>>>>> + msm_mux_qdss_cti_trig_out_a1,
>>>>>>> + msm_mux_wci22,
>>>>>>> + msm_mux_qdss_cti_trig_in_a0,
>>>>>>> + msm_mux_qpic_pad1,
>>>>>>> + msm_mux_qdss_cti_trig_out_a0,
>>>>>>> + msm_mux_qpic_pad2,
>>>>>>> + msm_mux_qpic_pad3,
>>>>>>> + msm_mux_qdss_traceclk_b,
>>>>>>> + msm_mux_qpic_pad0,
>>>>>>> + msm_mux_qdss_tracectl_b,
>>>>>>> + msm_mux_qpic_pad8,
>>>>>>> + msm_mux_pcm_zsi1,
>>>>>>> + msm_mux_qdss_tracedata_b,
>>>>>>> + msm_mux_led0,
>>>>>>> + msm_mux_pwm04,
>>>>>>
>>>>>> What does "04" mean here?
>>>>>
>>>>> There are 4 Pulse Width Modulation channels, pwmXY is pwm
>>>>> channel X and pin
>>>>> Y.
>>>>
>>>> So Y is alternative mux? Can we use letters for this as well?
>>>
>>> Ok
>>
>> Sorry, actually they are not alternative muxes. There are 4 different PWM
>> instances. Each PWM instance can handle 'n' different GPIOs (for example,
>> that can be connected to LED etc.).
>>
>
> So we have 4 PWMs and the output from a single PWM can muxed to drive
> the output of 4 pins?
>
> Then skip the last digit and just go pwm0, ... pwm3 and include all four
> pins that can be part of each instance. As the pingroup configuration is
> per pin in the TLMM it's possible to configure subsets of the pins in a
> group.
Ok
Thanks
Varada
> Regards,
> Bjorn
>
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum, a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
@ 2017-05-18 8:37 ` Varadarajan Narayanan
0 siblings, 0 replies; 49+ messages in thread
From: Varadarajan Narayanan @ 2017-05-18 8:37 UTC (permalink / raw)
To: linux-arm-kernel
On 5/18/2017 1:17 AM, Bjorn Andersson wrote:
> On Mon 15 May 04:24 PDT 2017, Varadarajan Narayanan wrote:
>
>>
>>
>> On 5/15/2017 2:35 PM, Varadarajan Narayanan wrote:
>>> On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
>>>> On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
>>>>
>>>>> On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
>>>>>> On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
>>>>>>
>>>> [..]
>>>>>>> +enum ipq8074_functions {
>>>>>>
>>>>>> Please keep these sorted alphabetically.
>>>>>
>>>>> Ok
>>>>>
>>>>>>> + msm_mux_gpio,
>>>>>>> + msm_mux_qpic_pad,
>>>>>>> + msm_mux_blsp5_i2c,
>>>>>>> + msm_mux_blsp5_spi,
>>>>>>> + msm_mux_wci20,
>>>>>>
>>>>>> What does "20" mean here?
>>>>>
>>>>> This is for Wireless Coex Interface. The same functionality can
>>>>> be muxed on
>>>>> to different GPIOs. WCI2, is the 2nd edition of the WCI standard
>>>>> and 0, 1
>>>>> are for the muxing to different GPIOs (alternate muxes).
>>>>>
>>>>
>>>> In other Qualcomm platforms the alternative muxes are denoted by letters
>>>> (a,b,c...). Would you mind picking up this naming scheme, or do you see
>>>> any problems with that? (E.g. wci2a in this case)
>>>
>>> Ok
>>>
>>>> Btw, do you need any additional configuration for selecting alternative
>>>> muxing or is that automagical these days?
>>>
>>> No additional configuration is needed.
>>>
>>>>>>> + msm_mux_blsp3_spi3,
>>>>>>> + msm_mux_burn0,
>>>>>>> + msm_mux_pcm_zsi0,
>>>>>>> + msm_mux_blsp5_uart,
>>>>>>> + msm_mux_mac12,
>>>>>>
>>>>>> What does "12" mean here?
>>>>>
>>>>> The SoC has three MAC cores. Each core has two pins for the
>>>>> smart antenna
>>>>> feature. macXY indicates the function select for MAC no. X and
>>>>> smart antenna
>>>>> no. Y.
>>>>>
>>>>
>>>> Ok
>>>>
>>>>>>> + msm_mux_blsp3_spi0,
>>>>>>> + msm_mux_burn1,
>>>>>>> + msm_mux_mac01,
>>>>>>> + msm_mux_qdss_cti_trig_out_b0,
>>>>>>> + msm_mux_qdss_cti_trig_in_b0,
>>>>>>> + msm_mux_qpic_pad4,
>>>>>>
>>>>>> What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
>>>>>> alternative muxings...?
>>>>>
>>>>> This is for the NAND and LCD display. The pins listed are the 9
>>>>> data pins.
>>>>>
>>>>
>>>> Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
>>>> possible to reference a partial group in the DTS, if that's necessary)
>>>
>>> There are two sets of 9 pins, either of which can go to NAND or LCD.
>>> Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
>>> Is that ok?
>>>
>>>>>>> + msm_mux_blsp4_uart0,
>>>>>>> + msm_mux_blsp4_i2c0,
>>>>>>> + msm_mux_blsp4_spi0,
>>>>>>> + msm_mux_mac21,
>>>>>>> + msm_mux_qdss_cti_trig_out_b1,
>>>>>>> + msm_mux_qpic_pad5,
>>>>>>> + msm_mux_qdss_cti_trig_in_b1,
>>>>>>> + msm_mux_qpic_pad6,
>>>>>>> + msm_mux_qpic_pad7,
>>>>>>> + msm_mux_cxc0,
>>>>>>> + msm_mux_mac13,
>>>>>>> + msm_mux_qdss_cti_trig_in_a1,
>>>>>>> + msm_mux_qdss_cti_trig_out_a1,
>>>>>>> + msm_mux_wci22,
>>>>>>> + msm_mux_qdss_cti_trig_in_a0,
>>>>>>> + msm_mux_qpic_pad1,
>>>>>>> + msm_mux_qdss_cti_trig_out_a0,
>>>>>>> + msm_mux_qpic_pad2,
>>>>>>> + msm_mux_qpic_pad3,
>>>>>>> + msm_mux_qdss_traceclk_b,
>>>>>>> + msm_mux_qpic_pad0,
>>>>>>> + msm_mux_qdss_tracectl_b,
>>>>>>> + msm_mux_qpic_pad8,
>>>>>>> + msm_mux_pcm_zsi1,
>>>>>>> + msm_mux_qdss_tracedata_b,
>>>>>>> + msm_mux_led0,
>>>>>>> + msm_mux_pwm04,
>>>>>>
>>>>>> What does "04" mean here?
>>>>>
>>>>> There are 4 Pulse Width Modulation channels, pwmXY is pwm
>>>>> channel X and pin
>>>>> Y.
>>>>
>>>> So Y is alternative mux? Can we use letters for this as well?
>>>
>>> Ok
>>
>> Sorry, actually they are not alternative muxes. There are 4 different PWM
>> instances. Each PWM instance can handle 'n' different GPIOs (for example,
>> that can be connected to LED etc.).
>>
>
> So we have 4 PWMs and the output from a single PWM can muxed to drive
> the output of 4 pins?
>
> Then skip the last digit and just go pwm0, ... pwm3 and include all four
> pins that can be part of each instance. As the pingroup configuration is
> per pin in the TLMM it's possible to configure subsets of the pins in a
> group.
Ok
Thanks
Varada
> Regards,
> Bjorn
>
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum, a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
2017-05-17 19:33 ` Bjorn Andersson
@ 2017-05-18 8:39 ` Varadarajan Narayanan
-1 siblings, 0 replies; 49+ messages in thread
From: Varadarajan Narayanan @ 2017-05-18 8:39 UTC (permalink / raw)
To: Bjorn Andersson
Cc: mark.rutland, devicetree, Manoharan Vijaya Raghavan, linux-gpio,
catalin.marinas, mturquette, sjaganat, sboyd, linux-kernel,
will.deacon, linux-clk, david.brown, absahu, robh+dt,
linux-arm-msm, andy.gross, sricharan, linux-soc, linus.walleij,
linux-arm-kernel
On 5/18/2017 1:03 AM, Bjorn Andersson wrote:
> On Mon 15 May 02:05 PDT 2017, Varadarajan Narayanan wrote:
>
>> On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
>>> On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
>>>
>>>> On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
>>>>> On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
> [..]
>>>>>> + msm_mux_qpic_pad4,
>>>>>
>>>>> What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
>>>>> alternative muxings...?
>>>>
>>>> This is for the NAND and LCD display. The pins listed are the 9 data pins.
>>>>
>>>
>>> Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
>>> possible to reference a partial group in the DTS, if that's necessary)
>>
>> There are two sets of 9 pins, either of which can go to NAND or LCD.
>> Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
>> Is that ok?
>>
>
> So you have NAND and LCD hardware muxed to either "a" or "b" and then
> you mux either "a" or "b" out onto actual pins?
>
> How is this first mux configured?
>
> I think the a/b scheme sounds reasonable, if above is how it works.
Sorry, I was wrong. I had misread the documentation.
There are 18 pins. 15 pins are common between LCD and NAND. The QPIC
controller arbitrates between LCD and NAND. Of the remaining 4, 2 are
for NAND and 2 are for LCD exclusively. We plan to group the qpic pins
into 3 groups namely, qpic_common, qpic_nand and qpic_lcd. Is that ok?
Thanks
Varada
>
> Regards,
> Bjorn
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum, a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
@ 2017-05-18 8:39 ` Varadarajan Narayanan
0 siblings, 0 replies; 49+ messages in thread
From: Varadarajan Narayanan @ 2017-05-18 8:39 UTC (permalink / raw)
To: linux-arm-kernel
On 5/18/2017 1:03 AM, Bjorn Andersson wrote:
> On Mon 15 May 02:05 PDT 2017, Varadarajan Narayanan wrote:
>
>> On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
>>> On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
>>>
>>>> On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
>>>>> On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
> [..]
>>>>>> + msm_mux_qpic_pad4,
>>>>>
>>>>> What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
>>>>> alternative muxings...?
>>>>
>>>> This is for the NAND and LCD display. The pins listed are the 9 data pins.
>>>>
>>>
>>> Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
>>> possible to reference a partial group in the DTS, if that's necessary)
>>
>> There are two sets of 9 pins, either of which can go to NAND or LCD.
>> Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
>> Is that ok?
>>
>
> So you have NAND and LCD hardware muxed to either "a" or "b" and then
> you mux either "a" or "b" out onto actual pins?
>
> How is this first mux configured?
>
> I think the a/b scheme sounds reasonable, if above is how it works.
Sorry, I was wrong. I had misread the documentation.
There are 18 pins. 15 pins are common between LCD and NAND. The QPIC
controller arbitrates between LCD and NAND. Of the remaining 4, 2 are
for NAND and 2 are for LCD exclusively. We plan to group the qpic pins
into 3 groups namely, qpic_common, qpic_nand and qpic_lcd. Is that ok?
Thanks
Varada
>
> Regards,
> Bjorn
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum, a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
2017-05-18 8:39 ` Varadarajan Narayanan
@ 2017-05-20 5:54 ` Bjorn Andersson
-1 siblings, 0 replies; 49+ messages in thread
From: Bjorn Andersson @ 2017-05-20 5:54 UTC (permalink / raw)
To: Varadarajan Narayanan, linus.walleij
Cc: mark.rutland, devicetree, Manoharan Vijaya Raghavan, linux-gpio,
catalin.marinas, mturquette, sjaganat, sboyd, linux-kernel,
will.deacon, linux-clk, david.brown, absahu, robh+dt,
linux-arm-msm, andy.gross, sricharan, linux-soc,
linux-arm-kernel
On Thu 18 May 01:39 PDT 2017, Varadarajan Narayanan wrote:
>
>
> On 5/18/2017 1:03 AM, Bjorn Andersson wrote:
> > On Mon 15 May 02:05 PDT 2017, Varadarajan Narayanan wrote:
> >
> > > On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
> > > > On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
> > > >
> > > > > On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
> > > > > > On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
> > [..]
> > > > > > > + msm_mux_qpic_pad4,
> > > > > >
> > > > > > What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
> > > > > > alternative muxings...?
> > > > >
> > > > > This is for the NAND and LCD display. The pins listed are the 9 data pins.
> > > > >
> > > >
> > > > Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
> > > > possible to reference a partial group in the DTS, if that's necessary)
> > >
> > > There are two sets of 9 pins, either of which can go to NAND or LCD.
> > > Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
> > > Is that ok?
> > >
> >
> > So you have NAND and LCD hardware muxed to either "a" or "b" and then
> > you mux either "a" or "b" out onto actual pins?
> >
> > How is this first mux configured?
> >
> > I think the a/b scheme sounds reasonable, if above is how it works.
>
> Sorry, I was wrong. I had misread the documentation.
>
> There are 18 pins. 15 pins are common between LCD and NAND. The QPIC
> controller arbitrates between LCD and NAND. Of the remaining 4, 2 are for
> NAND and 2 are for LCD exclusively. We plan to group the qpic pins into 3
> groups namely, qpic_common, qpic_nand and qpic_lcd. Is that ok?
>
If you consider that you are defining the available functions for this
pinmuxer and then define the sets of pins exposing these available
functions it does make sense to just name it "qpic".
I think that naming them _common, _lcd and _nand is just adding
confusion when it comes to writing the dts files.
@Linus, do you have a different preference here?
Regards,
Bjorn
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
@ 2017-05-20 5:54 ` Bjorn Andersson
0 siblings, 0 replies; 49+ messages in thread
From: Bjorn Andersson @ 2017-05-20 5:54 UTC (permalink / raw)
To: linux-arm-kernel
On Thu 18 May 01:39 PDT 2017, Varadarajan Narayanan wrote:
>
>
> On 5/18/2017 1:03 AM, Bjorn Andersson wrote:
> > On Mon 15 May 02:05 PDT 2017, Varadarajan Narayanan wrote:
> >
> > > On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
> > > > On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
> > > >
> > > > > On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
> > > > > > On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
> > [..]
> > > > > > > + msm_mux_qpic_pad4,
> > > > > >
> > > > > > What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
> > > > > > alternative muxings...?
> > > > >
> > > > > This is for the NAND and LCD display. The pins listed are the 9 data pins.
> > > > >
> > > >
> > > > Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
> > > > possible to reference a partial group in the DTS, if that's necessary)
> > >
> > > There are two sets of 9 pins, either of which can go to NAND or LCD.
> > > Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
> > > Is that ok?
> > >
> >
> > So you have NAND and LCD hardware muxed to either "a" or "b" and then
> > you mux either "a" or "b" out onto actual pins?
> >
> > How is this first mux configured?
> >
> > I think the a/b scheme sounds reasonable, if above is how it works.
>
> Sorry, I was wrong. I had misread the documentation.
>
> There are 18 pins. 15 pins are common between LCD and NAND. The QPIC
> controller arbitrates between LCD and NAND. Of the remaining 4, 2 are for
> NAND and 2 are for LCD exclusively. We plan to group the qpic pins into 3
> groups namely, qpic_common, qpic_nand and qpic_lcd. Is that ok?
>
If you consider that you are defining the available functions for this
pinmuxer and then define the sets of pins exposing these available
functions it does make sense to just name it "qpic".
I think that naming them _common, _lcd and _nand is just adding
confusion when it comes to writing the dts files.
@Linus, do you have a different preference here?
Regards,
Bjorn
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
2017-05-20 5:54 ` Bjorn Andersson
(?)
(?)
@ 2017-05-23 9:26 ` Linus Walleij
-1 siblings, 0 replies; 49+ messages in thread
From: Linus Walleij @ 2017-05-23 9:26 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Varadarajan Narayanan, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA, Manoharan Vijaya Raghavan,
linux-gpio-u79uwXL29TY76Z2rM5mHXA, Catalin Marinas,
Michael Turquette, sjaganat-sgV2jX0FEOL9JmXXK+q4OQ, Stephen Boyd,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Will Deacon, linux-clk,
David Brown, absahu-sgV2jX0FEOL9JmXXK+q4OQ, Rob Herring,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA, Andy Gross, Sricharan R
On Sat, May 20, 2017 at 7:54 AM, Bjorn Andersson
<bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote:
> On Thu 18 May 01:39 PDT 2017, Varadarajan Narayanan wrote:
>> There are 18 pins. 15 pins are common between LCD and NAND. The QPIC
>> controller arbitrates between LCD and NAND. Of the remaining 4, 2 are for
>> NAND and 2 are for LCD exclusively. We plan to group the qpic pins into 3
>> groups namely, qpic_common, qpic_nand and qpic_lcd. Is that ok?
>>
>
> If you consider that you are defining the available functions for this
> pinmuxer and then define the sets of pins exposing these available
> functions it does make sense to just name it "qpic".
>
> I think that naming them _common, _lcd and _nand is just adding
> confusion when it comes to writing the dts files.
>
> @Linus, do you have a different preference here?
No I pretty much trust the driver maintainer to know this best.
Yours,
Linus Walleij
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
@ 2017-05-23 9:26 ` Linus Walleij
0 siblings, 0 replies; 49+ messages in thread
From: Linus Walleij @ 2017-05-23 9:26 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Varadarajan Narayanan, Mark Rutland, devicetree,
Manoharan Vijaya Raghavan, linux-gpio, Catalin Marinas,
Michael Turquette, sjaganat, Stephen Boyd, linux-kernel,
Will Deacon, linux-clk, David Brown, absahu, Rob Herring,
linux-arm-msm, Andy Gross, Sricharan R,
open list:ARM/QUALCOMM SUPPORT, linux-arm-kernel
On Sat, May 20, 2017 at 7:54 AM, Bjorn Andersson
<bjorn.andersson@linaro.org> wrote:
> On Thu 18 May 01:39 PDT 2017, Varadarajan Narayanan wrote:
>> There are 18 pins. 15 pins are common between LCD and NAND. The QPIC
>> controller arbitrates between LCD and NAND. Of the remaining 4, 2 are for
>> NAND and 2 are for LCD exclusively. We plan to group the qpic pins into 3
>> groups namely, qpic_common, qpic_nand and qpic_lcd. Is that ok?
>>
>
> If you consider that you are defining the available functions for this
> pinmuxer and then define the sets of pins exposing these available
> functions it does make sense to just name it "qpic".
>
> I think that naming them _common, _lcd and _nand is just adding
> confusion when it comes to writing the dts files.
>
> @Linus, do you have a different preference here?
No I pretty much trust the driver maintainer to know this best.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
@ 2017-05-23 9:26 ` Linus Walleij
0 siblings, 0 replies; 49+ messages in thread
From: Linus Walleij @ 2017-05-23 9:26 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Varadarajan Narayanan, Mark Rutland, devicetree,
Manoharan Vijaya Raghavan, linux-gpio, Catalin Marinas,
Michael Turquette, sjaganat, Stephen Boyd, linux-kernel,
Will Deacon, linux-clk, David Brown, absahu, Rob Herring,
linux-arm-msm, Andy Gross, Sricharan R,
open list:ARM/QUALCOMM SUPPORT, linux-arm-kernel
On Sat, May 20, 2017 at 7:54 AM, Bjorn Andersson
<bjorn.andersson@linaro.org> wrote:
> On Thu 18 May 01:39 PDT 2017, Varadarajan Narayanan wrote:
>> There are 18 pins. 15 pins are common between LCD and NAND. The QPIC
>> controller arbitrates between LCD and NAND. Of the remaining 4, 2 are for
>> NAND and 2 are for LCD exclusively. We plan to group the qpic pins into 3
>> groups namely, qpic_common, qpic_nand and qpic_lcd. Is that ok?
>>
>
> If you consider that you are defining the available functions for this
> pinmuxer and then define the sets of pins exposing these available
> functions it does make sense to just name it "qpic".
>
> I think that naming them _common, _lcd and _nand is just adding
> confusion when it comes to writing the dts files.
>
> @Linus, do you have a different preference here?
No I pretty much trust the driver maintainer to know this best.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver
@ 2017-05-23 9:26 ` Linus Walleij
0 siblings, 0 replies; 49+ messages in thread
From: Linus Walleij @ 2017-05-23 9:26 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, May 20, 2017 at 7:54 AM, Bjorn Andersson
<bjorn.andersson@linaro.org> wrote:
> On Thu 18 May 01:39 PDT 2017, Varadarajan Narayanan wrote:
>> There are 18 pins. 15 pins are common between LCD and NAND. The QPIC
>> controller arbitrates between LCD and NAND. Of the remaining 4, 2 are for
>> NAND and 2 are for LCD exclusively. We plan to group the qpic pins into 3
>> groups namely, qpic_common, qpic_nand and qpic_lcd. Is that ok?
>>
>
> If you consider that you are defining the available functions for this
> pinmuxer and then define the sets of pins exposing these available
> functions it does make sense to just name it "qpic".
>
> I think that naming them _common, _lcd and _nand is just adding
> confusion when it comes to writing the dts files.
>
> @Linus, do you have a different preference here?
No I pretty much trust the driver maintainer to know this best.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 49+ messages in thread
end of thread, other threads:[~2017-05-23 9:26 UTC | newest]
Thread overview: 49+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-05-04 11:53 [PATCH v2 0/5] Add minimal boot support for IPQ8074 Varadarajan Narayanan
2017-05-04 11:53 ` Varadarajan Narayanan
2017-05-04 11:53 ` Varadarajan Narayanan
2017-05-04 11:53 ` [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver Varadarajan Narayanan
2017-05-04 11:53 ` Varadarajan Narayanan
2017-05-08 5:49 ` Varadarajan Narayanan
2017-05-08 5:49 ` Varadarajan Narayanan
2017-05-08 16:38 ` Rob Herring
2017-05-08 16:38 ` Rob Herring
2017-05-10 22:43 ` Bjorn Andersson
2017-05-10 22:43 ` Bjorn Andersson
2017-05-11 10:33 ` Varadarajan Narayanan
2017-05-11 10:33 ` Varadarajan Narayanan
2017-05-14 4:23 ` Bjorn Andersson
2017-05-14 4:23 ` Bjorn Andersson
2017-05-15 9:05 ` Varadarajan Narayanan
2017-05-15 9:05 ` Varadarajan Narayanan
[not found] ` <7afc7191-bcb1-a566-eac5-a4fe1293c773-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-05-15 11:24 ` Varadarajan Narayanan
2017-05-15 11:24 ` Varadarajan Narayanan
2017-05-15 11:24 ` Varadarajan Narayanan
2017-05-17 19:47 ` Bjorn Andersson
2017-05-17 19:47 ` Bjorn Andersson
2017-05-18 8:37 ` Varadarajan Narayanan
2017-05-18 8:37 ` Varadarajan Narayanan
2017-05-18 8:37 ` Varadarajan Narayanan
2017-05-17 19:33 ` Bjorn Andersson
2017-05-17 19:33 ` Bjorn Andersson
2017-05-18 8:39 ` Varadarajan Narayanan
2017-05-18 8:39 ` Varadarajan Narayanan
2017-05-20 5:54 ` Bjorn Andersson
2017-05-20 5:54 ` Bjorn Andersson
2017-05-23 9:26 ` Linus Walleij
2017-05-23 9:26 ` Linus Walleij
2017-05-23 9:26 ` Linus Walleij
2017-05-23 9:26 ` Linus Walleij
2017-05-04 11:53 ` [PATCH v2 2/5] dt-bindings: qcom: Add IPQ8074 bindings Varadarajan Narayanan
2017-05-04 11:53 ` Varadarajan Narayanan
2017-05-08 16:38 ` Rob Herring
2017-05-08 16:38 ` Rob Herring
2017-05-04 11:53 ` [PATCH v2 3/5] clk: qcom: ipq8074: Add Global Clock Controller support Varadarajan Narayanan
2017-05-04 11:53 ` Varadarajan Narayanan
[not found] ` <1493898841-20583-4-git-send-email-varada-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-05-08 16:40 ` Rob Herring
2017-05-08 16:40 ` Rob Herring
2017-05-08 16:40 ` Rob Herring
2017-05-04 11:54 ` [PATCH v2 4/5] arm64: dts: Add ipq8074 SoC and HK01 board support Varadarajan Narayanan
2017-05-04 11:54 ` Varadarajan Narayanan
[not found] ` <1493898841-20583-1-git-send-email-varada-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-05-04 11:54 ` [PATCH v2 5/5] arm64: defconfig: Enable QCOM IPQ8074 clock and pinctrl Varadarajan Narayanan
2017-05-04 11:54 ` Varadarajan Narayanan
2017-05-04 11:54 ` Varadarajan Narayanan
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