* [PATCH 00/31] DC Linux Patches May 23, 2017
@ 2017-05-23 14:08 Harry Wentland
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:08 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland
* Use update_surfaces for stream instead of special casing it
* Fix wrong scanline reporting
* Bunch of other bug fixes for Raven, Vega, and others
* Some small cleanups and a large cleanup in memory interface
Amy Zhang (2):
drm/amd/display: Program CSC Mode For BT2020
drm/amd/display: Disable ABM when eDP is disabled
Andrey Grodzovsky (7):
drm/amd/display: Fix slow FPS.
drm/amd/display: Use dc_update_surfaces_for_stream for flip.
drm/amd/display: Clen unused interface.
drm/amd/display: Unify loop for surface update and page flip.
drm/amd/display: Add missed wait_for_prev_commits.
drm/amd/display: Query for update plane type.
drm/amd/display: Remove redundant condition.
Ayyappa Chandolu (1):
drm/amd/display: Fix ASSR enablement on DP to EDP converter
Dmytro Laktyushkin (7):
drm/amd/display: fix mpo blanking out on one of planes being set not
visible
drm/amd/display: dce 8 - 12 mem_input refactor to new style
drm/amd/display: add missing GRPH_UPDATE_LOCK field macro for
dce_mem_input
drm/amd/display: make dc_get_validate_context re-entrant
drm/amd/display: revert dc_get_validate_context re-entrancy fix
drm/amd/display: remove GRPH_SURFACE_UPDATE_IMMEDIATE_EN field
programming
drm/amd/display: fix flip register write sequence
Harry Wentland (2):
drm/amd/display: Remove unused addr var in TG
drm/amd/display: No need to assert on stream_status
Leo (Sunpeng) Li (3):
drm/amd/display: Fix dcn10 cursor set position hang
drm/amd/display: Refactor use_lut() from dce110 to dce
drm/amd/display: Implement input gamma LUT
Roman Li (1):
drm/amd/display: Fix 5th display lightup on Vega10
Tom St Denis (6):
drm/amd/display: Tidy up
dce120_timing_generator_enable_advanced_request()
drm/amd/display: Fix indentation in dce120_tg_program_timing()
drm/amd/display: Make dce120_tg_is_blanked() more legible
drm/amd/display: Clean up indentation in dce120_tg_set_blank()
drm/amd/display: Tidy up dce120_clock_source_create()
drm/amd/display: Tidy up mem_input_program_surface_flip_and_addr()
Tony Cheng (2):
drm/amd/display: read VM settings from MMHUB
drm/amd/display: fix YUV surface address programming sequence
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 +-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 172 +++++---
drivers/gpu/drm/amd/display/dc/core/dc.c | 61 ++-
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 16 +
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 6 +-
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 30 +-
drivers/gpu/drm/amd/display/dc/dc.h | 14 +-
drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | 21 +
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | 12 +
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 2 +
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 297 ++++++++++++--
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 115 ++++--
.../drm/amd/display/dc/dce100/dce100_resource.c | 100 ++---
drivers/gpu/drm/amd/display/dc/dce110/Makefile | 3 +-
.../amd/display/dc/dce110/dce110_hw_sequencer.c | 27 +-
.../drm/amd/display/dc/dce110/dce110_mem_input.c | 437 ---------------------
.../drm/amd/display/dc/dce110/dce110_mem_input.h | 121 ------
.../drm/amd/display/dc/dce110/dce110_mem_input_v.c | 158 ++++----
.../drm/amd/display/dc/dce110/dce110_mem_input_v.h | 66 +---
.../drm/amd/display/dc/dce110/dce110_resource.c | 80 ++--
drivers/gpu/drm/amd/display/dc/dce112/Makefile | 2 +-
.../drm/amd/display/dc/dce112/dce112_mem_input.c | 54 ---
.../drm/amd/display/dc/dce112/dce112_mem_input.h | 38 --
.../drm/amd/display/dc/dce112/dce112_resource.c | 104 ++---
.../drm/amd/display/dc/dce112/dce112_resource.h | 3 +-
drivers/gpu/drm/amd/display/dc/dce120/Makefile | 2 +-
.../drm/amd/display/dc/dce120/dce120_mem_input.c | 340 ----------------
.../drm/amd/display/dc/dce120/dce120_mem_input.h | 37 --
.../drm/amd/display/dc/dce120/dce120_resource.c | 79 +---
.../display/dc/dce120/dce120_timing_generator.c | 85 ++--
drivers/gpu/drm/amd/display/dc/dce80/Makefile | 3 +-
.../gpu/drm/amd/display/dc/dce80/dce80_mem_input.c | 83 ----
.../gpu/drm/amd/display/dc/dce80/dce80_mem_input.h | 36 --
.../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 100 ++---
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 47 ++-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | 92 ++++-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h | 22 ++
.../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 112 +++---
.../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 26 +-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 3 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 38 +-
drivers/gpu/drm/amd/display/dc/inc/core_types.h | 3 +-
drivers/gpu/drm/amd/display/dc/inc/hw/abm.h | 1 +
drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 16 +-
drivers/gpu/drm/amd/display/dc/inc/resource.h | 9 +-
45 files changed, 1034 insertions(+), 2052 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c
delete mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h
delete mode 100644 drivers/gpu/drm/amd/display/dc/dce112/dce112_mem_input.c
delete mode 100644 drivers/gpu/drm/amd/display/dc/dce112/dce112_mem_input.h
delete mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c
delete mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.h
delete mode 100644 drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c
delete mode 100644 drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.h
--
2.11.0
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 01/31] drm/amd/display: Program CSC Mode For BT2020
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
@ 2017-05-23 14:08 ` Harry Wentland
2017-05-23 14:08 ` [PATCH 02/31] drm/amd/display: fix mpo blanking out on one of planes being set not visible Harry Wentland
` (29 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:08 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Amy Zhang
From: Amy Zhang <Amy.Zhang@amd.com>
- Add BT2020 color space in the set output csc default
Change-Id: I50a4aa392b0bfb403b9e633c083ae230485b2f35
Signed-off-by: Amy Zhang <Amy.Zhang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
index fce08e5235e6..148e192f5f76 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
@@ -338,9 +338,11 @@ static void opp_set_output_csc_default(
if (default_adjust != NULL) {
switch (default_adjust->out_color_space) {
case COLOR_SPACE_SRGB:
+ case COLOR_SPACE_2020_RGB_FULLRANGE:
ocsc_mode = 0;
break;
case COLOR_SPACE_SRGB_LIMITED:
+ case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
ocsc_mode = 1;
break;
case COLOR_SPACE_YCBCR601:
@@ -349,6 +351,7 @@ static void opp_set_output_csc_default(
break;
case COLOR_SPACE_YCBCR709:
case COLOR_SPACE_YCBCR709_LIMITED:
+ case COLOR_SPACE_2020_YCBCR:
ocsc_mode = 3;
break;
case COLOR_SPACE_UNKNOWN:
--
2.11.0
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 02/31] drm/amd/display: fix mpo blanking out on one of planes being set not visible
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2017-05-23 14:08 ` [PATCH 01/31] drm/amd/display: Program CSC Mode For BT2020 Harry Wentland
@ 2017-05-23 14:08 ` Harry Wentland
2017-05-23 14:08 ` [PATCH 03/31] drm/amd/display: Fix slow FPS Harry Wentland
` (28 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:08 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Change-Id: Ib270db25b4bcb14226f740aa5a8926d0f9c736ca
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 3 +-
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 3 +-
.../amd/display/dc/dce110/dce110_hw_sequencer.c | 10 +++---
.../drm/amd/display/dc/dce110/dce110_mem_input_v.c | 3 +-
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 41 ++++++++++++++++++----
.../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 20 +++--------
drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 8 ++---
7 files changed, 51 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
index 9da539db287c..0552fc5f7ecc 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
@@ -403,8 +403,7 @@ void dce_mem_input_program_surface_config(struct mem_input *mi,
union plane_size *plane_size,
enum dc_rotation_angle rotation,
struct dc_plane_dcc_param *dcc,
- bool horizontal_mirror,
- bool visible)
+ bool horizontal_mirror)
{
REG_UPDATE(GRPH_ENABLE, GRPH_ENABLE, 1);
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
index be37f52e9ba1..4977f5f6e7e2 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
@@ -277,8 +277,7 @@ void dce_mem_input_program_surface_config(struct mem_input *mi,
union plane_size *plane_size,
enum dc_rotation_angle rotation,
struct dc_plane_dcc_param *dcc,
- bool horizontal_mirror,
- bool visible);
+ bool horizontal_mirror);
void dce_mem_input_allocate_dmif(struct mem_input *mi,
uint32_t h_total,
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 8a663003017c..20ad1cb263db 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1986,8 +1986,9 @@ static void set_plane_config(
&surface->public.plane_size,
surface->public.rotation,
NULL,
- false,
- pipe_ctx->surface->public.visible);
+ false);
+ if (mi->funcs->set_blank)
+ mi->funcs->set_blank(mi, pipe_ctx->surface->public.visible);
if (dc->public.config.gpu_vm_support)
mi->funcs->mem_input_program_pte_vm(
@@ -2432,8 +2433,9 @@ static void dce110_program_front_end_for_pipe(
&surface->public.plane_size,
surface->public.rotation,
NULL,
- false,
- pipe_ctx->surface->public.visible);
+ false);
+ if (mi->funcs->set_blank)
+ mi->funcs->set_blank(mi, pipe_ctx->surface->public.visible);
if (dc->public.config.gpu_vm_support)
mi->funcs->mem_input_program_pte_vm(
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
index 02739d3efa97..78dd3ae3af5f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
@@ -664,8 +664,7 @@ void dce110_mem_input_v_program_surface_config(
union plane_size *plane_size,
enum dc_rotation_angle rotation,
struct dc_plane_dcc_param *dcc,
- bool horizotal_mirror,
- bool visible)
+ bool horizotal_mirror)
{
struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 6cb3924225da..28b47bed72cf 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -848,7 +848,7 @@ static void reset_front_end_for_pipe(
unlock_master_tg_and_wait(dc->ctx, pipe_ctx->tg->inst);
- pipe_ctx->mi->funcs->disable_request(pipe_ctx->mi);
+ pipe_ctx->mi->funcs->set_blank(pipe_ctx->mi, true);
wait_no_outstanding_request(dc->ctx, pipe_ctx->pipe_idx);
@@ -1513,6 +1513,35 @@ static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust);
}
+static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
+{
+ if (pipe_ctx->surface->public.visible)
+ return true;
+ if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
+ return true;
+ return false;
+}
+
+static bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
+{
+ if (pipe_ctx->surface->public.visible)
+ return true;
+ if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
+ return true;
+ return false;
+}
+
+static bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
+{
+ if (pipe_ctx->surface->public.visible)
+ return true;
+ if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
+ return true;
+ if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
+ return true;
+ return false;
+}
+
static void update_dchubp_dpp(
struct core_dc *dc,
struct pipe_ctx *pipe_ctx,
@@ -1633,12 +1662,9 @@ static void update_dchubp_dpp(
&size,
surface->public.rotation,
&surface->public.dcc,
- surface->public.horizontal_mirror,
- surface->public.visible);
-
- /* Only support one plane for now. */
- pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, !surface->public.visible);
+ surface->public.horizontal_mirror);
+ mi->funcs->set_blank(mi, !is_pipe_tree_visible(pipe_ctx));
}
static void program_all_pipe_in_tree(
@@ -1669,10 +1695,13 @@ static void program_all_pipe_in_tree(
pipe_ctx->tg->funcs->program_global_sync(
pipe_ctx->tg);
+ pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, !is_pipe_tree_visible(pipe_ctx));
update_dchubp_dpp(dc, pipe_ctx, context);
+
+ /* Only support one plane for now. */
}
if (pipe_ctx->bottom_pipe != NULL)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
index 50b24456d495..587ded13140b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
@@ -38,8 +38,9 @@
#define FN(reg_name, field_name) \
mi->mi_shift->field_name, mi->mi_mask->field_name
-static void set_blank(struct dcn10_mem_input *mi, bool blank)
+static void dcn_mi_set_blank(struct mem_input *mem_input, bool blank)
{
+ struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
uint32_t blank_en = blank ? 1 : 0;
REG_UPDATE_2(DCHUBP_CNTL,
@@ -47,15 +48,6 @@ static void set_blank(struct dcn10_mem_input *mi, bool blank)
HUBP_TTU_DISABLE, blank_en);
}
-
-static void disable_request(struct mem_input *mem_input)
-{
- struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
-
- /* To disable the requestors, set blank_en to 1 */
- set_blank(mi, true);
-}
-
static void vready_workaround(struct mem_input *mem_input,
struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
{
@@ -402,8 +394,7 @@ static void mem_input_program_surface_config(
union plane_size *plane_size,
enum dc_rotation_angle rotation,
struct dc_plane_dcc_param *dcc,
- bool horizontal_mirror,
- bool visible)
+ bool horizontal_mirror)
{
struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
@@ -412,8 +403,6 @@ static void mem_input_program_surface_config(
program_size_and_rotation(
mi, rotation, format, plane_size, dcc, horizontal_mirror);
program_pixel_format(mi, format);
-
- set_blank(mi, !visible);
}
static void program_requestor(
@@ -573,7 +562,6 @@ static void mem_input_setup(
/* otg is locked when this func is called. Register are double buffered.
* disable the requestors is not needed
*/
- /* disable_request(mem_input); */
program_requestor(mem_input, rq_regs);
program_deadline(mem_input, dlg_attr, ttu_attr);
vready_workaround(mem_input, pipe_dest);
@@ -1065,7 +1053,6 @@ static struct mem_input_funcs dcn10_mem_input_funcs = {
.mem_input_program_display_marks = mem_input_program_display_marks,
.allocate_mem_input = NULL,
.free_mem_input = NULL,
- .disable_request = disable_request,
.mem_input_program_surface_flip_and_addr =
mem_input_program_surface_flip_and_addr,
.mem_input_program_surface_config =
@@ -1075,6 +1062,7 @@ static struct mem_input_funcs dcn10_mem_input_funcs = {
.program_watermarks = program_watermarks,
.mem_input_update_dchub = mem_input_update_dchub,
.mem_input_program_pte_vm = dcn_mem_input_program_pte_vm,
+ .set_blank = dcn_mi_set_blank,
};
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
index c4aea24d4574..79fbc60e21c9 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
@@ -94,9 +94,6 @@ struct mem_input_funcs {
struct _vcs_dpi_display_ttu_regs_st *ttu_regs,
struct _vcs_dpi_display_rq_regs_st *rq_regs,
struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);
-
- void (*disable_request)(struct mem_input *mem_input);
-
#endif
void (*mem_input_program_display_marks)(
@@ -142,13 +139,14 @@ struct mem_input_funcs {
union plane_size *plane_size,
enum dc_rotation_angle rotation,
struct dc_plane_dcc_param *dcc,
- bool horizontal_mirror,
- bool visible);
+ bool horizontal_mirror);
bool (*mem_input_is_flip_pending)(struct mem_input *mem_input);
void (*mem_input_update_dchub)(struct mem_input *mem_input,
struct dchub_init_data *dh_data);
+
+ void (*set_blank)(struct mem_input *mi, bool blank);
};
#endif
--
2.11.0
_______________________________________________
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^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 03/31] drm/amd/display: Fix slow FPS.
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2017-05-23 14:08 ` [PATCH 01/31] drm/amd/display: Program CSC Mode For BT2020 Harry Wentland
2017-05-23 14:08 ` [PATCH 02/31] drm/amd/display: fix mpo blanking out on one of planes being set not visible Harry Wentland
@ 2017-05-23 14:08 ` Harry Wentland
2017-05-23 14:08 ` [PATCH 04/31] drm/amd/display: Disable ABM when eDP is disabled Harry Wentland
` (27 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:08 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Andrey Grodzovsky
From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Typo in expresion.
Change-Id: I156388e19ccfa40996a16383c1532ffde687427e
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Reviewed-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 9813688fdec1..cd06229bef2e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -141,8 +141,8 @@ static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
&h_position,
&v_position);
- *position = (v_position) || (h_position << 16);
- *vbl = (v_blank_start) || (v_blank_end << 16);
+ *position = v_position | (h_position << 16);
+ *vbl = v_blank_start | (v_blank_end << 16);
}
return 0;
--
2.11.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 04/31] drm/amd/display: Disable ABM when eDP is disabled
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2017-05-23 14:08 ` [PATCH 03/31] drm/amd/display: Fix slow FPS Harry Wentland
@ 2017-05-23 14:08 ` Harry Wentland
2017-05-23 14:08 ` [PATCH 05/31] drm/amd/display: dce 8 - 12 mem_input refactor to new style Harry Wentland
` (26 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:08 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Amy Zhang
From: Amy Zhang <Amy.Zhang@amd.com>
- Add immediate ABM disable when eDP is disabled
- Fix purple screen when ABM is mistakenly enabled
on non eDP display
Change-Id: Iff09807f7051126ba95b043061a2f7b1600b34a2
Signed-off-by: Amy Zhang <Amy.Zhang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 16 ++++++++++++++++
drivers/gpu/drm/amd/display/dc/dc.h | 2 ++
drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | 21 +++++++++++++++++++++
drivers/gpu/drm/amd/display/dc/inc/hw/abm.h | 1 +
4 files changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index ffc0eeaad175..59977640f938 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1415,6 +1415,22 @@ bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level,
return true;
}
+
+bool dc_link_set_abm_disable(const struct dc_link *dc_link)
+{
+ struct core_link *link = DC_LINK_TO_CORE(dc_link);
+ struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc);
+ struct abm *abm = core_dc->res_pool->abm;
+
+ if ((abm == NULL) || (abm->funcs->set_backlight_level == NULL))
+ return false;
+
+ abm->funcs->set_abm_immediate_disable(abm);
+
+ return true;
+}
+
+
bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable)
{
struct core_link *link = DC_LINK_TO_CORE(dc_link);
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 9a19d6f5a6a3..0610805cdb05 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -714,6 +714,8 @@ const struct graphics_object_id dc_get_link_id_at_index(
bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level,
uint32_t frame_ramp, const struct dc_stream *stream);
+bool dc_link_set_abm_disable(const struct dc_link *dc_link);
+
bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable);
bool dc_link_setup_psr(const struct dc_link *dc_link,
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
index cefffe164fe0..b4fa78292ad2 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
@@ -49,6 +49,8 @@
#define MCP_ABM_PIPE_SET 0x66
#define MCP_BL_SET 0x67
+#define MCP_DISABLE_ABM_IMMEDIATELY 255
+
struct abm_backlight_registers {
unsigned int BL_PWM_CNTL;
unsigned int BL_PWM_CNTL2;
@@ -315,6 +317,24 @@ static bool dce_abm_set_level(struct abm *abm, uint32_t level)
return true;
}
+static bool dce_abm_immediate_disable(struct abm *abm)
+{
+ struct dce_abm *abm_dce = TO_DCE_ABM(abm);
+
+ REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
+ 100, 800);
+
+ /* setDMCUParam_ABMLevel */
+ REG_UPDATE_2(MASTER_COMM_CMD_REG,
+ MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_LEVEL_SET,
+ MASTER_COMM_CMD_REG_BYTE2, MCP_DISABLE_ABM_IMMEDIATELY);
+
+ /* notifyDMCUMsg */
+ REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
+
+ return true;
+}
+
static bool dce_abm_init_backlight(struct abm *abm)
{
struct dce_abm *abm_dce = TO_DCE_ABM(abm);
@@ -414,6 +434,7 @@ static const struct abm_funcs dce_funcs = {
.init_backlight = dce_abm_init_backlight,
.set_backlight_level = dce_abm_set_backlight_level,
.get_current_backlight_8_bit = dce_abm_get_current_backlight_8_bit,
+ .set_abm_immediate_disable = dce_abm_immediate_disable,
.is_dmcu_initialized = is_dmcu_initialized
};
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h
index da465b3e98e8..c93b9b9a817c 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h
@@ -35,6 +35,7 @@ struct abm {
struct abm_funcs {
void (*abm_init)(struct abm *abm);
bool (*set_abm_level)(struct abm *abm, unsigned int abm_level);
+ bool (*set_abm_immediate_disable)(struct abm *abm);
bool (*init_backlight)(struct abm *abm);
bool (*set_backlight_level)(struct abm *abm,
unsigned int backlight_level,
--
2.11.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 05/31] drm/amd/display: dce 8 - 12 mem_input refactor to new style
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (3 preceding siblings ...)
2017-05-23 14:08 ` [PATCH 04/31] drm/amd/display: Disable ABM when eDP is disabled Harry Wentland
@ 2017-05-23 14:08 ` Harry Wentland
2017-05-23 14:08 ` [PATCH 06/31] drm/amd/display: Use dc_update_surfaces_for_stream for flip Harry Wentland
` (25 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:08 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Change-Id: Ie24528a1e8e70a94eb4f029289ea1c4e8f8722b7
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 306 +++++++++++++--
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 115 ++++--
.../drm/amd/display/dc/dce100/dce100_resource.c | 78 +---
drivers/gpu/drm/amd/display/dc/dce110/Makefile | 3 +-
.../drm/amd/display/dc/dce110/dce110_mem_input.c | 437 ---------------------
.../drm/amd/display/dc/dce110/dce110_mem_input.h | 121 ------
.../drm/amd/display/dc/dce110/dce110_mem_input_v.c | 155 +++-----
.../drm/amd/display/dc/dce110/dce110_mem_input_v.h | 66 +---
.../drm/amd/display/dc/dce110/dce110_resource.c | 58 +--
drivers/gpu/drm/amd/display/dc/dce112/Makefile | 2 +-
.../drm/amd/display/dc/dce112/dce112_mem_input.c | 54 ---
.../drm/amd/display/dc/dce112/dce112_mem_input.h | 38 --
.../drm/amd/display/dc/dce112/dce112_resource.c | 77 +---
drivers/gpu/drm/amd/display/dc/dce120/Makefile | 2 +-
.../drm/amd/display/dc/dce120/dce120_mem_input.c | 340 ----------------
.../drm/amd/display/dc/dce120/dce120_mem_input.h | 37 --
.../drm/amd/display/dc/dce120/dce120_resource.c | 75 +---
drivers/gpu/drm/amd/display/dc/dce80/Makefile | 3 +-
.../gpu/drm/amd/display/dc/dce80/dce80_mem_input.c | 83 ----
.../gpu/drm/amd/display/dc/dce80/dce80_mem_input.h | 36 --
.../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 78 +---
drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 8 -
22 files changed, 476 insertions(+), 1696 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c
delete mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h
delete mode 100644 drivers/gpu/drm/amd/display/dc/dce112/dce112_mem_input.c
delete mode 100644 drivers/gpu/drm/amd/display/dc/dce112/dce112_mem_input.h
delete mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c
delete mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.h
delete mode 100644 drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c
delete mode 100644 drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.h
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
index 0552fc5f7ecc..718688c41f7b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
@@ -23,18 +23,18 @@
*
*/
-#include "mem_input.h"
+#include "dce_mem_input.h"
#include "reg_helper.h"
#include "basics/conversion.h"
#define CTX \
- mi->ctx
+ dce_mi->base.ctx
#define REG(reg)\
- mi->regs->reg
+ dce_mi->regs->reg
#undef FN
#define FN(reg_name, field_name) \
- mi->shifts->field_name, mi->masks->field_name
+ dce_mi->shifts->field_name, dce_mi->masks->field_name
struct pte_setting {
unsigned int bpp;
@@ -130,11 +130,13 @@ static bool is_vert_scan(enum dc_rotation_angle rotation)
}
}
-void dce_mem_input_program_pte_vm(struct mem_input *mi,
+static void dce_mi_program_pte_vm(
+ struct mem_input *mi,
enum surface_pixel_format format,
union dc_tiling_info *tiling_info,
enum dc_rotation_angle rotation)
{
+ struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);
enum mi_bits_per_pixel mi_bpp = get_mi_bpp(format);
enum mi_tiling_format mi_tiling = get_mi_tiling(tiling_info);
const struct pte_setting *pte = &pte_settings[mi_tiling][mi_bpp];
@@ -158,7 +160,8 @@ void dce_mem_input_program_pte_vm(struct mem_input *mi,
DVMM_MAX_PTE_REQ_OUTSTANDING, 0xff);
}
-static void program_urgency_watermark(struct mem_input *mi,
+static void program_urgency_watermark(
+ struct dce_mem_input *dce_mi,
uint32_t wm_select,
uint32_t urgency_low_wm,
uint32_t urgency_high_wm)
@@ -171,7 +174,8 @@ static void program_urgency_watermark(struct mem_input *mi,
URGENCY_HIGH_WATERMARK, urgency_high_wm);
}
-static void program_nbp_watermark(struct mem_input *mi,
+static void program_nbp_watermark(
+ struct dce_mem_input *dce_mi,
uint32_t wm_select,
uint32_t nbp_wm)
{
@@ -202,7 +206,8 @@ static void program_nbp_watermark(struct mem_input *mi,
}
}
-static void program_stutter_watermark(struct mem_input *mi,
+static void program_stutter_watermark(
+ struct dce_mem_input *dce_mi,
uint32_t wm_select,
uint32_t stutter_mark)
{
@@ -217,41 +222,67 @@ static void program_stutter_watermark(struct mem_input *mi,
STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark);
}
-void dce_mem_input_program_display_marks(struct mem_input *mi,
+static void dce_mi_program_display_marks(
+ struct mem_input *mi,
struct dce_watermarks nbp,
struct dce_watermarks stutter,
struct dce_watermarks urgent,
uint32_t total_dest_line_time_ns)
{
+ struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);
uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;
- program_urgency_watermark(mi, 0, /* set a */
+ program_urgency_watermark(dce_mi, 2, /* set a */
urgent.a_mark, total_dest_line_time_ns);
- program_urgency_watermark(mi, 1, /* set b */
+ program_urgency_watermark(dce_mi, 1, /* set d */
+ urgent.d_mark, total_dest_line_time_ns);
+
+ REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL,
+ STUTTER_ENABLE, stutter_en,
+ STUTTER_IGNORE_FBC, 1);
+ program_nbp_watermark(dce_mi, 2, nbp.a_mark); /* set a */
+ program_nbp_watermark(dce_mi, 1, nbp.d_mark); /* set d */
+
+ program_stutter_watermark(dce_mi, 2, stutter.a_mark); /* set a */
+ program_stutter_watermark(dce_mi, 1, stutter.d_mark); /* set d */
+}
+
+static void dce120_mi_program_display_marks(struct mem_input *mi,
+ struct dce_watermarks nbp,
+ struct dce_watermarks stutter,
+ struct dce_watermarks urgent,
+ uint32_t total_dest_line_time_ns)
+{
+ struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);
+ uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;
+
+ program_urgency_watermark(dce_mi, 0, /* set a */
+ urgent.a_mark, total_dest_line_time_ns);
+ program_urgency_watermark(dce_mi, 1, /* set b */
urgent.b_mark, total_dest_line_time_ns);
- program_urgency_watermark(mi, 2, /* set c */
+ program_urgency_watermark(dce_mi, 2, /* set c */
urgent.c_mark, total_dest_line_time_ns);
- program_urgency_watermark(mi, 3, /* set d */
+ program_urgency_watermark(dce_mi, 3, /* set d */
urgent.d_mark, total_dest_line_time_ns);
REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL,
STUTTER_ENABLE, stutter_en,
STUTTER_IGNORE_FBC, 1);
- program_nbp_watermark(mi, 0, nbp.a_mark); /* set a */
- program_nbp_watermark(mi, 1, nbp.b_mark); /* set b */
- program_nbp_watermark(mi, 2, nbp.c_mark); /* set c */
- program_nbp_watermark(mi, 3, nbp.d_mark); /* set d */
-
- program_stutter_watermark(mi, 0, stutter.a_mark); /* set a */
- program_stutter_watermark(mi, 1, stutter.b_mark); /* set b */
- program_stutter_watermark(mi, 2, stutter.c_mark); /* set c */
- program_stutter_watermark(mi, 3, stutter.d_mark); /* set d */
+ program_nbp_watermark(dce_mi, 0, nbp.a_mark); /* set a */
+ program_nbp_watermark(dce_mi, 1, nbp.b_mark); /* set b */
+ program_nbp_watermark(dce_mi, 2, nbp.c_mark); /* set c */
+ program_nbp_watermark(dce_mi, 3, nbp.d_mark); /* set d */
+
+ program_stutter_watermark(dce_mi, 0, stutter.a_mark); /* set a */
+ program_stutter_watermark(dce_mi, 1, stutter.b_mark); /* set b */
+ program_stutter_watermark(dce_mi, 2, stutter.c_mark); /* set c */
+ program_stutter_watermark(dce_mi, 3, stutter.d_mark); /* set d */
}
-static void program_tiling(struct mem_input *mi,
- const union dc_tiling_info *info)
+static void program_tiling(
+ struct dce_mem_input *dce_mi, const union dc_tiling_info *info)
{
- if (mi->masks->GRPH_SW_MODE) { /* GFX9 */
+ if (dce_mi->masks->GRPH_SW_MODE) { /* GFX9 */
REG_UPDATE_6(GRPH_CONTROL,
GRPH_SW_MODE, info->gfx9.swizzle,
GRPH_NUM_BANKS, log_2(info->gfx9.num_banks),
@@ -265,7 +296,7 @@ static void program_tiling(struct mem_input *mi,
*/
}
- if (mi->masks->GRPH_ARRAY_MODE) { /* GFX8 */
+ if (dce_mi->masks->GRPH_ARRAY_MODE) { /* GFX8 */
REG_UPDATE_9(GRPH_CONTROL,
GRPH_NUM_BANKS, info->gfx8.num_banks,
GRPH_BANK_WIDTH, info->gfx8.bank_width,
@@ -285,7 +316,7 @@ static void program_tiling(struct mem_input *mi,
static void program_size_and_rotation(
- struct mem_input *mi,
+ struct dce_mem_input *dce_mi,
enum dc_rotation_angle rotation,
const union plane_size *plane_size)
{
@@ -326,7 +357,7 @@ static void program_size_and_rotation(
}
static void program_grph_pixel_format(
- struct mem_input *mi,
+ struct dce_mem_input *dce_mi,
enum surface_pixel_format format)
{
uint32_t red_xbar = 0, blue_xbar = 0; /* no swap */
@@ -397,7 +428,8 @@ static void program_grph_pixel_format(
GRPH_PRESCALE_B_SIGN, sign);
}
-void dce_mem_input_program_surface_config(struct mem_input *mi,
+static void dce_mi_program_surface_config(
+ struct mem_input *mi,
enum surface_pixel_format format,
union dc_tiling_info *tiling_info,
union plane_size *plane_size,
@@ -405,14 +437,15 @@ void dce_mem_input_program_surface_config(struct mem_input *mi,
struct dc_plane_dcc_param *dcc,
bool horizontal_mirror)
{
+ struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);
REG_UPDATE(GRPH_ENABLE, GRPH_ENABLE, 1);
- program_tiling(mi, tiling_info);
- program_size_and_rotation(mi, rotation, plane_size);
+ program_tiling(dce_mi, tiling_info);
+ program_size_and_rotation(dce_mi, rotation, plane_size);
if (format >= SURFACE_PIXEL_FORMAT_GRPH_BEGIN &&
format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
- program_grph_pixel_format(mi, format);
+ program_grph_pixel_format(dce_mi, format);
}
static uint32_t get_dmif_switch_time_us(
@@ -461,12 +494,14 @@ static uint32_t get_dmif_switch_time_us(
return frame_time;
}
-void dce_mem_input_allocate_dmif(struct mem_input *mi,
+static void dce_mi_allocate_dmif(
+ struct mem_input *mi,
uint32_t h_total,
uint32_t v_total,
uint32_t pix_clk_khz,
uint32_t total_stream_num)
{
+ struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);
const uint32_t retry_delay = 10;
uint32_t retry_count = get_dmif_switch_time_us(
h_total,
@@ -497,18 +532,20 @@ void dce_mem_input_allocate_dmif(struct mem_input *mi,
PIXEL_DURATION, pix_dur);
}
- if (mi->wa.single_head_rdreq_dmif_limit) {
+ if (dce_mi->wa.single_head_rdreq_dmif_limit) {
uint32_t eanble = (total_stream_num > 1) ? 0 :
- mi->wa.single_head_rdreq_dmif_limit;
+ dce_mi->wa.single_head_rdreq_dmif_limit;
REG_UPDATE(MC_HUB_RDREQ_DMIF_LIMIT,
ENABLE, eanble);
}
}
-void dce_mem_input_free_dmif(struct mem_input *mi,
+static void dce_mi_free_dmif(
+ struct mem_input *mi,
uint32_t total_stream_num)
{
+ struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);
uint32_t buffers_allocated;
uint32_t dmif_buffer_control;
@@ -525,11 +562,204 @@ void dce_mem_input_free_dmif(struct mem_input *mi,
DMIF_BUFFERS_ALLOCATION_COMPLETED, 1,
10, 3500);
- if (mi->wa.single_head_rdreq_dmif_limit) {
+ if (dce_mi->wa.single_head_rdreq_dmif_limit) {
uint32_t eanble = (total_stream_num > 1) ? 0 :
- mi->wa.single_head_rdreq_dmif_limit;
+ dce_mi->wa.single_head_rdreq_dmif_limit;
REG_UPDATE(MC_HUB_RDREQ_DMIF_LIMIT,
ENABLE, eanble);
}
}
+
+
+static void program_sec_addr(
+ struct dce_mem_input *dce_mi,
+ PHYSICAL_ADDRESS_LOC address)
+{
+ /*high register MUST be programmed first*/
+ REG_SET(GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0,
+ GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
+ address.high_part);
+
+ REG_SET_2(GRPH_SECONDARY_SURFACE_ADDRESS, 0,
+ GRPH_SECONDARY_SURFACE_ADDRESS, address.low_part >> 8,
+ GRPH_SECONDARY_DFQ_ENABLE, 0);
+}
+
+static void program_pri_addr(
+ struct dce_mem_input *dce_mi,
+ PHYSICAL_ADDRESS_LOC address)
+{
+ /*high register MUST be programmed first*/
+ REG_SET(GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
+ GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
+ address.high_part);
+
+ REG_SET(GRPH_PRIMARY_SURFACE_ADDRESS, 0,
+ GRPH_PRIMARY_SURFACE_ADDRESS,
+ address.low_part >> 8);
+}
+
+
+static bool dce_mi_is_flip_pending(struct mem_input *mem_input)
+{
+ struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mem_input);
+ uint32_t update_pending;
+
+ REG_GET(GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING, &update_pending);
+ if (update_pending)
+ return true;
+
+ mem_input->current_address = mem_input->request_address;
+ return false;
+}
+
+static bool dce_mi_program_surface_flip_and_addr(
+ struct mem_input *mem_input,
+ const struct dc_plane_address *address,
+ bool flip_immediate)
+{
+ struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mem_input);
+
+ /* TODO: Figure out if two modes are needed:
+ * non-XDMA Mode: GRPH_SURFACE_UPDATE_IMMEDIATE_EN = 1
+ * XDMA Mode: GRPH_SURFACE_UPDATE_H_RETRACE_EN = 1
+ */
+ REG_UPDATE(GRPH_UPDATE,
+ GRPH_UPDATE_LOCK, 1);
+
+ if (flip_immediate) {
+ REG_UPDATE_2(GRPH_FLIP_CONTROL,
+ GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0,
+ GRPH_SURFACE_UPDATE_H_RETRACE_EN, 1);
+ } else {
+ REG_UPDATE_2(GRPH_FLIP_CONTROL,
+ GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0,
+ GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
+ }
+
+ switch (address->type) {
+ case PLN_ADDR_TYPE_GRAPHICS:
+ if (address->grph.addr.quad_part == 0)
+ break;
+ program_pri_addr(dce_mi, address->grph.addr);
+ break;
+ case PLN_ADDR_TYPE_GRPH_STEREO:
+ if (address->grph_stereo.left_addr.quad_part == 0
+ || address->grph_stereo.right_addr.quad_part == 0)
+ break;
+ program_pri_addr(dce_mi, address->grph_stereo.left_addr);
+ program_sec_addr(dce_mi, address->grph_stereo.right_addr);
+ break;
+ default:
+ /* not supported */
+ BREAK_TO_DEBUGGER();
+ break;
+ }
+
+ mem_input->request_address = *address;
+
+ if (flip_immediate)
+ mem_input->current_address = *address;
+
+ REG_UPDATE(GRPH_UPDATE,
+ GRPH_UPDATE_LOCK, 0);
+
+ return true;
+}
+
+static void dce_mi_update_dchub(struct mem_input *mi,
+ struct dchub_init_data *dh_data)
+{
+ struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);
+ /* TODO: port code from dal2 */
+ switch (dh_data->fb_mode) {
+ case FRAME_BUFFER_MODE_ZFB_ONLY:
+ /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/
+ REG_UPDATE_2(DCHUB_FB_LOCATION,
+ FB_TOP, 0,
+ FB_BASE, 0x0FFFF);
+
+ REG_UPDATE(DCHUB_AGP_BASE,
+ AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
+
+ REG_UPDATE(DCHUB_AGP_BOT,
+ AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
+
+ REG_UPDATE(DCHUB_AGP_TOP,
+ AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);
+ break;
+ case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
+ /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
+ REG_UPDATE(DCHUB_AGP_BASE,
+ AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
+
+ REG_UPDATE(DCHUB_AGP_BOT,
+ AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
+
+ REG_UPDATE(DCHUB_AGP_TOP,
+ AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);
+ break;
+ case FRAME_BUFFER_MODE_LOCAL_ONLY:
+ /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
+ REG_UPDATE(DCHUB_AGP_BASE,
+ AGP_BASE, 0);
+
+ REG_UPDATE(DCHUB_AGP_BOT,
+ AGP_BOT, 0x03FFFF);
+
+ REG_UPDATE(DCHUB_AGP_TOP,
+ AGP_TOP, 0);
+ break;
+ default:
+ break;
+ }
+
+ dh_data->dchub_initialzied = true;
+ dh_data->dchub_info_valid = false;
+}
+
+static struct mem_input_funcs dce_mi_funcs = {
+ .mem_input_program_display_marks = dce_mi_program_display_marks,
+ .allocate_mem_input = dce_mi_allocate_dmif,
+ .free_mem_input = dce_mi_free_dmif,
+ .mem_input_program_surface_flip_and_addr =
+ dce_mi_program_surface_flip_and_addr,
+ .mem_input_program_pte_vm = dce_mi_program_pte_vm,
+ .mem_input_program_surface_config =
+ dce_mi_program_surface_config,
+ .mem_input_is_flip_pending = dce_mi_is_flip_pending,
+ .mem_input_update_dchub = dce_mi_update_dchub
+};
+
+
+void dce_mem_input_construct(
+ struct dce_mem_input *dce_mi,
+ struct dc_context *ctx,
+ int inst,
+ const struct dce_mem_input_registers *regs,
+ const struct dce_mem_input_shift *mi_shift,
+ const struct dce_mem_input_mask *mi_mask)
+{
+ dce_mi->base.ctx = ctx;
+
+ dce_mi->base.inst = inst;
+ dce_mi->base.funcs = &dce_mi_funcs;
+
+ dce_mi->regs = regs;
+ dce_mi->shifts = mi_shift;
+ dce_mi->masks = mi_mask;
+
+}
+
+void dce112_mem_input_construct(
+ struct dce_mem_input *dce_mi,
+ struct dc_context *ctx,
+ int inst,
+ const struct dce_mem_input_registers *regs,
+ const struct dce_mem_input_shift *mi_shift,
+ const struct dce_mem_input_mask *mi_mask)
+{
+ dce_mem_input_construct(dce_mi, ctx, inst, regs, mi_shift, mi_mask);
+ dce_mi->base.funcs->mem_input_program_display_marks = dce120_mi_program_display_marks;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
index 4977f5f6e7e2..55481f5adcdf 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
@@ -26,8 +26,10 @@
#define __DCE_MEM_INPUT_H__
#include "dc_hw_types.h"
-struct dce_watermarks;
-struct mem_input;
+#include "mem_input.h"
+
+#define TO_DCE_MEM_INPUT(mem_input)\
+ container_of(mem_input, struct dce_mem_input, base)
#define MI_DCE_BASE_REG_LIST(id)\
SRI(GRPH_ENABLE, DCP, id),\
@@ -40,6 +42,12 @@ struct mem_input;
SRI(HW_ROTATION, DCP, id),\
SRI(GRPH_SWAP_CNTL, DCP, id),\
SRI(PRESCALE_GRPH_CONTROL, DCP, id),\
+ SRI(GRPH_UPDATE, DCP, id),\
+ SRI(GRPH_FLIP_CONTROL, DCP, id),\
+ SRI(GRPH_PRIMARY_SURFACE_ADDRESS, DCP, id),\
+ SRI(GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, DCP, id),\
+ SRI(GRPH_SECONDARY_SURFACE_ADDRESS, DCP, id),\
+ SRI(GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, DCP, id),\
SRI(DPG_PIPE_ARBITRATION_CONTROL1, DMIF_PG, id),\
SRI(DPG_WATERMARK_MASK_CONTROL, DMIF_PG, id),\
SRI(DPG_PIPE_URGENCY_CONTROL, DMIF_PG, id),\
@@ -67,7 +75,11 @@ struct mem_input;
MI_DCE_PTE_REG_LIST(id),\
SRI(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, DCP, id),\
SRI(DPG_PIPE_STUTTER_CONTROL2, DMIF_PG, id),\
- SRI(DPG_PIPE_LOW_POWER_CONTROL, DMIF_PG, id)
+ SRI(DPG_PIPE_LOW_POWER_CONTROL, DMIF_PG, id),\
+ SR(DCHUB_FB_LOCATION),\
+ SR(DCHUB_AGP_BASE),\
+ SR(DCHUB_AGP_BOT),\
+ SR(DCHUB_AGP_TOP)
struct dce_mem_input_registers {
/* DCP */
@@ -84,6 +96,12 @@ struct dce_mem_input_registers {
uint32_t GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT;
uint32_t DVMM_PTE_CONTROL;
uint32_t DVMM_PTE_ARB_CONTROL;
+ uint32_t GRPH_UPDATE;
+ uint32_t GRPH_FLIP_CONTROL;
+ uint32_t GRPH_PRIMARY_SURFACE_ADDRESS;
+ uint32_t GRPH_PRIMARY_SURFACE_ADDRESS_HIGH;
+ uint32_t GRPH_SECONDARY_SURFACE_ADDRESS;
+ uint32_t GRPH_SECONDARY_SURFACE_ADDRESS_HIGH;
/* DMIF_PG */
uint32_t DPG_PIPE_ARBITRATION_CONTROL1;
uint32_t DPG_WATERMARK_MASK_CONTROL;
@@ -96,6 +114,11 @@ struct dce_mem_input_registers {
uint32_t DMIF_BUFFER_CONTROL;
/* MC_HUB */
uint32_t MC_HUB_RDREQ_DMIF_LIMIT;
+ /*DCHUB*/
+ uint32_t DCHUB_FB_LOCATION;
+ uint32_t DCHUB_AGP_BASE;
+ uint32_t DCHUB_AGP_BOT;
+ uint32_t DCHUB_AGP_TOP;
};
/* Set_Filed_for_Block */
@@ -129,9 +152,16 @@ struct dce_mem_input_registers {
SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_SELECT, mask_sh),\
SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_R_SIGN, mask_sh),\
SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_G_SIGN, mask_sh),\
- SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_B_SIGN, mask_sh)
+ SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_B_SIGN, mask_sh),\
+ SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
+ SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_SURFACE_ADDRESS, mask_sh),\
+ SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
+ SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS, GRPH_PRIMARY_SURFACE_ADDRESS, mask_sh),\
+ SFB(blk, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING, mask_sh),\
+ SFB(blk, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN, mask_sh)
#define MI_DCP_DCE11_MASK_SH_LIST(mask_sh, blk)\
+ SFB(blk, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_IMMEDIATE_EN, mask_sh),\
SFB(blk, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, mask_sh)
#define MI_DCP_PTE_MASK_SH_LIST(mask_sh, blk)\
@@ -189,13 +219,22 @@ struct dce_mem_input_registers {
SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\
SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_WATERMARK, mask_sh)
+#define MI_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\
+ SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\
+ SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\
+ SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\
+ SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\
+ SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh)
+
#define MI_DCE12_MASK_SH_LIST(mask_sh)\
MI_DCP_MASK_SH_LIST(mask_sh, DCP0_),\
+ SF(DCP0_GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_DFQ_ENABLE, mask_sh),\
MI_DCP_DCE11_MASK_SH_LIST(mask_sh, DCP0_),\
MI_DCP_PTE_MASK_SH_LIST(mask_sh, DCP0_),\
MI_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\
MI_DCE12_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\
- MI_GFX9_TILE_MASK_SH_LIST(mask_sh, DCP0_)
+ MI_GFX9_TILE_MASK_SH_LIST(mask_sh, DCP0_),\
+ MI_GFX9_DCHUB_MASK_SH_LIST(mask_sh)
#define MI_REG_FIELD_LIST(type) \
type GRPH_ENABLE; \
@@ -232,6 +271,15 @@ struct dce_mem_input_registers {
type GRPH_SE_ENABLE; \
type GRPH_NUM_SHADER_ENGINES; \
type GRPH_NUM_PIPES; \
+ type GRPH_SECONDARY_SURFACE_ADDRESS_HIGH; \
+ type GRPH_SECONDARY_SURFACE_ADDRESS; \
+ type GRPH_SECONDARY_DFQ_ENABLE; \
+ type GRPH_PRIMARY_SURFACE_ADDRESS_HIGH; \
+ type GRPH_PRIMARY_SURFACE_ADDRESS; \
+ type GRPH_SURFACE_UPDATE_PENDING; \
+ type GRPH_SURFACE_UPDATE_IMMEDIATE_EN; \
+ type GRPH_SURFACE_UPDATE_H_RETRACE_EN; \
+ type GRPH_UPDATE_LOCK; \
type PIXEL_DURATION; \
type URGENCY_WATERMARK_MASK; \
type PSTATE_CHANGE_WATERMARK_MASK; \
@@ -253,6 +301,11 @@ struct dce_mem_input_registers {
type DMIF_BUFFERS_ALLOCATED; \
type DMIF_BUFFERS_ALLOCATION_COMPLETED; \
type ENABLE; /* MC_HUB_RDREQ_DMIF_LIMIT */\
+ type FB_BASE; \
+ type FB_TOP; \
+ type AGP_BASE; \
+ type AGP_TOP; \
+ type AGP_BOT; \
struct dce_mem_input_shift {
MI_REG_FIELD_LIST(uint8_t)
@@ -266,32 +319,30 @@ struct dce_mem_input_wa {
uint8_t single_head_rdreq_dmif_limit;
};
-void dce_mem_input_program_pte_vm(struct mem_input *mi,
- enum surface_pixel_format format,
- union dc_tiling_info *tiling_info,
- enum dc_rotation_angle rotation);
-
-void dce_mem_input_program_surface_config(struct mem_input *mi,
- enum surface_pixel_format format,
- union dc_tiling_info *tiling_info,
- union plane_size *plane_size,
- enum dc_rotation_angle rotation,
- struct dc_plane_dcc_param *dcc,
- bool horizontal_mirror);
-
-void dce_mem_input_allocate_dmif(struct mem_input *mi,
- uint32_t h_total,
- uint32_t v_total,
- uint32_t pix_clk_khz,
- uint32_t total_stream_num);
-
-void dce_mem_input_free_dmif(struct mem_input *mi,
- uint32_t total_stream_num);
-
-void dce_mem_input_program_display_marks(struct mem_input *mi,
- struct dce_watermarks nbp,
- struct dce_watermarks stutter,
- struct dce_watermarks urgent,
- uint32_t total_dest_line_time_ns);
+struct dce_mem_input {
+ struct mem_input base;
+
+ const struct dce_mem_input_registers *regs;
+ const struct dce_mem_input_shift *shifts;
+ const struct dce_mem_input_mask *masks;
+
+ struct dce_mem_input_wa wa;
+};
+
+void dce_mem_input_construct(
+ struct dce_mem_input *dce_mi,
+ struct dc_context *ctx,
+ int inst,
+ const struct dce_mem_input_registers *regs,
+ const struct dce_mem_input_shift *mi_shift,
+ const struct dce_mem_input_mask *mi_mask);
+
+void dce112_mem_input_construct(
+ struct dce_mem_input *dce_mi,
+ struct dc_context *ctx,
+ int inst,
+ const struct dce_mem_input_registers *regs,
+ const struct dce_mem_input_shift *mi_shift,
+ const struct dce_mem_input_mask *mi_mask);
#endif /*__DCE_MEM_INPUT_H__*/
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 254f9e4d0fc8..8f1fe95dd76c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -35,8 +35,8 @@
#include "irq/dce110/irq_service_dce110.h"
#include "dce/dce_link_encoder.h"
#include "dce/dce_stream_encoder.h"
-#include "dce110/dce110_mem_input.h"
-#include "dce110/dce110_mem_input_v.h"
+
+#include "dce/dce_mem_input.h"
#include "dce/dce_ipp.h"
#include "dce/dce_transform.h"
#include "dce/dce_opp.h"
@@ -123,51 +123,6 @@ static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = {
}
};
-static const struct dce110_mem_input_reg_offsets dce100_mi_reg_offsets[] = {
- {
- .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE0_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- },
- {
- .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE1_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- },
- {
- .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE2_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- },
- {
- .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE3_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- },
- {
- .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE4_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- },
- {
- .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE5_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- }
-};
-
/* set register offset */
#define SR(reg_name)\
.reg_name = mm ## reg_name
@@ -510,28 +465,18 @@ static const struct dce_mem_input_mask mi_masks = {
static struct mem_input *dce100_mem_input_create(
struct dc_context *ctx,
- uint32_t inst,
- const struct dce110_mem_input_reg_offsets *offset)
+ uint32_t inst)
{
- struct dce110_mem_input *mem_input110 =
- dm_alloc(sizeof(struct dce110_mem_input));
+ struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input));
- if (!mem_input110)
+ if (!dce_mi) {
+ BREAK_TO_DEBUGGER();
return NULL;
-
- if (dce110_mem_input_construct(mem_input110, ctx, inst, offset)) {
- struct mem_input *mi = &mem_input110->base;
-
- mi->regs = &mi_regs[inst];
- mi->shifts = &mi_shifts;
- mi->masks = &mi_masks;
- mi->wa.single_head_rdreq_dmif_limit = 2;
- return mi;
}
- BREAK_TO_DEBUGGER();
- dm_free(mem_input110);
- return NULL;
+ dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
+ dce_mi->wa.single_head_rdreq_dmif_limit = 2;
+ return &dce_mi->base;
}
static void dce100_transform_destroy(struct transform **xfm)
@@ -671,7 +616,7 @@ static void destruct(struct dce110_resource_pool *pool)
dce_ipp_destroy(&pool->base.ipps[i]);
if (pool->base.mis[i] != NULL) {
- dm_free(TO_DCE110_MEM_INPUT(pool->base.mis[i]));
+ dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i]));
pool->base.mis[i] = NULL;
}
@@ -986,8 +931,7 @@ static bool construct(
goto res_create_fail;
}
- pool->base.mis[i] = dce100_mem_input_create(ctx, i,
- &dce100_mi_reg_offsets[i]);
+ pool->base.mis[i] = dce100_mem_input_create(ctx, i);
if (pool->base.mis[i] == NULL) {
BREAK_TO_DEBUGGER();
dm_error(
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/Makefile b/drivers/gpu/drm/amd/display/dc/dce110/Makefile
index c54bf0330701..98d956e2f218 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dce110/Makefile
@@ -3,8 +3,7 @@
# It provides the control and status of HW CRTC block.
DCE110 = dce110_timing_generator.o \
-dce110_compressor.o dce110_mem_input.o dce110_hw_sequencer.o \
-dce110_resource.o \
+dce110_compressor.o dce110_hw_sequencer.o dce110_resource.o \
dce110_opp_regamma_v.o dce110_opp_csc_v.o dce110_timing_generator_v.o \
dce110_mem_input_v.o dce110_opp_v.o dce110_transform_v.o
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c
deleted file mode 100644
index 45e1a8d15d9b..000000000000
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c
+++ /dev/null
@@ -1,437 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-#include "dm_services.h"
-
-#include "dce/dce_11_0_d.h"
-#include "dce/dce_11_0_sh_mask.h"
-/* TODO: this needs to be looked at, used by Stella's workaround*/
-#include "gmc/gmc_8_2_d.h"
-#include "gmc/gmc_8_2_sh_mask.h"
-
-#include "include/logger_interface.h"
-
-#include "dce110_mem_input.h"
-
-#define DCP_REG(reg) (reg + mem_input110->offsets.dcp)
-#define DMIF_REG(reg) (reg + mem_input110->offsets.dmif)
-#define PIPE_REG(reg) (reg + mem_input110->offsets.pipe)
-
-static void program_sec_addr(
- struct dce110_mem_input *mem_input110,
- PHYSICAL_ADDRESS_LOC address)
-{
- uint32_t value = 0;
- uint32_t temp;
-
- /*high register MUST be programmed first*/
- temp = address.high_part &
- GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK;
- set_reg_field_value(value, temp,
- GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
- GRPH_SECONDARY_SURFACE_ADDRESS_HIGH);
- dm_write_reg(mem_input110->base.ctx,
- DCP_REG(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH), value);
-
- value = 0;
- temp = address.low_part >>
- GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT;
- set_reg_field_value(value, temp,
- GRPH_SECONDARY_SURFACE_ADDRESS,
- GRPH_SECONDARY_SURFACE_ADDRESS);
- dm_write_reg(mem_input110->base.ctx,
- DCP_REG(mmGRPH_SECONDARY_SURFACE_ADDRESS), value);
-}
-
-static void program_pri_addr(
- struct dce110_mem_input *mem_input110,
- PHYSICAL_ADDRESS_LOC address)
-{
- uint32_t value = 0;
- uint32_t temp;
-
- /*high register MUST be programmed first*/
- temp = address.high_part &
- GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK;
- set_reg_field_value(value, temp,
- GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
- GRPH_PRIMARY_SURFACE_ADDRESS_HIGH);
- dm_write_reg(mem_input110->base.ctx,
- DCP_REG(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH), value);
-
- value = 0;
- temp = address.low_part >>
- GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT;
- set_reg_field_value(value, temp,
- GRPH_PRIMARY_SURFACE_ADDRESS,
- GRPH_PRIMARY_SURFACE_ADDRESS);
- dm_write_reg(mem_input110->base.ctx,
- DCP_REG(mmGRPH_PRIMARY_SURFACE_ADDRESS), value);
-}
-
-bool dce110_mem_input_is_flip_pending(struct mem_input *mem_input)
-{
- struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input);
- uint32_t value;
-
- value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_UPDATE));
-
- if (get_reg_field_value(value, GRPH_UPDATE,
- GRPH_SURFACE_UPDATE_PENDING))
- return true;
-
- mem_input->current_address = mem_input->request_address;
- return false;
-}
-
-bool dce110_mem_input_program_surface_flip_and_addr(
- struct mem_input *mem_input,
- const struct dc_plane_address *address,
- bool flip_immediate)
-{
- struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input);
-
- uint32_t value = 0;
- uint32_t value_old = 0;
- uint32_t lock_value = 0;
-
- lock_value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_UPDATE));
- set_reg_field_value(lock_value, 1, GRPH_UPDATE, GRPH_UPDATE_LOCK);
- dm_write_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_UPDATE), lock_value);
-
- value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_FLIP_CONTROL));
- value_old = value;
- if (flip_immediate) {
- set_reg_field_value(value, 0, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_IMMEDIATE_EN);
- set_reg_field_value(value, 1, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN);
- } else {
- set_reg_field_value(value, 0, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_IMMEDIATE_EN);
- set_reg_field_value(value, 0, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN);
- }
- if (value != value_old) {
- dm_write_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_FLIP_CONTROL), value);
- }
-
- switch (address->type) {
- case PLN_ADDR_TYPE_GRAPHICS:
- if (address->grph.addr.quad_part == 0)
- break;
- program_pri_addr(mem_input110, address->grph.addr);
- break;
- case PLN_ADDR_TYPE_GRPH_STEREO:
- if (address->grph_stereo.left_addr.quad_part == 0
- || address->grph_stereo.right_addr.quad_part == 0)
- break;
- program_pri_addr(mem_input110, address->grph_stereo.left_addr);
- program_sec_addr(mem_input110, address->grph_stereo.right_addr);
- break;
- default:
- /* not supported */
- BREAK_TO_DEBUGGER();
- break;
- }
-
- mem_input->request_address = *address;
- if (flip_immediate)
- mem_input->current_address = *address;
-
- lock_value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_UPDATE));
- set_reg_field_value(lock_value, 0, GRPH_UPDATE, GRPH_UPDATE_LOCK);
- dm_write_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_UPDATE), lock_value);
-
- return true;
-}
-
-static void program_urgency_watermark(
- const struct dc_context *ctx,
- const uint32_t offset,
- struct dce_watermarks marks_low,
- uint32_t total_dest_line_time_ns)
-{
- /* register value */
- uint32_t urgency_cntl = 0;
- uint32_t wm_mask_cntl = 0;
-
- uint32_t urgency_addr = offset + mmDPG_PIPE_URGENCY_CONTROL;
- uint32_t wm_addr = offset + mmDPG_WATERMARK_MASK_CONTROL;
-
- /*Write mask to enable reading/writing of watermark set A*/
- wm_mask_cntl = dm_read_reg(ctx, wm_addr);
- set_reg_field_value(wm_mask_cntl,
- 1,
- DPG_WATERMARK_MASK_CONTROL,
- URGENCY_WATERMARK_MASK);
- dm_write_reg(ctx, wm_addr, wm_mask_cntl);
-
- urgency_cntl = dm_read_reg(ctx, urgency_addr);
-
- set_reg_field_value(
- urgency_cntl,
- marks_low.d_mark,
- DPG_PIPE_URGENCY_CONTROL,
- URGENCY_LOW_WATERMARK);
-
- set_reg_field_value(
- urgency_cntl,
- total_dest_line_time_ns,
- DPG_PIPE_URGENCY_CONTROL,
- URGENCY_HIGH_WATERMARK);
- dm_write_reg(ctx, urgency_addr, urgency_cntl);
-
- /*Write mask to enable reading/writing of watermark set B*/
- wm_mask_cntl = dm_read_reg(ctx, wm_addr);
- set_reg_field_value(wm_mask_cntl,
- 2,
- DPG_WATERMARK_MASK_CONTROL,
- URGENCY_WATERMARK_MASK);
- dm_write_reg(ctx, wm_addr, wm_mask_cntl);
-
- urgency_cntl = dm_read_reg(ctx, urgency_addr);
-
- set_reg_field_value(urgency_cntl,
- marks_low.a_mark,
- DPG_PIPE_URGENCY_CONTROL,
- URGENCY_LOW_WATERMARK);
-
- set_reg_field_value(urgency_cntl,
- total_dest_line_time_ns,
- DPG_PIPE_URGENCY_CONTROL,
- URGENCY_HIGH_WATERMARK);
- dm_write_reg(ctx, urgency_addr, urgency_cntl);
-}
-
-static void program_stutter_watermark(
- const struct dc_context *ctx,
- const uint32_t offset,
- struct dce_watermarks marks)
-{
- /* register value */
- uint32_t stutter_cntl = 0;
- uint32_t wm_mask_cntl = 0;
-
- uint32_t stutter_addr = offset + mmDPG_PIPE_STUTTER_CONTROL;
- uint32_t wm_addr = offset + mmDPG_WATERMARK_MASK_CONTROL;
-
- /*Write mask to enable reading/writing of watermark set A*/
-
- wm_mask_cntl = dm_read_reg(ctx, wm_addr);
- set_reg_field_value(wm_mask_cntl,
- 1,
- DPG_WATERMARK_MASK_CONTROL,
- STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK);
- dm_write_reg(ctx, wm_addr, wm_mask_cntl);
-
- stutter_cntl = dm_read_reg(ctx, stutter_addr);
-
- if (ctx->dc->debug.disable_stutter) {
- set_reg_field_value(stutter_cntl,
- 0,
- DPG_PIPE_STUTTER_CONTROL,
- STUTTER_ENABLE);
- } else {
- set_reg_field_value(stutter_cntl,
- 1,
- DPG_PIPE_STUTTER_CONTROL,
- STUTTER_ENABLE);
- }
-
- set_reg_field_value(stutter_cntl,
- 1,
- DPG_PIPE_STUTTER_CONTROL,
- STUTTER_IGNORE_FBC);
-
- /*Write watermark set A*/
- set_reg_field_value(stutter_cntl,
- marks.d_mark,
- DPG_PIPE_STUTTER_CONTROL,
- STUTTER_EXIT_SELF_REFRESH_WATERMARK);
- dm_write_reg(ctx, stutter_addr, stutter_cntl);
-
- /*Write mask to enable reading/writing of watermark set B*/
- wm_mask_cntl = dm_read_reg(ctx, wm_addr);
- set_reg_field_value(wm_mask_cntl,
- 2,
- DPG_WATERMARK_MASK_CONTROL,
- STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK);
- dm_write_reg(ctx, wm_addr, wm_mask_cntl);
-
- stutter_cntl = dm_read_reg(ctx, stutter_addr);
-
- /*Write watermark set B*/
- set_reg_field_value(stutter_cntl,
- marks.a_mark,
- DPG_PIPE_STUTTER_CONTROL,
- STUTTER_EXIT_SELF_REFRESH_WATERMARK);
- dm_write_reg(ctx, stutter_addr, stutter_cntl);
-}
-
-static void program_nbp_watermark(
- const struct dc_context *ctx,
- const uint32_t offset,
- struct dce_watermarks marks)
-{
- uint32_t value;
- uint32_t addr;
- /* Write mask to enable reading/writing of watermark set A */
- addr = offset + mmDPG_WATERMARK_MASK_CONTROL;
- value = dm_read_reg(ctx, addr);
- set_reg_field_value(
- value,
- 1,
- DPG_WATERMARK_MASK_CONTROL,
- NB_PSTATE_CHANGE_WATERMARK_MASK);
- dm_write_reg(ctx, addr, value);
-
- addr = offset + mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL;
- value = dm_read_reg(ctx, addr);
- set_reg_field_value(
- value,
- 1,
- DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
- NB_PSTATE_CHANGE_ENABLE);
- set_reg_field_value(
- value,
- 1,
- DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
- NB_PSTATE_CHANGE_URGENT_DURING_REQUEST);
- set_reg_field_value(
- value,
- 1,
- DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
- NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST);
- dm_write_reg(ctx, addr, value);
-
- /* Write watermark set A */
- value = dm_read_reg(ctx, addr);
- set_reg_field_value(
- value,
- marks.d_mark,
- DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
- NB_PSTATE_CHANGE_WATERMARK);
- dm_write_reg(ctx, addr, value);
-
- /* Write mask to enable reading/writing of watermark set B */
- addr = offset + mmDPG_WATERMARK_MASK_CONTROL;
- value = dm_read_reg(ctx, addr);
- set_reg_field_value(
- value,
- 2,
- DPG_WATERMARK_MASK_CONTROL,
- NB_PSTATE_CHANGE_WATERMARK_MASK);
- dm_write_reg(ctx, addr, value);
-
- addr = offset + mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL;
- value = dm_read_reg(ctx, addr);
- set_reg_field_value(
- value,
- 1,
- DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
- NB_PSTATE_CHANGE_ENABLE);
- set_reg_field_value(
- value,
- 1,
- DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
- NB_PSTATE_CHANGE_URGENT_DURING_REQUEST);
- set_reg_field_value(
- value,
- 1,
- DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
- NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST);
- dm_write_reg(ctx, addr, value);
-
- /* Write watermark set B */
- value = dm_read_reg(ctx, addr);
- set_reg_field_value(
- value,
- marks.a_mark,
- DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
- NB_PSTATE_CHANGE_WATERMARK);
- dm_write_reg(ctx, addr, value);
-}
-
-void dce110_mem_input_program_display_marks(
- struct mem_input *mem_input,
- struct dce_watermarks nbp,
- struct dce_watermarks stutter,
- struct dce_watermarks urgent,
- uint32_t total_dest_line_time_ns)
-{
- struct dce110_mem_input *bm_dce110 = TO_DCE110_MEM_INPUT(mem_input);
-
- program_urgency_watermark(
- mem_input->ctx,
- bm_dce110->offsets.dmif,
- urgent,
- total_dest_line_time_ns);
-
- program_nbp_watermark(
- mem_input->ctx,
- bm_dce110->offsets.dmif,
- nbp);
-
- program_stutter_watermark(
- mem_input->ctx,
- bm_dce110->offsets.dmif,
- stutter);
-}
-
-static struct mem_input_funcs dce110_mem_input_funcs = {
- .mem_input_program_display_marks =
- dce110_mem_input_program_display_marks,
- .allocate_mem_input = dce_mem_input_allocate_dmif,
- .free_mem_input = dce_mem_input_free_dmif,
- .mem_input_program_surface_flip_and_addr =
- dce110_mem_input_program_surface_flip_and_addr,
- .mem_input_program_pte_vm =
- dce_mem_input_program_pte_vm,
- .mem_input_program_surface_config =
- dce_mem_input_program_surface_config,
- .mem_input_is_flip_pending =
- dce110_mem_input_is_flip_pending,
- .mem_input_update_dchub = NULL
-};
-/*****************************************/
-/* Constructor, Destructor */
-/*****************************************/
-
-bool dce110_mem_input_construct(
- struct dce110_mem_input *mem_input110,
- struct dc_context *ctx,
- uint32_t inst,
- const struct dce110_mem_input_reg_offsets *offsets)
-{
- /* supported stutter method
- * STUTTER_MODE_ENHANCED
- * STUTTER_MODE_QUAD_DMIF_BUFFER
- * STUTTER_MODE_WATERMARK_NBP_STATE
- */
- mem_input110->base.funcs = &dce110_mem_input_funcs;
- mem_input110->base.ctx = ctx;
-
- mem_input110->base.inst = inst;
-
- mem_input110->offsets = *offsets;
-
- return true;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h
deleted file mode 100644
index 5f10f266f096..000000000000
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/* Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DC_MEM_INPUT_DCE110_H__
-#define __DC_MEM_INPUT_DCE110_H__
-
-#include "mem_input.h"
-
-#define TO_DCE110_MEM_INPUT(mi)\
- container_of(mi, struct dce110_mem_input, base)
-
-struct dce110_mem_input_reg_offsets {
- uint32_t dcp;
- uint32_t dmif;
- uint32_t pipe;
-};
-
-struct dce110_mem_input {
- struct mem_input base;
- struct dce110_mem_input_reg_offsets offsets;
-};
-
-bool dce110_mem_input_construct(
- struct dce110_mem_input *mem_input110,
- struct dc_context *ctx,
- uint32_t inst,
- const struct dce110_mem_input_reg_offsets *offsets);
-
-/*
- * dce110_mem_input_program_display_marks
- *
- * This function will program nbp stutter and urgency watermarks to minimum
- * allowable values
- */
-void dce110_mem_input_program_display_marks(
- struct mem_input *mem_input,
- struct dce_watermarks nbp,
- struct dce_watermarks stutter,
- struct dce_watermarks urgent,
- uint32_t total_dest_line_time_ns);
-
-/*
- * dce110_allocate_mem_input
- *
- * This function will allocate a dmif buffer and program required
- * pixel duration for pipe
- */
-void dce110_allocate_mem_input(
- struct mem_input *mem_input,
- uint32_t h_total,/* for current stream */
- uint32_t v_total,/* for current stream */
- uint32_t pix_clk_khz,/* for current stream */
- uint32_t total_stream_num);
-
-/*
- * dce110_free_mem_input
- *
- * This function will deallocate a dmif buffer from pipe
- */
-void dce110_free_mem_input(
- struct mem_input *mem_input,
- uint32_t total_stream_num);
-
-/*
- * dce110_mem_input_program_surface_flip_and_addr
- *
- * This function programs hsync/vsync mode and surface address
- */
-bool dce110_mem_input_program_surface_flip_and_addr(
- struct mem_input *mem_input,
- const struct dc_plane_address *address,
- bool flip_immediate);
-
-/*
- * dce110_mem_input_program_surface_config
- *
- * This function will program surface tiling, size, rotation and pixel format
- * to corresponding dcp registers.
- */
-bool dce110_mem_input_program_surface_config(
- struct mem_input *mem_input,
- enum surface_pixel_format format,
- union dc_tiling_info *tiling_info,
- union plane_size *plane_size,
- enum dc_rotation_angle rotation,
- struct dc_plane_dcc_param *dcc,
- bool horizontal_mirror,
- bool visible);
-
-/*
- * dce110_mem_input_is_flip_pending
- *
- * This function will wait until the surface update-pending bit is cleared.
- * This is necessary when a flip immediate call is requested as we shouldn't
- * return until the flip has actually occurred.
- */
-bool dce110_mem_input_is_flip_pending(
- struct mem_input *mem_input);
-
-#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
index 78dd3ae3af5f..9777a4d961d5 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
@@ -33,29 +33,17 @@
#include "include/logger_interface.h"
#include "inc/dce_calcs.h"
-#include "dce110_mem_input.h"
-
-#define DCP_REG(reg) (reg + mem_input110->offsets.dcp)
-/*#define DMIF_REG(reg) (reg + mem_input110->offsets.dmif)*/
-/*#define PIPE_REG(reg) (reg + mem_input110->offsets.pipe)*/
-
-static const struct dce110_mem_input_reg_offsets dce110_mi_v_reg_offsets[] = {
- {
- .dcp = 0,
- .dmif = 0,
- .pipe = 0,
- }
-};
+#include "dce/dce_mem_input.h"
static void set_flip_control(
- struct dce110_mem_input *mem_input110,
+ struct dce_mem_input *mem_input110,
bool immediate)
{
uint32_t value = 0;
value = dm_read_reg(
mem_input110->base.ctx,
- DCP_REG(mmUNP_FLIP_CONTROL));
+ mmUNP_FLIP_CONTROL);
set_reg_field_value(value, 1,
UNP_FLIP_CONTROL,
@@ -63,13 +51,13 @@ static void set_flip_control(
dm_write_reg(
mem_input110->base.ctx,
- DCP_REG(mmUNP_FLIP_CONTROL),
+ mmUNP_FLIP_CONTROL,
value);
}
/* chroma part */
static void program_pri_addr_c(
- struct dce110_mem_input *mem_input110,
+ struct dce_mem_input *mem_input110,
PHYSICAL_ADDRESS_LOC address)
{
uint32_t value = 0;
@@ -84,7 +72,7 @@ UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MAS
dm_write_reg(
mem_input110->base.ctx,
- DCP_REG(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C),
+ mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C,
value);
temp = 0;
@@ -98,13 +86,13 @@ UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MAS
dm_write_reg(
mem_input110->base.ctx,
- DCP_REG(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C),
+ mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C,
value);
}
/* luma part */
static void program_pri_addr_l(
- struct dce110_mem_input *mem_input110,
+ struct dce_mem_input *mem_input110,
PHYSICAL_ADDRESS_LOC address)
{
uint32_t value = 0;
@@ -120,7 +108,7 @@ UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MAS
dm_write_reg(
mem_input110->base.ctx,
- DCP_REG(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L),
+ mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L,
value);
temp = 0;
@@ -134,12 +122,12 @@ UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MAS
dm_write_reg(
mem_input110->base.ctx,
- DCP_REG(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L),
+ mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L,
value);
}
static void program_addr(
- struct dce110_mem_input *mem_input110,
+ struct dce_mem_input *mem_input110,
const struct dc_plane_address *addr)
{
switch (addr->type) {
@@ -162,19 +150,19 @@ static void program_addr(
}
}
-static void enable(struct dce110_mem_input *mem_input110)
+static void enable(struct dce_mem_input *mem_input110)
{
uint32_t value = 0;
- value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmUNP_GRPH_ENABLE));
+ value = dm_read_reg(mem_input110->base.ctx, mmUNP_GRPH_ENABLE);
set_reg_field_value(value, 1, UNP_GRPH_ENABLE, GRPH_ENABLE);
dm_write_reg(mem_input110->base.ctx,
- DCP_REG(mmUNP_GRPH_ENABLE),
+ mmUNP_GRPH_ENABLE,
value);
}
static void program_tiling(
- struct dce110_mem_input *mem_input110,
+ struct dce_mem_input *mem_input110,
const union dc_tiling_info *info,
const enum surface_pixel_format pixel_format)
{
@@ -239,7 +227,7 @@ static void program_tiling(
}
static void program_size_and_rotation(
- struct dce110_mem_input *mem_input110,
+ struct dce_mem_input *mem_input110,
enum dc_rotation_angle rotation,
const union plane_size *plane_size)
{
@@ -277,7 +265,7 @@ static void program_size_and_rotation(
dm_write_reg(
mem_input110->base.ctx,
- DCP_REG(mmUNP_GRPH_PITCH_L),
+ mmUNP_GRPH_PITCH_L,
value);
value = 0;
@@ -285,7 +273,7 @@ static void program_size_and_rotation(
UNP_GRPH_PITCH_C, GRPH_PITCH_C);
dm_write_reg(
mem_input110->base.ctx,
- DCP_REG(mmUNP_GRPH_PITCH_C),
+ mmUNP_GRPH_PITCH_C,
value);
value = 0;
@@ -293,7 +281,7 @@ static void program_size_and_rotation(
UNP_GRPH_X_START_L, GRPH_X_START_L);
dm_write_reg(
mem_input110->base.ctx,
- DCP_REG(mmUNP_GRPH_X_START_L),
+ mmUNP_GRPH_X_START_L,
value);
value = 0;
@@ -301,7 +289,7 @@ static void program_size_and_rotation(
UNP_GRPH_X_START_C, GRPH_X_START_C);
dm_write_reg(
mem_input110->base.ctx,
- DCP_REG(mmUNP_GRPH_X_START_C),
+ mmUNP_GRPH_X_START_C,
value);
value = 0;
@@ -309,7 +297,7 @@ static void program_size_and_rotation(
UNP_GRPH_Y_START_L, GRPH_Y_START_L);
dm_write_reg(
mem_input110->base.ctx,
- DCP_REG(mmUNP_GRPH_Y_START_L),
+ mmUNP_GRPH_Y_START_L,
value);
value = 0;
@@ -317,7 +305,7 @@ static void program_size_and_rotation(
UNP_GRPH_Y_START_C, GRPH_Y_START_C);
dm_write_reg(
mem_input110->base.ctx,
- DCP_REG(mmUNP_GRPH_Y_START_C),
+ mmUNP_GRPH_Y_START_C,
value);
value = 0;
@@ -326,7 +314,7 @@ static void program_size_and_rotation(
UNP_GRPH_X_END_L, GRPH_X_END_L);
dm_write_reg(
mem_input110->base.ctx,
- DCP_REG(mmUNP_GRPH_X_END_L),
+ mmUNP_GRPH_X_END_L,
value);
value = 0;
@@ -335,7 +323,7 @@ static void program_size_and_rotation(
UNP_GRPH_X_END_C, GRPH_X_END_C);
dm_write_reg(
mem_input110->base.ctx,
- DCP_REG(mmUNP_GRPH_X_END_C),
+ mmUNP_GRPH_X_END_C,
value);
value = 0;
@@ -344,7 +332,7 @@ static void program_size_and_rotation(
UNP_GRPH_Y_END_L, GRPH_Y_END_L);
dm_write_reg(
mem_input110->base.ctx,
- DCP_REG(mmUNP_GRPH_Y_END_L),
+ mmUNP_GRPH_Y_END_L,
value);
value = 0;
@@ -353,7 +341,7 @@ static void program_size_and_rotation(
UNP_GRPH_Y_END_C, GRPH_Y_END_C);
dm_write_reg(
mem_input110->base.ctx,
- DCP_REG(mmUNP_GRPH_Y_END_C),
+ mmUNP_GRPH_Y_END_C,
value);
value = 0;
@@ -378,12 +366,12 @@ static void program_size_and_rotation(
dm_write_reg(
mem_input110->base.ctx,
- DCP_REG(mmUNP_HW_ROTATION),
+ mmUNP_HW_ROTATION,
value);
}
static void program_pixel_format(
- struct dce110_mem_input *mem_input110,
+ struct dce_mem_input *mem_input110,
enum surface_pixel_format format)
{
if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
@@ -393,7 +381,7 @@ static void program_pixel_format(
value = dm_read_reg(
mem_input110->base.ctx,
- DCP_REG(mmUNP_GRPH_CONTROL));
+ mmUNP_GRPH_CONTROL);
switch (format) {
case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
@@ -440,12 +428,12 @@ static void program_pixel_format(
dm_write_reg(
mem_input110->base.ctx,
- DCP_REG(mmUNP_GRPH_CONTROL),
+ mmUNP_GRPH_CONTROL,
value);
value = dm_read_reg(
mem_input110->base.ctx,
- DCP_REG(mmUNP_GRPH_CONTROL_EXP));
+ mmUNP_GRPH_CONTROL_EXP);
/* VIDEO FORMAT 0 */
set_reg_field_value(
@@ -455,7 +443,7 @@ static void program_pixel_format(
VIDEO_FORMAT);
dm_write_reg(
mem_input110->base.ctx,
- DCP_REG(mmUNP_GRPH_CONTROL_EXP),
+ mmUNP_GRPH_CONTROL_EXP,
value);
} else {
@@ -465,7 +453,7 @@ static void program_pixel_format(
value = dm_read_reg(
mem_input110->base.ctx,
- DCP_REG(mmUNP_GRPH_CONTROL_EXP));
+ mmUNP_GRPH_CONTROL_EXP);
switch (format) {
case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
@@ -487,17 +475,17 @@ static void program_pixel_format(
dm_write_reg(
mem_input110->base.ctx,
- DCP_REG(mmUNP_GRPH_CONTROL_EXP),
+ mmUNP_GRPH_CONTROL_EXP,
value);
}
}
-bool dce110_mem_input_v_is_surface_pending(struct mem_input *mem_input)
+bool dce_mem_input_v_is_surface_pending(struct mem_input *mem_input)
{
- struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input);
+ struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input);
uint32_t value;
- value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmUNP_GRPH_UPDATE));
+ value = dm_read_reg(mem_input110->base.ctx, mmUNP_GRPH_UPDATE);
if (get_reg_field_value(value, UNP_GRPH_UPDATE,
GRPH_SURFACE_UPDATE_PENDING))
@@ -507,12 +495,12 @@ bool dce110_mem_input_v_is_surface_pending(struct mem_input *mem_input)
return false;
}
-bool dce110_mem_input_v_program_surface_flip_and_addr(
+bool dce_mem_input_v_program_surface_flip_and_addr(
struct mem_input *mem_input,
const struct dc_plane_address *address,
bool flip_immediate)
{
- struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input);
+ struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input);
set_flip_control(mem_input110, flip_immediate);
program_addr(mem_input110,
@@ -584,13 +572,13 @@ static const unsigned int *get_dvmm_hw_setting(
}
}
-void dce110_mem_input_v_program_pte_vm(
+void dce_mem_input_v_program_pte_vm(
struct mem_input *mem_input,
enum surface_pixel_format format,
union dc_tiling_info *tiling_info,
enum dc_rotation_angle rotation)
{
- struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input);
+ struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input);
const unsigned int *pte = get_dvmm_hw_setting(tiling_info, format, false);
const unsigned int *pte_chroma = get_dvmm_hw_setting(tiling_info, format, true);
@@ -628,36 +616,36 @@ void dce110_mem_input_v_program_pte_vm(
break;
}
- value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT));
+ value = dm_read_reg(mem_input110->base.ctx, mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT);
/* TODO: un-hardcode requestlimit */
set_reg_field_value(value, 0xff, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L);
set_reg_field_value(value, 0xff, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C);
- dm_write_reg(mem_input110->base.ctx, DCP_REG(mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT), value);
+ dm_write_reg(mem_input110->base.ctx, mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT, value);
- value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmUNP_DVMM_PTE_CONTROL));
+ value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL);
set_reg_field_value(value, page_width, UNP_DVMM_PTE_CONTROL, DVMM_PAGE_WIDTH);
set_reg_field_value(value, page_height, UNP_DVMM_PTE_CONTROL, DVMM_PAGE_HEIGHT);
set_reg_field_value(value, min_pte_before_flip, UNP_DVMM_PTE_CONTROL, DVMM_MIN_PTE_BEFORE_FLIP);
- dm_write_reg(mem_input110->base.ctx, DCP_REG(mmUNP_DVMM_PTE_CONTROL), value);
+ dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL, value);
- value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmUNP_DVMM_PTE_ARB_CONTROL));
+ value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL);
set_reg_field_value(value, pte[5], UNP_DVMM_PTE_ARB_CONTROL, DVMM_PTE_REQ_PER_CHUNK);
set_reg_field_value(value, 0xff, UNP_DVMM_PTE_ARB_CONTROL, DVMM_MAX_PTE_REQ_OUTSTANDING);
- dm_write_reg(mem_input110->base.ctx, DCP_REG(mmUNP_DVMM_PTE_ARB_CONTROL), value);
+ dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL, value);
- value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmUNP_DVMM_PTE_CONTROL_C));
+ value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL_C);
set_reg_field_value(value, page_width_chroma, UNP_DVMM_PTE_CONTROL_C, DVMM_PAGE_WIDTH_C);
set_reg_field_value(value, page_height_chroma, UNP_DVMM_PTE_CONTROL_C, DVMM_PAGE_HEIGHT_C);
set_reg_field_value(value, min_pte_before_flip_chroma, UNP_DVMM_PTE_CONTROL_C, DVMM_MIN_PTE_BEFORE_FLIP_C);
- dm_write_reg(mem_input110->base.ctx, DCP_REG(mmUNP_DVMM_PTE_CONTROL_C), value);
+ dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL_C, value);
- value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmUNP_DVMM_PTE_ARB_CONTROL_C));
+ value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL_C);
set_reg_field_value(value, pte_chroma[5], UNP_DVMM_PTE_ARB_CONTROL_C, DVMM_PTE_REQ_PER_CHUNK_C);
set_reg_field_value(value, 0xff, UNP_DVMM_PTE_ARB_CONTROL_C, DVMM_MAX_PTE_REQ_OUTSTANDING_C);
- dm_write_reg(mem_input110->base.ctx, DCP_REG(mmUNP_DVMM_PTE_ARB_CONTROL_C), value);
+ dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL_C, value);
}
-void dce110_mem_input_v_program_surface_config(
+void dce_mem_input_v_program_surface_config(
struct mem_input *mem_input,
enum surface_pixel_format format,
union dc_tiling_info *tiling_info,
@@ -666,7 +654,7 @@ void dce110_mem_input_v_program_surface_config(
struct dc_plane_dcc_param *dcc,
bool horizotal_mirror)
{
- struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input);
+ struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input);
enable(mem_input110);
program_tiling(mem_input110, tiling_info, format);
@@ -943,7 +931,7 @@ static void program_nbp_watermark_c(
marks);
}
-void dce110_mem_input_v_program_display_marks(
+void dce_mem_input_v_program_display_marks(
struct mem_input *mem_input,
struct dce_watermarks nbp,
struct dce_watermarks stutter,
@@ -965,7 +953,7 @@ void dce110_mem_input_v_program_display_marks(
}
-void dce110_mem_input_program_chroma_display_marks(
+void dce_mem_input_program_chroma_display_marks(
struct mem_input *mem_input,
struct dce_watermarks nbp,
struct dce_watermarks stutter,
@@ -1036,42 +1024,29 @@ void dce110_free_mem_input_v(
static struct mem_input_funcs dce110_mem_input_v_funcs = {
.mem_input_program_display_marks =
- dce110_mem_input_v_program_display_marks,
+ dce_mem_input_v_program_display_marks,
.mem_input_program_chroma_display_marks =
- dce110_mem_input_program_chroma_display_marks,
+ dce_mem_input_program_chroma_display_marks,
.allocate_mem_input = dce110_allocate_mem_input_v,
.free_mem_input = dce110_free_mem_input_v,
.mem_input_program_surface_flip_and_addr =
- dce110_mem_input_v_program_surface_flip_and_addr,
+ dce_mem_input_v_program_surface_flip_and_addr,
.mem_input_program_pte_vm =
- dce110_mem_input_v_program_pte_vm,
+ dce_mem_input_v_program_pte_vm,
.mem_input_program_surface_config =
- dce110_mem_input_v_program_surface_config,
+ dce_mem_input_v_program_surface_config,
.mem_input_is_flip_pending =
- dce110_mem_input_v_is_surface_pending
+ dce_mem_input_v_is_surface_pending
};
/*****************************************/
/* Constructor, Destructor */
/*****************************************/
-bool dce110_mem_input_v_construct(
- struct dce110_mem_input *mem_input110,
+void dce110_mem_input_v_construct(
+ struct dce_mem_input *dce_mi,
struct dc_context *ctx)
{
- mem_input110->base.funcs = &dce110_mem_input_v_funcs;
- mem_input110->base.ctx = ctx;
-
- mem_input110->base.inst = 0;
-
- mem_input110->offsets = dce110_mi_v_reg_offsets[0];
-
- return true;
+ dce_mi->base.funcs = &dce110_mem_input_v_funcs;
+ dce_mi->base.ctx = ctx;
}
-#if 0
-void dce110_mem_input_v_destroy(struct mem_input **mem_input)
-{
- dm_free(TO_DCE110_MEM_INPUT(*mem_input));
- *mem_input = NULL;
-}
-#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.h
index b2667eefa3d0..f01d4a607fea 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.h
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.h
@@ -26,70 +26,10 @@
#define __DC_MEM_INPUT_V_DCE110_H__
#include "mem_input.h"
-#include "dce110_mem_input.h"
+#include "dce/dce_mem_input.h"
-bool dce110_mem_input_v_construct(
- struct dce110_mem_input *mem_input110,
+void dce110_mem_input_v_construct(
+ struct dce_mem_input *dce_mi,
struct dc_context *ctx);
-/*
- * This function will program nbp stutter and urgency watermarks to minimum
- * allowable values
- */
-void dce110_mem_input_v_program_display_marks(
- struct mem_input *mem_input,
- struct dce_watermarks nbp,
- struct dce_watermarks stutter,
- struct dce_watermarks urgent,
- uint32_t total_dest_line_time_ns);
-
-/*
- * This function will allocate a dmif buffer and program required
- * pixel duration for pipe
- */
-void dce110_allocate_mem_v_input(
- struct mem_input *mem_input,
- uint32_t h_total,/* for current stream */
- uint32_t v_total,/* for current stream */
- uint32_t pix_clk_khz,/* for current stream */
- uint32_t total_stream_num);
-
-/*
- * This function will deallocate a dmif buffer from pipe
- */
-void dce110_free_mem_v_input(
- struct mem_input *mem_input,
- uint32_t total_stream_num);
-
-/*
- * This function programs hsync/vsync mode and surface address
- */
-bool dce110_mem_input_v_program_surface_flip_and_addr(
- struct mem_input *mem_input,
- const struct dc_plane_address *address,
- bool flip_immediate);
-
-/*
- * dce110_mem_input_v_program_scatter_gather
- *
- * This function will program scatter gather registers.
- */
-bool dce110_mem_input_v_program_pte_vm(
- struct mem_input *mem_input,
- enum surface_pixel_format format,
- union dc_tiling_info *tiling_info,
- enum dc_rotation_angle rotation);
-
-/*
- * This function will program surface tiling, size, rotation and pixel format
- * to corresponding dcp registers.
- */
-bool dce110_mem_input_v_program_surface_config(
- struct mem_input *mem_input,
- enum surface_pixel_format format,
- union dc_tiling_info *tiling_info,
- union plane_size *plane_size,
- enum dc_rotation_angle rotation,
- bool visible);
-
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index 041d11968566..3ed5b9445535 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -38,7 +38,7 @@
#include "dce110/dce110_timing_generator_v.h"
#include "dce/dce_link_encoder.h"
#include "dce/dce_stream_encoder.h"
-#include "dce110/dce110_mem_input.h"
+#include "dce/dce_mem_input.h"
#include "dce110/dce110_mem_input_v.h"
#include "dce/dce_ipp.h"
#include "dce/dce_transform.h"
@@ -133,30 +133,6 @@ static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = {
}
};
-static const struct dce110_mem_input_reg_offsets dce110_mi_reg_offsets[] = {
- {
- .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE0_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- },
- {
- .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE1_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- },
- {
- .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE2_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- }
-};
-
/* set register offset */
#define SR(reg_name)\
.reg_name = mm ## reg_name
@@ -520,30 +496,21 @@ static const struct dce_mem_input_mask mi_masks = {
.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
};
+
static struct mem_input *dce110_mem_input_create(
struct dc_context *ctx,
- uint32_t inst,
- const struct dce110_mem_input_reg_offsets *offset)
+ uint32_t inst)
{
- struct dce110_mem_input *mem_input110 =
- dm_alloc(sizeof(struct dce110_mem_input));
+ struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input));
- if (!mem_input110)
+ if (!dce_mi) {
+ BREAK_TO_DEBUGGER();
return NULL;
-
- if (dce110_mem_input_construct(mem_input110, ctx, inst, offset)) {
- struct mem_input *mi = &mem_input110->base;
-
- mi->regs = &mi_regs[inst];
- mi->shifts = &mi_shifts;
- mi->masks = &mi_masks;
- mi->wa.single_head_rdreq_dmif_limit = 3;
- return mi;
}
- BREAK_TO_DEBUGGER();
- dm_free(mem_input110);
- return NULL;
+ dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
+ dce_mi->wa.single_head_rdreq_dmif_limit = 3;
+ return &dce_mi->base;
}
static void dce110_transform_destroy(struct transform **xfm)
@@ -698,7 +665,7 @@ static void destruct(struct dce110_resource_pool *pool)
dce_ipp_destroy(&pool->base.ipps[i]);
if (pool->base.mis[i] != NULL) {
- dm_free(TO_DCE110_MEM_INPUT(pool->base.mis[i]));
+ dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i]));
pool->base.mis[i] = NULL;
}
@@ -1132,7 +1099,7 @@ static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool)
{
struct dce110_timing_generator *dce110_tgv = dm_alloc(sizeof (*dce110_tgv));
struct dce_transform *dce110_xfmv = dm_alloc(sizeof (*dce110_xfmv));
- struct dce110_mem_input *dce110_miv = dm_alloc(sizeof (*dce110_miv));
+ struct dce_mem_input *dce110_miv = dm_alloc(sizeof (*dce110_miv));
struct dce110_opp *dce110_oppv = dm_alloc(sizeof (*dce110_oppv));
if ((dce110_tgv == NULL) ||
@@ -1345,8 +1312,7 @@ static bool construct(
goto res_create_fail;
}
- pool->base.mis[i] = dce110_mem_input_create(ctx, i,
- &dce110_mi_reg_offsets[i]);
+ pool->base.mis[i] = dce110_mem_input_create(ctx, i);
if (pool->base.mis[i] == NULL) {
BREAK_TO_DEBUGGER();
dm_error(
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/Makefile b/drivers/gpu/drm/amd/display/dc/dce112/Makefile
index 2d536fbc60c4..265ac4310d85 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dce112/Makefile
@@ -3,7 +3,7 @@
# It provides the control and status of HW CRTC block.
DCE112 = dce112_compressor.o dce112_hw_sequencer.o \
-dce112_resource.o dce112_mem_input.o
+dce112_resource.o
AMD_DAL_DCE112 = $(addprefix $(AMDDALPATH)/dc/dce112/,$(DCE112))
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_mem_input.c
deleted file mode 100644
index c29007dafe21..000000000000
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_mem_input.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-#include "dm_services.h"
-#include "dce112_mem_input.h"
-
-
-#include "dce/dce_11_2_d.h"
-#include "dce/dce_11_2_sh_mask.h"
-
-
-#define DCP_REG(reg) (reg + mem_input110->offsets.dcp)
-#define DMIF_REG(reg) (reg + mem_input110->offsets.dmif)
-#define PIPE_REG(reg) (reg + mem_input110->offsets.pipe)
-
-/*****************************************/
-/* Constructor, Destructor */
-/*****************************************/
-
-bool dce112_mem_input_construct(
- struct dce110_mem_input *mem_input110,
- struct dc_context *ctx,
- uint32_t inst,
- const struct dce110_mem_input_reg_offsets *offsets)
-{
- if (!dce110_mem_input_construct(mem_input110, ctx, inst, offsets))
- return false;
-
- mem_input110->base.funcs->mem_input_program_display_marks =
- dce_mem_input_program_display_marks;
-
- return true;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_mem_input.h
deleted file mode 100644
index de2aaf0f9a8e..000000000000
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_mem_input.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DC_MEM_INPUT_DCE112_H__
-#define __DC_MEM_INPUT_DCE112_H__
-
-#include "mem_input.h"
-#include "dce110/dce110_mem_input.h"
-
-bool dce112_mem_input_construct(
- struct dce110_mem_input *mem_input110,
- struct dc_context *ctx,
- uint32_t inst,
- const struct dce110_mem_input_reg_offsets *offsets);
-
-
-#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 0ed2616dd5cd..f405d6eecaa5 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -32,9 +32,10 @@
#include "include/irq_service_interface.h"
#include "dce110/dce110_resource.h"
#include "dce110/dce110_timing_generator.h"
-#include "dce112/dce112_mem_input.h"
#include "irq/dce110/irq_service_dce110.h"
+
+#include "dce/dce_mem_input.h"
#include "dce/dce_transform.h"
#include "dce/dce_link_encoder.h"
#include "dce/dce_stream_encoder.h"
@@ -132,51 +133,6 @@ static const struct dce110_timing_generator_offsets dce112_tg_offsets[] = {
}
};
-static const struct dce110_mem_input_reg_offsets dce112_mi_reg_offsets[] = {
- {
- .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE0_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- },
- {
- .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE1_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- },
- {
- .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE2_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- },
- {
- .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE3_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- },
- {
- .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE4_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- },
- {
- .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE5_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- }
-};
-
/* set register offset */
#define SR(reg_name)\
.reg_name = mm ## reg_name
@@ -541,27 +497,17 @@ static const struct dce_mem_input_mask mi_masks = {
static struct mem_input *dce112_mem_input_create(
struct dc_context *ctx,
- uint32_t inst,
- const struct dce110_mem_input_reg_offsets *offset)
+ uint32_t inst)
{
- struct dce110_mem_input *mem_input110 =
- dm_alloc(sizeof(struct dce110_mem_input));
+ struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input));
- if (!mem_input110)
+ if (!dce_mi) {
+ BREAK_TO_DEBUGGER();
return NULL;
-
- if (dce112_mem_input_construct(mem_input110, ctx, inst, offset)) {
- struct mem_input *mi = &mem_input110->base;
-
- mi->regs = &mi_regs[inst];
- mi->shifts = &mi_shifts;
- mi->masks = &mi_masks;
- return mi;
}
- BREAK_TO_DEBUGGER();
- dm_free(mem_input110);
- return NULL;
+ dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
+ return &dce_mi->base;
}
static void dce112_transform_destroy(struct transform **xfm)
@@ -705,7 +651,7 @@ static void destruct(struct dce110_resource_pool *pool)
dce_ipp_destroy(&pool->base.ipps[i]);
if (pool->base.mis[i] != NULL) {
- dm_free(TO_DCE110_MEM_INPUT(pool->base.mis[i]));
+ dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i]));
pool->base.mis[i] = NULL;
}
@@ -1347,10 +1293,7 @@ static bool construct(
goto res_create_fail;
}
- pool->base.mis[i] = dce112_mem_input_create(
- ctx,
- i,
- &dce112_mi_reg_offsets[i]);
+ pool->base.mis[i] = dce112_mem_input_create(ctx, i);
if (pool->base.mis[i] == NULL) {
BREAK_TO_DEBUGGER();
dm_error(
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/Makefile b/drivers/gpu/drm/amd/display/dc/dce120/Makefile
index 826c12ee368c..1779b963525c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dce120/Makefile
@@ -4,7 +4,7 @@
DCE120 = dce120_resource.o dce120_timing_generator.o \
-dce120_mem_input.o dce120_hw_sequencer.o
+dce120_hw_sequencer.o
AMD_DAL_DCE120 = $(addprefix $(AMDDALPATH)/dc/dce120/,$(DCE120))
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c
deleted file mode 100644
index c0677211bd93..000000000000
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c
+++ /dev/null
@@ -1,340 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-#include "dm_services.h"
-#include "dce120_mem_input.h"
-
-
-#include "vega10/DC/dce_12_0_offset.h"
-#include "vega10/DC/dce_12_0_sh_mask.h"
-#include "vega10/soc15ip.h"
-
-#define GENERAL_REG_UPDATE_N(reg_name, n, ...) \
- generic_reg_update_soc15(mem_input110->base.ctx, 0, reg_name, n, __VA_ARGS__)
-
-#define GENERAL_REG_UPDATE(reg, field, val) \
- GENERAL_REG_UPDATE_N(reg, 1, FD(reg##__##field), val)
-
-#define GENERAL_REG_UPDATE_2(reg, field1, val1, field2, val2) \
- GENERAL_REG_UPDATE_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2)
-
-
-
-#define DCP_REG_UPDATE_N(reg_name, n, ...) \
- generic_reg_update_soc15(mem_input110->base.ctx, mem_input110->offsets.dcp, reg_name, n, __VA_ARGS__)
-
-#define DCP_REG_SET_N(reg_name, n, ...) \
- generic_reg_set_soc15(mem_input110->base.ctx, mem_input110->offsets.dcp, reg_name, n, __VA_ARGS__)
-
-#define DCP_REG_UPDATE(reg, field, val) \
- DCP_REG_UPDATE_N(reg, 1, FD(reg##__##field), val)
-
-#define DCP_REG_UPDATE_2(reg, field1, val1, field2, val2) \
- DCP_REG_UPDATE_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2)
-
-#define DCP_REG_UPDATE_3(reg, field1, val1, field2, val2, field3, val3) \
- DCP_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3)
-
-#define DCP_REG_SET(reg, field, val) \
- DCP_REG_SET_N(reg, 1, FD(reg##__##field), val)
-
-#define DCP_REG_SET_2(reg, field1, val1, field2, val2) \
- DCP_REG_SET_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2)
-
-#define DCP_REG_SET_3(reg, field1, val1, field2, val2, field3, val3) \
- DCP_REG_SET_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3)
-
-
-
-#define DMIF_REG_UPDATE_N(reg_name, n, ...) \
- generic_reg_update_soc15(mem_input110->base.ctx, mem_input110->offsets.dmif, reg_name, n, __VA_ARGS__)
-
-#define DMIF_REG_SET_N(reg_name, n, ...) \
- generic_reg_set_soc15(mem_input110->base.ctx, mem_input110->offsets.dmif, reg_name, n, __VA_ARGS__)
-
-#define DMIF_REG_UPDATE(reg, field, val) \
- DMIF_REG_UPDATE_N(reg, 1, FD(reg##__##field), val)
-
-#define DMIF_REG_UPDATE_2(reg, field1, val1, field2, val2) \
- DMIF_REG_UPDATE_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2)
-
-#define DMIF_REG_UPDATE_3(reg, field1, val1, field2, val2, field3, val3) \
- DMIF_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3)
-
-#define DMIF_REG_SET(reg, field, val) \
- DMIF_REG_SET_N(reg, 1, FD(reg##__##field), val)
-
-#define DMIF_REG_SET_2(reg, field1, val1, field2, val2) \
- DMIF_REG_SET_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2)
-
-#define DMIF_REG_SET_3(reg, field1, val1, field2, val2, field3, val3) \
- DMIF_REG_SET_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3)
-
-
-
-#define PIPE_REG_UPDATE_N(reg_name, n, ...) \
- generic_reg_update_soc15(mem_input110->base.ctx, mem_input110->offsets.pipe, reg_name, n, __VA_ARGS__)
-
-#define PIPE_REG_SET_N(reg_name, n, ...) \
- generic_reg_set_soc15(mem_input110->base.ctx, mem_input110->offsets.pipe, reg_name, n, __VA_ARGS__)
-
-#define PIPE_REG_UPDATE(reg, field, val) \
- PIPE_REG_UPDATE_N(reg, 1, FD(reg##__##field), val)
-
-#define PIPE_REG_UPDATE_2(reg, field1, val1, field2, val2) \
- PIPE_REG_UPDATE_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2)
-
-#define PIPE_REG_UPDATE_3(reg, field1, val1, field2, val2, field3, val3) \
- PIPE_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3)
-
-#define PIPE_REG_SET(reg, field, val) \
- PIPE_REG_SET_N(reg, 1, FD(reg##__##field), val)
-
-#define PIPE_REG_SET_2(reg, field1, val1, field2, val2) \
- PIPE_REG_SET_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2)
-
-#define PIPE_REG_SET_3(reg, field1, val1, field2, val2, field3, val3) \
- PIPE_REG_SET_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3)
-
-
-
-static void program_sec_addr(
- struct dce110_mem_input *mem_input110,
- PHYSICAL_ADDRESS_LOC address)
-{
- uint32_t temp;
-
- /*high register MUST be programmed first*/
- temp = address.high_part &
- DCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK;
-
- DCP_REG_SET(
- DCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
- GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
- temp);
-
- temp = address.low_part >>
- DCP0_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT;
-
- DCP_REG_SET_2(
- DCP0_GRPH_SECONDARY_SURFACE_ADDRESS,
- GRPH_SECONDARY_SURFACE_ADDRESS, temp,
- GRPH_SECONDARY_DFQ_ENABLE, 0);
-}
-
-static void program_pri_addr(
- struct dce110_mem_input *mem_input110,
- PHYSICAL_ADDRESS_LOC address)
-{
- uint32_t temp;
-
- /*high register MUST be programmed first*/
- temp = address.high_part &
- DCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK;
-
- DCP_REG_SET(
- DCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
- GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
- temp);
-
- temp = address.low_part >>
- DCP0_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT;
-
- DCP_REG_SET(
- DCP0_GRPH_PRIMARY_SURFACE_ADDRESS,
- GRPH_PRIMARY_SURFACE_ADDRESS,
- temp);
-}
-
-
-static bool mem_input_is_flip_pending(struct mem_input *mem_input)
-{
- struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input);
- uint32_t value;
-
- value = dm_read_reg_soc15(mem_input110->base.ctx,
- mmDCP0_GRPH_UPDATE, mem_input110->offsets.dcp);
-
- if (get_reg_field_value(value, DCP0_GRPH_UPDATE,
- GRPH_SURFACE_UPDATE_PENDING))
- return true;
-
- mem_input->current_address = mem_input->request_address;
- return false;
-}
-
-static bool mem_input_program_surface_flip_and_addr(
- struct mem_input *mem_input,
- const struct dc_plane_address *address,
- bool flip_immediate)
-{
- struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input);
-
- /* TODO: Figure out if two modes are needed:
- * non-XDMA Mode: GRPH_SURFACE_UPDATE_IMMEDIATE_EN = 1
- * XDMA Mode: GRPH_SURFACE_UPDATE_H_RETRACE_EN = 1
- */
- DCP_REG_UPDATE(DCP0_GRPH_UPDATE,
- GRPH_UPDATE_LOCK, 1);
-
- if (flip_immediate) {
- DCP_REG_UPDATE_2(
- DCP0_GRPH_FLIP_CONTROL,
- GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0,
- GRPH_SURFACE_UPDATE_H_RETRACE_EN, 1);
- } else {
- DCP_REG_UPDATE_2(
- DCP0_GRPH_FLIP_CONTROL,
- GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0,
- GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
- }
-
- switch (address->type) {
- case PLN_ADDR_TYPE_GRAPHICS:
- if (address->grph.addr.quad_part == 0)
- break;
- program_pri_addr(mem_input110, address->grph.addr);
- break;
- case PLN_ADDR_TYPE_GRPH_STEREO:
- if (address->grph_stereo.left_addr.quad_part == 0
- || address->grph_stereo.right_addr.quad_part == 0)
- break;
- program_pri_addr(mem_input110, address->grph_stereo.left_addr);
- program_sec_addr(mem_input110, address->grph_stereo.right_addr);
- break;
- default:
- /* not supported */
- BREAK_TO_DEBUGGER();
- break;
- }
-
- mem_input->request_address = *address;
-
- if (flip_immediate)
- mem_input->current_address = *address;
-
- DCP_REG_UPDATE(DCP0_GRPH_UPDATE,
- GRPH_UPDATE_LOCK, 0);
-
- return true;
-}
-
-static void mem_input_update_dchub(struct mem_input *mi,
- struct dchub_init_data *dh_data)
-{
- struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mi);
- /* TODO: port code from dal2 */
- switch (dh_data->fb_mode) {
- case FRAME_BUFFER_MODE_ZFB_ONLY:
- /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/
- GENERAL_REG_UPDATE_2(
- DCHUB_FB_LOCATION,
- FB_TOP, 0,
- FB_BASE, 0x0FFFF);
-
- GENERAL_REG_UPDATE(
- DCHUB_AGP_BASE,
- AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
-
- GENERAL_REG_UPDATE(
- DCHUB_AGP_BOT,
- AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
-
- GENERAL_REG_UPDATE(
- DCHUB_AGP_TOP,
- AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);
- break;
- case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
- /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
- GENERAL_REG_UPDATE(
- DCHUB_AGP_BASE,
- AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
-
- GENERAL_REG_UPDATE(
- DCHUB_AGP_BOT,
- AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
-
- GENERAL_REG_UPDATE(
- DCHUB_AGP_TOP,
- AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);
- break;
- case FRAME_BUFFER_MODE_LOCAL_ONLY:
- /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
- GENERAL_REG_UPDATE(
- DCHUB_AGP_BASE,
- AGP_BASE, 0);
-
- GENERAL_REG_UPDATE(
- DCHUB_AGP_BOT,
- AGP_BOT, 0x03FFFF);
-
- GENERAL_REG_UPDATE(
- DCHUB_AGP_TOP,
- AGP_TOP, 0);
- break;
- default:
- break;
- }
-
- dh_data->dchub_initialzied = true;
- dh_data->dchub_info_valid = false;
-}
-
-static struct mem_input_funcs dce120_mem_input_funcs = {
- .mem_input_program_display_marks = dce_mem_input_program_display_marks,
- .allocate_mem_input = dce_mem_input_allocate_dmif,
- .free_mem_input = dce_mem_input_free_dmif,
- .mem_input_program_surface_flip_and_addr =
- mem_input_program_surface_flip_and_addr,
- .mem_input_program_pte_vm = dce_mem_input_program_pte_vm,
- .mem_input_program_surface_config =
- dce_mem_input_program_surface_config,
- .mem_input_is_flip_pending = mem_input_is_flip_pending,
- .mem_input_update_dchub = mem_input_update_dchub
-};
-
-/*****************************************/
-/* Constructor, Destructor */
-/*****************************************/
-
-bool dce120_mem_input_construct(
- struct dce110_mem_input *mem_input110,
- struct dc_context *ctx,
- uint32_t inst,
- const struct dce110_mem_input_reg_offsets *offsets)
-{
- /* supported stutter method
- * STUTTER_MODE_ENHANCED
- * STUTTER_MODE_QUAD_DMIF_BUFFER
- * STUTTER_MODE_WATERMARK_NBP_STATE
- */
-
- if (!dce110_mem_input_construct(mem_input110, ctx, inst, offsets))
- return false;
-
- mem_input110->base.funcs = &dce120_mem_input_funcs;
- mem_input110->offsets = *offsets;
-
- return true;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.h
deleted file mode 100644
index 379fd72155b9..000000000000
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DC_MEM_INPUT_DCE120_H__
-#define __DC_MEM_INPUT_DCE120_H__
-
-#include "mem_input.h"
-#include "dce110/dce110_mem_input.h"
-
-bool dce120_mem_input_construct(
- struct dce110_mem_input *mem_input110,
- struct dc_context *ctx,
- uint32_t inst,
- const struct dce110_mem_input_reg_offsets *offsets);
-
-#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index b13abb025e1b..1276dabfb208 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -41,8 +41,7 @@
#include "dce/dce_clock_source.h"
#include "dce/dce_clocks.h"
#include "dce/dce_ipp.h"
-#include "dce110/dce110_mem_input.h"
-#include "dce120/dce120_mem_input.h"
+#include "dce/dce_mem_input.h"
#include "dce110/dce110_hw_sequencer.h"
#include "dce120/dce120_hw_sequencer.h"
@@ -376,51 +375,6 @@ struct output_pixel_processor *dce120_opp_create(
return NULL;
}
-static const struct dce110_mem_input_reg_offsets dce120_mi_reg_offsets[] = {
- {
- .dcp = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
- .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
- - mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE0_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- },
- {
- .dcp = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
- .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
- - mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE1_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- },
- {
- .dcp = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
- .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
- - mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE2_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- },
- {
- .dcp = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
- .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
- - mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE3_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- },
- {
- .dcp = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
- .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
- - mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE4_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- },
- {
- .dcp = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
- .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
- - mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE5_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- }
-};
-
static const struct bios_registers bios_regs = {
.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX)
};
@@ -518,7 +472,7 @@ static void destruct(struct dce110_resource_pool *pool)
dce_ipp_destroy(&pool->base.ipps[i]);
if (pool->base.mis[i] != NULL) {
- dm_free(TO_DCE110_MEM_INPUT(pool->base.mis[i]));
+ dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i]));
pool->base.mis[i] = NULL;
}
@@ -708,27 +662,17 @@ static const struct dce_mem_input_mask mi_masks = {
static struct mem_input *dce120_mem_input_create(
struct dc_context *ctx,
- uint32_t inst,
- const struct dce110_mem_input_reg_offsets *offset)
+ uint32_t inst)
{
- struct dce110_mem_input *mem_input110 =
- dm_alloc(sizeof(struct dce110_mem_input));
+ struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input));
- if (!mem_input110)
+ if (!dce_mi) {
+ BREAK_TO_DEBUGGER();
return NULL;
-
- if (dce120_mem_input_construct(mem_input110, ctx, inst, offset)) {
- struct mem_input *mi = &mem_input110->base;
-
- mi->regs = &mi_regs[inst];
- mi->shifts = &mi_shifts;
- mi->masks = &mi_masks;
- return mi;
}
- BREAK_TO_DEBUGGER();
- dm_free(mem_input110);
- return NULL;
+ dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
+ return &dce_mi->base;
}
static struct transform *dce120_transform_create(
@@ -1007,8 +951,7 @@ static bool construct(
goto controller_create_fail;
}
- pool->base.mis[i] = dce120_mem_input_create(ctx,
- i, &dce120_mi_reg_offsets[i]);
+ pool->base.mis[i] = dce120_mem_input_create(ctx, i);
if (pool->base.mis[i] == NULL) {
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/Makefile b/drivers/gpu/drm/amd/display/dc/dce80/Makefile
index 1d54d5fa0fd2..c1105895e5fa 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dce80/Makefile
@@ -2,8 +2,7 @@
# Makefile for the 'controller' sub-component of DAL.
# It provides the control and status of HW CRTC block.
-DCE80 = dce80_timing_generator.o \
- dce80_compressor.o dce80_mem_input.o dce80_hw_sequencer.o \
+DCE80 = dce80_timing_generator.o dce80_compressor.o dce80_hw_sequencer.o \
dce80_resource.o
AMD_DAL_DCE80 = $(addprefix $(AMDDALPATH)/dc/dce80/,$(DCE80))
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c
deleted file mode 100644
index 933e3d819f27..000000000000
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-#include "dm_services.h"
-
-#include "dce/dce_8_0_d.h"
-#include "dce/dce_8_0_sh_mask.h"
-/* TODO: this needs to be looked at, used by Stella's workaround*/
-#include "gmc/gmc_7_1_d.h"
-#include "gmc/gmc_7_1_sh_mask.h"
-
-#include "include/logger_interface.h"
-#include "inc/dce_calcs.h"
-
-#include "../dce110/dce110_mem_input.h"
-#include "dce80_mem_input.h"
-
-#define MAX_WATERMARK 0xFFFF
-#define SAFE_NBP_MARK 0x7FFF
-
-#define DCP_REG(reg) (reg + mem_input80->offsets.dcp)
-#define DMIF_REG(reg) (reg + mem_input80->offsets.dmif)
-#define PIPE_REG(reg) (reg + mem_input80->offsets.pipe)
-
-static struct mem_input_funcs dce80_mem_input_funcs = {
- .mem_input_program_display_marks =
- dce110_mem_input_program_display_marks,
- .allocate_mem_input = dce_mem_input_allocate_dmif,
- .free_mem_input = dce_mem_input_free_dmif,
- .mem_input_program_surface_flip_and_addr =
- dce110_mem_input_program_surface_flip_and_addr,
- .mem_input_program_surface_config =
- dce_mem_input_program_surface_config,
- .mem_input_is_flip_pending =
- dce110_mem_input_is_flip_pending,
- .mem_input_update_dchub = NULL
-};
-
-/*****************************************/
-/* Constructor, Destructor */
-/*****************************************/
-
-bool dce80_mem_input_construct(
- struct dce110_mem_input *mem_input80,
- struct dc_context *ctx,
- uint32_t inst,
- const struct dce110_mem_input_reg_offsets *offsets)
-{
- /* supported stutter method
- * STUTTER_MODE_ENHANCED
- * STUTTER_MODE_QUAD_DMIF_BUFFER
- */
- mem_input80->base.funcs = &dce80_mem_input_funcs;
- mem_input80->base.ctx = ctx;
-
- mem_input80->base.inst = inst;
-
- mem_input80->offsets = *offsets;
-
- return true;
-}
-
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.h
deleted file mode 100644
index 357b9e2e9f1e..000000000000
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DC_MEM_INPUT_DCE80_H__
-#define __DC_MEM_INPUT_DCE80_H__
-
-#include "mem_input.h"
-
-bool dce80_mem_input_construct(
- struct dce110_mem_input *mem_input80,
- struct dc_context *ctx,
- uint32_t inst,
- const struct dce110_mem_input_reg_offsets *offsets);
-
-#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index 5735914a8737..095e437ce112 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -35,12 +35,12 @@
#include "include/irq_service_interface.h"
#include "irq/dce80/irq_service_dce80.h"
#include "dce110/dce110_timing_generator.h"
-#include "dce110/dce110_mem_input.h"
#include "dce110/dce110_resource.h"
#include "dce80/dce80_timing_generator.h"
+#include "dce/dce_mem_input.h"
#include "dce/dce_link_encoder.h"
#include "dce/dce_stream_encoder.h"
-#include "dce80/dce80_mem_input.h"
+#include "dce/dce_mem_input.h"
#include "dce/dce_ipp.h"
#include "dce/dce_transform.h"
#include "dce/dce_opp.h"
@@ -141,51 +141,6 @@ static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = {
}
};
-static const struct dce110_mem_input_reg_offsets dce80_mi_reg_offsets[] = {
- {
- .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE0_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- },
- {
- .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE1_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- },
- {
- .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE2_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- },
- {
- .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE3_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- },
- {
- .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE4_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- },
- {
- .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE5_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- }
-};
-
/* set register offset */
#define SR(reg_name)\
.reg_name = mm ## reg_name
@@ -541,28 +496,18 @@ static const struct dce_mem_input_mask mi_masks = {
static struct mem_input *dce80_mem_input_create(
struct dc_context *ctx,
- uint32_t inst,
- const struct dce110_mem_input_reg_offsets *offsets)
+ uint32_t inst)
{
- struct dce110_mem_input *mem_input80 =
- dm_alloc(sizeof(struct dce110_mem_input));
+ struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input));
- if (!mem_input80)
+ if (!dce_mi) {
+ BREAK_TO_DEBUGGER();
return NULL;
-
- if (dce80_mem_input_construct(mem_input80, ctx, inst, offsets)) {
- struct mem_input *mi = &mem_input80->base;
-
- mi->regs = &mi_regs[inst];
- mi->shifts = &mi_shifts;
- mi->masks = &mi_masks;
- mi->wa.single_head_rdreq_dmif_limit = 2;
- return mi;
}
- BREAK_TO_DEBUGGER();
- dm_free(mem_input80);
- return NULL;
+ dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
+ dce_mi->wa.single_head_rdreq_dmif_limit = 2;
+ return &dce_mi->base;
}
static void dce80_transform_destroy(struct transform **xfm)
@@ -684,7 +629,7 @@ static void destruct(struct dce110_resource_pool *pool)
dce_ipp_destroy(&pool->base.ipps[i]);
if (pool->base.mis[i] != NULL) {
- dm_free(TO_DCE110_MEM_INPUT(pool->base.mis[i]));
+ dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i]));
pool->base.mis[i] = NULL;
}
@@ -1000,8 +945,7 @@ static bool construct(
goto res_create_fail;
}
- pool->base.mis[i] = dce80_mem_input_create(ctx, i,
- &dce80_mi_reg_offsets[i]);
+ pool->base.mis[i] = dce80_mem_input_create(ctx, i);
if (pool->base.mis[i] == NULL) {
BREAK_TO_DEBUGGER();
dm_error("DC: failed to create memory input!\n");
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
index 79fbc60e21c9..bd0dfeb2afa2 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
@@ -28,8 +28,6 @@
#include "dc.h"
#include "include/grph_object_id.h"
-#include "dce/dce_mem_input.h" /* temporary */
-
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
#include "dml/display_mode_structs.h"
@@ -51,7 +49,6 @@ struct dcn_watermark_set {
struct dcn_watermarks c;
struct dcn_watermarks d;
};
-
#endif
struct dce_watermarks {
@@ -74,11 +71,6 @@ struct mem_input {
struct dc_plane_address current_address;
uint32_t inst;
struct stutter_modes stutter_mode;
-
- const struct dce_mem_input_registers *regs;
- const struct dce_mem_input_shift *shifts;
- const struct dce_mem_input_mask *masks;
- struct dce_mem_input_wa wa;
};
struct mem_input_funcs {
--
2.11.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 06/31] drm/amd/display: Use dc_update_surfaces_for_stream for flip.
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (4 preceding siblings ...)
2017-05-23 14:08 ` [PATCH 05/31] drm/amd/display: dce 8 - 12 mem_input refactor to new style Harry Wentland
@ 2017-05-23 14:08 ` Harry Wentland
2017-05-23 14:08 ` [PATCH 07/31] drm/amd/display: Clen unused interface Harry Wentland
` (24 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:08 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Andrey Grodzovsky
From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Today we use special interface for flip because of fear of cuncurency issues
over dc->current_ctx. This should be no longer an issue when flipping on
multiple CRTCs concurently since for fast update (as flip is) no new context
is created and the exsisitng is not destroyed. For full updates case when
removing or adding streams on once CRTC while flipping on another
Adding all current active CRTC's states to the atomic commit in
amdgpu_dm_atomic_check will garntee that any such full update commit
will wait for completion of any outstanding flip.
Change-Id: I0c7e972eec82ae6f61706800ef5d40ed480683d9
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Reviewed-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 ++++++---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 23 +++++++++++++++++++++-
2 files changed, 28 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index cd06229bef2e..36fe956b0a89 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1355,6 +1355,7 @@ static void dm_page_flip(struct amdgpu_device *adev,
struct amdgpu_crtc *acrtc;
const struct dc_stream *stream;
struct dc_flip_addrs addr = { {0} };
+ struct dc_surface_update surface_updates[1] = { {0} };
/*
* TODO risk of concurrency issues
@@ -1417,9 +1418,11 @@ static void dm_page_flip(struct amdgpu_device *adev,
acrtc->base.state->event = NULL;
}
- dc_flip_surface_addrs(adev->dm.dc,
- dc_stream_get_status(stream)->surfaces,
- &addr, 1);
+ surface_updates->surface = dc_stream_get_status(stream)->surfaces[0];
+ surface_updates->flip_addr = &addr;
+
+
+ dc_update_surfaces_for_stream(adev->dm.dc, surface_updates, 1, stream);
DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
__func__,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 8aeb10786b94..de5c63f42d65 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -3082,6 +3082,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
struct dc *dc = adev->dm.dc;
bool need_to_validate = false;
struct validate_context *context;
+ bool wait_4_prev_commits = false;
ret = drm_atomic_helper_check(dev, state);
@@ -3158,6 +3159,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
new_stream_count++;
need_to_validate = true;
+ wait_4_prev_commits = true;
break;
}
@@ -3203,6 +3205,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
new_stream_count++;
need_to_validate = true;
+ wait_4_prev_commits = true;
break;
}
@@ -3214,6 +3217,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
set,
set_count,
acrtc->stream);
+ wait_4_prev_commits = true;
}
break;
}
@@ -3306,9 +3310,26 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
context = dc_get_validate_context(dc, set, set_count);
- if (need_to_validate == false || set_count == 0 || context)
+ if (need_to_validate == false || set_count == 0 || context) {
+
ret = 0;
+ if (wait_4_prev_commits) {
+ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+ struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
+ struct drm_crtc_state *crtc_state;
+
+ if (acrtc->stream) {
+ crtc_state = drm_atomic_get_crtc_state(state, crtc);
+ if (IS_ERR(crtc_state)) {
+ ret = PTR_ERR(crtc_state);
+ break;
+ }
+ }
+ }
+ }
+ }
+
if (context) {
dc_resource_validate_ctx_destruct(context);
dm_free(context);
--
2.11.0
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^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 07/31] drm/amd/display: Clen unused interface.
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (5 preceding siblings ...)
2017-05-23 14:08 ` [PATCH 06/31] drm/amd/display: Use dc_update_surfaces_for_stream for flip Harry Wentland
@ 2017-05-23 14:08 ` Harry Wentland
2017-05-23 14:08 ` [PATCH 08/31] drm/amd/display: Fix dcn10 cursor set position hang Harry Wentland
` (23 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:08 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Andrey Grodzovsky
From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Change-Id: Icf443def80e33f255d2d4c151a36c06951d275d2
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 26 --------------------------
drivers/gpu/drm/amd/display/dc/dc.h | 12 ------------
2 files changed, 38 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 6d56cb0c29cc..b5ba822df55e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1515,32 +1515,6 @@ const struct audio **dc_get_audios(struct dc *dc)
return (const struct audio **)core_dc->res_pool->audios;
}
-void dc_flip_surface_addrs(
- struct dc *dc,
- const struct dc_surface *const surfaces[],
- struct dc_flip_addrs flip_addrs[],
- uint32_t count)
-{
- struct core_dc *core_dc = DC_TO_CORE(dc);
- int i, j;
-
- for (i = 0; i < count; i++) {
- struct core_surface *surface = DC_SURFACE_TO_CORE(surfaces[i]);
-
- surface->public.address = flip_addrs[i].address;
- surface->public.flip_immediate = flip_addrs[i].flip_immediate;
-
- for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
- struct pipe_ctx *pipe_ctx = &core_dc->current_context->res_ctx.pipe_ctx[j];
-
- if (pipe_ctx->surface != surface)
- continue;
-
- core_dc->hwss.update_plane_addr(core_dc, pipe_ctx);
- }
- }
-}
-
enum dc_irq_source dc_interrupt_to_irq_source(
struct dc *dc,
uint32_t src_id,
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 0610805cdb05..f2efa32fe4ac 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -394,18 +394,6 @@ struct dc_flip_addrs {
};
/*
- * Optimized flip address update function.
- *
- * After this call:
- * Surface addresses and flip attributes are programmed.
- * Surface flip occur at next configured time (h_sync or v_sync flip)
- */
-void dc_flip_surface_addrs(struct dc *dc,
- const struct dc_surface *const surfaces[],
- struct dc_flip_addrs flip_addrs[],
- uint32_t count);
-
-/*
* Set up surface attributes and associate to a stream
* The surfaces parameter is an absolute set of all surface active for the stream.
* If no surfaces are provided, the stream will be blanked; no memory read.
--
2.11.0
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^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 08/31] drm/amd/display: Fix dcn10 cursor set position hang
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (6 preceding siblings ...)
2017-05-23 14:08 ` [PATCH 07/31] drm/amd/display: Clen unused interface Harry Wentland
@ 2017-05-23 14:08 ` Harry Wentland
2017-05-23 14:08 ` [PATCH 09/31] drm/amd/display: add missing GRPH_UPDATE_LOCK field macro for dce_mem_input Harry Wentland
` (22 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:08 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Leo (Sunpeng) Li
From: "Leo (Sunpeng) Li" <sunpeng.li@amd.com>
Calling dcn10_cursor_set_position() before dcn10_cursor_set_attributes()
with invalid (0-value) attributes can cause the ASIC to hang. This fix
checks that address.quadpart is non-zero within set_position before calling
set_attributes.
Change-Id: I89d45b5e66b60bb936c02b97bcec36ff8c10465c
Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
index 3062b7de4fe2..082c98c11293 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
@@ -614,6 +614,16 @@ static void dcn10_cursor_set_position(
uint32_t cur_en = pos->enable ? 1 : 0;
uint32_t dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0;
+ /*
+ * Guard aganst cursor_set_position() from being called with invalid
+ * attributes
+ *
+ * TODO: Look at combining cursor_set_position() and
+ * cursor_set_attributes() into cursor_update()
+ */
+ if (ippn10->curs_attr.address.quad_part == 0)
+ return;
+
dst_x_offset *= param->ref_clk_khz;
dst_x_offset /= param->pixel_clk_khz;
--
2.11.0
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 09/31] drm/amd/display: add missing GRPH_UPDATE_LOCK field macro for dce_mem_input
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (7 preceding siblings ...)
2017-05-23 14:08 ` [PATCH 08/31] drm/amd/display: Fix dcn10 cursor set position hang Harry Wentland
@ 2017-05-23 14:08 ` Harry Wentland
2017-05-23 14:08 ` [PATCH 10/31] drm/amd/display: Unify loop for surface update and page flip Harry Wentland
` (21 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:08 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Change-Id: I891ab6c4681da08dd2d9111cb77a1f87348b2420
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
index 55481f5adcdf..9d083cd79b4c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
@@ -158,6 +158,7 @@ struct dce_mem_input_registers {
SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS, GRPH_PRIMARY_SURFACE_ADDRESS, mask_sh),\
SFB(blk, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING, mask_sh),\
+ SFB(blk, GRPH_UPDATE, GRPH_UPDATE_LOCK, mask_sh),\
SFB(blk, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN, mask_sh)
#define MI_DCP_DCE11_MASK_SH_LIST(mask_sh, blk)\
--
2.11.0
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^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 10/31] drm/amd/display: Unify loop for surface update and page flip.
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (8 preceding siblings ...)
2017-05-23 14:08 ` [PATCH 09/31] drm/amd/display: add missing GRPH_UPDATE_LOCK field macro for dce_mem_input Harry Wentland
@ 2017-05-23 14:08 ` Harry Wentland
2017-05-23 14:08 ` [PATCH 11/31] drm/amd/display: read VM settings from MMHUB Harry Wentland
` (20 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:08 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Andrey Grodzovsky
From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Remove extra loop we have for page flips and do flips in same loop we do
for surface create/update.
Add documentation for synchronization between commits on different crtcs.
Rename function to have DM prefix.
Change-Id: Ibb6644b15f75981eae7c65a891a9314fb5c23fe9
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 88 +++++++++++-----------
1 file changed, 42 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index de5c63f42d65..6d8a1277d59e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -2562,10 +2562,11 @@ static void amdgpu_dm_do_flip(
acrtc->crtc_id);
}
-void dc_commit_surfaces(struct drm_atomic_state *state,
+static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state,
struct drm_device *dev,
struct amdgpu_display_manager *dm,
- struct drm_crtc *pcrtc)
+ struct drm_crtc *pcrtc,
+ bool *wait_for_vblank)
{
uint32_t i;
struct drm_plane *plane;
@@ -2578,10 +2579,11 @@ void dc_commit_surfaces(struct drm_atomic_state *state,
for_each_plane_in_state(state, plane, old_plane_state, i) {
struct drm_plane_state *plane_state = plane->state;
struct drm_crtc *crtc = plane_state->crtc;
+ struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(crtc);
struct drm_framebuffer *fb = plane_state->fb;
struct drm_connector *connector;
struct dm_connector_state *dm_state = NULL;
- struct amdgpu_crtc *acrtc_attach;
+
enum dm_commit_action action;
bool pflip_needed;
@@ -2590,13 +2592,13 @@ void dc_commit_surfaces(struct drm_atomic_state *state,
action = get_dm_commit_action(crtc->state);
- /* Surfaces are created under two scenarios:
- * 1. This commit is not a page flip.
- * 2. This commit is a page flip, and streams are created.
+ /*
+ * TODO - TO decide if it's a flip or surface update
+ * stop relying on allow_modeset flag and query DC
+ * using dc_check_update_surfaces_for_stream.
*/
pflip_needed = !state->allow_modeset;
- if (!pflip_needed || action == DM_COMMIT_ACTION_DPMS_ON
- || action == DM_COMMIT_ACTION_SET) {
+ if (!pflip_needed) {
list_for_each_entry(connector,
&dev->mode_config.connector_list,
head) {
@@ -2626,11 +2628,23 @@ void dc_commit_surfaces(struct drm_atomic_state *state,
if (crtc == pcrtc) {
add_surface(dm->dc, crtc, plane,
&dc_surfaces_constructed[planes_count]);
- acrtc_attach = to_amdgpu_crtc(crtc);
dc_stream_attach = acrtc_attach->stream;
planes_count++;
}
+ } else if (crtc->state->planes_changed) {
+ *wait_for_vblank =
+ acrtc_attach->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
+ false : true;
+
+ amdgpu_dm_do_flip(
+ crtc,
+ fb,
+ drm_crtc_vblank_count(crtc) + *wait_for_vblank);
+
+ /*clean up the flags for next usage*/
+ acrtc_attach->flip_flags = 0;
}
+
}
if (planes_count) {
@@ -2652,8 +2666,6 @@ void amdgpu_dm_atomic_commit_tail(
struct drm_device *dev = state->dev;
struct amdgpu_device *adev = dev->dev_private;
struct amdgpu_display_manager *dm = &adev->dm;
- struct drm_plane *plane;
- struct drm_plane_state *old_plane_state;
uint32_t i, j;
uint32_t commit_streams_count = 0;
uint32_t new_crtcs_count = 0;
@@ -2818,7 +2830,7 @@ void amdgpu_dm_atomic_commit_tail(
/* update planes when needed per crtc*/
for_each_crtc_in_state(state, pcrtc, old_crtc_state, j)
- dc_commit_surfaces(state, dev, dm, pcrtc);
+ amdgpu_dm_commit_surfaces(state, dev, dm, pcrtc, &wait_for_vblank);
for (i = 0; i < new_crtcs_count; i++) {
/*
@@ -2832,34 +2844,6 @@ void amdgpu_dm_atomic_commit_tail(
manage_dm_interrupts(adev, acrtc, true);
dm_crtc_cursor_reset(&acrtc->base);
-
- }
-
- for_each_plane_in_state(state, plane, old_plane_state, i) {
- struct drm_plane_state *plane_state = plane->state;
- struct drm_crtc *crtc = plane_state->crtc;
- struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
- struct drm_framebuffer *fb = plane_state->fb;
- bool pflip_needed;
-
- if (!fb || !crtc || !crtc->state->planes_changed ||
- !crtc->state->active)
- continue;
- pflip_needed = !state->allow_modeset;
-
- if (pflip_needed) {
- wait_for_vblank =
- acrtc->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
- false : true;
-
- amdgpu_dm_do_flip(
- crtc,
- fb,
- drm_crtc_vblank_count(crtc) + wait_for_vblank);
-
- /*clean up the flags for next usage*/
- acrtc->flip_flags = 0;
- }
}
@@ -3082,7 +3066,11 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
struct dc *dc = adev->dm.dc;
bool need_to_validate = false;
struct validate_context *context;
- bool wait_4_prev_commits = false;
+ /*
+ * This bool will be set for true for any modeset/reset
+ * or surface update which implies non fast surfae update.
+ */
+ bool wait_for_prev_commits = false;
ret = drm_atomic_helper_check(dev, state);
@@ -3159,7 +3147,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
new_stream_count++;
need_to_validate = true;
- wait_4_prev_commits = true;
+ wait_for_prev_commits = true;
break;
}
@@ -3205,7 +3193,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
new_stream_count++;
need_to_validate = true;
- wait_4_prev_commits = true;
+ wait_for_prev_commits = true;
break;
}
@@ -3217,7 +3205,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
set,
set_count,
acrtc->stream);
- wait_4_prev_commits = true;
+ wait_for_prev_commits = true;
}
break;
}
@@ -3313,8 +3301,16 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
if (need_to_validate == false || set_count == 0 || context) {
ret = 0;
-
- if (wait_4_prev_commits) {
+ /*
+ * For full updates case when
+ * removing/adding/updateding streams on once CRTC while flipping
+ * on another CRTC,
+ * Adding all current active CRTC's states to the atomic commit in
+ * amdgpu_dm_atomic_check will guarantee that any such full update commit
+ * will wait for completion of any outstanding flip using DRMs
+ * synchronization events.
+ */
+ if (wait_for_prev_commits) {
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
struct drm_crtc_state *crtc_state;
--
2.11.0
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 11/31] drm/amd/display: read VM settings from MMHUB
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (9 preceding siblings ...)
2017-05-23 14:08 ` [PATCH 10/31] drm/amd/display: Unify loop for surface update and page flip Harry Wentland
@ 2017-05-23 14:08 ` Harry Wentland
2017-05-23 14:08 ` [PATCH 12/31] drm/amd/display: Fix 5th display lightup on Vega10 Harry Wentland
` (19 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:08 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
instead of GC, as after GFX off, GC can be power gated any time
Change-Id: Ia40d341ffd06fb1928bd8d95a4b3ef7eca4f73d1
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 24 +++++++++++-----------
.../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 14 ++++++-------
2 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
index 4a5eb6ae3524..20bd0f5d7b17 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
@@ -130,18 +130,18 @@
SR(DCHUBBUB_ARB_SAT_LEVEL),\
SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\
/* todo: get these from GVM instead of reading registers ourselves */\
- GC_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\
- GC_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\
- GC_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),\
- GC_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),\
- GC_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),\
- GC_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),\
- GC_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),\
- GC_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),\
- GC_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\
- GC_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),\
- GC_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\
- GC_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR)
+ MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\
+ MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\
+ MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),\
+ MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),\
+ MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),\
+ MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),\
+ MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),\
+ MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),\
+ MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\
+ MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),\
+ MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\
+ MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR)
struct dcn_mi_registers {
uint32_t DCHUBP_CNTL;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 4e5b225a2a08..7fdc5860857b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -122,15 +122,15 @@ enum dcn10_clk_src_array_id {
.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
mm ## reg_name
-/* GC */
-#define GC_BASE_INNER(seg) \
- GC_BASE__INST0_SEG ## seg
+/* MMHUB */
+#define MMHUB_BASE_INNER(seg) \
+ MMHUB_BASE__INST0_SEG ## seg
-#define GC_BASE(seg) \
- GC_BASE_INNER(seg)
+#define MMHUB_BASE(seg) \
+ MMHUB_BASE_INNER(seg)
-#define GC_SR(reg_name)\
- .reg_name = GC_BASE(mm ## reg_name ## _BASE_IDX) + \
+#define MMHUB_SR(reg_name)\
+ .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
mm ## reg_name
/* macros to expend register list macro defined in HW object header file
--
2.11.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 12/31] drm/amd/display: Fix 5th display lightup on Vega10
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (10 preceding siblings ...)
2017-05-23 14:08 ` [PATCH 11/31] drm/amd/display: read VM settings from MMHUB Harry Wentland
@ 2017-05-23 14:08 ` Harry Wentland
2017-05-23 14:08 ` [PATCH 13/31] drm/amd/display: make dc_get_validate_context re-entrant Harry Wentland
` (18 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:08 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Roman Li
From: Roman Li <Roman.Li@amd.com>
- fixing bug in calculation of reg offset for D5VGA_CONTROL
Change-Id: I0e08d59d03c8daaaf4848a71fac38c37eba492c5
Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index 245356e72b36..dc8eeac6ac96 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -410,7 +410,7 @@ void dce120_timing_generator_disable_vga(struct timing_generator *tg)
break;
case CONTROLLER_ID_D4:
addr = mmD1VGA_CONTROL;
- offset = mmD1VGA_CONTROL - mmD1VGA_CONTROL;
+ offset = mmD5VGA_CONTROL - mmD1VGA_CONTROL;
break;
case CONTROLLER_ID_D5:
addr = mmD6VGA_CONTROL;
--
2.11.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 13/31] drm/amd/display: make dc_get_validate_context re-entrant
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (11 preceding siblings ...)
2017-05-23 14:08 ` [PATCH 12/31] drm/amd/display: Fix 5th display lightup on Vega10 Harry Wentland
@ 2017-05-23 14:08 ` Harry Wentland
2017-05-23 14:08 ` [PATCH 14/31] drm/amd/display: revert dc_get_validate_context re-entrancy fix Harry Wentland
` (17 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:08 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Change-Id: Ie999d2dc977f0018ee289bfaee48e84d6135de2e
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 44 ++--------------------
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 30 +++++++--------
.../drm/amd/display/dc/dce100/dce100_resource.c | 22 ++++++-----
.../drm/amd/display/dc/dce110/dce110_resource.c | 22 ++++++-----
.../drm/amd/display/dc/dce112/dce112_resource.c | 27 +++++++------
.../drm/amd/display/dc/dce112/dce112_resource.h | 3 +-
.../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 22 ++++++-----
.../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 24 ++++++------
drivers/gpu/drm/amd/display/dc/inc/core_types.h | 3 +-
drivers/gpu/drm/amd/display/dc/inc/resource.h | 9 +++--
10 files changed, 92 insertions(+), 114 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index b5ba822df55e..0aafcc088284 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -653,40 +653,6 @@ void dc_destroy(struct dc **dc)
*dc = NULL;
}
-static bool is_validation_required(
- const struct core_dc *dc,
- const struct dc_validation_set set[],
- int set_count)
-{
- const struct validate_context *context = dc->current_context;
- int i, j;
-
- if (context->stream_count != set_count)
- return true;
-
- for (i = 0; i < set_count; i++) {
-
- if (set[i].surface_count != context->stream_status[i].surface_count)
- return true;
- if (!is_stream_unchanged(DC_STREAM_TO_CORE(set[i].stream), context->streams[i]))
- return true;
-
- for (j = 0; j < set[i].surface_count; j++) {
- struct dc_surface temp_surf = { 0 };
-
- temp_surf = *context->stream_status[i].surfaces[j];
- temp_surf.clip_rect = set[i].surfaces[j]->clip_rect;
- temp_surf.dst_rect.x = set[i].surfaces[j]->dst_rect.x;
- temp_surf.dst_rect.y = set[i].surfaces[j]->dst_rect.y;
-
- if (memcmp(&temp_surf, set[i].surfaces[j], sizeof(temp_surf)) != 0)
- return true;
- }
- }
-
- return false;
-}
-
struct validate_context *dc_get_validate_context(
const struct dc *dc,
const struct dc_validation_set set[],
@@ -700,13 +666,8 @@ struct validate_context *dc_get_validate_context(
if(context == NULL)
goto context_alloc_fail;
- if (!is_validation_required(core_dc, set, set_count)) {
- dc_resource_validate_ctx_copy_construct(core_dc->current_context, context);
- return context;
- }
-
result = core_dc->res_pool->funcs->validate_with_context(
- core_dc, set, set_count, context);
+ core_dc, set, set_count, context, NULL);
context_alloc_fail:
if (result != DC_OK) {
@@ -903,7 +864,8 @@ bool dc_commit_streams(
if (context == NULL)
goto context_alloc_fail;
- result = core_dc->res_pool->funcs->validate_with_context(core_dc, set, stream_count, context);
+ result = core_dc->res_pool->funcs->validate_with_context(
+ core_dc, set, stream_count, context, core_dc->current_context);
if (result != DC_OK){
dm_logger_write(core_dc->ctx->logger, LOG_ERROR,
"%s: Context validation failed! dc_status:%d\n",
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 7ca03d1ad163..ec5045734378 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1148,7 +1148,7 @@ bool resource_validate_attach_surfaces(
int i, j;
for (i = 0; i < set_count; i++) {
- for (j = 0; j < old_context->stream_count; j++)
+ for (j = 0; old_context && j < old_context->stream_count; j++)
if (is_stream_unchanged(
old_context->streams[j],
context->streams[i])) {
@@ -1387,9 +1387,7 @@ static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
return normalized_pix_clk;
}
-static void calculate_phy_pix_clks(
- const struct core_dc *dc,
- struct validate_context *context)
+static void calculate_phy_pix_clks(struct validate_context *context)
{
int i;
@@ -1410,21 +1408,22 @@ static void calculate_phy_pix_clks(
enum dc_status resource_map_pool_resources(
const struct core_dc *dc,
- struct validate_context *context)
+ struct validate_context *context,
+ struct validate_context *old_context)
{
const struct resource_pool *pool = dc->res_pool;
int i, j;
- calculate_phy_pix_clks(dc, context);
+ calculate_phy_pix_clks(context);
- for (i = 0; i < context->stream_count; i++) {
+ for (i = 0; old_context && i < context->stream_count; i++) {
struct core_stream *stream = context->streams[i];
- if (!resource_is_stream_unchanged(dc->current_context, stream)) {
- if (stream != NULL && dc->current_context->streams[i] != NULL) {
+ if (!resource_is_stream_unchanged(old_context, stream)) {
+ if (stream != NULL && old_context->streams[i] != NULL) {
stream->bit_depth_params =
- dc->current_context->streams[i]->bit_depth_params;
- stream->clamping = dc->current_context->streams[i]->clamping;
+ old_context->streams[i]->bit_depth_params;
+ stream->clamping = old_context->streams[i]->clamping;
continue;
}
}
@@ -1434,7 +1433,7 @@ enum dc_status resource_map_pool_resources(
struct pipe_ctx *pipe_ctx =
&context->res_ctx.pipe_ctx[j];
const struct pipe_ctx *old_pipe_ctx =
- &dc->current_context->res_ctx.pipe_ctx[j];
+ &old_context->res_ctx.pipe_ctx[j];
if (!are_stream_backends_same(old_pipe_ctx->stream, stream))
continue;
@@ -1475,7 +1474,7 @@ enum dc_status resource_map_pool_resources(
struct pipe_ctx *pipe_ctx = NULL;
int pipe_idx = -1;
- if (resource_is_stream_unchanged(dc->current_context, stream))
+ if (old_context && resource_is_stream_unchanged(old_context, stream))
continue;
/* acquire new resources */
pipe_idx = acquire_first_free_pipe(
@@ -2203,7 +2202,8 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
enum dc_status resource_map_clock_resources(
const struct core_dc *dc,
- struct validate_context *context)
+ struct validate_context *context,
+ struct validate_context *old_context)
{
int i, j;
const struct resource_pool *pool = dc->res_pool;
@@ -2212,7 +2212,7 @@ enum dc_status resource_map_clock_resources(
for (i = 0; i < context->stream_count; i++) {
const struct core_stream *stream = context->streams[i];
- if (resource_is_stream_unchanged(dc->current_context, stream))
+ if (old_context && resource_is_stream_unchanged(old_context, stream))
continue;
for (j = 0; j < MAX_PIPES; j++) {
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 8f1fe95dd76c..716f664f40ce 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -653,7 +653,8 @@ static void destruct(struct dce110_resource_pool *pool)
static enum dc_status validate_mapped_resource(
const struct core_dc *dc,
- struct validate_context *context)
+ struct validate_context *context,
+ struct validate_context *old_context)
{
enum dc_status status = DC_OK;
uint8_t i, j;
@@ -662,7 +663,7 @@ static enum dc_status validate_mapped_resource(
struct core_stream *stream = context->streams[i];
struct core_link *link = stream->sink->link;
- if (resource_is_stream_unchanged(dc->current_context, stream))
+ if (old_context && resource_is_stream_unchanged(old_context, stream))
continue;
for (j = 0; j < MAX_PIPES; j++) {
@@ -740,7 +741,8 @@ enum dc_status dce100_validate_with_context(
const struct core_dc *dc,
const struct dc_validation_set set[],
int set_count,
- struct validate_context *context)
+ struct validate_context *context,
+ struct validate_context *old_context)
{
struct dc_context *dc_ctx = dc->ctx;
enum dc_status result = DC_ERROR_UNEXPECTED;
@@ -755,19 +757,19 @@ enum dc_status dce100_validate_with_context(
context->stream_count++;
}
- result = resource_map_pool_resources(dc, context);
+ result = resource_map_pool_resources(dc, context, old_context);
if (result == DC_OK)
- result = resource_map_clock_resources(dc, context);
+ result = resource_map_clock_resources(dc, context, old_context);
if (!resource_validate_attach_surfaces(set, set_count,
- dc->current_context, context, dc->res_pool)) {
+ old_context, context, dc->res_pool)) {
DC_ERROR("Failed to attach surface to stream!\n");
return DC_FAIL_ATTACH_SURFACES;
}
if (result == DC_OK)
- result = validate_mapped_resource(dc, context);
+ result = validate_mapped_resource(dc, context, old_context);
if (result == DC_OK)
result = resource_build_scaling_params_for_context(dc, context);
@@ -790,13 +792,13 @@ enum dc_status dce100_validate_guaranteed(
dc_stream_retain(&context->streams[0]->public);
context->stream_count++;
- result = resource_map_pool_resources(dc, context);
+ result = resource_map_pool_resources(dc, context, NULL);
if (result == DC_OK)
- result = resource_map_clock_resources(dc, context);
+ result = resource_map_clock_resources(dc, context, NULL);
if (result == DC_OK)
- result = validate_mapped_resource(dc, context);
+ result = validate_mapped_resource(dc, context, NULL);
if (result == DC_OK) {
validate_guaranteed_copy_streams(
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index 3ed5b9445535..45759b9f15e5 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -769,7 +769,8 @@ static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigne
static enum dc_status validate_mapped_resource(
const struct core_dc *dc,
- struct validate_context *context)
+ struct validate_context *context,
+ struct validate_context *old_context)
{
enum dc_status status = DC_OK;
uint8_t i, j;
@@ -778,7 +779,7 @@ static enum dc_status validate_mapped_resource(
struct core_stream *stream = context->streams[i];
struct core_link *link = stream->sink->link;
- if (resource_is_stream_unchanged(dc->current_context, stream))
+ if (old_context && resource_is_stream_unchanged(old_context, stream))
continue;
for (j = 0; j < MAX_PIPES; j++) {
@@ -943,7 +944,8 @@ enum dc_status dce110_validate_with_context(
const struct core_dc *dc,
const struct dc_validation_set set[],
int set_count,
- struct validate_context *context)
+ struct validate_context *context,
+ struct validate_context *old_context)
{
struct dc_context *dc_ctx = dc->ctx;
enum dc_status result = DC_ERROR_UNEXPECTED;
@@ -958,19 +960,19 @@ enum dc_status dce110_validate_with_context(
context->stream_count++;
}
- result = resource_map_pool_resources(dc, context);
+ result = resource_map_pool_resources(dc, context, old_context);
if (result == DC_OK)
- result = resource_map_clock_resources(dc, context);
+ result = resource_map_clock_resources(dc, context, old_context);
if (!resource_validate_attach_surfaces(set, set_count,
- dc->current_context, context, dc->res_pool)) {
+ old_context, context, dc->res_pool)) {
DC_ERROR("Failed to attach surface to stream!\n");
return DC_FAIL_ATTACH_SURFACES;
}
if (result == DC_OK)
- result = validate_mapped_resource(dc, context);
+ result = validate_mapped_resource(dc, context, old_context);
if (result == DC_OK)
result = resource_build_scaling_params_for_context(dc, context);
@@ -993,13 +995,13 @@ enum dc_status dce110_validate_guaranteed(
dc_stream_retain(&context->streams[0]->public);
context->stream_count++;
- result = resource_map_pool_resources(dc, context);
+ result = resource_map_pool_resources(dc, context, NULL);
if (result == DC_OK)
- result = resource_map_clock_resources(dc, context);
+ result = resource_map_clock_resources(dc, context, NULL);
if (result == DC_OK)
- result = validate_mapped_resource(dc, context);
+ result = validate_mapped_resource(dc, context, NULL);
if (result == DC_OK) {
validate_guaranteed_copy_streams(
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index f405d6eecaa5..80f067343a91 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -722,7 +722,8 @@ static struct clock_source *find_matching_pll(
static enum dc_status validate_mapped_resource(
const struct core_dc *dc,
- struct validate_context *context)
+ struct validate_context *context,
+ struct validate_context *old_context)
{
enum dc_status status = DC_OK;
uint8_t i, j;
@@ -731,7 +732,7 @@ static enum dc_status validate_mapped_resource(
struct core_stream *stream = context->streams[i];
struct core_link *link = stream->sink->link;
- if (resource_is_stream_unchanged(dc->current_context, stream))
+ if (old_context && resource_is_stream_unchanged(old_context, stream))
continue;
for (j = 0; j < MAX_PIPES; j++) {
@@ -854,7 +855,8 @@ bool dce112_validate_bandwidth(
enum dc_status resource_map_phy_clock_resources(
const struct core_dc *dc,
- struct validate_context *context)
+ struct validate_context *context,
+ struct validate_context *old_context)
{
uint8_t i, j;
@@ -862,7 +864,7 @@ enum dc_status resource_map_phy_clock_resources(
for (i = 0; i < context->stream_count; i++) {
struct core_stream *stream = context->streams[i];
- if (resource_is_stream_unchanged(dc->current_context, stream))
+ if (old_context && resource_is_stream_unchanged(old_context, stream))
continue;
for (j = 0; j < MAX_PIPES; j++) {
@@ -922,7 +924,8 @@ enum dc_status dce112_validate_with_context(
const struct core_dc *dc,
const struct dc_validation_set set[],
int set_count,
- struct validate_context *context)
+ struct validate_context *context,
+ struct validate_context *old_context)
{
struct dc_context *dc_ctx = dc->ctx;
enum dc_status result = DC_ERROR_UNEXPECTED;
@@ -937,19 +940,19 @@ enum dc_status dce112_validate_with_context(
context->stream_count++;
}
- result = resource_map_pool_resources(dc, context);
+ result = resource_map_pool_resources(dc, context, old_context);
if (result == DC_OK)
- result = resource_map_phy_clock_resources(dc, context);
+ result = resource_map_phy_clock_resources(dc, context, old_context);
if (!resource_validate_attach_surfaces(set, set_count,
- dc->current_context, context, dc->res_pool)) {
+ old_context, context, dc->res_pool)) {
DC_ERROR("Failed to attach surface to stream!\n");
return DC_FAIL_ATTACH_SURFACES;
}
if (result == DC_OK)
- result = validate_mapped_resource(dc, context);
+ result = validate_mapped_resource(dc, context, old_context);
if (result == DC_OK)
result = resource_build_scaling_params_for_context(dc, context);
@@ -972,13 +975,13 @@ enum dc_status dce112_validate_guaranteed(
dc_stream_retain(&context->streams[0]->public);
context->stream_count++;
- result = resource_map_pool_resources(dc, context);
+ result = resource_map_pool_resources(dc, context, NULL);
if (result == DC_OK)
- result = resource_map_phy_clock_resources(dc, context);
+ result = resource_map_phy_clock_resources(dc, context, NULL);
if (result == DC_OK)
- result = validate_mapped_resource(dc, context);
+ result = validate_mapped_resource(dc, context, NULL);
if (result == DC_OK) {
validate_guaranteed_copy_streams(
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h
index dc842aace766..c6c0bbac5335 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h
@@ -39,7 +39,8 @@ enum dc_status dce112_validate_with_context(
const struct core_dc *dc,
const struct dc_validation_set set[],
int set_count,
- struct validate_context *context);
+ struct validate_context *context,
+ struct validate_context *old_context);
enum dc_status dce112_validate_guaranteed(
const struct core_dc *dc,
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index 095e437ce112..5861b3fdf7d2 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -669,7 +669,8 @@ static void destruct(struct dce110_resource_pool *pool)
static enum dc_status validate_mapped_resource(
const struct core_dc *dc,
- struct validate_context *context)
+ struct validate_context *context,
+ struct validate_context *old_context)
{
enum dc_status status = DC_OK;
uint8_t i, j;
@@ -678,7 +679,7 @@ static enum dc_status validate_mapped_resource(
struct core_stream *stream = context->streams[i];
struct core_link *link = stream->sink->link;
- if (resource_is_stream_unchanged(dc->current_context, stream))
+ if (old_context && resource_is_stream_unchanged(old_context, stream))
continue;
for (j = 0; j < MAX_PIPES; j++) {
@@ -757,7 +758,8 @@ enum dc_status dce80_validate_with_context(
const struct core_dc *dc,
const struct dc_validation_set set[],
int set_count,
- struct validate_context *context)
+ struct validate_context *context,
+ struct validate_context *old_context)
{
struct dc_context *dc_ctx = dc->ctx;
enum dc_status result = DC_ERROR_UNEXPECTED;
@@ -772,19 +774,19 @@ enum dc_status dce80_validate_with_context(
context->stream_count++;
}
- result = resource_map_pool_resources(dc, context);
+ result = resource_map_pool_resources(dc, context, old_context);
if (result == DC_OK)
- result = resource_map_clock_resources(dc, context);
+ result = resource_map_clock_resources(dc, context, old_context);
if (!resource_validate_attach_surfaces(set, set_count,
- dc->current_context, context, dc->res_pool)) {
+ old_context, context, dc->res_pool)) {
DC_ERROR("Failed to attach surface to stream!\n");
return DC_FAIL_ATTACH_SURFACES;
}
if (result == DC_OK)
- result = validate_mapped_resource(dc, context);
+ result = validate_mapped_resource(dc, context, old_context);
if (result == DC_OK)
result = resource_build_scaling_params_for_context(dc, context);
@@ -806,13 +808,13 @@ enum dc_status dce80_validate_guaranteed(
dc_stream_retain(&context->streams[0]->public);
context->stream_count++;
- result = resource_map_pool_resources(dc, context);
+ result = resource_map_pool_resources(dc, context, NULL);
if (result == DC_OK)
- result = resource_map_clock_resources(dc, context);
+ result = resource_map_clock_resources(dc, context, NULL);
if (result == DC_OK)
- result = validate_mapped_resource(dc, context);
+ result = validate_mapped_resource(dc, context, NULL);
if (result == DC_OK) {
validate_guaranteed_copy_streams(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 7fdc5860857b..94cd7a9b0b19 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -853,7 +853,8 @@ static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
static enum dc_status validate_mapped_resource(
const struct core_dc *dc,
- struct validate_context *context)
+ struct validate_context *context,
+ struct validate_context *old_context)
{
enum dc_status status = DC_OK;
uint8_t i, j;
@@ -862,8 +863,8 @@ static enum dc_status validate_mapped_resource(
struct core_stream *stream = context->streams[i];
struct core_link *link = stream->sink->link;
- if (resource_is_stream_unchanged(dc->current_context, stream)) {
- if (stream != NULL && dc->current_context->streams[i] != NULL) {
+ if (old_context && resource_is_stream_unchanged(old_context, stream)) {
+ if (stream != NULL && old_context->streams[i] != NULL) {
/* todo: shouldn't have to copy missing parameter here */
resource_build_bit_depth_reduction_params(stream,
&stream->bit_depth_params);
@@ -920,7 +921,8 @@ enum dc_status dcn10_validate_with_context(
const struct core_dc *dc,
const struct dc_validation_set set[],
int set_count,
- struct validate_context *context)
+ struct validate_context *context,
+ struct validate_context *old_context)
{
enum dc_status result = DC_OK;
int i;
@@ -934,20 +936,20 @@ enum dc_status dcn10_validate_with_context(
context->stream_count++;
}
- result = resource_map_pool_resources(dc, context);
+ result = resource_map_pool_resources(dc, context, old_context);
if (result != DC_OK)
return result;
- result = resource_map_phy_clock_resources(dc, context);
+ result = resource_map_phy_clock_resources(dc, context, old_context);
if (result != DC_OK)
return result;
- result = validate_mapped_resource(dc, context);
+ result = validate_mapped_resource(dc, context, old_context);
if (result != DC_OK)
return result;
if (!resource_validate_attach_surfaces(set, set_count,
- dc->current_context, context, dc->res_pool))
+ old_context, context, dc->res_pool))
return DC_FAIL_ATTACH_SURFACES;
result = resource_build_scaling_params_for_context(dc, context);
@@ -971,13 +973,13 @@ enum dc_status dcn10_validate_guaranteed(
dc_stream_retain(&context->streams[0]->public);
context->stream_count++;
- result = resource_map_pool_resources(dc, context);
+ result = resource_map_pool_resources(dc, context, NULL);
if (result == DC_OK)
- result = resource_map_phy_clock_resources(dc, context);
+ result = resource_map_phy_clock_resources(dc, context, NULL);
if (result == DC_OK)
- result = validate_mapped_resource(dc, context);
+ result = validate_mapped_resource(dc, context, NULL);
if (result == DC_OK) {
validate_guaranteed_copy_streams(
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 46bd0318e6be..d8a378dabb43 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -203,7 +203,8 @@ struct resource_funcs {
const struct core_dc *dc,
const struct dc_validation_set set[],
int set_count,
- struct validate_context *context);
+ struct validate_context *context,
+ struct validate_context *old_context);
enum dc_status (*validate_guaranteed)(
const struct core_dc *dc,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h
index 4e07b9fea669..7cac24d4ae86 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
@@ -80,7 +80,8 @@ void dc_destroy_resource_pool(struct core_dc *dc);
enum dc_status resource_map_pool_resources(
const struct core_dc *dc,
- struct validate_context *context);
+ struct validate_context *context,
+ struct validate_context *old_context);
bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx);
@@ -150,11 +151,13 @@ void resource_validate_ctx_update_pointer_after_copy(
enum dc_status resource_map_clock_resources(
const struct core_dc *dc,
- struct validate_context *context);
+ struct validate_context *context,
+ struct validate_context *old_context);
enum dc_status resource_map_phy_clock_resources(
const struct core_dc *dc,
- struct validate_context *context);
+ struct validate_context *context,
+ struct validate_context *old_context);
bool pipe_need_reprogram(
struct pipe_ctx *pipe_ctx_old,
--
2.11.0
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 14/31] drm/amd/display: revert dc_get_validate_context re-entrancy fix
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (12 preceding siblings ...)
2017-05-23 14:08 ` [PATCH 13/31] drm/amd/display: make dc_get_validate_context re-entrant Harry Wentland
@ 2017-05-23 14:08 ` Harry Wentland
2017-05-23 14:08 ` [PATCH 15/31] drm/amd/display: Refactor use_lut() from dce110 to dce Harry Wentland
` (16 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:08 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Apply dc_get_validate_context re-entrancy fix to dc_validate_resources instead
Change-Id: I8502010ff24f6b3b4ea932e1042fdca1a02a5a0c
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 71 ++++++++++++++++++++++++++++----
1 file changed, 62 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 0aafcc088284..773f0efc449b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -653,6 +653,40 @@ void dc_destroy(struct dc **dc)
*dc = NULL;
}
+static bool is_validation_required(
+ const struct core_dc *dc,
+ const struct dc_validation_set set[],
+ int set_count)
+{
+ const struct validate_context *context = dc->current_context;
+ int i, j;
+
+ if (context->stream_count != set_count)
+ return true;
+
+ for (i = 0; i < set_count; i++) {
+
+ if (set[i].surface_count != context->stream_status[i].surface_count)
+ return true;
+ if (!is_stream_unchanged(DC_STREAM_TO_CORE(set[i].stream), context->streams[i]))
+ return true;
+
+ for (j = 0; j < set[i].surface_count; j++) {
+ struct dc_surface temp_surf = { 0 };
+
+ temp_surf = *context->stream_status[i].surfaces[j];
+ temp_surf.clip_rect = set[i].surfaces[j]->clip_rect;
+ temp_surf.dst_rect.x = set[i].surfaces[j]->dst_rect.x;
+ temp_surf.dst_rect.y = set[i].surfaces[j]->dst_rect.y;
+
+ if (memcmp(&temp_surf, set[i].surfaces[j], sizeof(temp_surf)) != 0)
+ return true;
+ }
+ }
+
+ return false;
+}
+
struct validate_context *dc_get_validate_context(
const struct dc *dc,
const struct dc_validation_set set[],
@@ -663,11 +697,16 @@ struct validate_context *dc_get_validate_context(
struct validate_context *context;
context = dm_alloc(sizeof(struct validate_context));
- if(context == NULL)
+ if (context == NULL)
goto context_alloc_fail;
+ if (!is_validation_required(core_dc, set, set_count)) {
+ dc_resource_validate_ctx_copy_construct(core_dc->current_context, context);
+ return context;
+ }
+
result = core_dc->res_pool->funcs->validate_with_context(
- core_dc, set, set_count, context, NULL);
+ core_dc, set, set_count, context, core_dc->current_context);
context_alloc_fail:
if (result != DC_OK) {
@@ -690,16 +729,30 @@ bool dc_validate_resources(
const struct dc_validation_set set[],
uint8_t set_count)
{
- struct validate_context *ctx;
+ struct core_dc *core_dc = DC_TO_CORE(dc);
+ enum dc_status result = DC_ERROR_UNEXPECTED;
+ struct validate_context *context;
- ctx = dc_get_validate_context(dc, set, set_count);
- if (ctx) {
- dc_resource_validate_ctx_destruct(ctx);
- dm_free(ctx);
- return true;
+ context = dm_alloc(sizeof(struct validate_context));
+ if (context == NULL)
+ goto context_alloc_fail;
+
+ result = core_dc->res_pool->funcs->validate_with_context(
+ core_dc, set, set_count, context, NULL);
+
+context_alloc_fail:
+ if (result != DC_OK) {
+ dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
+ "%s:resource validation failed, dc_status:%d\n",
+ __func__,
+ result);
}
- return false;
+ dc_resource_validate_ctx_destruct(context);
+ dm_free(context);
+ context = NULL;
+
+ return result == DC_OK;
}
bool dc_validate_guaranteed(
--
2.11.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 15/31] drm/amd/display: Refactor use_lut() from dce110 to dce
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (13 preceding siblings ...)
2017-05-23 14:08 ` [PATCH 14/31] drm/amd/display: revert dc_get_validate_context re-entrancy fix Harry Wentland
@ 2017-05-23 14:08 ` Harry Wentland
2017-05-23 14:08 ` [PATCH 16/31] drm/amd/display: Implement input gamma LUT Harry Wentland
` (15 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:08 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Leo (Sunpeng) Li
From: "Leo (Sunpeng) Li" <sunpeng.li@amd.com>
use_lut() checks if the input surface's pixel format is compatible with
a 256 entry LUT. This function can be used across different versions and
not just dce11.
Change-Id: Ia2813007c91f39939e0ceef65e2f68af0a5e235c
Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | 12 ++++++++++++
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 2 ++
.../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 17 ++---------------
3 files changed, 16 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
index 34c18712970c..cc3178acfc54 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
@@ -191,3 +191,15 @@ void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,
clk_src->id, tg_inst);
}
}
+
+/* Only use LUT for 8 bit formats */
+bool dce_use_lut(const struct core_surface *surface)
+{
+ switch (surface->public.format) {
+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
+ return true;
+ default:
+ return false;
+ }
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index dd13f47b6446..112f9c85c142 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -256,4 +256,6 @@ void dce_clock_gating_power_up(struct dce_hwseq *hws,
void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,
struct clock_source *clk_src,
unsigned int tg_inst);
+
+bool dce_use_lut(const struct core_surface *surface);
#endif /*__DCE_HWSEQ_H__*/
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 20ad1cb263db..65c691569eb7 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -28,10 +28,10 @@
#include "core_types.h"
#include "core_status.h"
#include "resource.h"
-#include "hw_sequencer.h"
#include "dm_helpers.h"
#include "dce110_hw_sequencer.h"
#include "dce110_timing_generator.h"
+#include "dce/dce_hwseq.h"
#include "bios/bios_parser_helper.h"
#include "timing_generator.h"
@@ -233,19 +233,6 @@ static void build_prescale_params(struct ipp_prescale_params *prescale_params,
}
}
-
-/* Only use LUT for 8 bit formats */
-static bool use_lut(const struct core_surface *surface)
-{
- switch (surface->public.format) {
- case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
- case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
- return true;
- default:
- return false;
- }
-}
-
static bool dce110_set_input_transfer_func(
struct pipe_ctx *pipe_ctx,
const struct core_surface *surface)
@@ -264,7 +251,7 @@ static bool dce110_set_input_transfer_func(
build_prescale_params(&prescale_params, surface);
ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
- if (surface->public.gamma_correction && use_lut(surface))
+ if (surface->public.gamma_correction && dce_use_lut(surface))
ipp->funcs->ipp_program_input_lut(ipp, surface->public.gamma_correction);
if (tf == NULL) {
--
2.11.0
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 16/31] drm/amd/display: Implement input gamma LUT
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (14 preceding siblings ...)
2017-05-23 14:08 ` [PATCH 15/31] drm/amd/display: Refactor use_lut() from dce110 to dce Harry Wentland
@ 2017-05-23 14:08 ` Harry Wentland
2017-05-23 14:08 ` [PATCH 17/31] drm/amd/display: Add missed wait_for_prev_commits Harry Wentland
` (14 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:08 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Leo (Sunpeng) Li
From: "Leo (Sunpeng) Li" <sunpeng.li@amd.com>
1. Implemented dcn10_ipp_program_input_lut(), following the existing
interface.
2. Added missing registers as needed
3. Change to REG_GET for *ram_select() funcs.
4. Removed gamma table init from DiagsDM::make_surface() for resolving
CRC errors. Reason: Legacy LUT will be deprecated soon for Raven in
favor of degamma/regamma.
Change-Id: I4c25bd0b70603d5aeae5b171b83e739e4b1382c5
Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 6 +-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | 82 +++++++++++++++++++++-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h | 22 ++++++
3 files changed, 108 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 28b47bed72cf..62a77f48d437 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -29,9 +29,9 @@
#include "core_types.h"
#include "core_status.h"
#include "resource.h"
-#include "hw_sequencer.h"
#include "dcn10_hw_sequencer.h"
#include "dce110/dce110_hw_sequencer.h"
+#include "dce/dce_hwseq.h"
#include "abm.h"
#include "dcn10/dcn10_transform.h"
@@ -952,6 +952,10 @@ static bool dcn10_set_input_transfer_func(
if (surface->public.in_transfer_func)
tf = DC_TRANSFER_FUNC_TO_CORE(surface->public.in_transfer_func);
+ if (surface->public.gamma_correction && dce_use_lut(surface))
+ ipp->funcs->ipp_program_input_lut(ipp,
+ surface->public.gamma_correction);
+
if (tf == NULL)
ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
else if (tf->public.type == TF_TYPE_PREDEFINED) {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
index 082c98c11293..1e7a55d9e9ec 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
@@ -814,7 +814,9 @@ static bool dcn10_degamma_ram_inuse(struct input_pixel_processor *ipp,
uint32_t status_reg = 0;
struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
- status_reg = (REG_READ(CM_IGAM_LUT_RW_CONTROL) & 0x0F00) >>16;
+ REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS,
+ &status_reg);
+
if (status_reg == 9) {
*ram_a_inuse = true;
ret = true;
@@ -825,6 +827,28 @@ static bool dcn10_degamma_ram_inuse(struct input_pixel_processor *ipp,
return ret;
}
+static bool dcn10_ingamma_ram_inuse(struct input_pixel_processor *ipp,
+ bool *ram_a_inuse)
+{
+ bool in_use = false;
+ uint32_t status_reg = 0;
+ struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
+
+ REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS,
+ &status_reg);
+
+ // 1 => IGAM_RAMA, 3 => IGAM_RAMA & DGAM_ROMA, 4 => IGAM_RAMA & DGAM_ROMB
+ if (status_reg == 1 || status_reg == 3 || status_reg == 4) {
+ *ram_a_inuse = true;
+ in_use = true;
+ // 2 => IGAM_RAMB, 5 => IGAM_RAMB & DGAM_ROMA, 6 => IGAM_RAMB & DGAM_ROMB
+ } else if (status_reg == 2 || status_reg == 5 || status_reg == 6) {
+ *ram_a_inuse = false;
+ in_use = true;
+ }
+ return in_use;
+}
+
static void dcn10_degamma_ram_select(struct input_pixel_processor *ipp,
bool use_ram_a)
{
@@ -855,6 +879,61 @@ static void dcn10_ipp_set_degamma_pwl(struct input_pixel_processor *ipp,
dcn10_degamma_ram_select(ipp, !is_ram_a);
}
+/*
+ * Input gamma LUT currently supports 256 values only. This means input color
+ * can have a maximum of 8 bits per channel (= 256 possible values) in order to
+ * have a one-to-one mapping with the LUT. Truncation will occur with color
+ * values greater than 8 bits.
+ *
+ * In the future, this function should support additional input gamma methods,
+ * such as piecewise linear mapping, and input gamma bypass.
+ */
+void dcn10_ipp_program_input_lut(
+ struct input_pixel_processor *ipp,
+ const struct dc_gamma *gamma)
+{
+ int i;
+ struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
+ bool rama_occupied = false;
+ uint32_t ram_num;
+ // Power on LUT memory.
+ REG_SET(CM_MEM_PWR_CTRL, 0, SHARED_MEM_PWR_DIS, 1);
+ dcn10_ipp_enable_cm_block(ipp);
+ // Determine whether to use RAM A or RAM B
+ dcn10_ingamma_ram_inuse(ipp, &rama_occupied);
+ if (!rama_occupied)
+ REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, 0);
+ else
+ REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, 1);
+ // RW mode is 256-entry LUT
+ REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_RW_MODE, 0);
+ // IGAM Input format should be 8 bits per channel.
+ REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 0);
+ // Do not mask any R,G,B values
+ REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_WRITE_EN_MASK, 7);
+ // LUT-256, unsigned, integer, new u0.12 format
+ REG_UPDATE_3(
+ CM_IGAM_CONTROL,
+ CM_IGAM_LUT_FORMAT_R, 3,
+ CM_IGAM_LUT_FORMAT_G, 3,
+ CM_IGAM_LUT_FORMAT_B, 3);
+ // Start at index 0 of IGAM LUT
+ REG_UPDATE(CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, 0);
+ for (i = 0; i < INPUT_LUT_ENTRIES; i++) {
+ REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR,
+ gamma->red[i]);
+ REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR,
+ gamma->green[i]);
+ REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR,
+ gamma->blue[i]);
+ }
+ // Power off LUT memory
+ REG_SET(CM_MEM_PWR_CTRL, 0, SHARED_MEM_PWR_DIS, 0);
+ // Enable IGAM LUT on ram we just wrote to. 2 => RAMA, 3 => RAMB
+ REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, rama_occupied ? 3 : 2);
+ REG_GET(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, &ram_num);
+}
+
/*****************************************/
/* Constructor, Destructor */
/*****************************************/
@@ -869,6 +948,7 @@ static const struct ipp_funcs dcn10_ipp_funcs = {
.ipp_cursor_set_attributes = dcn10_cursor_set_attributes,
.ipp_cursor_set_position = dcn10_cursor_set_position,
.ipp_set_degamma = dcn10_ipp_set_degamma,
+ .ipp_program_input_lut = dcn10_ipp_program_input_lut,
.ipp_full_bypass = dcn10_ipp_full_bypass,
.ipp_setup = dcn10_ipp_cnv_setup,
.ipp_program_degamma_pwl = dcn10_ipp_set_degamma_pwl,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
index a4ea4e774c72..511993519740 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
@@ -87,6 +87,8 @@
SRI(CM_DGAM_RAMA_REGION_14_15, CM, id), \
SRI(CM_MEM_PWR_CTRL, CM, id), \
SRI(CM_IGAM_LUT_RW_CONTROL, CM, id), \
+ SRI(CM_IGAM_LUT_RW_INDEX, CM, id), \
+ SRI(CM_IGAM_LUT_SEQ_COLOR, CM, id), \
SRI(CM_DGAM_LUT_WRITE_EN_MASK, CM, id), \
SRI(CM_DGAM_LUT_INDEX, CM, id), \
SRI(CM_DGAM_LUT_DATA, CM, id), \
@@ -238,7 +240,13 @@
IPP_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, mask_sh), \
+ IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, mask_sh), \
IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, mask_sh), \
+ IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_RW_MODE, mask_sh), \
+ IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, mask_sh), \
+ IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_WRITE_EN_MASK, mask_sh), \
+ IPP_SF(CM0_CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, mask_sh), \
+ IPP_SF(CM0_CM_IGAM_LUT_SEQ_COLOR, CM_IGAM_LUT_SEQ_COLOR, mask_sh), \
IPP_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_EN_MASK, mask_sh), \
IPP_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL, mask_sh), \
IPP_SF(CM0_CM_DGAM_LUT_INDEX, CM_DGAM_LUT_INDEX, mask_sh), \
@@ -251,6 +259,9 @@
IPP_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \
IPP_SF(CM0_CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, mask_sh), \
IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, mask_sh), \
+ IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_R, mask_sh), \
+ IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_G, mask_sh), \
+ IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_B, mask_sh), \
IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \
IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \
@@ -404,7 +415,16 @@
type CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET; \
type CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS; \
type SHARED_MEM_PWR_DIS; \
+ type CM_IGAM_LUT_FORMAT_R; \
+ type CM_IGAM_LUT_FORMAT_G; \
+ type CM_IGAM_LUT_FORMAT_B; \
type CM_IGAM_LUT_HOST_EN; \
+ type CM_IGAM_LUT_RW_INDEX; \
+ type CM_IGAM_LUT_RW_MODE; \
+ type CM_IGAM_LUT_WRITE_EN_MASK; \
+ type CM_IGAM_LUT_SEL; \
+ type CM_IGAM_LUT_SEQ_COLOR; \
+ type CM_IGAM_DGAM_CONFIG_STATUS; \
type CM_DGAM_LUT_WRITE_EN_MASK; \
type CM_DGAM_LUT_WRITE_SEL; \
type CM_DGAM_LUT_INDEX; \
@@ -507,6 +527,8 @@ struct dcn10_ipp_registers {
uint32_t CM_DGAM_RAMA_REGION_14_15;
uint32_t CM_MEM_PWR_CTRL;
uint32_t CM_IGAM_LUT_RW_CONTROL;
+ uint32_t CM_IGAM_LUT_RW_INDEX;
+ uint32_t CM_IGAM_LUT_SEQ_COLOR;
uint32_t CM_DGAM_LUT_WRITE_EN_MASK;
uint32_t CM_DGAM_LUT_INDEX;
uint32_t CM_DGAM_LUT_DATA;
--
2.11.0
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^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 17/31] drm/amd/display: Add missed wait_for_prev_commits.
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (15 preceding siblings ...)
2017-05-23 14:08 ` [PATCH 16/31] drm/amd/display: Implement input gamma LUT Harry Wentland
@ 2017-05-23 14:08 ` Harry Wentland
2017-05-23 14:08 ` [PATCH 18/31] drm/amd/display: Fix ASSR enablement on DP to EDP converter Harry Wentland
` (13 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:08 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Andrey Grodzovsky
From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Change-Id: Ie5f33497e8ab22da8ae3549028023e0e5837867f
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 6d8a1277d59e..ab6a969743a0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -3292,6 +3292,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
surface);
need_to_validate = true;
+ wait_for_prev_commits = true;
}
}
}
--
2.11.0
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^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 18/31] drm/amd/display: Fix ASSR enablement on DP to EDP converter
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (16 preceding siblings ...)
2017-05-23 14:08 ` [PATCH 17/31] drm/amd/display: Add missed wait_for_prev_commits Harry Wentland
@ 2017-05-23 14:08 ` Harry Wentland
2017-05-23 14:08 ` [PATCH 19/31] drm/amd/display: Tidy up dce120_timing_generator_enable_advanced_request() Harry Wentland
` (12 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:08 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ayyappa Chandolu
From: Ayyappa Chandolu <Ayyappa.Chandolu@amd.com>
ASSR mode is not enable when we connect eDP panel via DP to eDP converter.
connector_signal is coming as SIGNAL_TYPE_DISPLAY_PORT. Present code
ignoring panel_mode_edp for SIGNAL_TYPE_DISPLAY_PORT. Added checking
panel_mode_edp for all signals.
Change-Id: I2dbfe6aea7ad6035f59760f9e1244d54532de71b
Signed-off-by: Ayyappa Chandolu <Ayyappa.Chandolu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 316df150c1d9..4f46ff14fb69 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -203,10 +203,10 @@ enum dp_panel_mode dp_get_panel_mode(struct core_link *link)
default:
break;
}
+ }
- if (link->dpcd_caps.panel_mode_edp) {
- return DP_PANEL_MODE_EDP;
- }
+ if (link->dpcd_caps.panel_mode_edp) {
+ return DP_PANEL_MODE_EDP;
}
return DP_PANEL_MODE_DEFAULT;
--
2.11.0
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^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 19/31] drm/amd/display: Tidy up dce120_timing_generator_enable_advanced_request()
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (17 preceding siblings ...)
2017-05-23 14:08 ` [PATCH 18/31] drm/amd/display: Fix ASSR enablement on DP to EDP converter Harry Wentland
@ 2017-05-23 14:08 ` Harry Wentland
2017-05-23 14:08 ` [PATCH 20/31] drm/amd/display: Fix indentation in dce120_tg_program_timing() Harry Wentland
` (11 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:08 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tom St Denis
From: Tom St Denis <tom.stdenis@amd.com>
Simplify the function by removing identical looking code blocks.
Change-Id: Ibaad41529f5657189599328493d12d951de1e304
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
.../display/dc/dce120/dce120_timing_generator.c | 37 +++++++---------------
1 file changed, 12 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index dc8eeac6ac96..13cc0d49e007 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -669,36 +669,23 @@ void dce120_timing_generator_enable_advanced_request(
mmCRTC0_CRTC_START_LINE_CONTROL,
tg110->offsets.crtc);
-
- if (enable) {
- set_reg_field_value(
- value,
- 0,
- CRTC0_CRTC_START_LINE_CONTROL,
- CRTC_LEGACY_REQUESTOR_EN);
- } else {
- set_reg_field_value(
- value,
- 1,
- CRTC0_CRTC_START_LINE_CONTROL,
- CRTC_LEGACY_REQUESTOR_EN);
- }
+ set_reg_field_value(
+ value,
+ enable ? 0 : 1,
+ CRTC0_CRTC_START_LINE_CONTROL,
+ CRTC_LEGACY_REQUESTOR_EN);
/* Program advanced line position acc.to the best case from fetching data perspective to hide MC latency
* and prefilling Line Buffer in V Blank (to 10 lines as LB can store max 10 lines)
*/
if (v_sync_width_and_b_porch > 10)
- set_reg_field_value(
- value,
- 10,
- CRTC0_CRTC_START_LINE_CONTROL,
- CRTC_ADVANCED_START_LINE_POSITION);
- else
- set_reg_field_value(
- value,
- v_sync_width_and_b_porch,
- CRTC0_CRTC_START_LINE_CONTROL,
- CRTC_ADVANCED_START_LINE_POSITION);
+ v_sync_width_and_b_porch = 10;
+
+ set_reg_field_value(
+ value,
+ v_sync_width_and_b_porch,
+ CRTC0_CRTC_START_LINE_CONTROL,
+ CRTC_ADVANCED_START_LINE_POSITION);
dm_write_reg_soc15(tg->ctx,
mmCRTC0_CRTC_START_LINE_CONTROL,
--
2.11.0
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 20/31] drm/amd/display: Fix indentation in dce120_tg_program_timing()
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (18 preceding siblings ...)
2017-05-23 14:08 ` [PATCH 19/31] drm/amd/display: Tidy up dce120_timing_generator_enable_advanced_request() Harry Wentland
@ 2017-05-23 14:08 ` Harry Wentland
2017-05-23 14:08 ` [PATCH 21/31] drm/amd/display: Make dce120_tg_is_blanked() more legible Harry Wentland
` (10 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:08 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tom St Denis
From: Tom St Denis <tom.stdenis@amd.com>
Change-Id: I8f7cb2a366d112414fe4058affe36b14b38e7105
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index 13cc0d49e007..1c25dc66ff4f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -733,9 +733,9 @@ void dce120_tg_program_timing(struct timing_generator *tg,
bool use_vbios)
{
if (use_vbios)
- dce110_timing_generator_program_timing_generator(tg, timing);
- else
- dce120_timing_generator_program_blanking(tg, timing);
+ dce110_timing_generator_program_timing_generator(tg, timing);
+ else
+ dce120_timing_generator_program_blanking(tg, timing);
}
bool dce120_tg_is_blanked(struct timing_generator *tg)
--
2.11.0
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^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 21/31] drm/amd/display: Make dce120_tg_is_blanked() more legible
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (19 preceding siblings ...)
2017-05-23 14:08 ` [PATCH 20/31] drm/amd/display: Fix indentation in dce120_tg_program_timing() Harry Wentland
@ 2017-05-23 14:08 ` Harry Wentland
2017-05-23 14:09 ` [PATCH 22/31] drm/amd/display: Clean up indentation in dce120_tg_set_blank() Harry Wentland
` (9 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:08 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tom St Denis
From: Tom St Denis <tom.stdenis@amd.com>
Change-Id: I0a0cb44a5224a74dd4f0a819c3e8c38c2afca8a1
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
.../drm/amd/display/dc/dce120/dce120_timing_generator.c | 17 ++++++++---------
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index 1c25dc66ff4f..1e2843e5d97e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -746,15 +746,14 @@ bool dce120_tg_is_blanked(struct timing_generator *tg)
mmCRTC0_CRTC_BLANK_CONTROL,
tg110->offsets.crtc);
- if (
- get_reg_field_value(
- value,
- CRTC0_CRTC_BLANK_CONTROL,
- CRTC_BLANK_DATA_EN) == 1 &&
- get_reg_field_value(
- value,
- CRTC0_CRTC_BLANK_CONTROL,
- CRTC_CURRENT_BLANK_STATE) == 1)
+ if (get_reg_field_value(
+ value,
+ CRTC0_CRTC_BLANK_CONTROL,
+ CRTC_BLANK_DATA_EN) == 1 &&
+ get_reg_field_value(
+ value,
+ CRTC0_CRTC_BLANK_CONTROL,
+ CRTC_CURRENT_BLANK_STATE) == 1)
return true;
return false;
--
2.11.0
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^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 22/31] drm/amd/display: Clean up indentation in dce120_tg_set_blank()
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (20 preceding siblings ...)
2017-05-23 14:08 ` [PATCH 21/31] drm/amd/display: Make dce120_tg_is_blanked() more legible Harry Wentland
@ 2017-05-23 14:09 ` Harry Wentland
2017-05-23 14:09 ` [PATCH 23/31] drm/amd/display: Tidy up dce120_clock_source_create() Harry Wentland
` (8 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:09 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tom St Denis
From: Tom St Denis <tom.stdenis@amd.com>
Change-Id: Ib2f7b1a4c55033028b88351e8d278cfb77b71c4d
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
.../drm/amd/display/dc/dce120/dce120_timing_generator.c | 16 +++++-----------
1 file changed, 5 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index 1e2843e5d97e..c208196864ad 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -768,17 +768,11 @@ void dce120_tg_set_blank(struct timing_generator *tg,
CRTC0_CRTC_DOUBLE_BUFFER_CONTROL,
CRTC_BLANK_DATA_DOUBLE_BUFFER_EN, 0);
- if (enable_blanking) {
- CRTC_REG_SET(
- CRTC0_CRTC_BLANK_CONTROL,
- CRTC_BLANK_DATA_EN, 1);
-
- } else
- dm_write_reg_soc15(
- tg->ctx,
- mmCRTC0_CRTC_BLANK_CONTROL,
- tg110->offsets.crtc,
- 0);
+ if (enable_blanking)
+ CRTC_REG_SET(CRTC0_CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
+ else
+ dm_write_reg_soc15(tg->ctx, mmCRTC0_CRTC_BLANK_CONTROL,
+ tg110->offsets.crtc, 0);
}
bool dce120_tg_validate_timing(struct timing_generator *tg,
--
2.11.0
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^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 23/31] drm/amd/display: Tidy up dce120_clock_source_create()
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (21 preceding siblings ...)
2017-05-23 14:09 ` [PATCH 22/31] drm/amd/display: Clean up indentation in dce120_tg_set_blank() Harry Wentland
@ 2017-05-23 14:09 ` Harry Wentland
2017-05-23 14:09 ` [PATCH 24/31] drm/amd/display: Tidy up mem_input_program_surface_flip_and_addr() Harry Wentland
` (7 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:09 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tom St Denis
From: Tom St Denis <tom.stdenis@amd.com>
Also change sizeof to be automatic based on type declaration.
Change-Id: I0353d84fdbc889ba0be162566e711a8a7fbc0256
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index 1276dabfb208..ec485353ea4f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -398,13 +398,13 @@ struct clock_source *dce120_clock_source_create(
bool dp_clk_src)
{
struct dce110_clk_src *clk_src =
- dm_alloc(sizeof(struct dce110_clk_src));
+ dm_alloc(sizeof(*clk_src));
if (!clk_src)
return NULL;
if (dce110_clk_src_construct(clk_src, ctx, bios, id,
- regs, &cs_shift, &cs_mask)) {
+ regs, &cs_shift, &cs_mask)) {
clk_src->base.dp_clk_src = dp_clk_src;
return &clk_src->base;
}
--
2.11.0
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 24/31] drm/amd/display: Tidy up mem_input_program_surface_flip_and_addr()
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (22 preceding siblings ...)
2017-05-23 14:09 ` [PATCH 23/31] drm/amd/display: Tidy up dce120_clock_source_create() Harry Wentland
@ 2017-05-23 14:09 ` Harry Wentland
2017-05-23 14:09 ` [PATCH 25/31] drm/amd/display: Query for update plane type Harry Wentland
` (6 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:09 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tom St Denis
From: Tom St Denis <tom.stdenis@amd.com>
Change-Id: I0f893a9abad76da9b403da6103b192af39174088
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 25 ++++++++--------------
1 file changed, 9 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
index 718688c41f7b..673371e5f9f0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
@@ -625,18 +625,12 @@ static bool dce_mi_program_surface_flip_and_addr(
* non-XDMA Mode: GRPH_SURFACE_UPDATE_IMMEDIATE_EN = 1
* XDMA Mode: GRPH_SURFACE_UPDATE_H_RETRACE_EN = 1
*/
- REG_UPDATE(GRPH_UPDATE,
- GRPH_UPDATE_LOCK, 1);
-
- if (flip_immediate) {
- REG_UPDATE_2(GRPH_FLIP_CONTROL,
- GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0,
- GRPH_SURFACE_UPDATE_H_RETRACE_EN, 1);
- } else {
- REG_UPDATE_2(GRPH_FLIP_CONTROL,
- GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0,
- GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
- }
+ REG_UPDATE(GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
+
+ REG_UPDATE_2(
+ GRPH_FLIP_CONTROL,
+ GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0,
+ GRPH_SURFACE_UPDATE_H_RETRACE_EN, flip_immediate ? 1 : 0);
switch (address->type) {
case PLN_ADDR_TYPE_GRAPHICS:
@@ -645,8 +639,8 @@ static bool dce_mi_program_surface_flip_and_addr(
program_pri_addr(dce_mi, address->grph.addr);
break;
case PLN_ADDR_TYPE_GRPH_STEREO:
- if (address->grph_stereo.left_addr.quad_part == 0
- || address->grph_stereo.right_addr.quad_part == 0)
+ if (address->grph_stereo.left_addr.quad_part == 0 ||
+ address->grph_stereo.right_addr.quad_part == 0)
break;
program_pri_addr(dce_mi, address->grph_stereo.left_addr);
program_sec_addr(dce_mi, address->grph_stereo.right_addr);
@@ -662,8 +656,7 @@ static bool dce_mi_program_surface_flip_and_addr(
if (flip_immediate)
mem_input->current_address = *address;
- REG_UPDATE(GRPH_UPDATE,
- GRPH_UPDATE_LOCK, 0);
+ REG_UPDATE(GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
return true;
}
--
2.11.0
_______________________________________________
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^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 25/31] drm/amd/display: Query for update plane type.
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (23 preceding siblings ...)
2017-05-23 14:09 ` [PATCH 24/31] drm/amd/display: Tidy up mem_input_program_surface_flip_and_addr() Harry Wentland
@ 2017-05-23 14:09 ` Harry Wentland
2017-05-23 14:09 ` [PATCH 26/31] drm/amd/display: Remove redundant condition Harry Wentland
` (5 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:09 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Andrey Grodzovsky
From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Use DC interface to query for plane update type
so in case of FULL update you flush any outstanding
commits.
Change-Id: If9104ba3072f115a2fe2fe1e86882b1a8b07bb5e
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 69 +++++++++++++++++++++-
1 file changed, 68 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index ab6a969743a0..74981c24d6a6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -3048,6 +3048,61 @@ static uint32_t remove_from_val_sets(
return set_count;
}
+
+static enum surface_update_type amdgpu_dm_check_surfaces_update_type(
+ struct dc *dc,
+ const struct dc_surface **new_surfaces,
+ uint8_t new_surface_count,
+ const struct dc_stream *dc_stream)
+{
+ struct dc_surface_update srf_updates[MAX_SURFACES];
+ struct dc_flip_addrs flip_addr[MAX_SURFACES];
+ struct dc_plane_info plane_info[MAX_SURFACES];
+ struct dc_scaling_info scaling_info[MAX_SURFACES];
+ int i;
+ const struct dc_stream_status *stream_status =
+ dc_stream_get_status(dc_stream);
+ enum surface_update_type update_type;
+
+ ASSERT(stream_status);
+
+
+ memset(srf_updates, 0, sizeof(srf_updates));
+ memset(flip_addr, 0, sizeof(flip_addr));
+ memset(plane_info, 0, sizeof(plane_info));
+ memset(scaling_info, 0, sizeof(scaling_info));
+
+ for (i = 0; i < new_surface_count; i++) {
+ srf_updates[i].surface = new_surfaces[i];
+ srf_updates[i].gamma =
+ (struct dc_gamma *)new_surfaces[i]->gamma_correction;
+ flip_addr[i].address = new_surfaces[i]->address;
+ flip_addr[i].flip_immediate = new_surfaces[i]->flip_immediate;
+ plane_info[i].color_space = new_surfaces[i]->color_space;
+ plane_info[i].format = new_surfaces[i]->format;
+ plane_info[i].plane_size = new_surfaces[i]->plane_size;
+ plane_info[i].rotation = new_surfaces[i]->rotation;
+ plane_info[i].horizontal_mirror = new_surfaces[i]->horizontal_mirror;
+ plane_info[i].stereo_format = new_surfaces[i]->stereo_format;
+ plane_info[i].tiling_info = new_surfaces[i]->tiling_info;
+ plane_info[i].visible = new_surfaces[i]->visible;
+ plane_info[i].dcc = new_surfaces[i]->dcc;
+ scaling_info[i].scaling_quality = new_surfaces[i]->scaling_quality;
+ scaling_info[i].src_rect = new_surfaces[i]->src_rect;
+ scaling_info[i].dst_rect = new_surfaces[i]->dst_rect;
+ scaling_info[i].clip_rect = new_surfaces[i]->clip_rect;
+
+ srf_updates[i].flip_addr = &flip_addr[i];
+ srf_updates[i].plane_info = &plane_info[i];
+ srf_updates[i].scaling_info = &scaling_info[i];
+ }
+
+ update_type = dc_check_update_surfaces_for_stream(
+ dc, srf_updates, new_surface_count, NULL, stream_status);
+
+ return update_type;
+}
+
int amdgpu_dm_atomic_check(struct drm_device *dev,
struct drm_atomic_state *state)
{
@@ -3292,13 +3347,25 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
surface);
need_to_validate = true;
- wait_for_prev_commits = true;
}
}
}
context = dc_get_validate_context(dc, set, set_count);
+ for (i = 0; i < set_count; i++) {
+ for (j = 0; j < set[i].surface_count; j++) {
+ if (amdgpu_dm_check_surfaces_update_type(
+ dc,
+ set[i].surfaces,
+ set[i].surface_count,
+ set[i].stream) > UPDATE_TYPE_MED) {
+ wait_for_prev_commits = true;
+ break;
+ }
+ }
+ }
+
if (need_to_validate == false || set_count == 0 || context) {
ret = 0;
--
2.11.0
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 26/31] drm/amd/display: Remove redundant condition.
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (24 preceding siblings ...)
2017-05-23 14:09 ` [PATCH 25/31] drm/amd/display: Query for update plane type Harry Wentland
@ 2017-05-23 14:09 ` Harry Wentland
2017-05-23 14:09 ` [PATCH 27/31] drm/amd/display: fix YUV surface address programming sequence Harry Wentland
` (4 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:09 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Andrey Grodzovsky
From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
You cannot have modeset and flip in the same call for
same CRTC, in such case it will be set mode and set plane,
not a flip.
Change-Id: If7e7ef4a62dfc1c62b2a3fef63a4a6316d0155d3
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Reviewed-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 8 +-------
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 74981c24d6a6..5d34ce6c7faf 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -3296,15 +3296,9 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
action = get_dm_commit_action(crtc->state);
- /* Surfaces are created under two scenarios:
- * 1. This commit is not a page flip.
- * 2. This commit is a page flip, and streams are created.
- */
crtc_state = drm_atomic_get_crtc_state(state, crtc);
pflip_needed = !state->allow_modeset;
- if (!pflip_needed ||
- action == DM_COMMIT_ACTION_DPMS_ON ||
- action == DM_COMMIT_ACTION_SET) {
+ if (!pflip_needed) {
struct dc_surface *surface;
list_for_each_entry(connector,
--
2.11.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 27/31] drm/amd/display: fix YUV surface address programming sequence
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (25 preceding siblings ...)
2017-05-23 14:09 ` [PATCH 26/31] drm/amd/display: Remove redundant condition Harry Wentland
@ 2017-05-23 14:09 ` Harry Wentland
2017-05-23 14:09 ` [PATCH 28/31] drm/amd/display: remove GRPH_SURFACE_UPDATE_IMMEDIATE_EN field programming Harry Wentland
` (3 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:09 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
need to program DCSURF_PRIMARY_SURFACE_ADDRESS last as HW automatically
latch rest of addr regs on write when SURFACE_UPDATE_LOCK is not used
Change-Id: I9284f3cebd02ed3c25c844bc14a95ecc45b1d123
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 42 +++++++++++-----------
1 file changed, 20 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
index 587ded13140b..a52c614ec5b4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
@@ -237,16 +237,23 @@ static bool mem_input_program_surface_flip_and_addr(
struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
/* program flip type */
-
REG_UPDATE(DCSURF_FLIP_CONTROL,
SURFACE_FLIP_TYPE, flip_immediate);
- /* REG_UPDATE(FLIP_CONTROL, SURFACE_UPDATE_LOCK, 1); */
-
-
- /* program high first and then the low addr, order matters! */
+ /* HW automatically latch rest of address register on write to
+ * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used
+ *
+ * program high first and then the low addr, order matters!
+ */
switch (address->type) {
case PLN_ADDR_TYPE_GRAPHICS:
+ /* DCN1.0 does not support const color
+ * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1
+ * base on address->grph.dcc_const_color
+ * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma
+ * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma
+ */
+
if (address->grph.addr.quad_part == 0)
break;
@@ -268,14 +275,6 @@ static bool mem_input_program_surface_flip_and_addr(
REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS,
PRIMARY_SURFACE_ADDRESS,
address->grph.addr.low_part);
-
-
- /* DCN1.0 does not support const color
- * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1
- * base on address->grph.dcc_const_color
- * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma
- * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma
- */
break;
case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
if (address->video_progressive.luma_addr.quad_part == 0
@@ -301,14 +300,6 @@ static bool mem_input_program_surface_flip_and_addr(
address->video_progressive.chroma_meta_addr.low_part);
}
- REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
- PRIMARY_SURFACE_ADDRESS_HIGH,
- address->video_progressive.luma_addr.high_part);
-
- REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS,
- PRIMARY_SURFACE_ADDRESS,
- address->video_progressive.luma_addr.low_part);
-
REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C,
PRIMARY_SURFACE_ADDRESS_HIGH_C,
address->video_progressive.chroma_addr.high_part);
@@ -317,6 +308,14 @@ static bool mem_input_program_surface_flip_and_addr(
PRIMARY_SURFACE_ADDRESS_C,
address->video_progressive.chroma_addr.low_part);
+ REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
+ PRIMARY_SURFACE_ADDRESS_HIGH,
+ address->video_progressive.luma_addr.high_part);
+
+ REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS,
+ PRIMARY_SURFACE_ADDRESS,
+ address->video_progressive.luma_addr.low_part);
+
break;
case PLN_ADDR_TYPE_GRPH_STEREO:
if (address->grph_stereo.left_addr.quad_part == 0)
@@ -365,7 +364,6 @@ static bool mem_input_program_surface_flip_and_addr(
BREAK_TO_DEBUGGER();
break;
}
- /* REG_UPDATE(FLIP_CONTROL, SURFACE_UPDATE_LOCK, 0); */
mem_input->request_address = *address;
--
2.11.0
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 28/31] drm/amd/display: remove GRPH_SURFACE_UPDATE_IMMEDIATE_EN field programming
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (26 preceding siblings ...)
2017-05-23 14:09 ` [PATCH 27/31] drm/amd/display: fix YUV surface address programming sequence Harry Wentland
@ 2017-05-23 14:09 ` Harry Wentland
2017-05-23 14:09 ` [PATCH 29/31] drm/amd/display: fix flip register write sequence Harry Wentland
` (2 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:09 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
This is causing asserts for dce 8 and 10 since they do not contain this
field. It is also unnecessary for later DCEs as it is left in it's
default state of 0
Change-Id: Icdc977f8f1990065d3762efda5dd85224d9c534b
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 7 +------
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 2 --
2 files changed, 1 insertion(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
index 673371e5f9f0..157f4e1680e3 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
@@ -621,15 +621,10 @@ static bool dce_mi_program_surface_flip_and_addr(
{
struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mem_input);
- /* TODO: Figure out if two modes are needed:
- * non-XDMA Mode: GRPH_SURFACE_UPDATE_IMMEDIATE_EN = 1
- * XDMA Mode: GRPH_SURFACE_UPDATE_H_RETRACE_EN = 1
- */
REG_UPDATE(GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
- REG_UPDATE_2(
+ REG_UPDATE(
GRPH_FLIP_CONTROL,
- GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0,
GRPH_SURFACE_UPDATE_H_RETRACE_EN, flip_immediate ? 1 : 0);
switch (address->type) {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
index 9d083cd79b4c..05d39c0cbe87 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
@@ -162,7 +162,6 @@ struct dce_mem_input_registers {
SFB(blk, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN, mask_sh)
#define MI_DCP_DCE11_MASK_SH_LIST(mask_sh, blk)\
- SFB(blk, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_IMMEDIATE_EN, mask_sh),\
SFB(blk, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, mask_sh)
#define MI_DCP_PTE_MASK_SH_LIST(mask_sh, blk)\
@@ -278,7 +277,6 @@ struct dce_mem_input_registers {
type GRPH_PRIMARY_SURFACE_ADDRESS_HIGH; \
type GRPH_PRIMARY_SURFACE_ADDRESS; \
type GRPH_SURFACE_UPDATE_PENDING; \
- type GRPH_SURFACE_UPDATE_IMMEDIATE_EN; \
type GRPH_SURFACE_UPDATE_H_RETRACE_EN; \
type GRPH_UPDATE_LOCK; \
type PIXEL_DURATION; \
--
2.11.0
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 29/31] drm/amd/display: fix flip register write sequence
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (27 preceding siblings ...)
2017-05-23 14:09 ` [PATCH 28/31] drm/amd/display: remove GRPH_SURFACE_UPDATE_IMMEDIATE_EN field programming Harry Wentland
@ 2017-05-23 14:09 ` Harry Wentland
2017-05-23 14:09 ` [PATCH 30/31] drm/amd/display: Remove unused addr var in TG Harry Wentland
2017-05-23 14:09 ` [PATCH 31/31] drm/amd/display: No need to assert on stream_status Harry Wentland
30 siblings, 0 replies; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:09 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Change-Id: I0a1b924f5a9e66b3e24f8ac2ca1b6597da919305
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 56 ++++++++++------------
.../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 2 +
2 files changed, 28 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
index a52c614ec5b4..da2f99dcd766 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
@@ -237,7 +237,7 @@ static bool mem_input_program_surface_flip_and_addr(
struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
/* program flip type */
- REG_UPDATE(DCSURF_FLIP_CONTROL,
+ REG_SET(DCSURF_FLIP_CONTROL, 0,
SURFACE_FLIP_TYPE, flip_immediate);
/* HW automatically latch rest of address register on write to
@@ -258,21 +258,20 @@ static bool mem_input_program_surface_flip_and_addr(
break;
if (address->grph.meta_addr.quad_part != 0) {
-
- REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH,
+ REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
PRIMARY_META_SURFACE_ADDRESS_HIGH,
address->grph.meta_addr.high_part);
- REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS,
+ REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
PRIMARY_META_SURFACE_ADDRESS,
address->grph.meta_addr.low_part);
}
- REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
+ REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
PRIMARY_SURFACE_ADDRESS_HIGH,
address->grph.addr.high_part);
- REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS,
+ REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
PRIMARY_SURFACE_ADDRESS,
address->grph.addr.low_part);
break;
@@ -282,40 +281,38 @@ static bool mem_input_program_surface_flip_and_addr(
break;
if (address->video_progressive.luma_meta_addr.quad_part != 0) {
+ REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
+ PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
+ address->video_progressive.chroma_meta_addr.high_part);
- REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH,
+ REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
+ PRIMARY_META_SURFACE_ADDRESS_C,
+ address->video_progressive.chroma_meta_addr.low_part);
+
+ REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
PRIMARY_META_SURFACE_ADDRESS_HIGH,
address->video_progressive.luma_meta_addr.high_part);
- REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS,
+ REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
PRIMARY_META_SURFACE_ADDRESS,
address->video_progressive.luma_meta_addr.low_part);
-
- REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
- PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
- address->video_progressive.chroma_meta_addr.high_part);
-
- REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C,
- PRIMARY_META_SURFACE_ADDRESS_C,
- address->video_progressive.chroma_meta_addr.low_part);
}
- REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C,
+ REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
PRIMARY_SURFACE_ADDRESS_HIGH_C,
address->video_progressive.chroma_addr.high_part);
- REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS_C,
+ REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
PRIMARY_SURFACE_ADDRESS_C,
address->video_progressive.chroma_addr.low_part);
- REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
+ REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
PRIMARY_SURFACE_ADDRESS_HIGH,
address->video_progressive.luma_addr.high_part);
- REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS,
+ REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
PRIMARY_SURFACE_ADDRESS,
address->video_progressive.luma_addr.low_part);
-
break;
case PLN_ADDR_TYPE_GRPH_STEREO:
if (address->grph_stereo.left_addr.quad_part == 0)
@@ -324,39 +321,38 @@ static bool mem_input_program_surface_flip_and_addr(
break;
if (address->grph_stereo.right_meta_addr.quad_part != 0) {
- REG_UPDATE(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH,
+ REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,
SECONDARY_META_SURFACE_ADDRESS_HIGH,
address->grph_stereo.right_meta_addr.high_part);
- REG_UPDATE(DCSURF_SECONDARY_META_SURFACE_ADDRESS,
+ REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,
SECONDARY_META_SURFACE_ADDRESS,
address->grph_stereo.right_meta_addr.low_part);
}
if (address->grph_stereo.left_meta_addr.quad_part != 0) {
- REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH,
+ REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
PRIMARY_META_SURFACE_ADDRESS_HIGH,
address->grph_stereo.left_meta_addr.high_part);
- REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS,
+ REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
PRIMARY_META_SURFACE_ADDRESS,
address->grph_stereo.left_meta_addr.low_part);
}
- REG_UPDATE(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH,
+ REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,
SECONDARY_SURFACE_ADDRESS_HIGH,
address->grph_stereo.right_addr.high_part);
- REG_UPDATE(DCSURF_SECONDARY_SURFACE_ADDRESS,
+ REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,
SECONDARY_SURFACE_ADDRESS,
address->grph_stereo.right_addr.low_part);
-
- REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
+ REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
PRIMARY_SURFACE_ADDRESS_HIGH,
address->grph_stereo.left_addr.high_part);
- REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS,
+ REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
PRIMARY_SURFACE_ADDRESS,
address->grph_stereo.left_addr.low_part);
break;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
index 20bd0f5d7b17..48b313b213c0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
@@ -282,6 +282,7 @@ struct dcn_mi_registers {
MI_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\
MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\
MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_PENDING, mask_sh),\
+ MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\
MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\
MI_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
@@ -414,6 +415,7 @@ struct dcn_mi_registers {
type H_MIRROR_EN;\
type SURFACE_PIXEL_FORMAT;\
type SURFACE_FLIP_TYPE;\
+ type SURFACE_UPDATE_LOCK;\
type SURFACE_UPDATE_PENDING;\
type PRIMARY_SURFACE_ADDRESS_HIGH;\
type PRIMARY_SURFACE_ADDRESS;\
--
2.11.0
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 30/31] drm/amd/display: Remove unused addr var in TG
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (28 preceding siblings ...)
2017-05-23 14:09 ` [PATCH 29/31] drm/amd/display: fix flip register write sequence Harry Wentland
@ 2017-05-23 14:09 ` Harry Wentland
2017-05-23 14:09 ` [PATCH 31/31] drm/amd/display: No need to assert on stream_status Harry Wentland
30 siblings, 0 replies; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:09 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland
Change-Id: I3a2032942816f66fc8a89ea0911d3cac3d187d19
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c | 7 -------
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index c208196864ad..03b21e9a1156 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -386,34 +386,27 @@ bool dce120_timing_generator_did_triggered_reset_occur(
/* Move to enable accelerated mode */
void dce120_timing_generator_disable_vga(struct timing_generator *tg)
{
- uint32_t addr = 0;
uint32_t offset = 0;
uint32_t value = 0;
struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
switch (tg110->controller_id) {
case CONTROLLER_ID_D0:
- addr = mmD1VGA_CONTROL;
offset = 0;
break;
case CONTROLLER_ID_D1:
- addr = mmD2VGA_CONTROL;
offset = mmD2VGA_CONTROL - mmD1VGA_CONTROL;
break;
case CONTROLLER_ID_D2:
- addr = mmD3VGA_CONTROL;
offset = mmD3VGA_CONTROL - mmD1VGA_CONTROL;
break;
case CONTROLLER_ID_D3:
- addr = mmD4VGA_CONTROL;
offset = mmD4VGA_CONTROL - mmD1VGA_CONTROL;
break;
case CONTROLLER_ID_D4:
- addr = mmD1VGA_CONTROL;
offset = mmD5VGA_CONTROL - mmD1VGA_CONTROL;
break;
case CONTROLLER_ID_D5:
- addr = mmD6VGA_CONTROL;
offset = mmD6VGA_CONTROL - mmD1VGA_CONTROL;
break;
default:
--
2.11.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 31/31] drm/amd/display: No need to assert on stream_status
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (29 preceding siblings ...)
2017-05-23 14:09 ` [PATCH 30/31] drm/amd/display: Remove unused addr var in TG Harry Wentland
@ 2017-05-23 14:09 ` Harry Wentland
30 siblings, 0 replies; 32+ messages in thread
From: Harry Wentland @ 2017-05-23 14:09 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland
This will be NULL on a new stream. DC handles it gracefully.
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 5d34ce6c7faf..7182425bbcc2 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -3064,9 +3064,6 @@ static enum surface_update_type amdgpu_dm_check_surfaces_update_type(
dc_stream_get_status(dc_stream);
enum surface_update_type update_type;
- ASSERT(stream_status);
-
-
memset(srf_updates, 0, sizeof(srf_updates));
memset(flip_addr, 0, sizeof(flip_addr));
memset(plane_info, 0, sizeof(plane_info));
--
2.11.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
end of thread, other threads:[~2017-05-23 14:09 UTC | newest]
Thread overview: 32+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-05-23 14:08 [PATCH 00/31] DC Linux Patches May 23, 2017 Harry Wentland
[not found] ` <20170523140909.9924-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2017-05-23 14:08 ` [PATCH 01/31] drm/amd/display: Program CSC Mode For BT2020 Harry Wentland
2017-05-23 14:08 ` [PATCH 02/31] drm/amd/display: fix mpo blanking out on one of planes being set not visible Harry Wentland
2017-05-23 14:08 ` [PATCH 03/31] drm/amd/display: Fix slow FPS Harry Wentland
2017-05-23 14:08 ` [PATCH 04/31] drm/amd/display: Disable ABM when eDP is disabled Harry Wentland
2017-05-23 14:08 ` [PATCH 05/31] drm/amd/display: dce 8 - 12 mem_input refactor to new style Harry Wentland
2017-05-23 14:08 ` [PATCH 06/31] drm/amd/display: Use dc_update_surfaces_for_stream for flip Harry Wentland
2017-05-23 14:08 ` [PATCH 07/31] drm/amd/display: Clen unused interface Harry Wentland
2017-05-23 14:08 ` [PATCH 08/31] drm/amd/display: Fix dcn10 cursor set position hang Harry Wentland
2017-05-23 14:08 ` [PATCH 09/31] drm/amd/display: add missing GRPH_UPDATE_LOCK field macro for dce_mem_input Harry Wentland
2017-05-23 14:08 ` [PATCH 10/31] drm/amd/display: Unify loop for surface update and page flip Harry Wentland
2017-05-23 14:08 ` [PATCH 11/31] drm/amd/display: read VM settings from MMHUB Harry Wentland
2017-05-23 14:08 ` [PATCH 12/31] drm/amd/display: Fix 5th display lightup on Vega10 Harry Wentland
2017-05-23 14:08 ` [PATCH 13/31] drm/amd/display: make dc_get_validate_context re-entrant Harry Wentland
2017-05-23 14:08 ` [PATCH 14/31] drm/amd/display: revert dc_get_validate_context re-entrancy fix Harry Wentland
2017-05-23 14:08 ` [PATCH 15/31] drm/amd/display: Refactor use_lut() from dce110 to dce Harry Wentland
2017-05-23 14:08 ` [PATCH 16/31] drm/amd/display: Implement input gamma LUT Harry Wentland
2017-05-23 14:08 ` [PATCH 17/31] drm/amd/display: Add missed wait_for_prev_commits Harry Wentland
2017-05-23 14:08 ` [PATCH 18/31] drm/amd/display: Fix ASSR enablement on DP to EDP converter Harry Wentland
2017-05-23 14:08 ` [PATCH 19/31] drm/amd/display: Tidy up dce120_timing_generator_enable_advanced_request() Harry Wentland
2017-05-23 14:08 ` [PATCH 20/31] drm/amd/display: Fix indentation in dce120_tg_program_timing() Harry Wentland
2017-05-23 14:08 ` [PATCH 21/31] drm/amd/display: Make dce120_tg_is_blanked() more legible Harry Wentland
2017-05-23 14:09 ` [PATCH 22/31] drm/amd/display: Clean up indentation in dce120_tg_set_blank() Harry Wentland
2017-05-23 14:09 ` [PATCH 23/31] drm/amd/display: Tidy up dce120_clock_source_create() Harry Wentland
2017-05-23 14:09 ` [PATCH 24/31] drm/amd/display: Tidy up mem_input_program_surface_flip_and_addr() Harry Wentland
2017-05-23 14:09 ` [PATCH 25/31] drm/amd/display: Query for update plane type Harry Wentland
2017-05-23 14:09 ` [PATCH 26/31] drm/amd/display: Remove redundant condition Harry Wentland
2017-05-23 14:09 ` [PATCH 27/31] drm/amd/display: fix YUV surface address programming sequence Harry Wentland
2017-05-23 14:09 ` [PATCH 28/31] drm/amd/display: remove GRPH_SURFACE_UPDATE_IMMEDIATE_EN field programming Harry Wentland
2017-05-23 14:09 ` [PATCH 29/31] drm/amd/display: fix flip register write sequence Harry Wentland
2017-05-23 14:09 ` [PATCH 30/31] drm/amd/display: Remove unused addr var in TG Harry Wentland
2017-05-23 14:09 ` [PATCH 31/31] drm/amd/display: No need to assert on stream_status Harry Wentland
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