* [PATCH v6 0/4] DT and Driver review comments fix
@ 2017-05-24 8:12 ` Xiaowei Song
0 siblings, 0 replies; 18+ messages in thread
From: Xiaowei Song @ 2017-05-24 8:12 UTC (permalink / raw)
To: bhelgaas, kishon, jingoohan1, arnd, tn, keith.busch,
niklas.cassel, dhdang, liudongdong3, gabriele.paoloni, robh+dt,
mark.rutland, catalin.marinas, will.deacon
Cc: chenyao11, puck.chen, songxiaowei, guodong.xu, wangbinghui,
suzhuangluan, linux-pci, devicetree, linux-kernel
Before Version Patches
======================
patch V4
https://www.spinics.net/lists/linux-pci/msg61406.html
patch V3
https://www.spinics.net/lists/linux-pci/msg61399.html
Changes between V6 and V5
=========================
1. seperate Document from .dtsi patch.
2. fix issues according to review comments
from Bjorn Helgaas and Rob Herring: annotation stype, DT node,
patch post method and so on.
Patches list
============
Xiaowei Song (4):
PCI: hisi: Add DT binding for PCIe of Kirin SoC series
arm64: dts: hisi: add kirin pcie node
PCI: dwc: kirin: add PCIe Driver for HiSilicon Kirin SoC
defconfig: PCI: Enable Kirin PCIe defconfig
.../devicetree/bindings/pci/kirin-pcie.txt | 49 ++
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 31 ++
arch/arm64/configs/defconfig | 1 +
drivers/pci/dwc/Kconfig | 10 +
drivers/pci/dwc/Makefile | 1 +
drivers/pci/dwc/pcie-kirin.c | 511 +++++++++++++++++++++
6 files changed, 603 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt
create mode 100644 drivers/pci/dwc/pcie-kirin.c
--
2.11.GIT
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v6 0/4] DT and Driver review comments fix
@ 2017-05-24 8:12 ` Xiaowei Song
0 siblings, 0 replies; 18+ messages in thread
From: Xiaowei Song @ 2017-05-24 8:12 UTC (permalink / raw)
To: bhelgaas, kishon, jingoohan1, arnd, tn, keith.busch,
niklas.cassel, dhdang, liudongdong3, gabriele.paoloni, robh+dt,
mark.rutland, catalin.marinas, will.deacon
Cc: chenyao11, puck.chen, songxiaowei, guodong.xu, wangbinghui,
suzhuangluan, linux-pci, devicetree, linux-kernel
Before Version Patches
======================
patch V4
https://www.spinics.net/lists/linux-pci/msg61406.html
patch V3
https://www.spinics.net/lists/linux-pci/msg61399.html
Changes between V6 and V5
=========================
1. seperate Document from .dtsi patch.
2. fix issues according to review comments
from Bjorn Helgaas and Rob Herring: annotation stype, DT node,
patch post method and so on.
Patches list
============
Xiaowei Song (4):
PCI: hisi: Add DT binding for PCIe of Kirin SoC series
arm64: dts: hisi: add kirin pcie node
PCI: dwc: kirin: add PCIe Driver for HiSilicon Kirin SoC
defconfig: PCI: Enable Kirin PCIe defconfig
.../devicetree/bindings/pci/kirin-pcie.txt | 49 ++
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 31 ++
arch/arm64/configs/defconfig | 1 +
drivers/pci/dwc/Kconfig | 10 +
drivers/pci/dwc/Makefile | 1 +
drivers/pci/dwc/pcie-kirin.c | 511 +++++++++++++++++++++
6 files changed, 603 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt
create mode 100644 drivers/pci/dwc/pcie-kirin.c
--
2.11.GIT
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v6 1/4] PCI: hisi: Add DT binding for PCIe of Kirin SoC series
2017-05-24 8:12 ` Xiaowei Song
@ 2017-05-24 8:12 ` Xiaowei Song
-1 siblings, 0 replies; 18+ messages in thread
From: Xiaowei Song @ 2017-05-24 8:12 UTC (permalink / raw)
To: bhelgaas, kishon, jingoohan1, arnd, tn, keith.busch,
niklas.cassel, dhdang, liudongdong3, gabriele.paoloni, robh+dt,
mark.rutland, catalin.marinas, will.deacon
Cc: chenyao11, puck.chen, songxiaowei, guodong.xu, wangbinghui,
suzhuangluan, linux-pci, devicetree, linux-kernel
Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
---
.../devicetree/bindings/pci/kirin-pcie.txt | 49 ++++++++++++++++++++++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
new file mode 100644
index 000000000000..ffbdcba287f0
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
@@ -0,0 +1,49 @@
+HiSilicon Kirin SoCs PCIe host DT description
+
+Kirin PCIe host controller is based on Designware PCI core.
+It shares common functions with PCIe Designware core driver
+and inherits common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties
+- compatible:
+ "hisilicon,hi3660-pcie" for PCIe of Kirin960 SoC
+- reg: Should contain rc_dbi, apb, phy, config registers location and length.
+- reg-names: Must include the following entries:
+ "dbi": controller configuration registers;
+ "apb": apb Ctrl register defined by Kirin;
+ "phy": apb PHY register defined by Kirin;
+ "config": PCIe configuration space registers.
+- reset-gpio: The gpio to generate PCIe perst assert and deassert signal.
+
+Optional properties:
+
+Example based on kirin960:
+
+ pcie@f4000000 {
+ compatible = "hisilicon,kirin-pcie";
+ reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>,
+ <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>;
+ reg-names = "dbi","apb","phy", "config";
+ bus-range = <0x0 0x1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>;
+ num-lanes = <1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <0x0 0 0 2 &gic 0 0 0 283 4>,
+ <0x0 0 0 3 &gic 0 0 0 284 4>,
+ <0x0 0 0 4 &gic 0 0 0 285 4>;
+ clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
+ <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
+ <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
+ clock-names = "pcie_phy_ref", "pcie_aux",
+ "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
+ reset-gpio = <&gpio11 1 0 >;
+ };
--
2.11.GIT
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v6 1/4] PCI: hisi: Add DT binding for PCIe of Kirin SoC series
@ 2017-05-24 8:12 ` Xiaowei Song
0 siblings, 0 replies; 18+ messages in thread
From: Xiaowei Song @ 2017-05-24 8:12 UTC (permalink / raw)
To: bhelgaas, kishon, jingoohan1, arnd, tn, keith.busch,
niklas.cassel, dhdang, liudongdong3, gabriele.paoloni, robh+dt,
mark.rutland, catalin.marinas, will.deacon
Cc: chenyao11, puck.chen, songxiaowei, guodong.xu, wangbinghui,
suzhuangluan, linux-pci, devicetree, linux-kernel
Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
---
.../devicetree/bindings/pci/kirin-pcie.txt | 49 ++++++++++++++++++++++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
new file mode 100644
index 000000000000..ffbdcba287f0
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
@@ -0,0 +1,49 @@
+HiSilicon Kirin SoCs PCIe host DT description
+
+Kirin PCIe host controller is based on Designware PCI core.
+It shares common functions with PCIe Designware core driver
+and inherits common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties
+- compatible:
+ "hisilicon,hi3660-pcie" for PCIe of Kirin960 SoC
+- reg: Should contain rc_dbi, apb, phy, config registers location and length.
+- reg-names: Must include the following entries:
+ "dbi": controller configuration registers;
+ "apb": apb Ctrl register defined by Kirin;
+ "phy": apb PHY register defined by Kirin;
+ "config": PCIe configuration space registers.
+- reset-gpio: The gpio to generate PCIe perst assert and deassert signal.
+
+Optional properties:
+
+Example based on kirin960:
+
+ pcie@f4000000 {
+ compatible = "hisilicon,kirin-pcie";
+ reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>,
+ <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>;
+ reg-names = "dbi","apb","phy", "config";
+ bus-range = <0x0 0x1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>;
+ num-lanes = <1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <0x0 0 0 2 &gic 0 0 0 283 4>,
+ <0x0 0 0 3 &gic 0 0 0 284 4>,
+ <0x0 0 0 4 &gic 0 0 0 285 4>;
+ clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
+ <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
+ <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
+ clock-names = "pcie_phy_ref", "pcie_aux",
+ "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
+ reset-gpio = <&gpio11 1 0 >;
+ };
--
2.11.GIT
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v6 2/4] arm64: dts: hisi: add kirin pcie node
2017-05-24 8:12 ` Xiaowei Song
@ 2017-05-24 8:12 ` Xiaowei Song
-1 siblings, 0 replies; 18+ messages in thread
From: Xiaowei Song @ 2017-05-24 8:12 UTC (permalink / raw)
To: bhelgaas, kishon, jingoohan1, arnd, tn, keith.busch,
niklas.cassel, dhdang, liudongdong3, gabriele.paoloni, robh+dt,
mark.rutland, catalin.marinas, will.deacon
Cc: chenyao11, puck.chen, songxiaowei, guodong.xu, wangbinghui,
suzhuangluan, linux-pci, devicetree, linux-kernel
Add PCIe node for hi3660, and add binding documentation.
Cc: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
---
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 3983086bd67b..f41276b52248 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -156,5 +156,36 @@
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
+
+ pcie@f4000000 {
+ compatible = "hisilicon,kirin-pcie";
+ reg = <0x0 0xf4000000 0x0 0x1000>,
+ <0x0 0xff3fe000 0x0 0x1000>,
+ <0x0 0xf3f20000 0x0 0x40000>,
+ <0x0 0xF5000000 0x0 0x2000>;
+ reg-names = "dbi", "apb", "phy", "config";
+ bus-range = <0x0 0x1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x02000000 0x0 0x00000000 0x0
+ 0xf6000000 0x0 0x2000000>;
+ num-lanes = <1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>,
+ <0x0 0 0 2 &gic 0 0 0 283 4>,
+ <0x0 0 0 3 &gic 0 0 0 284 4>,
+ <0x0 0 0 4 &gic 0 0 0 285 4>;
+ clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
+ <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
+ <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
+ clock-names = "pcie_phy_ref", "pcie_aux",
+ "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
+ reset-gpio = <&gpio11 1 0 >;
+ status = "ok";
+ };
};
};
--
2.11.GIT
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v6 2/4] arm64: dts: hisi: add kirin pcie node
@ 2017-05-24 8:12 ` Xiaowei Song
0 siblings, 0 replies; 18+ messages in thread
From: Xiaowei Song @ 2017-05-24 8:12 UTC (permalink / raw)
To: bhelgaas, kishon, jingoohan1, arnd, tn, keith.busch,
niklas.cassel, dhdang, liudongdong3, gabriele.paoloni, robh+dt,
mark.rutland, catalin.marinas, will.deacon
Cc: chenyao11, puck.chen, songxiaowei, guodong.xu, wangbinghui,
suzhuangluan, linux-pci, devicetree, linux-kernel
Add PCIe node for hi3660, and add binding documentation.
Cc: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
---
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 3983086bd67b..f41276b52248 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -156,5 +156,36 @@
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
+
+ pcie@f4000000 {
+ compatible = "hisilicon,kirin-pcie";
+ reg = <0x0 0xf4000000 0x0 0x1000>,
+ <0x0 0xff3fe000 0x0 0x1000>,
+ <0x0 0xf3f20000 0x0 0x40000>,
+ <0x0 0xF5000000 0x0 0x2000>;
+ reg-names = "dbi", "apb", "phy", "config";
+ bus-range = <0x0 0x1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x02000000 0x0 0x00000000 0x0
+ 0xf6000000 0x0 0x2000000>;
+ num-lanes = <1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>,
+ <0x0 0 0 2 &gic 0 0 0 283 4>,
+ <0x0 0 0 3 &gic 0 0 0 284 4>,
+ <0x0 0 0 4 &gic 0 0 0 285 4>;
+ clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
+ <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
+ <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
+ clock-names = "pcie_phy_ref", "pcie_aux",
+ "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
+ reset-gpio = <&gpio11 1 0 >;
+ status = "ok";
+ };
};
};
--
2.11.GIT
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v6 3/4] PCI: dwc: kirin: add PCIe Driver for HiSilicon Kirin SoC
@ 2017-05-24 8:12 ` Xiaowei Song
0 siblings, 0 replies; 18+ messages in thread
From: Xiaowei Song @ 2017-05-24 8:12 UTC (permalink / raw)
To: bhelgaas, kishon, jingoohan1, arnd, tn, keith.busch,
niklas.cassel, dhdang, liudongdong3, gabriele.paoloni, robh+dt,
mark.rutland, catalin.marinas, will.deacon
Cc: chenyao11, puck.chen, songxiaowei, guodong.xu, wangbinghui,
suzhuangluan, linux-pci, devicetree, linux-kernel
Hisilicon PCIe Driver shares the common functions for PCIe dw-host
The poweron functions is developed on hi3660 SoC,
while Others Functions are common for Kirin series SoCs.
Low power mode(L1 sub-state and Suspend/Resume), hotplug
and MSI feature are not supported currently.
Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
---
drivers/pci/dwc/Kconfig | 10 +
drivers/pci/dwc/Makefile | 1 +
drivers/pci/dwc/pcie-kirin.c | 511 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 522 insertions(+)
create mode 100644 drivers/pci/dwc/pcie-kirin.c
diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
index d2d2ba5b8a68..13e617b78430 100644
--- a/drivers/pci/dwc/Kconfig
+++ b/drivers/pci/dwc/Kconfig
@@ -130,4 +130,14 @@ config PCIE_ARTPEC6
Say Y here to enable PCIe controller support on Axis ARTPEC-6
SoCs. This PCIe controller uses the DesignWare core.
+config PCIE_KIRIN
+ depends on OF && ARM64
+ bool "HiSilicon Kirin series SoCs PCIe controllers"
+ depends on PCI
+ select PCIEPORTBUS
+ select PCIE_DW_HOST
+ help
+ Say Y here if you want PCIe controller support on HiSilicon Kirin series SoCs
+ kirin960 SoC
+
endmenu
diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
index a2df13c28798..4bd69bacd4ab 100644
--- a/drivers/pci/dwc/Makefile
+++ b/drivers/pci/dwc/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
+obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
# The following drivers are for devices that use the generic ACPI
# pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/dwc/pcie-kirin.c b/drivers/pci/dwc/pcie-kirin.c
new file mode 100644
index 000000000000..3a0b078e1943
--- /dev/null
+++ b/drivers/pci/dwc/pcie-kirin.c
@@ -0,0 +1,511 @@
+/*
+ * PCIe host controller driver for Kirin Phone SoCs
+ *
+ * Copyright (C) 2017 Hilisicon Electronics Co., Ltd.
+ * http://www.huawei.com
+ *
+ * Author: Xiaowei Song <songxiaowei@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <asm/compiler.h>
+#include <linux/compiler.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_address.h>
+#include <linux/of_gpio.h>
+#include <linux/of_pci.h>
+#include <linux/pci.h>
+#include <linux/pci_regs.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/resource.h>
+#include <linux/types.h>
+#include "pcie-designware.h"
+
+#define to_kirin_pcie(x) dev_get_drvdata((x)->dev)
+
+#define REF_CLK_FREQ 100000000
+
+/* PCIe ELBI registers */
+#define SOC_PCIECTRL_CTRL0_ADDR 0x000
+#define SOC_PCIECTRL_CTRL1_ADDR 0x004
+#define SOC_PCIEPHY_CTRL2_ADDR 0x008
+#define SOC_PCIEPHY_CTRL3_ADDR 0x00c
+#define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21)
+
+#define PCIE_APP_LTSSM_ENABLE 0x01c
+#define PCIE_APB_PHY_CTRL0 0x0
+#define PCIE_APB_PHY_CTRL1 0x4
+#define PCIE_APB_PHY_STATUS0 0x400
+#define PCIE_LINKUP_ENABLE (0x8020)
+#define PCIE_LTSSM_ENABLE_BIT (0x1 << 11)
+#define PIPE_CLK_STABLE (0x1 << 19)
+#define PIPE_CLK_MAX_TRY_TIMES 10
+#define PHY_REF_PAD_BIT (0x1 << 8)
+#define PHY_PWR_DOWN_BIT (0x1 << 22)
+#define PHY_RST_ACK_BIT (0x1 << 16)
+
+/* info lacated in sysctrl */
+#define SCTRL_PCIE_CMOS_OFFSET 0x60
+#define SCTRL_PCIE_CMOS_BIT 0x10
+#define SCTRL_PCIE_ISO_OFFSET 0x44
+#define SCTRL_PCIE_ISO_BIT 0x30
+#define SCTRL_PCIE_HPCLK_OFFSET 0x190
+#define SCTRL_PCIE_HPCLK_BIT 0x184000
+#define SCTRL_PCIE_OE_OFFSET 0x14a
+#define PCIE_DEBOUNCE_PARAM 0xF0F400
+#define PCIE_OE_BYPASS (0x3 << 28)
+
+/* peri_crg ctrl */
+#define CRGCTRL_PCIE_ASSERT_OFFSET 0x88
+#define CRGCTRL_PCIE_ASSERT_BIT 0x8c000000
+
+/* Time for delay */
+#define REF_2_PERST_MIN (20000)
+#define REF_2_PERST_MAX (25000)
+#define PERST_2_ACCESS_MIN (10000)
+#define PERST_2_ACCESS_MAX (12000)
+#define LINK_WAIT_MIN (900)
+#define LINK_WAIT_MAX (1000)
+#define PIPE_CLK_WAIT_MIN (550)
+#define PIPE_CLK_WAIT_MAX (600)
+
+struct kirin_pcie {
+ struct dw_pcie *pci;
+ void __iomem *apb_base;
+ void __iomem *phy_base;
+ struct regmap *crgctrl;
+ struct regmap *sysctrl;
+ struct clk *apb_sys_clk;
+ struct clk *apb_phy_clk;
+ struct clk *phy_ref_clk;
+ struct clk *pcie_aclk;
+ struct clk *pcie_aux_clk;
+ int gpio_id_reset;
+};
+
+static inline void kirin_apb_ctrl_writel(struct kirin_pcie *kirin_pcie,
+ u32 val, u32 reg)
+{
+ writel(val, kirin_pcie->apb_base + reg);
+}
+
+static inline u32 kirin_apb_ctrl_readl(struct kirin_pcie *kirin_pcie,
+ u32 reg)
+{
+ return readl(kirin_pcie->apb_base + reg);
+}
+
+/*Registers in PCIePHY*/
+static inline void kirin_apb_phy_writel(struct kirin_pcie *kirin_pcie,
+ u32 val, u32 reg)
+{
+ writel(val, kirin_pcie->phy_base + reg);
+}
+
+static inline u32 kirin_apb_phy_readl(struct kirin_pcie *kirin_pcie,
+ u32 reg)
+{
+ return readl(kirin_pcie->phy_base + reg);
+}
+
+static int32_t kirin_pcie_get_clk(struct kirin_pcie *kirin_pcie,
+ struct platform_device *pdev)
+{
+ kirin_pcie->phy_ref_clk = devm_clk_get(&pdev->dev, "pcie_phy_ref");
+ if (IS_ERR(kirin_pcie->phy_ref_clk))
+ return PTR_ERR(kirin_pcie->phy_ref_clk);
+
+ kirin_pcie->pcie_aux_clk = devm_clk_get(&pdev->dev, "pcie_aux");
+ if (IS_ERR(kirin_pcie->pcie_aux_clk))
+ return PTR_ERR(kirin_pcie->pcie_aux_clk);
+
+ kirin_pcie->apb_phy_clk = devm_clk_get(&pdev->dev, "pcie_apb_phy");
+ if (IS_ERR(kirin_pcie->apb_phy_clk))
+ return PTR_ERR(kirin_pcie->apb_phy_clk);
+
+ kirin_pcie->apb_sys_clk = devm_clk_get(&pdev->dev, "pcie_apb_sys");
+ if (IS_ERR(kirin_pcie->apb_sys_clk))
+ return PTR_ERR(kirin_pcie->apb_sys_clk);
+
+ kirin_pcie->pcie_aclk = devm_clk_get(&pdev->dev, "pcie_aclk");
+ if (IS_ERR(kirin_pcie->pcie_aclk))
+ return PTR_ERR(kirin_pcie->pcie_aclk);
+
+ return 0;
+}
+
+static int32_t kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie,
+ struct platform_device *pdev)
+{
+ struct resource *apb;
+ struct resource *phy;
+ struct resource *dbi;
+
+ apb = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb");
+ kirin_pcie->apb_base = devm_ioremap_resource(&pdev->dev, apb);
+ if (IS_ERR(kirin_pcie->apb_base))
+ return PTR_ERR(kirin_pcie->apb_base);
+
+ phy = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
+ kirin_pcie->phy_base = devm_ioremap_resource(&pdev->dev, phy);
+ if (IS_ERR(kirin_pcie->phy_base))
+ return PTR_ERR(kirin_pcie->phy_base);
+
+ dbi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
+ kirin_pcie->pci->dbi_base = devm_ioremap_resource(&pdev->dev, dbi);
+ if (IS_ERR(kirin_pcie->pci->dbi_base))
+ return PTR_ERR(kirin_pcie->pci->dbi_base);
+
+ kirin_pcie->crgctrl =
+ syscon_regmap_lookup_by_compatible("hisilicon,hi3660-crgctrl");
+ if (IS_ERR(kirin_pcie->crgctrl))
+ return PTR_ERR(kirin_pcie->crgctrl);
+
+ kirin_pcie->sysctrl =
+ syscon_regmap_lookup_by_compatible("hisilicon,hi3660-sctrl");
+ if (IS_ERR(kirin_pcie->sysctrl))
+ return PTR_ERR(kirin_pcie->sysctrl);
+
+ return 0;
+}
+
+static int kirin_pcie_phy_init(struct kirin_pcie *kirin_pcie)
+{
+ u32 reg_val;
+ u32 time = PIPE_CLK_MAX_TRY_TIMES;
+
+ reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1);
+ reg_val &= ~PHY_REF_PAD_BIT;
+ kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1);
+
+ reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL0);
+ reg_val &= ~PHY_PWR_DOWN_BIT;
+ kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL0);
+ udelay(10);
+
+ reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1);
+ reg_val &= ~PHY_RST_ACK_BIT;
+ kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1);
+
+ usleep_range(PIPE_CLK_WAIT_MIN, PIPE_CLK_WAIT_MAX);
+ reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_STATUS0);
+ if (reg_val & PIPE_CLK_STABLE) {
+ dev_err(kirin_pcie->pci->dev, "PIPE clk is not stable\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void kirin_pcie_oe_enable(struct kirin_pcie *kirin_pcie)
+{
+ u32 val;
+
+ regmap_read(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, &val);
+ val |= PCIE_DEBOUNCE_PARAM;
+ val &= ~PCIE_OE_BYPASS;
+ regmap_write(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, val);
+}
+
+static int kirin_pcie_clk_ctrl(struct kirin_pcie *kirin_pcie, bool enable)
+{
+ int ret = 0;
+
+ if (!enable)
+ goto close_clk;
+
+ ret = clk_set_rate(kirin_pcie->phy_ref_clk, REF_CLK_FREQ);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(kirin_pcie->phy_ref_clk);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(kirin_pcie->apb_sys_clk);
+ if (ret)
+ goto apb_sys_fail;
+
+ ret = clk_prepare_enable(kirin_pcie->apb_phy_clk);
+ if (ret)
+ goto apb_phy_fail;
+
+ ret = clk_prepare_enable(kirin_pcie->pcie_aclk);
+ if (ret)
+ goto aclk_fail;
+
+ ret = clk_prepare_enable(kirin_pcie->pcie_aux_clk);
+ if (ret)
+ goto aux_clk_fail;
+
+ return 0;
+close_clk:
+ clk_disable_unprepare(kirin_pcie->pcie_aux_clk);
+aux_clk_fail:
+ clk_disable_unprepare(kirin_pcie->pcie_aclk);
+aclk_fail:
+ clk_disable_unprepare(kirin_pcie->apb_phy_clk);
+apb_phy_fail:
+ clk_disable_unprepare(kirin_pcie->apb_sys_clk);
+apb_sys_fail:
+ clk_disable_unprepare(kirin_pcie->phy_ref_clk);
+ return ret;
+}
+
+static int kirin_pcie_power_on(struct kirin_pcie *kirin_pcie)
+{
+ int ret;
+
+ /* Power supply for Host */
+ regmap_write(kirin_pcie->sysctrl,
+ SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT);
+ udelay(100);
+ kirin_pcie_oe_enable(kirin_pcie);
+
+ ret = kirin_pcie_clk_ctrl(kirin_pcie, true);
+ if (ret)
+ return ret;
+
+ /* ISO disable, PCIeCtrl,PHY assert and clk gate clear */
+ regmap_write(kirin_pcie->sysctrl,
+ SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT);
+ regmap_write(kirin_pcie->crgctrl,
+ CRGCTRL_PCIE_ASSERT_OFFSET, CRGCTRL_PCIE_ASSERT_BIT);
+ regmap_write(kirin_pcie->sysctrl,
+ SCTRL_PCIE_HPCLK_OFFSET, SCTRL_PCIE_HPCLK_BIT);
+
+ ret = kirin_pcie_phy_init(kirin_pcie);
+ if (ret)
+ goto close_clk;
+
+ /* perst assert Endpoint */
+ if (!gpio_request(kirin_pcie->gpio_id_reset, "pcie_perst")) {
+ usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX);
+ ret = gpio_direction_output(kirin_pcie->gpio_id_reset, 1);
+ if (ret)
+ goto close_clk;
+ usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX);
+
+ return 0;
+ }
+
+close_clk:
+ kirin_pcie_clk_ctrl(kirin_pcie, false);
+ return ret;
+}
+
+static void kirin_pcie_sideband_dbi_w_mode(struct kirin_pcie *kirin_pcie,
+ bool on)
+{
+ u32 val;
+
+ val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL0_ADDR);
+ if (on)
+ val = val | PCIE_ELBI_SLV_DBI_ENABLE;
+ else
+ val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;
+
+ kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL0_ADDR);
+}
+
+static void kirin_pcie_sideband_dbi_r_mode(struct kirin_pcie *kirin_pcie,
+ bool on)
+{
+ u32 val;
+
+ val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL1_ADDR);
+ if (on)
+ val = val | PCIE_ELBI_SLV_DBI_ENABLE;
+ else
+ val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;
+
+ kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL1_ADDR);
+}
+
+static int kirin_pcie_rd_own_conf(struct pcie_port *pp,
+ int where, int size, u32 *val)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
+ int ret;
+
+ kirin_pcie_sideband_dbi_r_mode(kirin_pcie, true);
+ ret = dw_pcie_read(pci->dbi_base + where, size, val);
+ kirin_pcie_sideband_dbi_r_mode(kirin_pcie, false);
+
+ return ret;
+}
+
+static int kirin_pcie_wr_own_conf(struct pcie_port *pp,
+ int where, int size, u32 val)
+{
+ int ret;
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
+
+ kirin_pcie_sideband_dbi_w_mode(kirin_pcie, true);
+ ret = dw_pcie_write(pci->dbi_base + where, size, val);
+ kirin_pcie_sideband_dbi_w_mode(kirin_pcie, false);
+
+ return ret;
+}
+
+static u32 kirin_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
+ u32 reg, size_t size)
+{
+ u32 ret;
+ struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
+
+ kirin_pcie_sideband_dbi_r_mode(kirin_pcie, true);
+ dw_pcie_read(base + reg, size, &ret);
+ kirin_pcie_sideband_dbi_r_mode(kirin_pcie, false);
+
+ return ret;
+}
+
+static void kirin_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base,
+ u32 reg, size_t size, u32 val)
+{
+ struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
+
+ kirin_pcie_sideband_dbi_w_mode(kirin_pcie, true);
+ dw_pcie_write(base + reg, size, val);
+ kirin_pcie_sideband_dbi_w_mode(kirin_pcie, false);
+}
+
+static int kirin_pcie_link_up(struct dw_pcie *pci)
+{
+ struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
+ u32 val = kirin_apb_ctrl_readl(kirin_pcie, PCIE_APB_PHY_STATUS0);
+
+ if ((val & PCIE_LINKUP_ENABLE) == PCIE_LINKUP_ENABLE)
+ return 1;
+
+ return 0;
+}
+
+static int kirin_pcie_establish_link(struct pcie_port *pp)
+{
+ int count = 0;
+
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
+
+ if (kirin_pcie_link_up(pci))
+ return 0;
+
+ dw_pcie_setup_rc(pp);
+
+ /* assert LTSSM enable */
+ kirin_apb_ctrl_writel(kirin_pcie, PCIE_LTSSM_ENABLE_BIT,
+ PCIE_APP_LTSSM_ENABLE);
+
+ /* check if the link is up or not */
+ while (!kirin_pcie_link_up(pci)) {
+ usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
+ count++;
+ if (count == 1000) {
+ dev_err(pci->dev, "Link Fail\n");
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
+static void kirin_pcie_host_init(struct pcie_port *pp)
+{
+ kirin_pcie_establish_link(pp);
+}
+
+static struct dw_pcie_ops kirin_dw_pcie_ops = {
+ .read_dbi = kirin_pcie_read_dbi,
+ .write_dbi = kirin_pcie_write_dbi,
+ .link_up = kirin_pcie_link_up,
+};
+
+static struct dw_pcie_host_ops kirin_pcie_host_ops = {
+ .rd_own_conf = kirin_pcie_rd_own_conf,
+ .wr_own_conf = kirin_pcie_wr_own_conf,
+ .host_init = kirin_pcie_host_init,
+};
+
+static int __init kirin_add_pcie_port(struct dw_pcie *pci,
+ struct platform_device *pdev)
+{
+ pci->pp.ops = &kirin_pcie_host_ops;
+
+ return dw_pcie_host_init(&pci->pp);
+}
+
+static int kirin_pcie_probe(struct platform_device *pdev)
+{
+ struct kirin_pcie *kirin_pcie;
+ struct dw_pcie *pci;
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ if (!pdev->dev.of_node) {
+ dev_err(&pdev->dev, "NULL node\n");
+ return -EINVAL;
+ }
+
+ kirin_pcie = devm_kzalloc(&pdev->dev,
+ sizeof(struct kirin_pcie), GFP_KERNEL);
+ if (!kirin_pcie)
+ return -ENOMEM;
+
+ pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
+ if (!pci)
+ return -ENOMEM;
+
+ pci->dev = dev;
+ pci->ops = &kirin_dw_pcie_ops;
+ kirin_pcie->pci = pci;
+
+ ret = kirin_pcie_get_clk(kirin_pcie, pdev);
+ if (ret)
+ return ret;
+
+ ret = kirin_pcie_get_resource(kirin_pcie, pdev);
+ if (ret)
+ return ret;
+
+ kirin_pcie->gpio_id_reset = of_get_named_gpio(pdev->dev.of_node,
+ "reset-gpio", 0);
+ if (kirin_pcie->gpio_id_reset < 0)
+ return -ENODEV;
+
+ ret = kirin_pcie_power_on(kirin_pcie);
+ if (ret)
+ return ret;
+
+ platform_set_drvdata(pdev, kirin_pcie);
+
+ return kirin_add_pcie_port(pci, pdev);
+}
+
+static const struct of_device_id kirin_pcie_match[] = {
+ { .compatible = "hisilicon,kirin-pcie" },
+ {},
+};
+
+struct platform_driver kirin_pcie_driver = {
+ .probe = kirin_pcie_probe,
+ .driver = {
+ .name = "kirin-pcie",
+ .of_match_table = kirin_pcie_match,
+ .suppress_bind_attrs = true,
+ },
+};
+
+builtin_platform_driver(kirin_pcie_driver);
--
2.11.GIT
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v6 3/4] PCI: dwc: kirin: add PCIe Driver for HiSilicon Kirin SoC
@ 2017-05-24 8:12 ` Xiaowei Song
0 siblings, 0 replies; 18+ messages in thread
From: Xiaowei Song @ 2017-05-24 8:12 UTC (permalink / raw)
To: bhelgaas-hpIqsD4AKlfQT0dZR+AlfA, kishon-l0cyMroinI0,
jingoohan1-Re5JQEeQqe8AvxtiuMwx3w, arnd-r2nGTMty4D4,
tn-nYOzD4b6Jr9Wk0Htik3J/w, keith.busch-ral2JQCrhuEAvxtiuMwx3w,
niklas.cassel-VrBV9hrLPhE, dhdang-qTEPVZfXA3Y,
liudongdong3-hv44wF8Li93QT0dZR+AlfA,
gabriele.paoloni-hv44wF8Li93QT0dZR+AlfA,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
catalin.marinas-5wv7dgnIgG8, will.deacon-5wv7dgnIgG8
Cc: chenyao11-hv44wF8Li93QT0dZR+AlfA,
puck.chen-C8/M+/jPZTeaMJb+Lgu22Q,
songxiaowei-C8/M+/jPZTeaMJb+Lgu22Q,
guodong.xu-QSEj5FYQhm4dnm+yROfE0A,
wangbinghui-C8/M+/jPZTeaMJb+Lgu22Q,
suzhuangluan-C8/M+/jPZTeaMJb+Lgu22Q,
linux-pci-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Hisilicon PCIe Driver shares the common functions for PCIe dw-host
The poweron functions is developed on hi3660 SoC,
while Others Functions are common for Kirin series SoCs.
Low power mode(L1 sub-state and Suspend/Resume), hotplug
and MSI feature are not supported currently.
Signed-off-by: Xiaowei Song <songxiaowei-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
---
drivers/pci/dwc/Kconfig | 10 +
drivers/pci/dwc/Makefile | 1 +
drivers/pci/dwc/pcie-kirin.c | 511 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 522 insertions(+)
create mode 100644 drivers/pci/dwc/pcie-kirin.c
diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
index d2d2ba5b8a68..13e617b78430 100644
--- a/drivers/pci/dwc/Kconfig
+++ b/drivers/pci/dwc/Kconfig
@@ -130,4 +130,14 @@ config PCIE_ARTPEC6
Say Y here to enable PCIe controller support on Axis ARTPEC-6
SoCs. This PCIe controller uses the DesignWare core.
+config PCIE_KIRIN
+ depends on OF && ARM64
+ bool "HiSilicon Kirin series SoCs PCIe controllers"
+ depends on PCI
+ select PCIEPORTBUS
+ select PCIE_DW_HOST
+ help
+ Say Y here if you want PCIe controller support on HiSilicon Kirin series SoCs
+ kirin960 SoC
+
endmenu
diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
index a2df13c28798..4bd69bacd4ab 100644
--- a/drivers/pci/dwc/Makefile
+++ b/drivers/pci/dwc/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
+obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
# The following drivers are for devices that use the generic ACPI
# pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/dwc/pcie-kirin.c b/drivers/pci/dwc/pcie-kirin.c
new file mode 100644
index 000000000000..3a0b078e1943
--- /dev/null
+++ b/drivers/pci/dwc/pcie-kirin.c
@@ -0,0 +1,511 @@
+/*
+ * PCIe host controller driver for Kirin Phone SoCs
+ *
+ * Copyright (C) 2017 Hilisicon Electronics Co., Ltd.
+ * http://www.huawei.com
+ *
+ * Author: Xiaowei Song <songxiaowei-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <asm/compiler.h>
+#include <linux/compiler.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_address.h>
+#include <linux/of_gpio.h>
+#include <linux/of_pci.h>
+#include <linux/pci.h>
+#include <linux/pci_regs.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/resource.h>
+#include <linux/types.h>
+#include "pcie-designware.h"
+
+#define to_kirin_pcie(x) dev_get_drvdata((x)->dev)
+
+#define REF_CLK_FREQ 100000000
+
+/* PCIe ELBI registers */
+#define SOC_PCIECTRL_CTRL0_ADDR 0x000
+#define SOC_PCIECTRL_CTRL1_ADDR 0x004
+#define SOC_PCIEPHY_CTRL2_ADDR 0x008
+#define SOC_PCIEPHY_CTRL3_ADDR 0x00c
+#define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21)
+
+#define PCIE_APP_LTSSM_ENABLE 0x01c
+#define PCIE_APB_PHY_CTRL0 0x0
+#define PCIE_APB_PHY_CTRL1 0x4
+#define PCIE_APB_PHY_STATUS0 0x400
+#define PCIE_LINKUP_ENABLE (0x8020)
+#define PCIE_LTSSM_ENABLE_BIT (0x1 << 11)
+#define PIPE_CLK_STABLE (0x1 << 19)
+#define PIPE_CLK_MAX_TRY_TIMES 10
+#define PHY_REF_PAD_BIT (0x1 << 8)
+#define PHY_PWR_DOWN_BIT (0x1 << 22)
+#define PHY_RST_ACK_BIT (0x1 << 16)
+
+/* info lacated in sysctrl */
+#define SCTRL_PCIE_CMOS_OFFSET 0x60
+#define SCTRL_PCIE_CMOS_BIT 0x10
+#define SCTRL_PCIE_ISO_OFFSET 0x44
+#define SCTRL_PCIE_ISO_BIT 0x30
+#define SCTRL_PCIE_HPCLK_OFFSET 0x190
+#define SCTRL_PCIE_HPCLK_BIT 0x184000
+#define SCTRL_PCIE_OE_OFFSET 0x14a
+#define PCIE_DEBOUNCE_PARAM 0xF0F400
+#define PCIE_OE_BYPASS (0x3 << 28)
+
+/* peri_crg ctrl */
+#define CRGCTRL_PCIE_ASSERT_OFFSET 0x88
+#define CRGCTRL_PCIE_ASSERT_BIT 0x8c000000
+
+/* Time for delay */
+#define REF_2_PERST_MIN (20000)
+#define REF_2_PERST_MAX (25000)
+#define PERST_2_ACCESS_MIN (10000)
+#define PERST_2_ACCESS_MAX (12000)
+#define LINK_WAIT_MIN (900)
+#define LINK_WAIT_MAX (1000)
+#define PIPE_CLK_WAIT_MIN (550)
+#define PIPE_CLK_WAIT_MAX (600)
+
+struct kirin_pcie {
+ struct dw_pcie *pci;
+ void __iomem *apb_base;
+ void __iomem *phy_base;
+ struct regmap *crgctrl;
+ struct regmap *sysctrl;
+ struct clk *apb_sys_clk;
+ struct clk *apb_phy_clk;
+ struct clk *phy_ref_clk;
+ struct clk *pcie_aclk;
+ struct clk *pcie_aux_clk;
+ int gpio_id_reset;
+};
+
+static inline void kirin_apb_ctrl_writel(struct kirin_pcie *kirin_pcie,
+ u32 val, u32 reg)
+{
+ writel(val, kirin_pcie->apb_base + reg);
+}
+
+static inline u32 kirin_apb_ctrl_readl(struct kirin_pcie *kirin_pcie,
+ u32 reg)
+{
+ return readl(kirin_pcie->apb_base + reg);
+}
+
+/*Registers in PCIePHY*/
+static inline void kirin_apb_phy_writel(struct kirin_pcie *kirin_pcie,
+ u32 val, u32 reg)
+{
+ writel(val, kirin_pcie->phy_base + reg);
+}
+
+static inline u32 kirin_apb_phy_readl(struct kirin_pcie *kirin_pcie,
+ u32 reg)
+{
+ return readl(kirin_pcie->phy_base + reg);
+}
+
+static int32_t kirin_pcie_get_clk(struct kirin_pcie *kirin_pcie,
+ struct platform_device *pdev)
+{
+ kirin_pcie->phy_ref_clk = devm_clk_get(&pdev->dev, "pcie_phy_ref");
+ if (IS_ERR(kirin_pcie->phy_ref_clk))
+ return PTR_ERR(kirin_pcie->phy_ref_clk);
+
+ kirin_pcie->pcie_aux_clk = devm_clk_get(&pdev->dev, "pcie_aux");
+ if (IS_ERR(kirin_pcie->pcie_aux_clk))
+ return PTR_ERR(kirin_pcie->pcie_aux_clk);
+
+ kirin_pcie->apb_phy_clk = devm_clk_get(&pdev->dev, "pcie_apb_phy");
+ if (IS_ERR(kirin_pcie->apb_phy_clk))
+ return PTR_ERR(kirin_pcie->apb_phy_clk);
+
+ kirin_pcie->apb_sys_clk = devm_clk_get(&pdev->dev, "pcie_apb_sys");
+ if (IS_ERR(kirin_pcie->apb_sys_clk))
+ return PTR_ERR(kirin_pcie->apb_sys_clk);
+
+ kirin_pcie->pcie_aclk = devm_clk_get(&pdev->dev, "pcie_aclk");
+ if (IS_ERR(kirin_pcie->pcie_aclk))
+ return PTR_ERR(kirin_pcie->pcie_aclk);
+
+ return 0;
+}
+
+static int32_t kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie,
+ struct platform_device *pdev)
+{
+ struct resource *apb;
+ struct resource *phy;
+ struct resource *dbi;
+
+ apb = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb");
+ kirin_pcie->apb_base = devm_ioremap_resource(&pdev->dev, apb);
+ if (IS_ERR(kirin_pcie->apb_base))
+ return PTR_ERR(kirin_pcie->apb_base);
+
+ phy = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
+ kirin_pcie->phy_base = devm_ioremap_resource(&pdev->dev, phy);
+ if (IS_ERR(kirin_pcie->phy_base))
+ return PTR_ERR(kirin_pcie->phy_base);
+
+ dbi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
+ kirin_pcie->pci->dbi_base = devm_ioremap_resource(&pdev->dev, dbi);
+ if (IS_ERR(kirin_pcie->pci->dbi_base))
+ return PTR_ERR(kirin_pcie->pci->dbi_base);
+
+ kirin_pcie->crgctrl =
+ syscon_regmap_lookup_by_compatible("hisilicon,hi3660-crgctrl");
+ if (IS_ERR(kirin_pcie->crgctrl))
+ return PTR_ERR(kirin_pcie->crgctrl);
+
+ kirin_pcie->sysctrl =
+ syscon_regmap_lookup_by_compatible("hisilicon,hi3660-sctrl");
+ if (IS_ERR(kirin_pcie->sysctrl))
+ return PTR_ERR(kirin_pcie->sysctrl);
+
+ return 0;
+}
+
+static int kirin_pcie_phy_init(struct kirin_pcie *kirin_pcie)
+{
+ u32 reg_val;
+ u32 time = PIPE_CLK_MAX_TRY_TIMES;
+
+ reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1);
+ reg_val &= ~PHY_REF_PAD_BIT;
+ kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1);
+
+ reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL0);
+ reg_val &= ~PHY_PWR_DOWN_BIT;
+ kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL0);
+ udelay(10);
+
+ reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1);
+ reg_val &= ~PHY_RST_ACK_BIT;
+ kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1);
+
+ usleep_range(PIPE_CLK_WAIT_MIN, PIPE_CLK_WAIT_MAX);
+ reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_STATUS0);
+ if (reg_val & PIPE_CLK_STABLE) {
+ dev_err(kirin_pcie->pci->dev, "PIPE clk is not stable\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void kirin_pcie_oe_enable(struct kirin_pcie *kirin_pcie)
+{
+ u32 val;
+
+ regmap_read(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, &val);
+ val |= PCIE_DEBOUNCE_PARAM;
+ val &= ~PCIE_OE_BYPASS;
+ regmap_write(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, val);
+}
+
+static int kirin_pcie_clk_ctrl(struct kirin_pcie *kirin_pcie, bool enable)
+{
+ int ret = 0;
+
+ if (!enable)
+ goto close_clk;
+
+ ret = clk_set_rate(kirin_pcie->phy_ref_clk, REF_CLK_FREQ);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(kirin_pcie->phy_ref_clk);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(kirin_pcie->apb_sys_clk);
+ if (ret)
+ goto apb_sys_fail;
+
+ ret = clk_prepare_enable(kirin_pcie->apb_phy_clk);
+ if (ret)
+ goto apb_phy_fail;
+
+ ret = clk_prepare_enable(kirin_pcie->pcie_aclk);
+ if (ret)
+ goto aclk_fail;
+
+ ret = clk_prepare_enable(kirin_pcie->pcie_aux_clk);
+ if (ret)
+ goto aux_clk_fail;
+
+ return 0;
+close_clk:
+ clk_disable_unprepare(kirin_pcie->pcie_aux_clk);
+aux_clk_fail:
+ clk_disable_unprepare(kirin_pcie->pcie_aclk);
+aclk_fail:
+ clk_disable_unprepare(kirin_pcie->apb_phy_clk);
+apb_phy_fail:
+ clk_disable_unprepare(kirin_pcie->apb_sys_clk);
+apb_sys_fail:
+ clk_disable_unprepare(kirin_pcie->phy_ref_clk);
+ return ret;
+}
+
+static int kirin_pcie_power_on(struct kirin_pcie *kirin_pcie)
+{
+ int ret;
+
+ /* Power supply for Host */
+ regmap_write(kirin_pcie->sysctrl,
+ SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT);
+ udelay(100);
+ kirin_pcie_oe_enable(kirin_pcie);
+
+ ret = kirin_pcie_clk_ctrl(kirin_pcie, true);
+ if (ret)
+ return ret;
+
+ /* ISO disable, PCIeCtrl,PHY assert and clk gate clear */
+ regmap_write(kirin_pcie->sysctrl,
+ SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT);
+ regmap_write(kirin_pcie->crgctrl,
+ CRGCTRL_PCIE_ASSERT_OFFSET, CRGCTRL_PCIE_ASSERT_BIT);
+ regmap_write(kirin_pcie->sysctrl,
+ SCTRL_PCIE_HPCLK_OFFSET, SCTRL_PCIE_HPCLK_BIT);
+
+ ret = kirin_pcie_phy_init(kirin_pcie);
+ if (ret)
+ goto close_clk;
+
+ /* perst assert Endpoint */
+ if (!gpio_request(kirin_pcie->gpio_id_reset, "pcie_perst")) {
+ usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX);
+ ret = gpio_direction_output(kirin_pcie->gpio_id_reset, 1);
+ if (ret)
+ goto close_clk;
+ usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX);
+
+ return 0;
+ }
+
+close_clk:
+ kirin_pcie_clk_ctrl(kirin_pcie, false);
+ return ret;
+}
+
+static void kirin_pcie_sideband_dbi_w_mode(struct kirin_pcie *kirin_pcie,
+ bool on)
+{
+ u32 val;
+
+ val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL0_ADDR);
+ if (on)
+ val = val | PCIE_ELBI_SLV_DBI_ENABLE;
+ else
+ val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;
+
+ kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL0_ADDR);
+}
+
+static void kirin_pcie_sideband_dbi_r_mode(struct kirin_pcie *kirin_pcie,
+ bool on)
+{
+ u32 val;
+
+ val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL1_ADDR);
+ if (on)
+ val = val | PCIE_ELBI_SLV_DBI_ENABLE;
+ else
+ val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;
+
+ kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL1_ADDR);
+}
+
+static int kirin_pcie_rd_own_conf(struct pcie_port *pp,
+ int where, int size, u32 *val)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
+ int ret;
+
+ kirin_pcie_sideband_dbi_r_mode(kirin_pcie, true);
+ ret = dw_pcie_read(pci->dbi_base + where, size, val);
+ kirin_pcie_sideband_dbi_r_mode(kirin_pcie, false);
+
+ return ret;
+}
+
+static int kirin_pcie_wr_own_conf(struct pcie_port *pp,
+ int where, int size, u32 val)
+{
+ int ret;
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
+
+ kirin_pcie_sideband_dbi_w_mode(kirin_pcie, true);
+ ret = dw_pcie_write(pci->dbi_base + where, size, val);
+ kirin_pcie_sideband_dbi_w_mode(kirin_pcie, false);
+
+ return ret;
+}
+
+static u32 kirin_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
+ u32 reg, size_t size)
+{
+ u32 ret;
+ struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
+
+ kirin_pcie_sideband_dbi_r_mode(kirin_pcie, true);
+ dw_pcie_read(base + reg, size, &ret);
+ kirin_pcie_sideband_dbi_r_mode(kirin_pcie, false);
+
+ return ret;
+}
+
+static void kirin_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base,
+ u32 reg, size_t size, u32 val)
+{
+ struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
+
+ kirin_pcie_sideband_dbi_w_mode(kirin_pcie, true);
+ dw_pcie_write(base + reg, size, val);
+ kirin_pcie_sideband_dbi_w_mode(kirin_pcie, false);
+}
+
+static int kirin_pcie_link_up(struct dw_pcie *pci)
+{
+ struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
+ u32 val = kirin_apb_ctrl_readl(kirin_pcie, PCIE_APB_PHY_STATUS0);
+
+ if ((val & PCIE_LINKUP_ENABLE) == PCIE_LINKUP_ENABLE)
+ return 1;
+
+ return 0;
+}
+
+static int kirin_pcie_establish_link(struct pcie_port *pp)
+{
+ int count = 0;
+
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
+
+ if (kirin_pcie_link_up(pci))
+ return 0;
+
+ dw_pcie_setup_rc(pp);
+
+ /* assert LTSSM enable */
+ kirin_apb_ctrl_writel(kirin_pcie, PCIE_LTSSM_ENABLE_BIT,
+ PCIE_APP_LTSSM_ENABLE);
+
+ /* check if the link is up or not */
+ while (!kirin_pcie_link_up(pci)) {
+ usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
+ count++;
+ if (count == 1000) {
+ dev_err(pci->dev, "Link Fail\n");
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
+static void kirin_pcie_host_init(struct pcie_port *pp)
+{
+ kirin_pcie_establish_link(pp);
+}
+
+static struct dw_pcie_ops kirin_dw_pcie_ops = {
+ .read_dbi = kirin_pcie_read_dbi,
+ .write_dbi = kirin_pcie_write_dbi,
+ .link_up = kirin_pcie_link_up,
+};
+
+static struct dw_pcie_host_ops kirin_pcie_host_ops = {
+ .rd_own_conf = kirin_pcie_rd_own_conf,
+ .wr_own_conf = kirin_pcie_wr_own_conf,
+ .host_init = kirin_pcie_host_init,
+};
+
+static int __init kirin_add_pcie_port(struct dw_pcie *pci,
+ struct platform_device *pdev)
+{
+ pci->pp.ops = &kirin_pcie_host_ops;
+
+ return dw_pcie_host_init(&pci->pp);
+}
+
+static int kirin_pcie_probe(struct platform_device *pdev)
+{
+ struct kirin_pcie *kirin_pcie;
+ struct dw_pcie *pci;
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ if (!pdev->dev.of_node) {
+ dev_err(&pdev->dev, "NULL node\n");
+ return -EINVAL;
+ }
+
+ kirin_pcie = devm_kzalloc(&pdev->dev,
+ sizeof(struct kirin_pcie), GFP_KERNEL);
+ if (!kirin_pcie)
+ return -ENOMEM;
+
+ pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
+ if (!pci)
+ return -ENOMEM;
+
+ pci->dev = dev;
+ pci->ops = &kirin_dw_pcie_ops;
+ kirin_pcie->pci = pci;
+
+ ret = kirin_pcie_get_clk(kirin_pcie, pdev);
+ if (ret)
+ return ret;
+
+ ret = kirin_pcie_get_resource(kirin_pcie, pdev);
+ if (ret)
+ return ret;
+
+ kirin_pcie->gpio_id_reset = of_get_named_gpio(pdev->dev.of_node,
+ "reset-gpio", 0);
+ if (kirin_pcie->gpio_id_reset < 0)
+ return -ENODEV;
+
+ ret = kirin_pcie_power_on(kirin_pcie);
+ if (ret)
+ return ret;
+
+ platform_set_drvdata(pdev, kirin_pcie);
+
+ return kirin_add_pcie_port(pci, pdev);
+}
+
+static const struct of_device_id kirin_pcie_match[] = {
+ { .compatible = "hisilicon,kirin-pcie" },
+ {},
+};
+
+struct platform_driver kirin_pcie_driver = {
+ .probe = kirin_pcie_probe,
+ .driver = {
+ .name = "kirin-pcie",
+ .of_match_table = kirin_pcie_match,
+ .suppress_bind_attrs = true,
+ },
+};
+
+builtin_platform_driver(kirin_pcie_driver);
--
2.11.GIT
--
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v6 4/4] defconfig: PCI: Enable Kirin PCIe defconfig
2017-05-24 8:12 ` Xiaowei Song
@ 2017-05-24 8:12 ` Xiaowei Song
-1 siblings, 0 replies; 18+ messages in thread
From: Xiaowei Song @ 2017-05-24 8:12 UTC (permalink / raw)
To: bhelgaas, kishon, jingoohan1, arnd, tn, keith.busch,
niklas.cassel, dhdang, liudongdong3, gabriele.paoloni, robh+dt,
mark.rutland, catalin.marinas, will.deacon
Cc: chenyao11, puck.chen, songxiaowei, guodong.xu, wangbinghui,
suzhuangluan, linux-pci, devicetree, linux-kernel
Cc: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 7c48028ec64a..d56d8f1062ab 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -71,6 +71,7 @@ CONFIG_PCI_XGENE=y
CONFIG_PCI_LAYERSCAPE=y
CONFIG_PCI_HISI=y
CONFIG_PCIE_QCOM=y
+CONFIG_PCIE_KIRIN=y
CONFIG_PCIE_ARMADA_8K=y
CONFIG_ARM64_VA_BITS_48=y
CONFIG_SCHED_MC=y
--
2.11.GIT
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v6 4/4] defconfig: PCI: Enable Kirin PCIe defconfig
@ 2017-05-24 8:12 ` Xiaowei Song
0 siblings, 0 replies; 18+ messages in thread
From: Xiaowei Song @ 2017-05-24 8:12 UTC (permalink / raw)
To: bhelgaas, kishon, jingoohan1, arnd, tn, keith.busch,
niklas.cassel, dhdang, liudongdong3, gabriele.paoloni, robh+dt,
mark.rutland, catalin.marinas, will.deacon
Cc: chenyao11, puck.chen, songxiaowei, guodong.xu, wangbinghui,
suzhuangluan, linux-pci, devicetree, linux-kernel
Cc: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 7c48028ec64a..d56d8f1062ab 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -71,6 +71,7 @@ CONFIG_PCI_XGENE=y
CONFIG_PCI_LAYERSCAPE=y
CONFIG_PCI_HISI=y
CONFIG_PCIE_QCOM=y
+CONFIG_PCIE_KIRIN=y
CONFIG_PCIE_ARMADA_8K=y
CONFIG_ARM64_VA_BITS_48=y
CONFIG_SCHED_MC=y
--
2.11.GIT
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v6 3/4] PCI: dwc: kirin: add PCIe Driver for HiSilicon Kirin SoC
2017-05-24 8:12 ` Xiaowei Song
@ 2017-05-24 11:28 ` Jingoo Han
-1 siblings, 0 replies; 18+ messages in thread
From: Jingoo Han @ 2017-05-24 11:28 UTC (permalink / raw)
To: 'Xiaowei Song'
Cc: bhelgaas, kishon, arnd, tn, keith.busch, niklas.cassel, dhdang,
liudongdong3, gabriele.paoloni, robh+dt, mark.rutland,
catalin.marinas, will.deacon, chenyao11, puck.chen, guodong.xu,
wangbinghui, suzhuangluan, linux-pci, devicetree, linux-kernel
On Wednesday, May 24, 2017 4:13 AM, Xiaowei Song wrote:
>
> Hisilicon PCIe Driver shares the common functions for PCIe dw-host
>
> The poweron functions is developed on hi3660 SoC,
> while Others Functions are common for Kirin series SoCs.
>
> Low power mode(L1 sub-state and Suspend/Resume), hotplug
> and MSI feature are not supported currently.
>
> Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
> ---
> drivers/pci/dwc/Kconfig | 10 +
> drivers/pci/dwc/Makefile | 1 +
> drivers/pci/dwc/pcie-kirin.c | 511
> +++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 522 insertions(+)
> create mode 100644 drivers/pci/dwc/pcie-kirin.c
>
> diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
> index d2d2ba5b8a68..13e617b78430 100644
> --- a/drivers/pci/dwc/Kconfig
> +++ b/drivers/pci/dwc/Kconfig
> @@ -130,4 +130,14 @@ config PCIE_ARTPEC6
> Say Y here to enable PCIe controller support on Axis ARTPEC-6
> SoCs. This PCIe controller uses the DesignWare core.
>
> +config PCIE_KIRIN
> + depends on OF && ARM64
> + bool "HiSilicon Kirin series SoCs PCIe controllers"
> + depends on PCI
> + select PCIEPORTBUS
> + select PCIE_DW_HOST
> + help
> + Say Y here if you want PCIe controller support on HiSilicon Kirin
> series SoCs
> + kirin960 SoC
> +
> endmenu
> diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
> index a2df13c28798..4bd69bacd4ab 100644
> --- a/drivers/pci/dwc/Makefile
> +++ b/drivers/pci/dwc/Makefile
> @@ -10,6 +10,7 @@ obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
> obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
> obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
> obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
> +obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
>
> # The following drivers are for devices that use the generic ACPI
> # pci_root.c driver but don't support standard ECAM config access.
> diff --git a/drivers/pci/dwc/pcie-kirin.c b/drivers/pci/dwc/pcie-kirin.c
> new file mode 100644
> index 000000000000..3a0b078e1943
> --- /dev/null
> +++ b/drivers/pci/dwc/pcie-kirin.c
> @@ -0,0 +1,511 @@
> +/*
> + * PCIe host controller driver for Kirin Phone SoCs
> + *
> + * Copyright (C) 2017 Hilisicon Electronics Co., Ltd.
> + * http://www.huawei.com
> + *
> + * Author: Xiaowei Song <songxiaowei@huawei.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <asm/compiler.h>
> +#include <linux/compiler.h>
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/gpio.h>
> +#include <linux/interrupt.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of_address.h>
> +#include <linux/of_gpio.h>
> +#include <linux/of_pci.h>
> +#include <linux/pci.h>
> +#include <linux/pci_regs.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/resource.h>
> +#include <linux/types.h>
> +#include "pcie-designware.h"
> +
> +#define to_kirin_pcie(x) dev_get_drvdata((x)->dev)
> +
> +#define REF_CLK_FREQ 100000000
> +
> +/* PCIe ELBI registers */
> +#define SOC_PCIECTRL_CTRL0_ADDR 0x000
> +#define SOC_PCIECTRL_CTRL1_ADDR 0x004
> +#define SOC_PCIEPHY_CTRL2_ADDR 0x008
> +#define SOC_PCIEPHY_CTRL3_ADDR 0x00c
> +#define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21)
> +
> +#define PCIE_APP_LTSSM_ENABLE 0x01c
> +#define PCIE_APB_PHY_CTRL0 0x0
> +#define PCIE_APB_PHY_CTRL1 0x4
> +#define PCIE_APB_PHY_STATUS0 0x400
> +#define PCIE_LINKUP_ENABLE (0x8020)
> +#define PCIE_LTSSM_ENABLE_BIT (0x1 << 11)
> +#define PIPE_CLK_STABLE (0x1 << 19)
> +#define PIPE_CLK_MAX_TRY_TIMES 10
> +#define PHY_REF_PAD_BIT (0x1 << 8)
> +#define PHY_PWR_DOWN_BIT (0x1 << 22)
> +#define PHY_RST_ACK_BIT (0x1 << 16)
> +
> +/* info lacated in sysctrl */
> +#define SCTRL_PCIE_CMOS_OFFSET 0x60
> +#define SCTRL_PCIE_CMOS_BIT 0x10
> +#define SCTRL_PCIE_ISO_OFFSET 0x44
> +#define SCTRL_PCIE_ISO_BIT 0x30
> +#define SCTRL_PCIE_HPCLK_OFFSET 0x190
> +#define SCTRL_PCIE_HPCLK_BIT 0x184000
> +#define SCTRL_PCIE_OE_OFFSET 0x14a
> +#define PCIE_DEBOUNCE_PARAM 0xF0F400
> +#define PCIE_OE_BYPASS (0x3 << 28)
> +
> +/* peri_crg ctrl */
> +#define CRGCTRL_PCIE_ASSERT_OFFSET 0x88
> +#define CRGCTRL_PCIE_ASSERT_BIT 0x8c000000
> +
> +/* Time for delay */
> +#define REF_2_PERST_MIN (20000)
> +#define REF_2_PERST_MAX (25000)
> +#define PERST_2_ACCESS_MIN (10000)
> +#define PERST_2_ACCESS_MAX (12000)
> +#define LINK_WAIT_MIN (900)
> +#define LINK_WAIT_MAX (1000)
> +#define PIPE_CLK_WAIT_MIN (550)
> +#define PIPE_CLK_WAIT_MAX (600)
Please remove unnecessary blankets as below.
#define REF_2_PERST_MIN 20000
#define REF_2_PERST_MAX 25000
.....
> +
> +struct kirin_pcie {
> + struct dw_pcie *pci;
> + void __iomem *apb_base;
> + void __iomem *phy_base;
> + struct regmap *crgctrl;
> + struct regmap *sysctrl;
> + struct clk *apb_sys_clk;
> + struct clk *apb_phy_clk;
> + struct clk *phy_ref_clk;
> + struct clk *pcie_aclk;
> + struct clk *pcie_aux_clk;
> + int gpio_id_reset;
> +};
> +
> +static inline void kirin_apb_ctrl_writel(struct kirin_pcie *kirin_pcie,
> + u32 val, u32 reg)
> +{
> + writel(val, kirin_pcie->apb_base + reg);
> +}
> +
> +static inline u32 kirin_apb_ctrl_readl(struct kirin_pcie *kirin_pcie,
> + u32 reg)
> +{
> + return readl(kirin_pcie->apb_base + reg);
> +}
> +
> +/*Registers in PCIePHY*/
> +static inline void kirin_apb_phy_writel(struct kirin_pcie *kirin_pcie,
> + u32 val, u32 reg)
> +{
> + writel(val, kirin_pcie->phy_base + reg);
> +}
> +
> +static inline u32 kirin_apb_phy_readl(struct kirin_pcie *kirin_pcie,
> + u32 reg)
> +{
> + return readl(kirin_pcie->phy_base + reg);
> +}
> +
> +static int32_t kirin_pcie_get_clk(struct kirin_pcie *kirin_pcie,
> + struct platform_device *pdev)
> +{
> + kirin_pcie->phy_ref_clk = devm_clk_get(&pdev->dev, "pcie_phy_ref");
> + if (IS_ERR(kirin_pcie->phy_ref_clk))
> + return PTR_ERR(kirin_pcie->phy_ref_clk);
> +
> + kirin_pcie->pcie_aux_clk = devm_clk_get(&pdev->dev, "pcie_aux");
> + if (IS_ERR(kirin_pcie->pcie_aux_clk))
> + return PTR_ERR(kirin_pcie->pcie_aux_clk);
> +
> + kirin_pcie->apb_phy_clk = devm_clk_get(&pdev->dev, "pcie_apb_phy");
> + if (IS_ERR(kirin_pcie->apb_phy_clk))
> + return PTR_ERR(kirin_pcie->apb_phy_clk);
> +
> + kirin_pcie->apb_sys_clk = devm_clk_get(&pdev->dev, "pcie_apb_sys");
> + if (IS_ERR(kirin_pcie->apb_sys_clk))
> + return PTR_ERR(kirin_pcie->apb_sys_clk);
> +
> + kirin_pcie->pcie_aclk = devm_clk_get(&pdev->dev, "pcie_aclk");
> + if (IS_ERR(kirin_pcie->pcie_aclk))
> + return PTR_ERR(kirin_pcie->pcie_aclk);
> +
> + return 0;
> +}
> +
> +static int32_t kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie,
> + struct platform_device *pdev)
> +{
> + struct resource *apb;
> + struct resource *phy;
> + struct resource *dbi;
> +
> + apb = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb");
> + kirin_pcie->apb_base = devm_ioremap_resource(&pdev->dev, apb);
> + if (IS_ERR(kirin_pcie->apb_base))
> + return PTR_ERR(kirin_pcie->apb_base);
> +
> + phy = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
> + kirin_pcie->phy_base = devm_ioremap_resource(&pdev->dev, phy);
> + if (IS_ERR(kirin_pcie->phy_base))
> + return PTR_ERR(kirin_pcie->phy_base);
> +
> + dbi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
> + kirin_pcie->pci->dbi_base = devm_ioremap_resource(&pdev->dev, dbi);
> + if (IS_ERR(kirin_pcie->pci->dbi_base))
> + return PTR_ERR(kirin_pcie->pci->dbi_base);
> +
> + kirin_pcie->crgctrl =
> + syscon_regmap_lookup_by_compatible("hisilicon,hi3660-
> crgctrl");
> + if (IS_ERR(kirin_pcie->crgctrl))
> + return PTR_ERR(kirin_pcie->crgctrl);
> +
> + kirin_pcie->sysctrl =
> +
syscon_regmap_lookup_by_compatible("hisilicon,hi3660-sctrl");
> + if (IS_ERR(kirin_pcie->sysctrl))
> + return PTR_ERR(kirin_pcie->sysctrl);
> +
> + return 0;
> +}
> +
> +static int kirin_pcie_phy_init(struct kirin_pcie *kirin_pcie)
> +{
> + u32 reg_val;
> + u32 time = PIPE_CLK_MAX_TRY_TIMES;
> +
> + reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1);
> + reg_val &= ~PHY_REF_PAD_BIT;
> + kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1);
> +
> + reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL0);
> + reg_val &= ~PHY_PWR_DOWN_BIT;
> + kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL0);
> + udelay(10);
> +
> + reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1);
> + reg_val &= ~PHY_RST_ACK_BIT;
> + kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1);
> +
> + usleep_range(PIPE_CLK_WAIT_MIN, PIPE_CLK_WAIT_MAX);
> + reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_STATUS0);
> + if (reg_val & PIPE_CLK_STABLE) {
> + dev_err(kirin_pcie->pci->dev, "PIPE clk is not stable\n");
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static void kirin_pcie_oe_enable(struct kirin_pcie *kirin_pcie)
> +{
> + u32 val;
> +
> + regmap_read(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, &val);
> + val |= PCIE_DEBOUNCE_PARAM;
> + val &= ~PCIE_OE_BYPASS;
> + regmap_write(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, val);
> +}
> +
> +static int kirin_pcie_clk_ctrl(struct kirin_pcie *kirin_pcie, bool
enable)
> +{
> + int ret = 0;
> +
> + if (!enable)
> + goto close_clk;
> +
> + ret = clk_set_rate(kirin_pcie->phy_ref_clk, REF_CLK_FREQ);
> + if (ret)
> + return ret;
> +
> + ret = clk_prepare_enable(kirin_pcie->phy_ref_clk);
> + if (ret)
> + return ret;
> +
> + ret = clk_prepare_enable(kirin_pcie->apb_sys_clk);
> + if (ret)
> + goto apb_sys_fail;
> +
> + ret = clk_prepare_enable(kirin_pcie->apb_phy_clk);
> + if (ret)
> + goto apb_phy_fail;
> +
> + ret = clk_prepare_enable(kirin_pcie->pcie_aclk);
> + if (ret)
> + goto aclk_fail;
> +
> + ret = clk_prepare_enable(kirin_pcie->pcie_aux_clk);
> + if (ret)
> + goto aux_clk_fail;
> +
> + return 0;
> +close_clk:
Please insert new line for readability as below.
return 0;
close_clk:
Best regards,
Jingoo Han
> + clk_disable_unprepare(kirin_pcie->pcie_aux_clk);
> +aux_clk_fail:
> + clk_disable_unprepare(kirin_pcie->pcie_aclk);
> +aclk_fail:
> + clk_disable_unprepare(kirin_pcie->apb_phy_clk);
> +apb_phy_fail:
> + clk_disable_unprepare(kirin_pcie->apb_sys_clk);
> +apb_sys_fail:
> + clk_disable_unprepare(kirin_pcie->phy_ref_clk);
> + return ret;
> +}
> +
> +static int kirin_pcie_power_on(struct kirin_pcie *kirin_pcie)
> +{
> + int ret;
> +
> + /* Power supply for Host */
> + regmap_write(kirin_pcie->sysctrl,
> + SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT);
> + udelay(100);
> + kirin_pcie_oe_enable(kirin_pcie);
> +
> + ret = kirin_pcie_clk_ctrl(kirin_pcie, true);
> + if (ret)
> + return ret;
> +
> + /* ISO disable, PCIeCtrl,PHY assert and clk gate clear */
> + regmap_write(kirin_pcie->sysctrl,
> + SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT);
> + regmap_write(kirin_pcie->crgctrl,
> + CRGCTRL_PCIE_ASSERT_OFFSET, CRGCTRL_PCIE_ASSERT_BIT);
> + regmap_write(kirin_pcie->sysctrl,
> + SCTRL_PCIE_HPCLK_OFFSET, SCTRL_PCIE_HPCLK_BIT);
> +
> + ret = kirin_pcie_phy_init(kirin_pcie);
> + if (ret)
> + goto close_clk;
> +
> + /* perst assert Endpoint */
> + if (!gpio_request(kirin_pcie->gpio_id_reset, "pcie_perst")) {
> + usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX);
> + ret = gpio_direction_output(kirin_pcie->gpio_id_reset, 1);
> + if (ret)
> + goto close_clk;
> + usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX);
> +
> + return 0;
> + }
> +
> +close_clk:
> + kirin_pcie_clk_ctrl(kirin_pcie, false);
> + return ret;
> +}
> +
> +static void kirin_pcie_sideband_dbi_w_mode(struct kirin_pcie *kirin_pcie,
> + bool on)
> +{
> + u32 val;
> +
> + val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL0_ADDR);
> + if (on)
> + val = val | PCIE_ELBI_SLV_DBI_ENABLE;
> + else
> + val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;
> +
> + kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL0_ADDR);
> +}
> +
> +static void kirin_pcie_sideband_dbi_r_mode(struct kirin_pcie *kirin_pcie,
> + bool on)
> +{
> + u32 val;
> +
> + val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL1_ADDR);
> + if (on)
> + val = val | PCIE_ELBI_SLV_DBI_ENABLE;
> + else
> + val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;
> +
> + kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL1_ADDR);
> +}
> +
> +static int kirin_pcie_rd_own_conf(struct pcie_port *pp,
> + int where, int size, u32 *val)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
> + int ret;
> +
> + kirin_pcie_sideband_dbi_r_mode(kirin_pcie, true);
> + ret = dw_pcie_read(pci->dbi_base + where, size, val);
> + kirin_pcie_sideband_dbi_r_mode(kirin_pcie, false);
> +
> + return ret;
> +}
> +
> +static int kirin_pcie_wr_own_conf(struct pcie_port *pp,
> + int where, int size, u32 val)
> +{
> + int ret;
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
> +
> + kirin_pcie_sideband_dbi_w_mode(kirin_pcie, true);
> + ret = dw_pcie_write(pci->dbi_base + where, size, val);
> + kirin_pcie_sideband_dbi_w_mode(kirin_pcie, false);
> +
> + return ret;
> +}
> +
> +static u32 kirin_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
> + u32 reg, size_t size)
> +{
> + u32 ret;
> + struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
> +
> + kirin_pcie_sideband_dbi_r_mode(kirin_pcie, true);
> + dw_pcie_read(base + reg, size, &ret);
> + kirin_pcie_sideband_dbi_r_mode(kirin_pcie, false);
> +
> + return ret;
> +}
> +
> +static void kirin_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base,
> + u32 reg, size_t size, u32 val)
> +{
> + struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
> +
> + kirin_pcie_sideband_dbi_w_mode(kirin_pcie, true);
> + dw_pcie_write(base + reg, size, val);
> + kirin_pcie_sideband_dbi_w_mode(kirin_pcie, false);
> +}
> +
> +static int kirin_pcie_link_up(struct dw_pcie *pci)
> +{
> + struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
> + u32 val = kirin_apb_ctrl_readl(kirin_pcie, PCIE_APB_PHY_STATUS0);
> +
> + if ((val & PCIE_LINKUP_ENABLE) == PCIE_LINKUP_ENABLE)
> + return 1;
> +
> + return 0;
> +}
> +
> +static int kirin_pcie_establish_link(struct pcie_port *pp)
> +{
> + int count = 0;
> +
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
> +
> + if (kirin_pcie_link_up(pci))
> + return 0;
> +
> + dw_pcie_setup_rc(pp);
> +
> + /* assert LTSSM enable */
> + kirin_apb_ctrl_writel(kirin_pcie, PCIE_LTSSM_ENABLE_BIT,
> + PCIE_APP_LTSSM_ENABLE);
> +
> + /* check if the link is up or not */
> + while (!kirin_pcie_link_up(pci)) {
> + usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
> + count++;
> + if (count == 1000) {
> + dev_err(pci->dev, "Link Fail\n");
> + return -EINVAL;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static void kirin_pcie_host_init(struct pcie_port *pp)
> +{
> + kirin_pcie_establish_link(pp);
> +}
> +
> +static struct dw_pcie_ops kirin_dw_pcie_ops = {
> + .read_dbi = kirin_pcie_read_dbi,
> + .write_dbi = kirin_pcie_write_dbi,
> + .link_up = kirin_pcie_link_up,
> +};
> +
> +static struct dw_pcie_host_ops kirin_pcie_host_ops = {
> + .rd_own_conf = kirin_pcie_rd_own_conf,
> + .wr_own_conf = kirin_pcie_wr_own_conf,
> + .host_init = kirin_pcie_host_init,
> +};
> +
> +static int __init kirin_add_pcie_port(struct dw_pcie *pci,
> + struct platform_device *pdev)
> +{
> + pci->pp.ops = &kirin_pcie_host_ops;
> +
> + return dw_pcie_host_init(&pci->pp);
> +}
> +
> +static int kirin_pcie_probe(struct platform_device *pdev)
> +{
> + struct kirin_pcie *kirin_pcie;
> + struct dw_pcie *pci;
> + struct device *dev = &pdev->dev;
> + int ret;
> +
> + if (!pdev->dev.of_node) {
> + dev_err(&pdev->dev, "NULL node\n");
> + return -EINVAL;
> + }
> +
> + kirin_pcie = devm_kzalloc(&pdev->dev,
> + sizeof(struct kirin_pcie), GFP_KERNEL);
> + if (!kirin_pcie)
> + return -ENOMEM;
> +
> + pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
> + if (!pci)
> + return -ENOMEM;
> +
> + pci->dev = dev;
> + pci->ops = &kirin_dw_pcie_ops;
> + kirin_pcie->pci = pci;
> +
> + ret = kirin_pcie_get_clk(kirin_pcie, pdev);
> + if (ret)
> + return ret;
> +
> + ret = kirin_pcie_get_resource(kirin_pcie, pdev);
> + if (ret)
> + return ret;
> +
> + kirin_pcie->gpio_id_reset = of_get_named_gpio(pdev->dev.of_node,
> + "reset-gpio", 0);
> + if (kirin_pcie->gpio_id_reset < 0)
> + return -ENODEV;
> +
> + ret = kirin_pcie_power_on(kirin_pcie);
> + if (ret)
> + return ret;
> +
> + platform_set_drvdata(pdev, kirin_pcie);
> +
> + return kirin_add_pcie_port(pci, pdev);
> +}
> +
> +static const struct of_device_id kirin_pcie_match[] = {
> + { .compatible = "hisilicon,kirin-pcie" },
> + {},
> +};
> +
> +struct platform_driver kirin_pcie_driver = {
> + .probe = kirin_pcie_probe,
> + .driver = {
> + .name = "kirin-pcie",
> + .of_match_table = kirin_pcie_match,
> + .suppress_bind_attrs = true,
> + },
> +};
> +
> +builtin_platform_driver(kirin_pcie_driver);
> --
> 2.11.GIT
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v6 3/4] PCI: dwc: kirin: add PCIe Driver for HiSilicon Kirin SoC
@ 2017-05-24 11:28 ` Jingoo Han
0 siblings, 0 replies; 18+ messages in thread
From: Jingoo Han @ 2017-05-24 11:28 UTC (permalink / raw)
To: 'Xiaowei Song'
Cc: bhelgaas, kishon, arnd, tn, keith.busch, niklas.cassel, dhdang,
liudongdong3, gabriele.paoloni, robh+dt, mark.rutland,
catalin.marinas, will.deacon, chenyao11, puck.chen, guodong.xu,
wangbinghui, suzhuangluan, linux-pci, devicetree, linux-kernel
On Wednesday, May 24, 2017 4:13 AM, Xiaowei Song wrote:
>
> Hisilicon PCIe Driver shares the common functions for PCIe dw-host
>
> The poweron functions is developed on hi3660 SoC,
> while Others Functions are common for Kirin series SoCs.
>
> Low power mode(L1 sub-state and Suspend/Resume), hotplug
> and MSI feature are not supported currently.
>
> Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
> ---
> drivers/pci/dwc/Kconfig | 10 +
> drivers/pci/dwc/Makefile | 1 +
> drivers/pci/dwc/pcie-kirin.c | 511
> +++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 522 insertions(+)
> create mode 100644 drivers/pci/dwc/pcie-kirin.c
>
> diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
> index d2d2ba5b8a68..13e617b78430 100644
> --- a/drivers/pci/dwc/Kconfig
> +++ b/drivers/pci/dwc/Kconfig
> @@ -130,4 +130,14 @@ config PCIE_ARTPEC6
> Say Y here to enable PCIe controller support on Axis ARTPEC-6
> SoCs. This PCIe controller uses the DesignWare core.
>
> +config PCIE_KIRIN
> + depends on OF && ARM64
> + bool "HiSilicon Kirin series SoCs PCIe controllers"
> + depends on PCI
> + select PCIEPORTBUS
> + select PCIE_DW_HOST
> + help
> + Say Y here if you want PCIe controller support on HiSilicon Kirin
> series SoCs
> + kirin960 SoC
> +
> endmenu
> diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
> index a2df13c28798..4bd69bacd4ab 100644
> --- a/drivers/pci/dwc/Makefile
> +++ b/drivers/pci/dwc/Makefile
> @@ -10,6 +10,7 @@ obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
> obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
> obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
> obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
> +obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
>
> # The following drivers are for devices that use the generic ACPI
> # pci_root.c driver but don't support standard ECAM config access.
> diff --git a/drivers/pci/dwc/pcie-kirin.c b/drivers/pci/dwc/pcie-kirin.c
> new file mode 100644
> index 000000000000..3a0b078e1943
> --- /dev/null
> +++ b/drivers/pci/dwc/pcie-kirin.c
> @@ -0,0 +1,511 @@
> +/*
> + * PCIe host controller driver for Kirin Phone SoCs
> + *
> + * Copyright (C) 2017 Hilisicon Electronics Co., Ltd.
> + * http://www.huawei.com
> + *
> + * Author: Xiaowei Song <songxiaowei@huawei.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <asm/compiler.h>
> +#include <linux/compiler.h>
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/gpio.h>
> +#include <linux/interrupt.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of_address.h>
> +#include <linux/of_gpio.h>
> +#include <linux/of_pci.h>
> +#include <linux/pci.h>
> +#include <linux/pci_regs.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/resource.h>
> +#include <linux/types.h>
> +#include "pcie-designware.h"
> +
> +#define to_kirin_pcie(x) dev_get_drvdata((x)->dev)
> +
> +#define REF_CLK_FREQ 100000000
> +
> +/* PCIe ELBI registers */
> +#define SOC_PCIECTRL_CTRL0_ADDR 0x000
> +#define SOC_PCIECTRL_CTRL1_ADDR 0x004
> +#define SOC_PCIEPHY_CTRL2_ADDR 0x008
> +#define SOC_PCIEPHY_CTRL3_ADDR 0x00c
> +#define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21)
> +
> +#define PCIE_APP_LTSSM_ENABLE 0x01c
> +#define PCIE_APB_PHY_CTRL0 0x0
> +#define PCIE_APB_PHY_CTRL1 0x4
> +#define PCIE_APB_PHY_STATUS0 0x400
> +#define PCIE_LINKUP_ENABLE (0x8020)
> +#define PCIE_LTSSM_ENABLE_BIT (0x1 << 11)
> +#define PIPE_CLK_STABLE (0x1 << 19)
> +#define PIPE_CLK_MAX_TRY_TIMES 10
> +#define PHY_REF_PAD_BIT (0x1 << 8)
> +#define PHY_PWR_DOWN_BIT (0x1 << 22)
> +#define PHY_RST_ACK_BIT (0x1 << 16)
> +
> +/* info lacated in sysctrl */
> +#define SCTRL_PCIE_CMOS_OFFSET 0x60
> +#define SCTRL_PCIE_CMOS_BIT 0x10
> +#define SCTRL_PCIE_ISO_OFFSET 0x44
> +#define SCTRL_PCIE_ISO_BIT 0x30
> +#define SCTRL_PCIE_HPCLK_OFFSET 0x190
> +#define SCTRL_PCIE_HPCLK_BIT 0x184000
> +#define SCTRL_PCIE_OE_OFFSET 0x14a
> +#define PCIE_DEBOUNCE_PARAM 0xF0F400
> +#define PCIE_OE_BYPASS (0x3 << 28)
> +
> +/* peri_crg ctrl */
> +#define CRGCTRL_PCIE_ASSERT_OFFSET 0x88
> +#define CRGCTRL_PCIE_ASSERT_BIT 0x8c000000
> +
> +/* Time for delay */
> +#define REF_2_PERST_MIN (20000)
> +#define REF_2_PERST_MAX (25000)
> +#define PERST_2_ACCESS_MIN (10000)
> +#define PERST_2_ACCESS_MAX (12000)
> +#define LINK_WAIT_MIN (900)
> +#define LINK_WAIT_MAX (1000)
> +#define PIPE_CLK_WAIT_MIN (550)
> +#define PIPE_CLK_WAIT_MAX (600)
Please remove unnecessary blankets as below.
#define REF_2_PERST_MIN 20000
#define REF_2_PERST_MAX 25000
.....
> +
> +struct kirin_pcie {
> + struct dw_pcie *pci;
> + void __iomem *apb_base;
> + void __iomem *phy_base;
> + struct regmap *crgctrl;
> + struct regmap *sysctrl;
> + struct clk *apb_sys_clk;
> + struct clk *apb_phy_clk;
> + struct clk *phy_ref_clk;
> + struct clk *pcie_aclk;
> + struct clk *pcie_aux_clk;
> + int gpio_id_reset;
> +};
> +
> +static inline void kirin_apb_ctrl_writel(struct kirin_pcie *kirin_pcie,
> + u32 val, u32 reg)
> +{
> + writel(val, kirin_pcie->apb_base + reg);
> +}
> +
> +static inline u32 kirin_apb_ctrl_readl(struct kirin_pcie *kirin_pcie,
> + u32 reg)
> +{
> + return readl(kirin_pcie->apb_base + reg);
> +}
> +
> +/*Registers in PCIePHY*/
> +static inline void kirin_apb_phy_writel(struct kirin_pcie *kirin_pcie,
> + u32 val, u32 reg)
> +{
> + writel(val, kirin_pcie->phy_base + reg);
> +}
> +
> +static inline u32 kirin_apb_phy_readl(struct kirin_pcie *kirin_pcie,
> + u32 reg)
> +{
> + return readl(kirin_pcie->phy_base + reg);
> +}
> +
> +static int32_t kirin_pcie_get_clk(struct kirin_pcie *kirin_pcie,
> + struct platform_device *pdev)
> +{
> + kirin_pcie->phy_ref_clk = devm_clk_get(&pdev->dev, "pcie_phy_ref");
> + if (IS_ERR(kirin_pcie->phy_ref_clk))
> + return PTR_ERR(kirin_pcie->phy_ref_clk);
> +
> + kirin_pcie->pcie_aux_clk = devm_clk_get(&pdev->dev, "pcie_aux");
> + if (IS_ERR(kirin_pcie->pcie_aux_clk))
> + return PTR_ERR(kirin_pcie->pcie_aux_clk);
> +
> + kirin_pcie->apb_phy_clk = devm_clk_get(&pdev->dev, "pcie_apb_phy");
> + if (IS_ERR(kirin_pcie->apb_phy_clk))
> + return PTR_ERR(kirin_pcie->apb_phy_clk);
> +
> + kirin_pcie->apb_sys_clk = devm_clk_get(&pdev->dev, "pcie_apb_sys");
> + if (IS_ERR(kirin_pcie->apb_sys_clk))
> + return PTR_ERR(kirin_pcie->apb_sys_clk);
> +
> + kirin_pcie->pcie_aclk = devm_clk_get(&pdev->dev, "pcie_aclk");
> + if (IS_ERR(kirin_pcie->pcie_aclk))
> + return PTR_ERR(kirin_pcie->pcie_aclk);
> +
> + return 0;
> +}
> +
> +static int32_t kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie,
> + struct platform_device *pdev)
> +{
> + struct resource *apb;
> + struct resource *phy;
> + struct resource *dbi;
> +
> + apb = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb");
> + kirin_pcie->apb_base = devm_ioremap_resource(&pdev->dev, apb);
> + if (IS_ERR(kirin_pcie->apb_base))
> + return PTR_ERR(kirin_pcie->apb_base);
> +
> + phy = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
> + kirin_pcie->phy_base = devm_ioremap_resource(&pdev->dev, phy);
> + if (IS_ERR(kirin_pcie->phy_base))
> + return PTR_ERR(kirin_pcie->phy_base);
> +
> + dbi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
> + kirin_pcie->pci->dbi_base = devm_ioremap_resource(&pdev->dev, dbi);
> + if (IS_ERR(kirin_pcie->pci->dbi_base))
> + return PTR_ERR(kirin_pcie->pci->dbi_base);
> +
> + kirin_pcie->crgctrl =
> + syscon_regmap_lookup_by_compatible("hisilicon,hi3660-
> crgctrl");
> + if (IS_ERR(kirin_pcie->crgctrl))
> + return PTR_ERR(kirin_pcie->crgctrl);
> +
> + kirin_pcie->sysctrl =
> +
syscon_regmap_lookup_by_compatible("hisilicon,hi3660-sctrl");
> + if (IS_ERR(kirin_pcie->sysctrl))
> + return PTR_ERR(kirin_pcie->sysctrl);
> +
> + return 0;
> +}
> +
> +static int kirin_pcie_phy_init(struct kirin_pcie *kirin_pcie)
> +{
> + u32 reg_val;
> + u32 time = PIPE_CLK_MAX_TRY_TIMES;
> +
> + reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1);
> + reg_val &= ~PHY_REF_PAD_BIT;
> + kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1);
> +
> + reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL0);
> + reg_val &= ~PHY_PWR_DOWN_BIT;
> + kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL0);
> + udelay(10);
> +
> + reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1);
> + reg_val &= ~PHY_RST_ACK_BIT;
> + kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1);
> +
> + usleep_range(PIPE_CLK_WAIT_MIN, PIPE_CLK_WAIT_MAX);
> + reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_STATUS0);
> + if (reg_val & PIPE_CLK_STABLE) {
> + dev_err(kirin_pcie->pci->dev, "PIPE clk is not stable\n");
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static void kirin_pcie_oe_enable(struct kirin_pcie *kirin_pcie)
> +{
> + u32 val;
> +
> + regmap_read(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, &val);
> + val |= PCIE_DEBOUNCE_PARAM;
> + val &= ~PCIE_OE_BYPASS;
> + regmap_write(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, val);
> +}
> +
> +static int kirin_pcie_clk_ctrl(struct kirin_pcie *kirin_pcie, bool
enable)
> +{
> + int ret = 0;
> +
> + if (!enable)
> + goto close_clk;
> +
> + ret = clk_set_rate(kirin_pcie->phy_ref_clk, REF_CLK_FREQ);
> + if (ret)
> + return ret;
> +
> + ret = clk_prepare_enable(kirin_pcie->phy_ref_clk);
> + if (ret)
> + return ret;
> +
> + ret = clk_prepare_enable(kirin_pcie->apb_sys_clk);
> + if (ret)
> + goto apb_sys_fail;
> +
> + ret = clk_prepare_enable(kirin_pcie->apb_phy_clk);
> + if (ret)
> + goto apb_phy_fail;
> +
> + ret = clk_prepare_enable(kirin_pcie->pcie_aclk);
> + if (ret)
> + goto aclk_fail;
> +
> + ret = clk_prepare_enable(kirin_pcie->pcie_aux_clk);
> + if (ret)
> + goto aux_clk_fail;
> +
> + return 0;
> +close_clk:
Please insert new line for readability as below.
return 0;
close_clk:
Best regards,
Jingoo Han
> + clk_disable_unprepare(kirin_pcie->pcie_aux_clk);
> +aux_clk_fail:
> + clk_disable_unprepare(kirin_pcie->pcie_aclk);
> +aclk_fail:
> + clk_disable_unprepare(kirin_pcie->apb_phy_clk);
> +apb_phy_fail:
> + clk_disable_unprepare(kirin_pcie->apb_sys_clk);
> +apb_sys_fail:
> + clk_disable_unprepare(kirin_pcie->phy_ref_clk);
> + return ret;
> +}
> +
> +static int kirin_pcie_power_on(struct kirin_pcie *kirin_pcie)
> +{
> + int ret;
> +
> + /* Power supply for Host */
> + regmap_write(kirin_pcie->sysctrl,
> + SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT);
> + udelay(100);
> + kirin_pcie_oe_enable(kirin_pcie);
> +
> + ret = kirin_pcie_clk_ctrl(kirin_pcie, true);
> + if (ret)
> + return ret;
> +
> + /* ISO disable, PCIeCtrl,PHY assert and clk gate clear */
> + regmap_write(kirin_pcie->sysctrl,
> + SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT);
> + regmap_write(kirin_pcie->crgctrl,
> + CRGCTRL_PCIE_ASSERT_OFFSET, CRGCTRL_PCIE_ASSERT_BIT);
> + regmap_write(kirin_pcie->sysctrl,
> + SCTRL_PCIE_HPCLK_OFFSET, SCTRL_PCIE_HPCLK_BIT);
> +
> + ret = kirin_pcie_phy_init(kirin_pcie);
> + if (ret)
> + goto close_clk;
> +
> + /* perst assert Endpoint */
> + if (!gpio_request(kirin_pcie->gpio_id_reset, "pcie_perst")) {
> + usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX);
> + ret = gpio_direction_output(kirin_pcie->gpio_id_reset, 1);
> + if (ret)
> + goto close_clk;
> + usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX);
> +
> + return 0;
> + }
> +
> +close_clk:
> + kirin_pcie_clk_ctrl(kirin_pcie, false);
> + return ret;
> +}
> +
> +static void kirin_pcie_sideband_dbi_w_mode(struct kirin_pcie *kirin_pcie,
> + bool on)
> +{
> + u32 val;
> +
> + val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL0_ADDR);
> + if (on)
> + val = val | PCIE_ELBI_SLV_DBI_ENABLE;
> + else
> + val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;
> +
> + kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL0_ADDR);
> +}
> +
> +static void kirin_pcie_sideband_dbi_r_mode(struct kirin_pcie *kirin_pcie,
> + bool on)
> +{
> + u32 val;
> +
> + val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL1_ADDR);
> + if (on)
> + val = val | PCIE_ELBI_SLV_DBI_ENABLE;
> + else
> + val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;
> +
> + kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL1_ADDR);
> +}
> +
> +static int kirin_pcie_rd_own_conf(struct pcie_port *pp,
> + int where, int size, u32 *val)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
> + int ret;
> +
> + kirin_pcie_sideband_dbi_r_mode(kirin_pcie, true);
> + ret = dw_pcie_read(pci->dbi_base + where, size, val);
> + kirin_pcie_sideband_dbi_r_mode(kirin_pcie, false);
> +
> + return ret;
> +}
> +
> +static int kirin_pcie_wr_own_conf(struct pcie_port *pp,
> + int where, int size, u32 val)
> +{
> + int ret;
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
> +
> + kirin_pcie_sideband_dbi_w_mode(kirin_pcie, true);
> + ret = dw_pcie_write(pci->dbi_base + where, size, val);
> + kirin_pcie_sideband_dbi_w_mode(kirin_pcie, false);
> +
> + return ret;
> +}
> +
> +static u32 kirin_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
> + u32 reg, size_t size)
> +{
> + u32 ret;
> + struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
> +
> + kirin_pcie_sideband_dbi_r_mode(kirin_pcie, true);
> + dw_pcie_read(base + reg, size, &ret);
> + kirin_pcie_sideband_dbi_r_mode(kirin_pcie, false);
> +
> + return ret;
> +}
> +
> +static void kirin_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base,
> + u32 reg, size_t size, u32 val)
> +{
> + struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
> +
> + kirin_pcie_sideband_dbi_w_mode(kirin_pcie, true);
> + dw_pcie_write(base + reg, size, val);
> + kirin_pcie_sideband_dbi_w_mode(kirin_pcie, false);
> +}
> +
> +static int kirin_pcie_link_up(struct dw_pcie *pci)
> +{
> + struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
> + u32 val = kirin_apb_ctrl_readl(kirin_pcie, PCIE_APB_PHY_STATUS0);
> +
> + if ((val & PCIE_LINKUP_ENABLE) == PCIE_LINKUP_ENABLE)
> + return 1;
> +
> + return 0;
> +}
> +
> +static int kirin_pcie_establish_link(struct pcie_port *pp)
> +{
> + int count = 0;
> +
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
> +
> + if (kirin_pcie_link_up(pci))
> + return 0;
> +
> + dw_pcie_setup_rc(pp);
> +
> + /* assert LTSSM enable */
> + kirin_apb_ctrl_writel(kirin_pcie, PCIE_LTSSM_ENABLE_BIT,
> + PCIE_APP_LTSSM_ENABLE);
> +
> + /* check if the link is up or not */
> + while (!kirin_pcie_link_up(pci)) {
> + usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
> + count++;
> + if (count == 1000) {
> + dev_err(pci->dev, "Link Fail\n");
> + return -EINVAL;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static void kirin_pcie_host_init(struct pcie_port *pp)
> +{
> + kirin_pcie_establish_link(pp);
> +}
> +
> +static struct dw_pcie_ops kirin_dw_pcie_ops = {
> + .read_dbi = kirin_pcie_read_dbi,
> + .write_dbi = kirin_pcie_write_dbi,
> + .link_up = kirin_pcie_link_up,
> +};
> +
> +static struct dw_pcie_host_ops kirin_pcie_host_ops = {
> + .rd_own_conf = kirin_pcie_rd_own_conf,
> + .wr_own_conf = kirin_pcie_wr_own_conf,
> + .host_init = kirin_pcie_host_init,
> +};
> +
> +static int __init kirin_add_pcie_port(struct dw_pcie *pci,
> + struct platform_device *pdev)
> +{
> + pci->pp.ops = &kirin_pcie_host_ops;
> +
> + return dw_pcie_host_init(&pci->pp);
> +}
> +
> +static int kirin_pcie_probe(struct platform_device *pdev)
> +{
> + struct kirin_pcie *kirin_pcie;
> + struct dw_pcie *pci;
> + struct device *dev = &pdev->dev;
> + int ret;
> +
> + if (!pdev->dev.of_node) {
> + dev_err(&pdev->dev, "NULL node\n");
> + return -EINVAL;
> + }
> +
> + kirin_pcie = devm_kzalloc(&pdev->dev,
> + sizeof(struct kirin_pcie), GFP_KERNEL);
> + if (!kirin_pcie)
> + return -ENOMEM;
> +
> + pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
> + if (!pci)
> + return -ENOMEM;
> +
> + pci->dev = dev;
> + pci->ops = &kirin_dw_pcie_ops;
> + kirin_pcie->pci = pci;
> +
> + ret = kirin_pcie_get_clk(kirin_pcie, pdev);
> + if (ret)
> + return ret;
> +
> + ret = kirin_pcie_get_resource(kirin_pcie, pdev);
> + if (ret)
> + return ret;
> +
> + kirin_pcie->gpio_id_reset = of_get_named_gpio(pdev->dev.of_node,
> + "reset-gpio", 0);
> + if (kirin_pcie->gpio_id_reset < 0)
> + return -ENODEV;
> +
> + ret = kirin_pcie_power_on(kirin_pcie);
> + if (ret)
> + return ret;
> +
> + platform_set_drvdata(pdev, kirin_pcie);
> +
> + return kirin_add_pcie_port(pci, pdev);
> +}
> +
> +static const struct of_device_id kirin_pcie_match[] = {
> + { .compatible = "hisilicon,kirin-pcie" },
> + {},
> +};
> +
> +struct platform_driver kirin_pcie_driver = {
> + .probe = kirin_pcie_probe,
> + .driver = {
> + .name = "kirin-pcie",
> + .of_match_table = kirin_pcie_match,
> + .suppress_bind_attrs = true,
> + },
> +};
> +
> +builtin_platform_driver(kirin_pcie_driver);
> --
> 2.11.GIT
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v6 0/4] DT and Driver review comments fix
2017-05-24 8:12 ` Xiaowei Song
@ 2017-05-24 11:30 ` Jingoo Han
-1 siblings, 0 replies; 18+ messages in thread
From: Jingoo Han @ 2017-05-24 11:30 UTC (permalink / raw)
To: 'Xiaowei Song'
Cc: bhelgaas, kishon, arnd, tn, keith.busch, niklas.cassel, dhdang,
liudongdong3, gabriele.paoloni, robh+dt, mark.rutland,
catalin.marinas, will.deacon, chenyao11, puck.chen, guodong.xu,
wangbinghui, suzhuangluan, linux-pci, devicetree, linux-kernel
On Wednesday, May 24, 2017 4:13 AM, Xiaowei Song wrote:
>
> Before Version Patches
> ======================
>
> patch V4
> https://www.spinics.net/lists/linux-pci/msg61406.html
>
> patch V3
> https://www.spinics.net/lists/linux-pci/msg61399.html
Hi Xiaowei Song,
I think that you need to receive 'tested-by' from other people such as
colleagues or other developers. Or, would you share the result of 'lspci'
for your HiSilicon Kirin PCIe Host controller? That will help other
maintainers to review your patches.
Best regards,
Jingoo Han
>
> Changes between V6 and V5
> =========================
> 1. seperate Document from .dtsi patch.
> 2. fix issues according to review comments
> from Bjorn Helgaas and Rob Herring: annotation stype, DT node,
> patch post method and so on.
>
> Patches list
> ============
>
> Xiaowei Song (4):
> PCI: hisi: Add DT binding for PCIe of Kirin SoC series
> arm64: dts: hisi: add kirin pcie node
> PCI: dwc: kirin: add PCIe Driver for HiSilicon Kirin SoC
> defconfig: PCI: Enable Kirin PCIe defconfig
>
> .../devicetree/bindings/pci/kirin-pcie.txt | 49 ++
> arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 31 ++
> arch/arm64/configs/defconfig | 1 +
> drivers/pci/dwc/Kconfig | 10 +
> drivers/pci/dwc/Makefile | 1 +
> drivers/pci/dwc/pcie-kirin.c | 511
> +++++++++++++++++++++
> 6 files changed, 603 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt
> create mode 100644 drivers/pci/dwc/pcie-kirin.c
>
> --
> 2.11.GIT
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v6 0/4] DT and Driver review comments fix
@ 2017-05-24 11:30 ` Jingoo Han
0 siblings, 0 replies; 18+ messages in thread
From: Jingoo Han @ 2017-05-24 11:30 UTC (permalink / raw)
To: 'Xiaowei Song'
Cc: bhelgaas, kishon, arnd, tn, keith.busch, niklas.cassel, dhdang,
liudongdong3, gabriele.paoloni, robh+dt, mark.rutland,
catalin.marinas, will.deacon, chenyao11, puck.chen, guodong.xu,
wangbinghui, suzhuangluan, linux-pci, devicetree, linux-kernel
On Wednesday, May 24, 2017 4:13 AM, Xiaowei Song wrote:
>
> Before Version Patches
> ======================
>
> patch V4
> https://www.spinics.net/lists/linux-pci/msg61406.html
>
> patch V3
> https://www.spinics.net/lists/linux-pci/msg61399.html
Hi Xiaowei Song,
I think that you need to receive 'tested-by' from other people such as
colleagues or other developers. Or, would you share the result of 'lspci'
for your HiSilicon Kirin PCIe Host controller? That will help other
maintainers to review your patches.
Best regards,
Jingoo Han
>
> Changes between V6 and V5
> =========================
> 1. seperate Document from .dtsi patch.
> 2. fix issues according to review comments
> from Bjorn Helgaas and Rob Herring: annotation stype, DT node,
> patch post method and so on.
>
> Patches list
> ============
>
> Xiaowei Song (4):
> PCI: hisi: Add DT binding for PCIe of Kirin SoC series
> arm64: dts: hisi: add kirin pcie node
> PCI: dwc: kirin: add PCIe Driver for HiSilicon Kirin SoC
> defconfig: PCI: Enable Kirin PCIe defconfig
>
> .../devicetree/bindings/pci/kirin-pcie.txt | 49 ++
> arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 31 ++
> arch/arm64/configs/defconfig | 1 +
> drivers/pci/dwc/Kconfig | 10 +
> drivers/pci/dwc/Makefile | 1 +
> drivers/pci/dwc/pcie-kirin.c | 511
> +++++++++++++++++++++
> 6 files changed, 603 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt
> create mode 100644 drivers/pci/dwc/pcie-kirin.c
>
> --
> 2.11.GIT
^ permalink raw reply [flat|nested] 18+ messages in thread
* 答复: [PATCH v6 3/4] PCI: dwc: kirin: add PCIe Driver for HiSilicon Kirin SoC
2017-05-24 11:28 ` Jingoo Han
(?)
@ 2017-05-25 0:56 ` songxiaowei
-1 siblings, 0 replies; 18+ messages in thread
From: songxiaowei @ 2017-05-25 0:56 UTC (permalink / raw)
To: Jingoo Han
Cc: bhelgaas, kishon, arnd, tn, keith.busch, niklas.cassel, dhdang,
liudongdong (C),
Gabriele Paoloni <gabriele.paoloni@huawei.com>,
robh+dt@kernel.org, mark.rutland, catalin.marinas, will.deacon,
chenyao (F), Chenfeng <puck.chen@hisilicon.com>,
guodong.xu@linaro.org (puck),
Wangbinghui, Suzhuangluan, linux-pci, devicetree, linux-kernel
Hi Jingoo
I'll fix these issues and thank a lot for your time.
Best wishes,
Xiaowei.
-----邮件原件-----
发件人: Jingoo Han [mailto:jingoohan1@gmail.com]
发送时间: 2017年5月24日 19:29
收件人: songxiaowei
抄送: bhelgaas@google.com; kishon@ti.com; arnd@arndb.de; tn@semihalf.com; keith.busch@intel.com; niklas.cassel@axis.com; dhdang@apm.com; liudongdong (C); Gabriele Paoloni; robh+dt@kernel.org; mark.rutland@arm.com; catalin.marinas@arm.com; will.deacon@arm.com; chenyao (F); Chenfeng (puck); guodong.xu@linaro.org; Wangbinghui; Suzhuangluan; linux-pci@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org
主题: Re: [PATCH v6 3/4] PCI: dwc: kirin: add PCIe Driver for HiSilicon Kirin SoC
On Wednesday, May 24, 2017 4:13 AM, Xiaowei Song wrote:
>
> Hisilicon PCIe Driver shares the common functions for PCIe dw-host
>
> The poweron functions is developed on hi3660 SoC, while Others
> Functions are common for Kirin series SoCs.
>
> Low power mode(L1 sub-state and Suspend/Resume), hotplug and MSI
> feature are not supported currently.
>
> Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
> ---
> drivers/pci/dwc/Kconfig | 10 +
> drivers/pci/dwc/Makefile | 1 +
> drivers/pci/dwc/pcie-kirin.c | 511
> +++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 522 insertions(+)
> create mode 100644 drivers/pci/dwc/pcie-kirin.c
>
> diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig index
> d2d2ba5b8a68..13e617b78430 100644
> --- a/drivers/pci/dwc/Kconfig
> +++ b/drivers/pci/dwc/Kconfig
> @@ -130,4 +130,14 @@ config PCIE_ARTPEC6
> Say Y here to enable PCIe controller support on Axis ARTPEC-6
> SoCs. This PCIe controller uses the DesignWare core.
>
> +config PCIE_KIRIN
> + depends on OF && ARM64
> + bool "HiSilicon Kirin series SoCs PCIe controllers"
> + depends on PCI
> + select PCIEPORTBUS
> + select PCIE_DW_HOST
> + help
> + Say Y here if you want PCIe controller support on HiSilicon Kirin
> series SoCs
> + kirin960 SoC
> +
> endmenu
> diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile index
> a2df13c28798..4bd69bacd4ab 100644
> --- a/drivers/pci/dwc/Makefile
> +++ b/drivers/pci/dwc/Makefile
> @@ -10,6 +10,7 @@ obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
> obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
> obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
> obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
> +obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
>
> # The following drivers are for devices that use the generic ACPI #
> pci_root.c driver but don't support standard ECAM config access.
> diff --git a/drivers/pci/dwc/pcie-kirin.c
> b/drivers/pci/dwc/pcie-kirin.c new file mode 100644 index
> 000000000000..3a0b078e1943
> --- /dev/null
> +++ b/drivers/pci/dwc/pcie-kirin.c
> @@ -0,0 +1,511 @@
> +/*
> + * PCIe host controller driver for Kirin Phone SoCs
> + *
> + * Copyright (C) 2017 Hilisicon Electronics Co., Ltd.
> + * http://www.huawei.com
> + *
> + * Author: Xiaowei Song <songxiaowei@huawei.com>
> + *
> + * This program is free software; you can redistribute it and/or
> +modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <asm/compiler.h>
> +#include <linux/compiler.h>
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/gpio.h>
> +#include <linux/interrupt.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of_address.h>
> +#include <linux/of_gpio.h>
> +#include <linux/of_pci.h>
> +#include <linux/pci.h>
> +#include <linux/pci_regs.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/resource.h>
> +#include <linux/types.h>
> +#include "pcie-designware.h"
> +
> +#define to_kirin_pcie(x) dev_get_drvdata((x)->dev)
> +
> +#define REF_CLK_FREQ 100000000
> +
> +/* PCIe ELBI registers */
> +#define SOC_PCIECTRL_CTRL0_ADDR 0x000 #define SOC_PCIECTRL_CTRL1_ADDR
> +0x004 #define SOC_PCIEPHY_CTRL2_ADDR 0x008 #define
> +SOC_PCIEPHY_CTRL3_ADDR 0x00c
> +#define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21)
> +
> +#define PCIE_APP_LTSSM_ENABLE 0x01c
> +#define PCIE_APB_PHY_CTRL0 0x0
> +#define PCIE_APB_PHY_CTRL1 0x4
> +#define PCIE_APB_PHY_STATUS0 0x400
> +#define PCIE_LINKUP_ENABLE (0x8020)
> +#define PCIE_LTSSM_ENABLE_BIT (0x1 << 11)
> +#define PIPE_CLK_STABLE (0x1 << 19)
> +#define PIPE_CLK_MAX_TRY_TIMES 10
> +#define PHY_REF_PAD_BIT (0x1 << 8)
> +#define PHY_PWR_DOWN_BIT (0x1 << 22)
> +#define PHY_RST_ACK_BIT (0x1 << 16)
> +
> +/* info lacated in sysctrl */
> +#define SCTRL_PCIE_CMOS_OFFSET 0x60
> +#define SCTRL_PCIE_CMOS_BIT 0x10
> +#define SCTRL_PCIE_ISO_OFFSET 0x44
> +#define SCTRL_PCIE_ISO_BIT 0x30
> +#define SCTRL_PCIE_HPCLK_OFFSET 0x190
> +#define SCTRL_PCIE_HPCLK_BIT 0x184000
> +#define SCTRL_PCIE_OE_OFFSET 0x14a
> +#define PCIE_DEBOUNCE_PARAM 0xF0F400
> +#define PCIE_OE_BYPASS (0x3 << 28)
> +
> +/* peri_crg ctrl */
> +#define CRGCTRL_PCIE_ASSERT_OFFSET 0x88
> +#define CRGCTRL_PCIE_ASSERT_BIT 0x8c000000
> +
> +/* Time for delay */
> +#define REF_2_PERST_MIN (20000)
> +#define REF_2_PERST_MAX (25000)
> +#define PERST_2_ACCESS_MIN (10000)
> +#define PERST_2_ACCESS_MAX (12000)
> +#define LINK_WAIT_MIN (900)
> +#define LINK_WAIT_MAX (1000)
> +#define PIPE_CLK_WAIT_MIN (550)
> +#define PIPE_CLK_WAIT_MAX (600)
Please remove unnecessary blankets as below.
#define REF_2_PERST_MIN 20000
#define REF_2_PERST_MAX 25000
.....
> +
> +struct kirin_pcie {
> + struct dw_pcie *pci;
> + void __iomem *apb_base;
> + void __iomem *phy_base;
> + struct regmap *crgctrl;
> + struct regmap *sysctrl;
> + struct clk *apb_sys_clk;
> + struct clk *apb_phy_clk;
> + struct clk *phy_ref_clk;
> + struct clk *pcie_aclk;
> + struct clk *pcie_aux_clk;
> + int gpio_id_reset;
> +};
> +
> +static inline void kirin_apb_ctrl_writel(struct kirin_pcie *kirin_pcie,
> + u32 val, u32 reg)
> +{
> + writel(val, kirin_pcie->apb_base + reg); }
> +
> +static inline u32 kirin_apb_ctrl_readl(struct kirin_pcie *kirin_pcie,
> + u32 reg)
> +{
> + return readl(kirin_pcie->apb_base + reg); }
> +
> +/*Registers in PCIePHY*/
> +static inline void kirin_apb_phy_writel(struct kirin_pcie *kirin_pcie,
> + u32 val, u32 reg)
> +{
> + writel(val, kirin_pcie->phy_base + reg); }
> +
> +static inline u32 kirin_apb_phy_readl(struct kirin_pcie *kirin_pcie,
> + u32 reg)
> +{
> + return readl(kirin_pcie->phy_base + reg); }
> +
> +static int32_t kirin_pcie_get_clk(struct kirin_pcie *kirin_pcie,
> + struct platform_device *pdev)
> +{
> + kirin_pcie->phy_ref_clk = devm_clk_get(&pdev->dev, "pcie_phy_ref");
> + if (IS_ERR(kirin_pcie->phy_ref_clk))
> + return PTR_ERR(kirin_pcie->phy_ref_clk);
> +
> + kirin_pcie->pcie_aux_clk = devm_clk_get(&pdev->dev, "pcie_aux");
> + if (IS_ERR(kirin_pcie->pcie_aux_clk))
> + return PTR_ERR(kirin_pcie->pcie_aux_clk);
> +
> + kirin_pcie->apb_phy_clk = devm_clk_get(&pdev->dev, "pcie_apb_phy");
> + if (IS_ERR(kirin_pcie->apb_phy_clk))
> + return PTR_ERR(kirin_pcie->apb_phy_clk);
> +
> + kirin_pcie->apb_sys_clk = devm_clk_get(&pdev->dev, "pcie_apb_sys");
> + if (IS_ERR(kirin_pcie->apb_sys_clk))
> + return PTR_ERR(kirin_pcie->apb_sys_clk);
> +
> + kirin_pcie->pcie_aclk = devm_clk_get(&pdev->dev, "pcie_aclk");
> + if (IS_ERR(kirin_pcie->pcie_aclk))
> + return PTR_ERR(kirin_pcie->pcie_aclk);
> +
> + return 0;
> +}
> +
> +static int32_t kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie,
> + struct platform_device *pdev)
> +{
> + struct resource *apb;
> + struct resource *phy;
> + struct resource *dbi;
> +
> + apb = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb");
> + kirin_pcie->apb_base = devm_ioremap_resource(&pdev->dev, apb);
> + if (IS_ERR(kirin_pcie->apb_base))
> + return PTR_ERR(kirin_pcie->apb_base);
> +
> + phy = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
> + kirin_pcie->phy_base = devm_ioremap_resource(&pdev->dev, phy);
> + if (IS_ERR(kirin_pcie->phy_base))
> + return PTR_ERR(kirin_pcie->phy_base);
> +
> + dbi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
> + kirin_pcie->pci->dbi_base = devm_ioremap_resource(&pdev->dev, dbi);
> + if (IS_ERR(kirin_pcie->pci->dbi_base))
> + return PTR_ERR(kirin_pcie->pci->dbi_base);
> +
> + kirin_pcie->crgctrl =
> + syscon_regmap_lookup_by_compatible("hisilicon,hi3660-
> crgctrl");
> + if (IS_ERR(kirin_pcie->crgctrl))
> + return PTR_ERR(kirin_pcie->crgctrl);
> +
> + kirin_pcie->sysctrl =
> +
syscon_regmap_lookup_by_compatible("hisilicon,hi3660-sctrl");
> + if (IS_ERR(kirin_pcie->sysctrl))
> + return PTR_ERR(kirin_pcie->sysctrl);
> +
> + return 0;
> +}
> +
> +static int kirin_pcie_phy_init(struct kirin_pcie *kirin_pcie) {
> + u32 reg_val;
> + u32 time = PIPE_CLK_MAX_TRY_TIMES;
> +
> + reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1);
> + reg_val &= ~PHY_REF_PAD_BIT;
> + kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1);
> +
> + reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL0);
> + reg_val &= ~PHY_PWR_DOWN_BIT;
> + kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL0);
> + udelay(10);
> +
> + reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1);
> + reg_val &= ~PHY_RST_ACK_BIT;
> + kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1);
> +
> + usleep_range(PIPE_CLK_WAIT_MIN, PIPE_CLK_WAIT_MAX);
> + reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_STATUS0);
> + if (reg_val & PIPE_CLK_STABLE) {
> + dev_err(kirin_pcie->pci->dev, "PIPE clk is not stable\n");
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static void kirin_pcie_oe_enable(struct kirin_pcie *kirin_pcie) {
> + u32 val;
> +
> + regmap_read(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, &val);
> + val |= PCIE_DEBOUNCE_PARAM;
> + val &= ~PCIE_OE_BYPASS;
> + regmap_write(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, val); }
> +
> +static int kirin_pcie_clk_ctrl(struct kirin_pcie *kirin_pcie, bool
enable)
> +{
> + int ret = 0;
> +
> + if (!enable)
> + goto close_clk;
> +
> + ret = clk_set_rate(kirin_pcie->phy_ref_clk, REF_CLK_FREQ);
> + if (ret)
> + return ret;
> +
> + ret = clk_prepare_enable(kirin_pcie->phy_ref_clk);
> + if (ret)
> + return ret;
> +
> + ret = clk_prepare_enable(kirin_pcie->apb_sys_clk);
> + if (ret)
> + goto apb_sys_fail;
> +
> + ret = clk_prepare_enable(kirin_pcie->apb_phy_clk);
> + if (ret)
> + goto apb_phy_fail;
> +
> + ret = clk_prepare_enable(kirin_pcie->pcie_aclk);
> + if (ret)
> + goto aclk_fail;
> +
> + ret = clk_prepare_enable(kirin_pcie->pcie_aux_clk);
> + if (ret)
> + goto aux_clk_fail;
> +
> + return 0;
> +close_clk:
Please insert new line for readability as below.
return 0;
close_clk:
Best regards,
Jingoo Han
> + clk_disable_unprepare(kirin_pcie->pcie_aux_clk);
> +aux_clk_fail:
> + clk_disable_unprepare(kirin_pcie->pcie_aclk);
> +aclk_fail:
> + clk_disable_unprepare(kirin_pcie->apb_phy_clk);
> +apb_phy_fail:
> + clk_disable_unprepare(kirin_pcie->apb_sys_clk);
> +apb_sys_fail:
> + clk_disable_unprepare(kirin_pcie->phy_ref_clk);
> + return ret;
> +}
> +
> +static int kirin_pcie_power_on(struct kirin_pcie *kirin_pcie) {
> + int ret;
> +
> + /* Power supply for Host */
> + regmap_write(kirin_pcie->sysctrl,
> + SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT);
> + udelay(100);
> + kirin_pcie_oe_enable(kirin_pcie);
> +
> + ret = kirin_pcie_clk_ctrl(kirin_pcie, true);
> + if (ret)
> + return ret;
> +
> + /* ISO disable, PCIeCtrl,PHY assert and clk gate clear */
> + regmap_write(kirin_pcie->sysctrl,
> + SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT);
> + regmap_write(kirin_pcie->crgctrl,
> + CRGCTRL_PCIE_ASSERT_OFFSET, CRGCTRL_PCIE_ASSERT_BIT);
> + regmap_write(kirin_pcie->sysctrl,
> + SCTRL_PCIE_HPCLK_OFFSET, SCTRL_PCIE_HPCLK_BIT);
> +
> + ret = kirin_pcie_phy_init(kirin_pcie);
> + if (ret)
> + goto close_clk;
> +
> + /* perst assert Endpoint */
> + if (!gpio_request(kirin_pcie->gpio_id_reset, "pcie_perst")) {
> + usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX);
> + ret = gpio_direction_output(kirin_pcie->gpio_id_reset, 1);
> + if (ret)
> + goto close_clk;
> + usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX);
> +
> + return 0;
> + }
> +
> +close_clk:
> + kirin_pcie_clk_ctrl(kirin_pcie, false);
> + return ret;
> +}
> +
> +static void kirin_pcie_sideband_dbi_w_mode(struct kirin_pcie *kirin_pcie,
> + bool on)
> +{
> + u32 val;
> +
> + val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL0_ADDR);
> + if (on)
> + val = val | PCIE_ELBI_SLV_DBI_ENABLE;
> + else
> + val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;
> +
> + kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL0_ADDR); }
> +
> +static void kirin_pcie_sideband_dbi_r_mode(struct kirin_pcie *kirin_pcie,
> + bool on)
> +{
> + u32 val;
> +
> + val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL1_ADDR);
> + if (on)
> + val = val | PCIE_ELBI_SLV_DBI_ENABLE;
> + else
> + val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;
> +
> + kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL1_ADDR); }
> +
> +static int kirin_pcie_rd_own_conf(struct pcie_port *pp,
> + int where, int size, u32 *val)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
> + int ret;
> +
> + kirin_pcie_sideband_dbi_r_mode(kirin_pcie, true);
> + ret = dw_pcie_read(pci->dbi_base + where, size, val);
> + kirin_pcie_sideband_dbi_r_mode(kirin_pcie, false);
> +
> + return ret;
> +}
> +
> +static int kirin_pcie_wr_own_conf(struct pcie_port *pp,
> + int where, int size, u32 val)
> +{
> + int ret;
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
> +
> + kirin_pcie_sideband_dbi_w_mode(kirin_pcie, true);
> + ret = dw_pcie_write(pci->dbi_base + where, size, val);
> + kirin_pcie_sideband_dbi_w_mode(kirin_pcie, false);
> +
> + return ret;
> +}
> +
> +static u32 kirin_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
> + u32 reg, size_t size)
> +{
> + u32 ret;
> + struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
> +
> + kirin_pcie_sideband_dbi_r_mode(kirin_pcie, true);
> + dw_pcie_read(base + reg, size, &ret);
> + kirin_pcie_sideband_dbi_r_mode(kirin_pcie, false);
> +
> + return ret;
> +}
> +
> +static void kirin_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base,
> + u32 reg, size_t size, u32 val)
> +{
> + struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
> +
> + kirin_pcie_sideband_dbi_w_mode(kirin_pcie, true);
> + dw_pcie_write(base + reg, size, val);
> + kirin_pcie_sideband_dbi_w_mode(kirin_pcie, false); }
> +
> +static int kirin_pcie_link_up(struct dw_pcie *pci) {
> + struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
> + u32 val = kirin_apb_ctrl_readl(kirin_pcie, PCIE_APB_PHY_STATUS0);
> +
> + if ((val & PCIE_LINKUP_ENABLE) == PCIE_LINKUP_ENABLE)
> + return 1;
> +
> + return 0;
> +}
> +
> +static int kirin_pcie_establish_link(struct pcie_port *pp) {
> + int count = 0;
> +
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
> +
> + if (kirin_pcie_link_up(pci))
> + return 0;
> +
> + dw_pcie_setup_rc(pp);
> +
> + /* assert LTSSM enable */
> + kirin_apb_ctrl_writel(kirin_pcie, PCIE_LTSSM_ENABLE_BIT,
> + PCIE_APP_LTSSM_ENABLE);
> +
> + /* check if the link is up or not */
> + while (!kirin_pcie_link_up(pci)) {
> + usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
> + count++;
> + if (count == 1000) {
> + dev_err(pci->dev, "Link Fail\n");
> + return -EINVAL;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static void kirin_pcie_host_init(struct pcie_port *pp) {
> + kirin_pcie_establish_link(pp);
> +}
> +
> +static struct dw_pcie_ops kirin_dw_pcie_ops = {
> + .read_dbi = kirin_pcie_read_dbi,
> + .write_dbi = kirin_pcie_write_dbi,
> + .link_up = kirin_pcie_link_up,
> +};
> +
> +static struct dw_pcie_host_ops kirin_pcie_host_ops = {
> + .rd_own_conf = kirin_pcie_rd_own_conf,
> + .wr_own_conf = kirin_pcie_wr_own_conf,
> + .host_init = kirin_pcie_host_init,
> +};
> +
> +static int __init kirin_add_pcie_port(struct dw_pcie *pci,
> + struct platform_device *pdev)
> +{
> + pci->pp.ops = &kirin_pcie_host_ops;
> +
> + return dw_pcie_host_init(&pci->pp);
> +}
> +
> +static int kirin_pcie_probe(struct platform_device *pdev) {
> + struct kirin_pcie *kirin_pcie;
> + struct dw_pcie *pci;
> + struct device *dev = &pdev->dev;
> + int ret;
> +
> + if (!pdev->dev.of_node) {
> + dev_err(&pdev->dev, "NULL node\n");
> + return -EINVAL;
> + }
> +
> + kirin_pcie = devm_kzalloc(&pdev->dev,
> + sizeof(struct kirin_pcie), GFP_KERNEL);
> + if (!kirin_pcie)
> + return -ENOMEM;
> +
> + pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
> + if (!pci)
> + return -ENOMEM;
> +
> + pci->dev = dev;
> + pci->ops = &kirin_dw_pcie_ops;
> + kirin_pcie->pci = pci;
> +
> + ret = kirin_pcie_get_clk(kirin_pcie, pdev);
> + if (ret)
> + return ret;
> +
> + ret = kirin_pcie_get_resource(kirin_pcie, pdev);
> + if (ret)
> + return ret;
> +
> + kirin_pcie->gpio_id_reset = of_get_named_gpio(pdev->dev.of_node,
> + "reset-gpio", 0);
> + if (kirin_pcie->gpio_id_reset < 0)
> + return -ENODEV;
> +
> + ret = kirin_pcie_power_on(kirin_pcie);
> + if (ret)
> + return ret;
> +
> + platform_set_drvdata(pdev, kirin_pcie);
> +
> + return kirin_add_pcie_port(pci, pdev); }
> +
> +static const struct of_device_id kirin_pcie_match[] = {
> + { .compatible = "hisilicon,kirin-pcie" },
> + {},
> +};
> +
> +struct platform_driver kirin_pcie_driver = {
> + .probe = kirin_pcie_probe,
> + .driver = {
> + .name = "kirin-pcie",
> + .of_match_table = kirin_pcie_match,
> + .suppress_bind_attrs = true,
> + },
> +};
> +
> +builtin_platform_driver(kirin_pcie_driver);
> --
> 2.11.GIT
^ permalink raw reply [flat|nested] 18+ messages in thread
* 答复: [PATCH v6 0/4] DT and Driver review comments fix
2017-05-24 11:30 ` Jingoo Han
(?)
@ 2017-05-25 1:05 ` songxiaowei
-1 siblings, 0 replies; 18+ messages in thread
From: songxiaowei @ 2017-05-25 1:05 UTC (permalink / raw)
To: Jingoo Han
Cc: bhelgaas, kishon, arnd, tn, keith.busch, niklas.cassel, dhdang,
liudongdong (C),
Gabriele Paoloni <gabriele.paoloni@huawei.com>,
robh+dt@kernel.org, mark.rutland, catalin.marinas, will.deacon,
chenyao (F), Chenfeng <puck.chen@hisilicon.com>,
guodong.xu@linaro.org (puck),
Wangbinghui, Suzhuangluan, linux-pci, devicetree, linux-kernel
发件人: Jingoo Han [mailto:jingoohan1@gmail.com]
发送时间: 2017年5月24日 19:31
收件人: songxiaowei
抄送: bhelgaas@google.com; kishon@ti.com; arnd@arndb.de; tn@semihalf.com; keith.busch@intel.com; niklas.cassel@axis.com; dhdang@apm.com; liudongdong (C); Gabriele Paoloni; robh+dt@kernel.org; mark.rutland@arm.com; catalin.marinas@arm.com; will.deacon@arm.com; chenyao (F); Chenfeng (puck); guodong.xu@linaro.org; Wangbinghui; Suzhuangluan; linux-pci@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org
主题: Re: [PATCH v6 0/4] DT and Driver review comments fix
On Wednesday, May 24, 2017 4:13 AM, Xiaowei Song wrote:
>
> Before Version Patches
> ======================
>
> patch V4
> https://www.spinics.net/lists/linux-pci/msg61406.html
>
> patch V3
> https://www.spinics.net/lists/linux-pci/msg61399.html
Hi Xiaowei Song,
I think that you need to receive 'tested-by' from other people such as colleagues or other developers. Or, would you share the result of 'lspci'
for your HiSilicon Kirin PCIe Host controller? That will help other maintainers to review your patches.
[songxiaowei] These patches were also sent to google engineers for Hikey960 Board produced by LeMaker, and I'll try to get their test result.
The result of 'lspci' connected with Broadcom WIFI and Intel SSD will be posted today.
Thank a lot,
-Xiaowei.
Best regards,
Jingoo Han
>
> Changes between V6 and V5
> =========================
> 1. seperate Document from .dtsi patch.
> 2. fix issues according to review comments
> from Bjorn Helgaas and Rob Herring: annotation stype, DT node,
> patch post method and so on.
>
> Patches list
> ============
>
> Xiaowei Song (4):
> PCI: hisi: Add DT binding for PCIe of Kirin SoC series
> arm64: dts: hisi: add kirin pcie node
> PCI: dwc: kirin: add PCIe Driver for HiSilicon Kirin SoC
> defconfig: PCI: Enable Kirin PCIe defconfig
>
> .../devicetree/bindings/pci/kirin-pcie.txt | 49 ++
> arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 31 ++
> arch/arm64/configs/defconfig | 1 +
> drivers/pci/dwc/Kconfig | 10 +
> drivers/pci/dwc/Makefile | 1 +
> drivers/pci/dwc/pcie-kirin.c | 511
> +++++++++++++++++++++
> 6 files changed, 603 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/pci/kirin-pcie.txt
> create mode 100644 drivers/pci/dwc/pcie-kirin.c
>
> --
> 2.11.GIT
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v6 2/4] arm64: dts: hisi: add kirin pcie node
@ 2017-05-28 6:07 ` kbuild test robot
0 siblings, 0 replies; 18+ messages in thread
From: kbuild test robot @ 2017-05-28 6:07 UTC (permalink / raw)
To: Xiaowei Song
Cc: kbuild-all, bhelgaas, kishon, jingoohan1, arnd, tn, keith.busch,
niklas.cassel, dhdang, liudongdong3, gabriele.paoloni, robh+dt,
mark.rutland, catalin.marinas, will.deacon, chenyao11, puck.chen,
songxiaowei, guodong.xu, wangbinghui, suzhuangluan, linux-pci,
devicetree, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1066 bytes --]
Hi Xiaowei,
[auto build test ERROR on pci/next]
[also build test ERROR on v4.12-rc2 next-20170526]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Xiaowei-Song/DT-and-Driver-review-comments-fix/20170525-040217
base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
config: arm64-tizen_tm2_defconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm64
All errors (new ones prefixed by >>):
>> Error: arch/arm64/boot/dts/hisilicon/hi3660.dtsi:180.24-25 syntax error
FATAL ERROR: Unable to parse input tree
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 35398 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v6 2/4] arm64: dts: hisi: add kirin pcie node
@ 2017-05-28 6:07 ` kbuild test robot
0 siblings, 0 replies; 18+ messages in thread
From: kbuild test robot @ 2017-05-28 6:07 UTC (permalink / raw)
Cc: kbuild-all-JC7UmRfGjtg, bhelgaas-hpIqsD4AKlfQT0dZR+AlfA,
kishon-l0cyMroinI0, jingoohan1-Re5JQEeQqe8AvxtiuMwx3w,
arnd-r2nGTMty4D4, tn-nYOzD4b6Jr9Wk0Htik3J/w,
keith.busch-ral2JQCrhuEAvxtiuMwx3w, niklas.cassel-VrBV9hrLPhE,
dhdang-qTEPVZfXA3Y, liudongdong3-hv44wF8Li93QT0dZR+AlfA,
gabriele.paoloni-hv44wF8Li93QT0dZR+AlfA,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
catalin.marinas-5wv7dgnIgG8, will.deacon-5wv7dgnIgG8,
chenyao11-hv44wF8Li93QT0dZR+AlfA,
puck.chen-C8/M+/jPZTeaMJb+Lgu22Q,
songxiaowei-C8/M+/jPZTeaMJb+Lgu22Q,
guodong.xu-QSEj5FYQhm4dnm+yROfE0A,
wangbinghui-C8/M+/jPZTeaMJb+Lgu22Q,
suzhuangluan-C8/M+/jPZTeaMJb+Lgu22Q,
linux-pci-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
[-- Attachment #1: Type: text/plain, Size: 1066 bytes --]
Hi Xiaowei,
[auto build test ERROR on pci/next]
[also build test ERROR on v4.12-rc2 next-20170526]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Xiaowei-Song/DT-and-Driver-review-comments-fix/20170525-040217
base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
config: arm64-tizen_tm2_defconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm64
All errors (new ones prefixed by >>):
>> Error: arch/arm64/boot/dts/hisilicon/hi3660.dtsi:180.24-25 syntax error
FATAL ERROR: Unable to parse input tree
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 35398 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2017-05-28 6:07 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-05-24 8:12 [PATCH v6 0/4] DT and Driver review comments fix Xiaowei Song
2017-05-24 8:12 ` Xiaowei Song
2017-05-24 8:12 ` [PATCH v6 1/4] PCI: hisi: Add DT binding for PCIe of Kirin SoC series Xiaowei Song
2017-05-24 8:12 ` Xiaowei Song
2017-05-24 8:12 ` [PATCH v6 2/4] arm64: dts: hisi: add kirin pcie node Xiaowei Song
2017-05-24 8:12 ` Xiaowei Song
2017-05-28 6:07 ` kbuild test robot
2017-05-28 6:07 ` kbuild test robot
2017-05-24 8:12 ` [PATCH v6 3/4] PCI: dwc: kirin: add PCIe Driver for HiSilicon Kirin SoC Xiaowei Song
2017-05-24 8:12 ` Xiaowei Song
2017-05-24 11:28 ` Jingoo Han
2017-05-24 11:28 ` Jingoo Han
2017-05-25 0:56 ` 答复: " songxiaowei
2017-05-24 8:12 ` [PATCH v6 4/4] defconfig: PCI: Enable Kirin PCIe defconfig Xiaowei Song
2017-05-24 8:12 ` Xiaowei Song
2017-05-24 11:30 ` [PATCH v6 0/4] DT and Driver review comments fix Jingoo Han
2017-05-24 11:30 ` Jingoo Han
2017-05-25 1:05 ` 答复: " songxiaowei
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