From: Alexandre Belloni <alexandre.belloni@free-electrons.com> To: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com>, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Alexandre Belloni <alexandre.belloni@free-electrons.com> Subject: [PATCH 45/58] ARM: at91: add TCB registers definitions Date: Tue, 30 May 2017 23:51:26 +0200 [thread overview] Message-ID: <20170530215139.9983-46-alexandre.belloni@free-electrons.com> (raw) In-Reply-To: <20170530215139.9983-1-alexandre.belloni@free-electrons.com> Add registers and bits definitions for the timer counter blocks found on Atmel ARM SoCs. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> --- include/soc/at91/atmel_tcb.h | 229 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 229 insertions(+) create mode 100644 include/soc/at91/atmel_tcb.h diff --git a/include/soc/at91/atmel_tcb.h b/include/soc/at91/atmel_tcb.h new file mode 100644 index 000000000000..f48e60f8ab92 --- /dev/null +++ b/include/soc/at91/atmel_tcb.h @@ -0,0 +1,229 @@ +/* + * Copyright (C) 2016 Atmel + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __SOC_ATMEL_TCB_H +#define __SOC_ATMEL_TCB_H + +/* Channel registers */ +#define ATMEL_TC_COFFS(c) ((c) * 0x40) +#define ATMEL_TC_CCR(c) ATMEL_TC_COFFS(c) +#define ATMEL_TC_CMR(c) (ATMEL_TC_COFFS(c) + 0x4) +#define ATMEL_TC_SMMR(c) (ATMEL_TC_COFFS(c) + 0x8) +#define ATMEL_TC_RAB(c) (ATMEL_TC_COFFS(c) + 0xc) +#define ATMEL_TC_CV(c) (ATMEL_TC_COFFS(c) + 0x10) +#define ATMEL_TC_RA(c) (ATMEL_TC_COFFS(c) + 0x14) +#define ATMEL_TC_RB(c) (ATMEL_TC_COFFS(c) + 0x18) +#define ATMEL_TC_RC(c) (ATMEL_TC_COFFS(c) + 0x1c) +#define ATMEL_TC_SR(c) (ATMEL_TC_COFFS(c) + 0x20) +#define ATMEL_TC_IER(c) (ATMEL_TC_COFFS(c) + 0x24) +#define ATMEL_TC_IDR(c) (ATMEL_TC_COFFS(c) + 0x28) +#define ATMEL_TC_IMR(c) (ATMEL_TC_COFFS(c) + 0x2c) +#define ATMEL_TC_EMR(c) (ATMEL_TC_COFFS(c) + 0x30) + +/* Block registers */ +#define ATMEL_TC_BCR 0xc0 +#define ATMEL_TC_BMR 0xc4 +#define ATMEL_TC_QIER 0xc8 +#define ATMEL_TC_QIDR 0xcc +#define ATMEL_TC_QIMR 0xd0 +#define ATMEL_TC_QISR 0xd4 +#define ATMEL_TC_FMR 0xd8 +#define ATMEL_TC_WPMR 0xe4 + +/* CCR fields */ +#define ATMEL_TC_CCR_CLKEN BIT(0) +#define ATMEL_TC_CCR_CLKDIS BIT(1) +#define ATMEL_TC_CCR_SWTRG BIT(2) + +/* Common CMR fields */ +#define ATMEL_TC_CMR_TCLKS_MSK GENMASK(2, 0) +#define ATMEL_TC_CMR_TCLK(x) (x) +#define ATMEL_TC_CMR_XC(x) ((x) + 5) +#define ATMEL_TC_CMR_CLKI BIT(3) +#define ATMEL_TC_CMR_BURST_MSK GENMASK(5, 4) +#define ATMEL_TC_CMR_BURST_XC(x) (((x) + 1) << 4) +#define ATMEL_TC_CMR_WAVE BIT(15) + +/* Capture mode CMR fields */ +#define ATMEL_TC_CMR_LDBSTOP BIT(6) +#define ATMEL_TC_CMR_LDBDIS BIT(7) +#define ATMEL_TC_CMR_ETRGEDG_MSK GENMASK(9, 8) +#define ATMEL_TC_CMR_ETRGEDG_NONE (0 << 8) +#define ATMEL_TC_CMR_ETRGEDG_RISING (1 << 8) +#define ATMEL_TC_CMR_ETRGEDG_FALLING (2 << 8) +#define ATMEL_TC_CMR_ETRGEDG_BOTH (3 << 8) +#define ATMEL_TC_CMR_ABETRG BIT(10) +#define ATMEL_TC_CMR_CPCTRG BIT(14) +#define ATMEL_TC_CMR_LDRA_MSK GENMASK(17, 16) +#define ATMEL_TC_CMR_LDRA_NONE (0 << 16) +#define ATMEL_TC_CMR_LDRA_RISING (1 << 16) +#define ATMEL_TC_CMR_LDRA_FALLING (2 << 16) +#define ATMEL_TC_CMR_LDRA_BOTH (3 << 16) +#define ATMEL_TC_CMR_LDRB_MSK GENMASK(19, 18) +#define ATMEL_TC_CMR_LDRB_NONE (0 << 18) +#define ATMEL_TC_CMR_LDRB_RISING (1 << 18) +#define ATMEL_TC_CMR_LDRB_FALLING (2 << 18) +#define ATMEL_TC_CMR_LDRB_BOTH (3 << 18) +#define ATMEL_TC_CMR_SBSMPLR_MSK GENMASK(22, 20) +#define ATMEL_TC_CMR_SBSMPLR(x) ((x) << 20) + +/* Waveform mode CMR fields */ +#define ATMEL_TC_CMR_CPCSTOP BIT(6) +#define ATMEL_TC_CMR_CPCDIS BIT(7) +#define ATMEL_TC_CMR_EEVTEDG_MSK GENMASK(9, 8) +#define ATMEL_TC_CMR_EEVTEDG_NONE (0 << 8) +#define ATMEL_TC_CMR_EEVTEDG_RISING (1 << 8) +#define ATMEL_TC_CMR_EEVTEDG_FALLING (2 << 8) +#define ATMEL_TC_CMR_EEVTEDG_BOTH (3 << 8) +#define ATMEL_TC_CMR_EEVT_MSK GENMASK(11, 10) +#define ATMEL_TC_CMR_EEVT_XC(x) (((x) + 1) << 10) +#define ATMEL_TC_CMR_ENETRG BIT(12) +#define ATMEL_TC_CMR_WAVESEL_MSK GENMASK(14, 13) +#define ATMEL_TC_CMR_WAVESEL_UP (0 << 13) +#define ATMEL_TC_CMR_WAVESEL_UPDOWN (1 << 13) +#define ATMEL_TC_CMR_WAVESEL_UPRC (2 << 13) +#define ATMEL_TC_CMR_WAVESEL_UPDOWNRC (3 << 13) +#define ATMEL_TC_CMR_ACPA_MSK GENMASK(17, 16) +#define ATMEL_TC_CMR_ACPA(a) (ATMEL_TC_CMR_ACTION_##a << 16) +#define ATMEL_TC_CMR_ACPC_MSK GENMASK(19, 18) +#define ATMEL_TC_CMR_ACPC(a) (ATMEL_TC_CMR_ACTION_##a << 18) +#define ATMEL_TC_CMR_AEEVT_MSK GENMASK(21, 20) +#define ATMEL_TC_CMR_AEEVT(a) (ATMEL_TC_CMR_ACTION_##a << 20) +#define ATMEL_TC_CMR_ASWTRG_MSK GENMASK(23, 22) +#define ATMEL_TC_CMR_ASWTRG(a) (ATMEL_TC_CMR_ACTION_##a << 22) +#define ATMEL_TC_CMR_BCPB_MSK GENMASK(25, 24) +#define ATMEL_TC_CMR_BCPB(a) (ATMEL_TC_CMR_ACTION_##a << 24) +#define ATMEL_TC_CMR_BCPC_MSK GENMASK(27, 26) +#define ATMEL_TC_CMR_BCPC(a) (ATMEL_TC_CMR_ACTION_##a << 26) +#define ATMEL_TC_CMR_BEEVT_MSK GENMASK(29, 28) +#define ATMEL_TC_CMR_BEEVT(a) (ATMEL_TC_CMR_ACTION_##a << 28) +#define ATMEL_TC_CMR_BSWTRG_MSK GENMASK(31, 30) +#define ATMEL_TC_CMR_BSWTRG(a) (ATMEL_TC_CMR_ACTION_##a << 30) +#define ATMEL_TC_CMR_ACTION_NONE 0 +#define ATMEL_TC_CMR_ACTION_SET 1 +#define ATMEL_TC_CMR_ACTION_CLEAR 2 +#define ATMEL_TC_CMR_ACTION_TOGGLE 3 + +/* SMMR fields */ +#define ATMEL_TC_SMMR_GCEN BIT(0) +#define ATMEL_TC_SMMR_DOWN BIT(1) + +/* SR/IER/IDR/IMR fields */ +#define ATMEL_TC_COVFS BIT(0) +#define ATMEL_TC_LOVRS BIT(1) +#define ATMEL_TC_CPAS BIT(2) +#define ATMEL_TC_CPBS BIT(3) +#define ATMEL_TC_CPCS BIT(4) +#define ATMEL_TC_LDRAS BIT(5) +#define ATMEL_TC_LDRBS BIT(6) +#define ATMEL_TC_ETRGS BIT(7) +#define ATMEL_TC_CLKSTA BIT(16) +#define ATMEL_TC_MTIOA BIT(17) +#define ATMEL_TC_MTIOB BIT(18) + +/* EMR fields */ +#define ATMEL_TC_EMR_TRIGSRCA_MSK GENMASK(1, 0) +#define ATMEL_TC_EMR_TRIGSRCA_TIOA 0 +#define ATMEL_TC_EMR_TRIGSRCA_PWMX 1 +#define ATMEL_TC_EMR_TRIGSRCB_MSK GENMASK(5, 4) +#define ATMEL_TC_EMR_TRIGSRCB_TIOB (0 << 4) +#define ATMEL_TC_EMR_TRIGSRCB_PWM (1 << 4) +#define ATMEL_TC_EMR_NOCLKDIV BIT(8) + +/* BCR fields */ +#define ATMEL_TC_BCR_SYNC BIT(0) + +/* BMR fields */ +#define ATMEL_TC_BMR_TCXC_MSK(c) GENMASK(((c) * 2) + 1, (c) * 2) +#define ATMEL_TC_BMR_TCXC(x, c) ((x) << (2 * (c))) +#define ATMEL_TC_BMR_QDEN BIT(8) +#define ATMEL_TC_BMR_POSEN BIT(9) +#define ATMEL_TC_BMR_SPEEDEN BIT(10) +#define ATMEL_TC_BMR_QDTRANS BIT(11) +#define ATMEL_TC_BMR_EDGPHA BIT(12) +#define ATMEL_TC_BMR_INVA BIT(13) +#define ATMEL_TC_BMR_INVB BIT(14) +#define ATMEL_TC_BMR_INVIDX BIT(15) +#define ATMEL_TC_BMR_SWAP BIT(16) +#define ATMEL_TC_BMR_IDXPHB BIT(17) +#define ATMEL_TC_BMR_AUTOC BIT(18) +#define ATMEL_TC_MAXFILT_MSK GENMASK(25, 20) +#define ATMEL_TC_MAXFILT(x) (((x) - 1) << 20) +#define ATMEL_TC_MAXCMP_MSK GENMASK(29, 26) +#define ATMEL_TC_MAXCMP(x) ((x) << 26) + +/* QEDC fields */ +#define ATMEL_TC_QEDC_IDX BIT(0) +#define ATMEL_TC_QEDC_DIRCHG BIT(1) +#define ATMEL_TC_QEDC_QERR BIT(2) +#define ATMEL_TC_QEDC_MPE BIT(3) +#define ATMEL_TC_QEDC_DIR BIT(8) + +/* FMR fields */ +#define ATMEL_TC_FMR_ENCF(x) BIT(x) + +/* WPMR fields */ +#define ATMEL_TC_WPMR_WPKEY (0x54494d << 8) +#define ATMEL_TC_WPMR_WPEN BIT(0) + +static inline struct clk *tcb_clk_get(struct device_node *node, int channel) +{ + struct clk *clk; + char clk_name[] = "t0_clk"; + + clk_name[1] += channel; + clk = of_clk_get_by_name(node->parent, clk_name); + if (!IS_ERR(clk)) + return clk; + + return of_clk_get_by_name(node->parent, "t0_clk"); +} + +static inline int tcb_irq_get(struct device_node *node, int channel) +{ + int irq; + + irq = of_irq_get(node->parent, channel); + if (irq > 0) + return irq; + + return of_irq_get(node->parent, 0); +} + +static const u8 atmel_tc_divisors[5] = { 2, 8, 32, 128, 0, }; + +struct atmel_tcb_info { + int bits; +}; + +static const struct atmel_tcb_info atmel_tcb_infos[] = { + { .bits = 16 }, + { .bits = 32 }, +}; + +static const struct of_device_id atmel_tcb_dt_ids[] = { + { + .compatible = "atmel,at91rm9200-tcb", + .data = &atmel_tcb_infos[0], + }, { + .compatible = "atmel,at91sam9x5-tcb", + .data = &atmel_tcb_infos[1], + }, { + /* sentinel */ + } +}; + +#endif /* __SOC_ATMEL_TCB_H */ -- 2.11.0
WARNING: multiple messages have this Message-ID (diff)
From: alexandre.belloni@free-electrons.com (Alexandre Belloni) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 45/58] ARM: at91: add TCB registers definitions Date: Tue, 30 May 2017 23:51:26 +0200 [thread overview] Message-ID: <20170530215139.9983-46-alexandre.belloni@free-electrons.com> (raw) In-Reply-To: <20170530215139.9983-1-alexandre.belloni@free-electrons.com> Add registers and bits definitions for the timer counter blocks found on Atmel ARM SoCs. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> --- include/soc/at91/atmel_tcb.h | 229 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 229 insertions(+) create mode 100644 include/soc/at91/atmel_tcb.h diff --git a/include/soc/at91/atmel_tcb.h b/include/soc/at91/atmel_tcb.h new file mode 100644 index 000000000000..f48e60f8ab92 --- /dev/null +++ b/include/soc/at91/atmel_tcb.h @@ -0,0 +1,229 @@ +/* + * Copyright (C) 2016 Atmel + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __SOC_ATMEL_TCB_H +#define __SOC_ATMEL_TCB_H + +/* Channel registers */ +#define ATMEL_TC_COFFS(c) ((c) * 0x40) +#define ATMEL_TC_CCR(c) ATMEL_TC_COFFS(c) +#define ATMEL_TC_CMR(c) (ATMEL_TC_COFFS(c) + 0x4) +#define ATMEL_TC_SMMR(c) (ATMEL_TC_COFFS(c) + 0x8) +#define ATMEL_TC_RAB(c) (ATMEL_TC_COFFS(c) + 0xc) +#define ATMEL_TC_CV(c) (ATMEL_TC_COFFS(c) + 0x10) +#define ATMEL_TC_RA(c) (ATMEL_TC_COFFS(c) + 0x14) +#define ATMEL_TC_RB(c) (ATMEL_TC_COFFS(c) + 0x18) +#define ATMEL_TC_RC(c) (ATMEL_TC_COFFS(c) + 0x1c) +#define ATMEL_TC_SR(c) (ATMEL_TC_COFFS(c) + 0x20) +#define ATMEL_TC_IER(c) (ATMEL_TC_COFFS(c) + 0x24) +#define ATMEL_TC_IDR(c) (ATMEL_TC_COFFS(c) + 0x28) +#define ATMEL_TC_IMR(c) (ATMEL_TC_COFFS(c) + 0x2c) +#define ATMEL_TC_EMR(c) (ATMEL_TC_COFFS(c) + 0x30) + +/* Block registers */ +#define ATMEL_TC_BCR 0xc0 +#define ATMEL_TC_BMR 0xc4 +#define ATMEL_TC_QIER 0xc8 +#define ATMEL_TC_QIDR 0xcc +#define ATMEL_TC_QIMR 0xd0 +#define ATMEL_TC_QISR 0xd4 +#define ATMEL_TC_FMR 0xd8 +#define ATMEL_TC_WPMR 0xe4 + +/* CCR fields */ +#define ATMEL_TC_CCR_CLKEN BIT(0) +#define ATMEL_TC_CCR_CLKDIS BIT(1) +#define ATMEL_TC_CCR_SWTRG BIT(2) + +/* Common CMR fields */ +#define ATMEL_TC_CMR_TCLKS_MSK GENMASK(2, 0) +#define ATMEL_TC_CMR_TCLK(x) (x) +#define ATMEL_TC_CMR_XC(x) ((x) + 5) +#define ATMEL_TC_CMR_CLKI BIT(3) +#define ATMEL_TC_CMR_BURST_MSK GENMASK(5, 4) +#define ATMEL_TC_CMR_BURST_XC(x) (((x) + 1) << 4) +#define ATMEL_TC_CMR_WAVE BIT(15) + +/* Capture mode CMR fields */ +#define ATMEL_TC_CMR_LDBSTOP BIT(6) +#define ATMEL_TC_CMR_LDBDIS BIT(7) +#define ATMEL_TC_CMR_ETRGEDG_MSK GENMASK(9, 8) +#define ATMEL_TC_CMR_ETRGEDG_NONE (0 << 8) +#define ATMEL_TC_CMR_ETRGEDG_RISING (1 << 8) +#define ATMEL_TC_CMR_ETRGEDG_FALLING (2 << 8) +#define ATMEL_TC_CMR_ETRGEDG_BOTH (3 << 8) +#define ATMEL_TC_CMR_ABETRG BIT(10) +#define ATMEL_TC_CMR_CPCTRG BIT(14) +#define ATMEL_TC_CMR_LDRA_MSK GENMASK(17, 16) +#define ATMEL_TC_CMR_LDRA_NONE (0 << 16) +#define ATMEL_TC_CMR_LDRA_RISING (1 << 16) +#define ATMEL_TC_CMR_LDRA_FALLING (2 << 16) +#define ATMEL_TC_CMR_LDRA_BOTH (3 << 16) +#define ATMEL_TC_CMR_LDRB_MSK GENMASK(19, 18) +#define ATMEL_TC_CMR_LDRB_NONE (0 << 18) +#define ATMEL_TC_CMR_LDRB_RISING (1 << 18) +#define ATMEL_TC_CMR_LDRB_FALLING (2 << 18) +#define ATMEL_TC_CMR_LDRB_BOTH (3 << 18) +#define ATMEL_TC_CMR_SBSMPLR_MSK GENMASK(22, 20) +#define ATMEL_TC_CMR_SBSMPLR(x) ((x) << 20) + +/* Waveform mode CMR fields */ +#define ATMEL_TC_CMR_CPCSTOP BIT(6) +#define ATMEL_TC_CMR_CPCDIS BIT(7) +#define ATMEL_TC_CMR_EEVTEDG_MSK GENMASK(9, 8) +#define ATMEL_TC_CMR_EEVTEDG_NONE (0 << 8) +#define ATMEL_TC_CMR_EEVTEDG_RISING (1 << 8) +#define ATMEL_TC_CMR_EEVTEDG_FALLING (2 << 8) +#define ATMEL_TC_CMR_EEVTEDG_BOTH (3 << 8) +#define ATMEL_TC_CMR_EEVT_MSK GENMASK(11, 10) +#define ATMEL_TC_CMR_EEVT_XC(x) (((x) + 1) << 10) +#define ATMEL_TC_CMR_ENETRG BIT(12) +#define ATMEL_TC_CMR_WAVESEL_MSK GENMASK(14, 13) +#define ATMEL_TC_CMR_WAVESEL_UP (0 << 13) +#define ATMEL_TC_CMR_WAVESEL_UPDOWN (1 << 13) +#define ATMEL_TC_CMR_WAVESEL_UPRC (2 << 13) +#define ATMEL_TC_CMR_WAVESEL_UPDOWNRC (3 << 13) +#define ATMEL_TC_CMR_ACPA_MSK GENMASK(17, 16) +#define ATMEL_TC_CMR_ACPA(a) (ATMEL_TC_CMR_ACTION_##a << 16) +#define ATMEL_TC_CMR_ACPC_MSK GENMASK(19, 18) +#define ATMEL_TC_CMR_ACPC(a) (ATMEL_TC_CMR_ACTION_##a << 18) +#define ATMEL_TC_CMR_AEEVT_MSK GENMASK(21, 20) +#define ATMEL_TC_CMR_AEEVT(a) (ATMEL_TC_CMR_ACTION_##a << 20) +#define ATMEL_TC_CMR_ASWTRG_MSK GENMASK(23, 22) +#define ATMEL_TC_CMR_ASWTRG(a) (ATMEL_TC_CMR_ACTION_##a << 22) +#define ATMEL_TC_CMR_BCPB_MSK GENMASK(25, 24) +#define ATMEL_TC_CMR_BCPB(a) (ATMEL_TC_CMR_ACTION_##a << 24) +#define ATMEL_TC_CMR_BCPC_MSK GENMASK(27, 26) +#define ATMEL_TC_CMR_BCPC(a) (ATMEL_TC_CMR_ACTION_##a << 26) +#define ATMEL_TC_CMR_BEEVT_MSK GENMASK(29, 28) +#define ATMEL_TC_CMR_BEEVT(a) (ATMEL_TC_CMR_ACTION_##a << 28) +#define ATMEL_TC_CMR_BSWTRG_MSK GENMASK(31, 30) +#define ATMEL_TC_CMR_BSWTRG(a) (ATMEL_TC_CMR_ACTION_##a << 30) +#define ATMEL_TC_CMR_ACTION_NONE 0 +#define ATMEL_TC_CMR_ACTION_SET 1 +#define ATMEL_TC_CMR_ACTION_CLEAR 2 +#define ATMEL_TC_CMR_ACTION_TOGGLE 3 + +/* SMMR fields */ +#define ATMEL_TC_SMMR_GCEN BIT(0) +#define ATMEL_TC_SMMR_DOWN BIT(1) + +/* SR/IER/IDR/IMR fields */ +#define ATMEL_TC_COVFS BIT(0) +#define ATMEL_TC_LOVRS BIT(1) +#define ATMEL_TC_CPAS BIT(2) +#define ATMEL_TC_CPBS BIT(3) +#define ATMEL_TC_CPCS BIT(4) +#define ATMEL_TC_LDRAS BIT(5) +#define ATMEL_TC_LDRBS BIT(6) +#define ATMEL_TC_ETRGS BIT(7) +#define ATMEL_TC_CLKSTA BIT(16) +#define ATMEL_TC_MTIOA BIT(17) +#define ATMEL_TC_MTIOB BIT(18) + +/* EMR fields */ +#define ATMEL_TC_EMR_TRIGSRCA_MSK GENMASK(1, 0) +#define ATMEL_TC_EMR_TRIGSRCA_TIOA 0 +#define ATMEL_TC_EMR_TRIGSRCA_PWMX 1 +#define ATMEL_TC_EMR_TRIGSRCB_MSK GENMASK(5, 4) +#define ATMEL_TC_EMR_TRIGSRCB_TIOB (0 << 4) +#define ATMEL_TC_EMR_TRIGSRCB_PWM (1 << 4) +#define ATMEL_TC_EMR_NOCLKDIV BIT(8) + +/* BCR fields */ +#define ATMEL_TC_BCR_SYNC BIT(0) + +/* BMR fields */ +#define ATMEL_TC_BMR_TCXC_MSK(c) GENMASK(((c) * 2) + 1, (c) * 2) +#define ATMEL_TC_BMR_TCXC(x, c) ((x) << (2 * (c))) +#define ATMEL_TC_BMR_QDEN BIT(8) +#define ATMEL_TC_BMR_POSEN BIT(9) +#define ATMEL_TC_BMR_SPEEDEN BIT(10) +#define ATMEL_TC_BMR_QDTRANS BIT(11) +#define ATMEL_TC_BMR_EDGPHA BIT(12) +#define ATMEL_TC_BMR_INVA BIT(13) +#define ATMEL_TC_BMR_INVB BIT(14) +#define ATMEL_TC_BMR_INVIDX BIT(15) +#define ATMEL_TC_BMR_SWAP BIT(16) +#define ATMEL_TC_BMR_IDXPHB BIT(17) +#define ATMEL_TC_BMR_AUTOC BIT(18) +#define ATMEL_TC_MAXFILT_MSK GENMASK(25, 20) +#define ATMEL_TC_MAXFILT(x) (((x) - 1) << 20) +#define ATMEL_TC_MAXCMP_MSK GENMASK(29, 26) +#define ATMEL_TC_MAXCMP(x) ((x) << 26) + +/* QEDC fields */ +#define ATMEL_TC_QEDC_IDX BIT(0) +#define ATMEL_TC_QEDC_DIRCHG BIT(1) +#define ATMEL_TC_QEDC_QERR BIT(2) +#define ATMEL_TC_QEDC_MPE BIT(3) +#define ATMEL_TC_QEDC_DIR BIT(8) + +/* FMR fields */ +#define ATMEL_TC_FMR_ENCF(x) BIT(x) + +/* WPMR fields */ +#define ATMEL_TC_WPMR_WPKEY (0x54494d << 8) +#define ATMEL_TC_WPMR_WPEN BIT(0) + +static inline struct clk *tcb_clk_get(struct device_node *node, int channel) +{ + struct clk *clk; + char clk_name[] = "t0_clk"; + + clk_name[1] += channel; + clk = of_clk_get_by_name(node->parent, clk_name); + if (!IS_ERR(clk)) + return clk; + + return of_clk_get_by_name(node->parent, "t0_clk"); +} + +static inline int tcb_irq_get(struct device_node *node, int channel) +{ + int irq; + + irq = of_irq_get(node->parent, channel); + if (irq > 0) + return irq; + + return of_irq_get(node->parent, 0); +} + +static const u8 atmel_tc_divisors[5] = { 2, 8, 32, 128, 0, }; + +struct atmel_tcb_info { + int bits; +}; + +static const struct atmel_tcb_info atmel_tcb_infos[] = { + { .bits = 16 }, + { .bits = 32 }, +}; + +static const struct of_device_id atmel_tcb_dt_ids[] = { + { + .compatible = "atmel,at91rm9200-tcb", + .data = &atmel_tcb_infos[0], + }, { + .compatible = "atmel,at91sam9x5-tcb", + .data = &atmel_tcb_infos[1], + }, { + /* sentinel */ + } +}; + +#endif /* __SOC_ATMEL_TCB_H */ -- 2.11.0
next prev parent reply other threads:[~2017-05-30 21:56 UTC|newest] Thread overview: 189+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-05-30 21:50 [PATCH 00/58] ARM: at91: rework Atmel TCB drivers Alexandre Belloni 2017-05-30 21:50 ` Alexandre Belloni 2017-05-30 21:50 ` Alexandre Belloni 2017-05-30 21:50 ` [PATCH 01/58] ARM: at91: Document new TCB bindings Alexandre Belloni 2017-05-30 21:50 ` Alexandre Belloni 2017-06-07 21:17 ` Rob Herring 2017-06-07 21:17 ` Rob Herring 2017-06-07 21:17 ` Rob Herring 2017-05-30 21:50 ` [PATCH 02/58] ARM: dts: at91: at91rm9200: TC blocks are also simple-mfd and syscon devices Alexandre Belloni 2017-05-30 21:50 ` Alexandre Belloni 2017-05-30 21:50 ` [PATCH 03/58] ARM: dts: at91: at91rm9200ek: use TCB0 as clocksource Alexandre Belloni 2017-05-30 21:50 ` Alexandre Belloni 2017-05-30 21:50 ` [PATCH 04/58] ARM: dts: at91: mpa1600: " Alexandre Belloni 2017-05-30 21:50 ` Alexandre Belloni 2017-05-30 21:50 ` [PATCH 05/58] ARM: dts: at91: at91sam9260: TC blocks are also simple-mfd and syscon devices Alexandre Belloni 2017-05-30 21:50 ` Alexandre Belloni 2017-05-30 21:50 ` [PATCH 06/58] ARM: dts: at91: at91sam9260ek: use TCB0 as clocksource Alexandre Belloni 2017-05-30 21:50 ` Alexandre Belloni 2017-05-30 21:50 ` [PATCH 07/58] ARM: dts: at91: sam9_l9260: " Alexandre Belloni 2017-05-30 21:50 ` Alexandre Belloni 2017-05-30 21:50 ` [PATCH 08/58] ARM: dts: at91: ethernut5: " Alexandre Belloni 2017-05-30 21:50 ` Alexandre Belloni 2017-05-30 21:50 ` [PATCH 09/58] ARM: dts: at91: foxg20: " Alexandre Belloni 2017-05-30 21:50 ` Alexandre Belloni 2017-05-30 21:50 ` [PATCH 10/58] ARM: dts: at91: animeo_ip: " Alexandre Belloni 2017-05-30 21:50 ` Alexandre Belloni 2017-05-30 21:50 ` [PATCH 11/58] ARM: dts: at91: kizbox: " Alexandre Belloni 2017-05-30 21:50 ` Alexandre Belloni 2017-05-30 21:50 ` [PATCH 12/58] ARM: dts: at91: at91sam9g20ek: " Alexandre Belloni 2017-05-30 21:50 ` Alexandre Belloni 2017-05-30 21:50 ` [PATCH 13/58] ARM: dts: at91: ge863-pro3: " Alexandre Belloni 2017-05-30 21:50 ` Alexandre Belloni 2017-05-30 21:50 ` [PATCH 14/58] ARM: dts: at91: at91sam9261: TC blocks are also simple-mfd and syscon devices Alexandre Belloni 2017-05-30 21:50 ` Alexandre Belloni 2017-05-30 21:50 ` [PATCH 15/58] ARM: dts: at91: at91sam9261ek: use TCB0 as clocksource Alexandre Belloni 2017-05-30 21:50 ` Alexandre Belloni 2017-05-30 21:50 ` [PATCH 16/58] ARM: dts: at91: at91sam9263: TC blocks are also simple-mfd and syscon devices Alexandre Belloni 2017-05-30 21:50 ` Alexandre Belloni 2017-05-30 21:50 ` [PATCH 17/58] ARM: dts: at91: at91sam9263ek: use TCB0 as clocksource Alexandre Belloni 2017-05-30 21:50 ` Alexandre Belloni 2017-05-30 21:50 ` [PATCH 18/58] ARM: dts: at91: calao: " Alexandre Belloni 2017-05-30 21:50 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 19/58] ARM: dts: at91: at91sam9g45: TC blocks are also simple-mfd and syscon devices Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 20/58] ARM: dts: at91: at91sam9m10g45ek: use TCB0 as clocksource Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 21/58] ARM: dts: at91: pm9g45: " Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 22/58] ARM: dts: at91: at91sam9rl: TC blocks are also simple-mfd and syscon devices Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 23/58] ARM: dts: at91: at91sam9rlek: use TCB0 as clocksource Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 24/58] ARM: dts: at91: at91sam9n12: TC blocks are also simple-mfd and syscon devices Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 25/58] ARM: dts: at91: at91sam9n12ek: use TCB0 as clocksource Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 26/58] ARM: dts: at91: at91sam9x5: TC blocks are also simple-mfd and syscon devices Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 27/58] ARM: dts: at91: at91sam9x5cm: use TCB0 as clocksource Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 28/58] ARM: dts: at91: acme/g25: " Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 29/58] ARM: dts: at91: cosino: " Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 30/58] ARM: dts: at91: kizboxmini: " Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 31/58] ARM: dts: at91: sama5d3: TC blocks are also simple-mfd and syscon devices Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 32/58] ARM: dts: at91: sama5d3xek: use TCB0 as clocksource Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 33/58] ARM: dts: at91: sama5d3 Xplained: " Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 34/58] ARM: dts: at91: kizbox2: " Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 35/58] ARM: dts: at91: sama5d3xek_cmp: " Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 36/58] ARM: dts: at91: linea/tse850-3: " Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-06-01 18:52 ` Peter Rosin 2017-06-01 18:52 ` Peter Rosin 2017-05-30 21:51 ` [PATCH 37/58] ARM: dts: at91: sama5d4: TC blocks are also simple-mfd and syscon devices Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 38/58] ARM: dts: at91: sama5d4: Add TCB2 Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 39/58] ARM: dts: at91: sama5d4ek: use TCB2 as clocksource Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 40/58] ARM: dts: at91: sama5d4 Xplained: " Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 41/58] ARM: dts: at91: ma5d4: " Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 42/58] ARM: dts: at91: vinco: " Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-06-02 12:48 ` Gregory CLEMENT 2017-06-02 12:48 ` Gregory CLEMENT 2017-05-30 21:51 ` [PATCH 43/58] ARM: dts: at91: sama5d2: TC blocks are also simple-mfd and syscon devices Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 44/58] ARM: dts: at91: sama5d2 Xplained: use TCB0 as clocksource Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni [this message] 2017-05-30 21:51 ` [PATCH 45/58] ARM: at91: add TCB registers definitions Alexandre Belloni 2017-05-30 21:51 ` [PATCH 46/58] clocksource/drivers: Add a new driver for the Atmel ARM TC blocks Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-06-06 15:21 ` Daniel Lezcano 2017-06-06 15:21 ` Daniel Lezcano 2017-06-06 18:05 ` Alexandre Belloni 2017-06-06 18:05 ` Alexandre Belloni 2017-06-07 14:17 ` Daniel Lezcano 2017-06-07 14:17 ` Daniel Lezcano 2017-06-07 15:09 ` Alexandre Belloni 2017-06-07 15:09 ` Alexandre Belloni 2017-06-07 21:38 ` Daniel Lezcano 2017-06-07 21:38 ` Daniel Lezcano 2017-06-07 23:11 ` Alexandre Belloni 2017-06-07 23:11 ` Alexandre Belloni 2017-06-08 6:52 ` Boris Brezillon 2017-06-08 6:52 ` Boris Brezillon 2017-06-07 15:27 ` Alexandre Belloni 2017-06-07 15:27 ` Alexandre Belloni 2017-06-07 21:08 ` Daniel Lezcano 2017-06-07 21:08 ` Daniel Lezcano 2017-06-07 23:17 ` Alexandre Belloni 2017-06-07 23:17 ` Alexandre Belloni 2017-06-08 5:42 ` Boris Brezillon 2017-06-08 5:42 ` Boris Brezillon 2017-06-08 5:42 ` Boris Brezillon 2017-06-08 7:44 ` Daniel Lezcano 2017-06-08 7:44 ` Daniel Lezcano 2017-06-08 7:59 ` Alexandre Belloni 2017-06-08 7:59 ` Alexandre Belloni 2017-06-08 7:59 ` Alexandre Belloni 2017-06-08 8:24 ` Daniel Lezcano 2017-06-08 8:24 ` Daniel Lezcano 2017-06-08 8:33 ` Boris Brezillon 2017-06-08 8:33 ` Boris Brezillon 2017-06-08 8:33 ` Boris Brezillon 2017-06-08 8:42 ` Alexandre Belloni 2017-06-08 8:42 ` Alexandre Belloni 2017-06-08 8:13 ` Boris Brezillon 2017-06-08 8:13 ` Boris Brezillon 2017-06-08 8:40 ` Daniel Lezcano 2017-06-08 8:40 ` Daniel Lezcano 2017-06-08 8:40 ` Daniel Lezcano 2017-06-08 8:57 ` Boris Brezillon 2017-06-08 8:57 ` Boris Brezillon 2017-06-08 8:57 ` Boris Brezillon 2017-06-12 12:54 ` Nicolas Ferre 2017-06-12 12:54 ` Nicolas Ferre 2017-06-12 12:54 ` Nicolas Ferre 2017-06-12 13:25 ` Daniel Lezcano 2017-06-12 13:25 ` Daniel Lezcano 2017-06-12 13:25 ` Daniel Lezcano 2017-06-12 15:26 ` Nicolas Ferre 2017-06-12 15:26 ` Nicolas Ferre 2017-06-12 15:26 ` Nicolas Ferre 2017-06-08 6:21 ` Boris Brezillon 2017-06-08 6:21 ` Boris Brezillon 2017-05-30 21:51 ` [PATCH 47/58] clocksource/drivers: timer-atmel-tcbclksrc: add clockevent device Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 48/58] clocksource/drivers: timer-atmel-tcbclksrc: add clockevent device on separate channel Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 49/58] clocksource/drivers: atmel-pit: allow unselecting ATMEL_PIT Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 50/58] ARM: at91/defconfig: sama5: unselect ATMEL_PIT Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 51/58] ARM: at91/defconfig: at91_dt " Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 52/58] PWM: atmel-tcb: switch to new binding Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 53/58] ARM: dts: at91: kizbox: switch to new pwm-atmel-tcb binding Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 54/58] clocksource/drivers: remove tcb_clksrc Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 55/58] misc: remove atmel_tclib.c Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 56/58] ARM: configs: at91: remove ATMEL_TCLIB Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 57/58] ARM: multi_v7_defconfig: Remove ATMEL_TCLIB Kconfig symbol Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-30 21:51 ` [PATCH 58/58] ARM: multi_v5_defconfig: " Alexandre Belloni 2017-05-30 21:51 ` Alexandre Belloni 2017-05-31 6:34 ` [PATCH 00/58] ARM: at91: rework Atmel TCB drivers Peter Rosin 2017-05-31 6:34 ` Peter Rosin 2017-05-31 6:34 ` Peter Rosin 2017-05-31 7:21 ` Alexandre Belloni 2017-05-31 7:21 ` Alexandre Belloni 2017-05-31 7:21 ` Alexandre Belloni 2017-07-06 6:40 ` Thierry Reding 2017-07-06 6:40 ` Thierry Reding 2017-07-06 6:40 ` Thierry Reding
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20170530215139.9983-46-alexandre.belloni@free-electrons.com \ --to=alexandre.belloni@free-electrons.com \ --cc=boris.brezillon@free-electrons.com \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=nicolas.ferre@microchip.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.