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From: Yi Sun <yi.y.sun@linux.intel.com>
To: Jan Beulich <JBeulich@suse.com>
Cc: kevin.tian@intel.com, wei.liu2@citrix.com,
	he.chen@linux.intel.com, andrew.cooper3@citrix.com,
	dario.faggioli@citrix.com, ian.jackson@eu.citrix.com,
	mengxu@cis.upenn.edu, xen-devel@lists.xenproject.org,
	chao.p.peng@linux.intel.com, roger.pau@citrix.com
Subject: Re: [PATCH v11 05/23] x86: refactor psr: L3 CAT: implement Domain init/free and schedule flows.
Date: Wed, 31 May 2017 14:37:10 +0800	[thread overview]
Message-ID: <20170531063710.GC3420@yi.y.sun> (raw)
In-Reply-To: <592D8F3F020000780015DA45@prv-mh.provo.novell.com>

On 17-05-30 07:26:55, Jan Beulich wrote:
> >>> On 03.05.17 at 10:44, <yi.y.sun@linux.intel.com> wrote:
> > +static unsigned int get_max_cos_max(const struct psr_socket_info *info)
> > +{
> > +    unsigned int cos_max = 0, i;
> > +
> > +    for ( i = 0; i < PSR_SOCKET_FEAT_NUM; i++ )
> > +    {
> > +        const struct feat_node *feat = info->features[i];
> > +        if ( !feat )
> 
> Blank line between declaration(s) and statement(s) please.
> 
> > +            continue;
> > +
> > +        cos_max = max(feat->cos_max, cos_max);
> 
> And you're likely better off inverting the condition and dropping
> the "continue".
> 
Will modify the above points.

> > +static void psr_assoc_cos(uint64_t *reg, unsigned int cos,
> > +                          uint64_t cos_mask)
> > +{
> > +    *reg = (*reg & ~cos_mask) |
> > +            (((uint64_t)cos << PSR_ASSOC_REG_SHIFT) & cos_mask);
> > +}
> 
> Indirection is normally only needed if a function needs to return
> more than one value. Is there a reason you can't have this one
> return the computed result?
> 
This is inherited from old code. I think it is to avoid indentation issue in
caller below. Anyway, I will modify it according to your comment.

> > @@ -376,6 +412,14 @@ void psr_ctxt_switch_to(struct domain *d)
> >      if ( psr_cmt_enabled() )
> >          psr_assoc_rmid(&reg, d->arch.psr_rmid);
> >  
> > +    /* IDLE domain's 'psr_cos_ids' is NULL so we set default value for it. */
> > +    if ( psra->cos_mask )
> > +        psr_assoc_cos(&reg,
> > +                      d->arch.psr_cos_ids ?
> > +                      d->arch.psr_cos_ids[cpu_to_socket(smp_processor_id())] :
> > +                      0,
> 
> While this doesn't really conflict with our coding style, it makes
> reading harder than necessary. Please use either
> 
>     if ( psra->cos_mask )
>         psr_assoc_cos(&reg,
>                       (d->arch.psr_cos_ids ?
>                        d->arch.psr_cos_ids[cpu_to_socket(smp_processor_id())] :
>                        0),
> 
> or
> 
>     if ( psra->cos_mask )
>         psr_assoc_cos(&reg,
>                       d->arch.psr_cos_ids
>                       ? d->arch.psr_cos_ids[cpu_to_socket(smp_processor_id())]
>                       : 0,
> 
> to allow immediate recognition that it is a single argument's expression
> that spans three lines.
> 
Thank you!

> As to the idle domain aspect - is there a strict need to write a new
> value for the idle domain at all? I.e. can't you just skip the write in
> that case, knowing you'll write a proper value anyway once the
> next non-idle vCPU gets scheduled here? Which then raises the
> question on d->arch.psr_cos_ids being NULL - is that strictly only
> possible for the idle domain, or are there also other cases? This
> determines how the if() condition should be re-written ...
> 
I agree with you that IDLE domain can be skipped. But considering that some
domains' 'psr_cos_ids' may fail to be allocated, we have to set default value
for these domains. So, I think we should keep this but skip IDLE domain in
'psr_ctxt_switch_to' caller.

> > @@ -401,14 +445,37 @@ int psr_set_l3_cbm(struct domain *d, unsigned int socket,
> >      return 0;
> >  }
> >  
> > -int psr_domain_init(struct domain *d)
> > +/* Called with domain lock held, no extra lock needed for 'psr_cos_ids' */
> > +static void psr_free_cos(struct domain *d)
> > +{
> > +    xfree(d->arch.psr_cos_ids);
> > +    d->arch.psr_cos_ids = NULL;
> > +}
> > +
> > +static int psr_alloc_cos(struct domain *d)
> >  {
> > +    d->arch.psr_cos_ids = xzalloc_array(unsigned int, nr_sockets);
> > +    if ( !d->arch.psr_cos_ids )
> > +        return -ENOMEM;
> > +
> >      return 0;
> >  }
> >  
> > +int psr_domain_init(struct domain *d)
> > +{
> > +    /* Init to success value */
> > +    int ret = 0;
> > +
> > +    if ( psr_alloc_feat_enabled() )
> > +        ret = psr_alloc_cos(d);
> > +
> > +    return ret;
> > +}
> 
> Along the lines of the above - do we really need to fail domain
> creation if we can't alloc psr_cos_ids? Granted there'll be other
> allocation failures, but from an abstract pov this is an optional
> feature, and hence the domain could do fine without.
> 
Ok, will modiy related codes.

> Jan

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  reply	other threads:[~2017-05-31  6:37 UTC|newest]

Thread overview: 74+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-05-03  8:44 [PATCH v11 00/23] Enable L2 Cache Allocation Technology & Refactor psr.c Yi Sun
2017-05-03  8:44 ` [PATCH v11 01/23] docs: create Cache Allocation Technology (CAT) and Code and Data Prioritization (CDP) feature document Yi Sun
2017-05-03  8:44 ` [PATCH v11 02/23] x86: move cpuid_count_leaf from cpuid.c to processor.h Yi Sun
2017-05-03  8:44 ` [PATCH v11 03/23] x86: refactor psr: remove L3 CAT/CDP codes Yi Sun
2017-05-03  8:44 ` [PATCH v11 04/23] x86: refactor psr: L3 CAT: implement main data structures, CPU init and free flows Yi Sun
2017-05-30 13:05   ` Jan Beulich
2017-05-31  2:44     ` Yi Sun
2017-05-31  6:02       ` Jan Beulich
2017-05-31  9:36   ` Jan Beulich
2017-06-01  3:18     ` Yi Sun
2017-06-01  6:57       ` Jan Beulich
2017-05-03  8:44 ` [PATCH v11 05/23] x86: refactor psr: L3 CAT: implement Domain init/free and schedule flows Yi Sun
2017-05-30 13:26   ` Jan Beulich
2017-05-31  6:37     ` Yi Sun [this message]
2017-05-31  6:57       ` Jan Beulich
2017-05-03  8:44 ` [PATCH v11 06/23] x86: refactor psr: L3 CAT: implement get hw info flow Yi Sun
2017-05-30 13:51   ` Jan Beulich
2017-05-03  8:44 ` [PATCH v11 07/23] x86: refactor psr: L3 CAT: implement get value flow Yi Sun
2017-05-30 14:05   ` Jan Beulich
2017-05-31  7:30     ` Yi Sun
2017-05-31  7:45       ` Jan Beulich
2017-05-31  8:05         ` Yi Sun
2017-05-31  8:10           ` Jan Beulich
2017-06-01  3:14             ` Yi Sun
2017-05-03  8:44 ` [PATCH v11 08/23] x86: refactor psr: L3 CAT: set value: implement framework Yi Sun
2017-05-30 14:32   ` Jan Beulich
2017-06-01 10:00     ` Yi Sun
2017-06-01 10:45       ` Jan Beulich
2017-06-02  2:49         ` Yi Sun
2017-06-06  7:43           ` Jan Beulich
2017-06-06  8:18             ` Yi Sun
2017-06-06  8:39               ` Jan Beulich
2017-05-03  8:44 ` [PATCH v11 09/23] x86: refactor psr: L3 CAT: set value: assemble features value array Yi Sun
2017-05-30 15:17   ` Jan Beulich
2017-05-03  8:44 ` [PATCH v11 10/23] x86: refactor psr: L3 CAT: set value: implement cos finding flow Yi Sun
2017-05-30 15:23   ` Jan Beulich
2017-05-03  8:44 ` [PATCH v11 11/23] x86: refactor psr: L3 CAT: set value: implement cos id picking flow Yi Sun
2017-05-03  8:44 ` [PATCH v11 12/23] x86: refactor psr: L3 CAT: set value: implement write msr flow Yi Sun
2017-05-30 15:35   ` Jan Beulich
2017-06-05  8:10     ` Yi Sun
2017-05-03  8:44 ` [PATCH v11 13/23] x86: refactor psr: CDP: implement CPU init flow Yi Sun
2017-05-31  9:37   ` Jan Beulich
2017-06-02  7:26     ` Yi Sun
2017-06-06  7:45       ` Jan Beulich
2017-06-06  8:13         ` Yi Sun
2017-06-06  8:38           ` Jan Beulich
2017-06-07  1:31             ` Yi Sun
2017-06-07  7:28               ` Yi Sun
2017-06-07  8:14               ` Jan Beulich
2017-06-07  9:00                 ` Yi Sun
2017-05-03  8:44 ` [PATCH v11 14/23] x86: refactor psr: CDP: implement get hw info flow Yi Sun
2017-05-31  9:40   ` Jan Beulich
2017-06-05  8:09     ` Yi Sun
2017-05-03  8:44 ` [PATCH v11 15/23] x86: refactor psr: CDP: implement set value callback function Yi Sun
2017-05-31  9:44   ` Jan Beulich
2017-06-02  7:59     ` Yi Sun
2017-06-06  7:48       ` Jan Beulich
2017-06-06  8:22         ` Yi Sun
2017-06-06  8:43           ` Jan Beulich
2017-06-06 10:43             ` Yi Sun
2017-06-06 10:49               ` Jan Beulich
2017-05-03  8:44 ` [PATCH v11 16/23] x86: L2 CAT: implement CPU init flow Yi Sun
2017-05-03  8:44 ` [PATCH v11 17/23] x86: L2 CAT: implement get hw info flow Yi Sun
2017-05-03  8:44 ` [PATCH v11 18/23] x86: L2 CAT: implement get value flow Yi Sun
2017-05-31  9:51   ` Jan Beulich
2017-05-03  8:44 ` [PATCH v11 19/23] x86: L2 CAT: implement set " Yi Sun
2017-05-31  9:52   ` Jan Beulich
2017-05-03  8:44 ` [PATCH v11 20/23] tools: L2 CAT: support get HW info for L2 CAT Yi Sun
2017-05-11 12:39   ` Wei Liu
2017-05-03  8:44 ` [PATCH v11 21/23] tools: L2 CAT: support show cbm " Yi Sun
2017-05-11 12:40   ` Wei Liu
2017-05-03  8:44 ` [PATCH v11 22/23] tools: L2 CAT: support set " Yi Sun
2017-05-11 12:43   ` Wei Liu
2017-05-03  8:44 ` [PATCH v11 23/23] docs: add L2 CAT description in docs Yi Sun

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