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From: Yi Sun <yi.y.sun@linux.intel.com>
To: Jan Beulich <JBeulich@suse.com>
Cc: kevin.tian@intel.com, wei.liu2@citrix.com,
	he.chen@linux.intel.com, andrew.cooper3@citrix.com,
	dario.faggioli@citrix.com, ian.jackson@eu.citrix.com,
	mengxu@cis.upenn.edu, xen-devel@lists.xenproject.org,
	chao.p.peng@linux.intel.com, roger.pau@citrix.com
Subject: Re: [PATCH v11 13/23] x86: refactor psr: CDP: implement CPU init flow.
Date: Wed, 7 Jun 2017 17:00:56 +0800	[thread overview]
Message-ID: <20170607090056.GW3420@yi.y.sun> (raw)
In-Reply-To: <5937D20202000078001602B9@prv-mh.provo.novell.com>

On 17-06-07 02:14:26, Jan Beulich wrote:
> >>> On 07.06.17 at 03:31, <yi.y.sun@linux.intel.com> wrote:
> > On 17-06-06 02:38:27, Jan Beulich wrote:
> >> >>> On 06.06.17 at 10:13, <yi.y.sun@linux.intel.com> wrote:
> >> > On 17-06-06 01:45:11, Jan Beulich wrote:
> >> >> >>> On 02.06.17 at 09:26, <yi.y.sun@linux.intel.com> wrote:
> >> >> > On 17-05-31 03:37:48, Jan Beulich wrote:
> >> >> >> >>> On 03.05.17 at 10:44, <yi.y.sun@linux.intel.com> wrote:
> >> >> >> > +        /* Cut half of cos_max when CDP is enabled. */
> >> >> >> > +        feat->cos_max >>= 1;
> >> >> >> > +
> >> >> >> > +        /* We only write mask1 since mask0 is always all ones by default. */
> >> >> >> 
> >> >> >> Is this, btw, just reset state or even guaranteed after offlining
> >> >> >> and re-onlining a CPU?
> >> >> >> 
> >> >> > Below MSRs are all per socket. So, we just need reset them when socket is
> >> >> > online.
> >> >> 
> >> >> Which I hope you've understood then means the comment and
> >> >> presumably also the code here need further refinement.
> >> >> 
> >> > Spec states it below. So, the mask0 is guranteed.
> >> > "the default mask in IA32_L3_MASK_0 - which is all “1”s (on reset)"
> >> 
> >> Sigh. I did ask very clearly (and this is still visible above) about
> >> the case where the CPU did _not_ undergo a reset cycle.
> >> 
> > Sorry, I think I must mis-understand your question. SW never modifies value
> > of COS ID 0 mask register. So, the value in mask0 will not be changed after
> > socket first online (mask0 is set to default by HW this time). So, we think
> > it is not necessary to restore mask0 value to default here.
> 
> Is the register read-only? If so, writing it would indeed be
> unnecessary (and likely wrong, as it might raise #GP then
> instead of being ignored). If not, firmware may have written it,
> so you'll want to write it even during boot time CPU bringup.
> 
No, it is writable. I will restore mask0 to default value here.
Furthermore, for L3/L2 CAT mask0, we may need to restore mask0
too.

> Jan

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  reply	other threads:[~2017-06-07  9:01 UTC|newest]

Thread overview: 74+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-05-03  8:44 [PATCH v11 00/23] Enable L2 Cache Allocation Technology & Refactor psr.c Yi Sun
2017-05-03  8:44 ` [PATCH v11 01/23] docs: create Cache Allocation Technology (CAT) and Code and Data Prioritization (CDP) feature document Yi Sun
2017-05-03  8:44 ` [PATCH v11 02/23] x86: move cpuid_count_leaf from cpuid.c to processor.h Yi Sun
2017-05-03  8:44 ` [PATCH v11 03/23] x86: refactor psr: remove L3 CAT/CDP codes Yi Sun
2017-05-03  8:44 ` [PATCH v11 04/23] x86: refactor psr: L3 CAT: implement main data structures, CPU init and free flows Yi Sun
2017-05-30 13:05   ` Jan Beulich
2017-05-31  2:44     ` Yi Sun
2017-05-31  6:02       ` Jan Beulich
2017-05-31  9:36   ` Jan Beulich
2017-06-01  3:18     ` Yi Sun
2017-06-01  6:57       ` Jan Beulich
2017-05-03  8:44 ` [PATCH v11 05/23] x86: refactor psr: L3 CAT: implement Domain init/free and schedule flows Yi Sun
2017-05-30 13:26   ` Jan Beulich
2017-05-31  6:37     ` Yi Sun
2017-05-31  6:57       ` Jan Beulich
2017-05-03  8:44 ` [PATCH v11 06/23] x86: refactor psr: L3 CAT: implement get hw info flow Yi Sun
2017-05-30 13:51   ` Jan Beulich
2017-05-03  8:44 ` [PATCH v11 07/23] x86: refactor psr: L3 CAT: implement get value flow Yi Sun
2017-05-30 14:05   ` Jan Beulich
2017-05-31  7:30     ` Yi Sun
2017-05-31  7:45       ` Jan Beulich
2017-05-31  8:05         ` Yi Sun
2017-05-31  8:10           ` Jan Beulich
2017-06-01  3:14             ` Yi Sun
2017-05-03  8:44 ` [PATCH v11 08/23] x86: refactor psr: L3 CAT: set value: implement framework Yi Sun
2017-05-30 14:32   ` Jan Beulich
2017-06-01 10:00     ` Yi Sun
2017-06-01 10:45       ` Jan Beulich
2017-06-02  2:49         ` Yi Sun
2017-06-06  7:43           ` Jan Beulich
2017-06-06  8:18             ` Yi Sun
2017-06-06  8:39               ` Jan Beulich
2017-05-03  8:44 ` [PATCH v11 09/23] x86: refactor psr: L3 CAT: set value: assemble features value array Yi Sun
2017-05-30 15:17   ` Jan Beulich
2017-05-03  8:44 ` [PATCH v11 10/23] x86: refactor psr: L3 CAT: set value: implement cos finding flow Yi Sun
2017-05-30 15:23   ` Jan Beulich
2017-05-03  8:44 ` [PATCH v11 11/23] x86: refactor psr: L3 CAT: set value: implement cos id picking flow Yi Sun
2017-05-03  8:44 ` [PATCH v11 12/23] x86: refactor psr: L3 CAT: set value: implement write msr flow Yi Sun
2017-05-30 15:35   ` Jan Beulich
2017-06-05  8:10     ` Yi Sun
2017-05-03  8:44 ` [PATCH v11 13/23] x86: refactor psr: CDP: implement CPU init flow Yi Sun
2017-05-31  9:37   ` Jan Beulich
2017-06-02  7:26     ` Yi Sun
2017-06-06  7:45       ` Jan Beulich
2017-06-06  8:13         ` Yi Sun
2017-06-06  8:38           ` Jan Beulich
2017-06-07  1:31             ` Yi Sun
2017-06-07  7:28               ` Yi Sun
2017-06-07  8:14               ` Jan Beulich
2017-06-07  9:00                 ` Yi Sun [this message]
2017-05-03  8:44 ` [PATCH v11 14/23] x86: refactor psr: CDP: implement get hw info flow Yi Sun
2017-05-31  9:40   ` Jan Beulich
2017-06-05  8:09     ` Yi Sun
2017-05-03  8:44 ` [PATCH v11 15/23] x86: refactor psr: CDP: implement set value callback function Yi Sun
2017-05-31  9:44   ` Jan Beulich
2017-06-02  7:59     ` Yi Sun
2017-06-06  7:48       ` Jan Beulich
2017-06-06  8:22         ` Yi Sun
2017-06-06  8:43           ` Jan Beulich
2017-06-06 10:43             ` Yi Sun
2017-06-06 10:49               ` Jan Beulich
2017-05-03  8:44 ` [PATCH v11 16/23] x86: L2 CAT: implement CPU init flow Yi Sun
2017-05-03  8:44 ` [PATCH v11 17/23] x86: L2 CAT: implement get hw info flow Yi Sun
2017-05-03  8:44 ` [PATCH v11 18/23] x86: L2 CAT: implement get value flow Yi Sun
2017-05-31  9:51   ` Jan Beulich
2017-05-03  8:44 ` [PATCH v11 19/23] x86: L2 CAT: implement set " Yi Sun
2017-05-31  9:52   ` Jan Beulich
2017-05-03  8:44 ` [PATCH v11 20/23] tools: L2 CAT: support get HW info for L2 CAT Yi Sun
2017-05-11 12:39   ` Wei Liu
2017-05-03  8:44 ` [PATCH v11 21/23] tools: L2 CAT: support show cbm " Yi Sun
2017-05-11 12:40   ` Wei Liu
2017-05-03  8:44 ` [PATCH v11 22/23] tools: L2 CAT: support set " Yi Sun
2017-05-11 12:43   ` Wei Liu
2017-05-03  8:44 ` [PATCH v11 23/23] docs: add L2 CAT description in docs Yi Sun

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