[PATCH 00/19] DC Linux Patches May 31, 2017

[PATCH 00/19] DC Linux Patches May 31, 2017

[Harry Wentland]

 * Fix missed scaler programming
 * Some cleanups in atomic_check and commit_tail
 * Restrict DCN to x86
 * Bunch of DCN and other fixes


Amy Zhang (1):
  drm/amd/display: Disable PSR entry abort to prevent intermittent
    freezes

Andrey Grodzovsky (4):
  drm/amd/display: program scaler not called.
  drm/amd/display: Fix handling of scaling and underscan.
  drm/amd/display: Clean unused interface.
  drm/amd/display: Get rid of get_dm_commit_action

Charlene Liu (1):
  drm/amd/display: Add disable_psr debug flag

Corbin McElhanney (1):
  drm/amd/display: Allow update stream without surface

Dmytro Laktyushkin (2):
  drm/amd/display: add always_scale debug flag to dc
  drm/amd/display: stop adjusting scl taps when scl ratio is one on dcn

Harry Wentland (3):
  drm/amd/display: Limit DCN to x86 arch
  drm/amd/display: Don't guard x86 in Makefile
  drm/amd/display: Don't commit surfaces if no stream

Hersen Wu (1):
  drm/amd/display: create_links bug with empty DDI slot

Indrajit Das (1):
  drm/amd/display: enable static audio routing

Jeff Smith (1):
  drm/amd/display: default spd packet to invalid

Jerry Zuo (1):
  drm/amd/display: fix NULL pointer in dm_commit_surfaces

Shirish S (2):
  drm/amd/display: re-order the luma chroma addres updation
  drm/amd/display: update NV12/NV21 as the YUV format

Zeyu Fan (1):
  drm/amd/display: Add FORCE_HDR timing flag

 drivers/gpu/drm/amd/display/Kconfig                |   2 +-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c    | 343 +++++++++------------
 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c |   7 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c           | 126 ++++----
 drivers/gpu/drm/amd/display/dc/core/dc_link.c      |   5 +
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  |   3 +-
 drivers/gpu/drm/amd/display/dc/dc.h                |   8 +-
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h       |   2 +
 .../amd/display/dc/dce110/dce110_hw_sequencer.c    |   6 +-
 .../drm/amd/display/dc/dce110/dce110_mem_input_v.c |   6 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_transform.c |  32 +-
 11 files changed, 247 insertions(+), 293 deletions(-)

-- 
2.11.0

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[PATCH 01/19] drm/amd/display: add always_scale debug flag to dc

[Harry Wentland]

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

Change-Id: Ie2f36ef791ae61da6a806c1b6ad6195db52afd83
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h                    |  1 +
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c | 14 +++++++++-----
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index f2efa32fe4ac..3b35487897b7 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -181,6 +181,7 @@ struct dc_debug {
 	int urgent_latency_ns;
 	int percent_of_ideal_drambw;
 	int dram_clock_change_latency_ns;
+	int always_scale;
 #endif
 	bool disable_pplib_clock_request;
 	bool disable_clock_gate;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c
index 3718fb5a3238..609805877508 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c
@@ -157,7 +157,8 @@ static void transform_set_otg_blank(
 			OTG_V_BLANK_END, v_blank_end);
 }
 
-static enum dscl_mode_sel get_dscl_mode(const struct scaler_data *data)
+static enum dscl_mode_sel get_dscl_mode(
+		const struct scaler_data *data, bool dbg_always_scale)
 {
 	const long long one = dal_fixed31_32_one.value;
 	bool ycbcr = false;
@@ -177,7 +178,8 @@ static enum dscl_mode_sel get_dscl_mode(const struct scaler_data *data)
 	if (data->ratios.horz.value == one
 			&& data->ratios.vert.value == one
 			&& data->ratios.horz_c.value == one
-			&& data->ratios.vert_c.value == one)
+			&& data->ratios.vert_c.value == one
+			&& !dbg_always_scale)
 		return DSCL_MODE_SCALING_444_BYPASS;
 
 	if (!format420) {
@@ -603,7 +605,8 @@ void transform_set_scaler_auto_scale(
 {
 	enum lb_memory_config lb_config;
 	struct dcn10_transform *xfm = TO_DCN10_TRANSFORM(xfm_base);
-	enum dscl_mode_sel dscl_mode = get_dscl_mode(scl_data);
+	enum dscl_mode_sel dscl_mode = get_dscl_mode(
+			scl_data, xfm_base->ctx->dc->debug.always_scale);
 	bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN
 				&& scl_data->format <= PIXEL_FORMAT_VIDEO_END;
 
@@ -611,7 +614,7 @@ void transform_set_scaler_auto_scale(
 
 	transform_set_otg_blank(xfm, scl_data);
 
-	REG_UPDATE(SCL_MODE, DSCL_MODE, get_dscl_mode(scl_data));
+	REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode);
 
 	transform_set_viewport(xfm, &scl_data->viewport, &scl_data->viewport_c);
 
@@ -740,7 +743,8 @@ static void transform_set_scaler_manual_scale(
 {
 	enum lb_memory_config lb_config;
 	struct dcn10_transform *xfm = TO_DCN10_TRANSFORM(xfm_base);
-	enum dscl_mode_sel dscl_mode = get_dscl_mode(scl_data);
+	enum dscl_mode_sel dscl_mode = get_dscl_mode(
+			scl_data, xfm_base->ctx->dc->debug.always_scale);
 	bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN
 				&& scl_data->format <= PIXEL_FORMAT_VIDEO_END;
 
-- 
2.11.0

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[PATCH 02/19] drm/amd/display: program scaler not called.

[Harry Wentland]

From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>

Scaler code in case of UPDATE_TYPE_MED was not called
since new pipe context and current context are the same.

Change-Id: Ib8ce1c3497fff24ce78e20a092139a755fb1423d
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c           | 23 ++++++++++++++++++++--
 .../amd/display/dc/dce110/dce110_hw_sequencer.c    |  6 ++----
 2 files changed, 23 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index b428c7c6559b..4900e8073c69 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1011,12 +1011,23 @@ bool dc_commit_surfaces_to_stream(
 	struct dc_plane_info plane_info[MAX_SURFACES];
 	struct dc_scaling_info scaling_info[MAX_SURFACES];
 	int i;
+	bool ret;
+	struct dc_stream_update *stream_update =
+			dm_alloc(sizeof(struct dc_stream_update));
+
+	if (!stream_update) {
+		BREAK_TO_DEBUGGER();
+		return false;
+	}
 
 	memset(updates, 0, sizeof(updates));
 	memset(flip_addr, 0, sizeof(flip_addr));
 	memset(plane_info, 0, sizeof(plane_info));
 	memset(scaling_info, 0, sizeof(scaling_info));
 
+	stream_update->src = dc_stream->src;
+	stream_update->dst = dc_stream->dst;
+
 	for (i = 0; i < new_surface_count; i++) {
 		updates[i].surface = new_surfaces[i];
 		updates[i].gamma =
@@ -1041,9 +1052,17 @@ bool dc_commit_surfaces_to_stream(
 		updates[i].plane_info = &plane_info[i];
 		updates[i].scaling_info = &scaling_info[i];
 	}
-	dc_update_surfaces_for_stream(dc, updates, new_surface_count, dc_stream);
 
-	return dc_post_update_surfaces_to_stream(dc);
+	dc_update_surfaces_and_stream(
+			dc,
+			updates,
+			new_surface_count,
+			dc_stream, stream_update);
+
+	ret = dc_post_update_surfaces_to_stream(dc);
+
+	dm_free(stream_update);
+	return ret;
 }
 
 static bool is_surface_in_context(
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 65c691569eb7..7dd4b02b5938 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2408,10 +2408,8 @@ static void dce110_program_front_end_for_pipe(
 	pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust);
 
 	pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
-	if (old_pipe && memcmp(&old_pipe->scl_data,
-				&pipe_ctx->scl_data,
-				sizeof(struct scaler_data)) != 0)
-		program_scaler(dc, pipe_ctx);
+
+	program_scaler(dc, pipe_ctx);
 
 	mi->funcs->mem_input_program_surface_config(
 			mi,
-- 
2.11.0

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[PATCH 03/19] drm/amd/display: Limit DCN to x86 arch

[Harry Wentland]

DCN bw calcs currently rely on the following gcc options:
  -mhard-float -msse -mpreferred-stack-boundary=4

We probably shouldn't really try building this on architectures
other than x86.

Change-Id: I63d214b2f6fe9b3fc0d59bd00563e0543f0baa8c
CC: Alex Deucher <Alexander.Deucher@amd.com>
CC: Christian König <christian.koenig@amd.com>
CC: Michel Dänzer <michel.daenzer@amd.com>
CC: Tony Cheng <Tony.Cheng@amd.com>
CC: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/Kconfig           | 2 +-
 drivers/gpu/drm/amd/display/dc/calcs/Makefile | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig
index 2b8d77cebe03..62ea9f600374 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -11,7 +11,7 @@ config DRM_AMD_DC
 
 config DRM_AMD_DC_DCN1_0
         bool "DCN 1.0 Raven family"
-        depends on DRM_AMD_DC
+        depends on DRM_AMD_DC && X86
         help
             Choose this option if you want to have
             RV family for display engine
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
index a095472bf4b5..2e4ce0918c02 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
@@ -3,9 +3,11 @@
 # It calculates Bandwidth and Watermarks values for HW programming
 #
 
+ifeq ($(ARCH),x86)
 CFLAGS_dcn_calcs.o := -mhard-float -msse -mpreferred-stack-boundary=4
 CFLAGS_dcn_calc_auto.o := -mhard-float -msse -mpreferred-stack-boundary=4
 CFLAGS_dcn_calc_math.o := -mhard-float -msse -mpreferred-stack-boundary=4
+endif
 
 BW_CALCS = dce_calcs.o bw_fixed.o custom_float.o
 
-- 
2.11.0

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[PATCH 04/19] drm/amd/display: Fix handling of scaling and underscan.

[Harry Wentland]

From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>

Summury of changes:

1: Both in check and commit Connector properties were handled as
   part of for_each(crtc) loop while they shoud have been handled
   in a dedicated for_each(connector)
   loop since they are connector properties. Moved.

2: Removed hacky plane add in amdgpu_dm_connector_atomic_set_property
   to force iteration on plane forconnector property. This was
   causing double call to commit_surface_for_stream both in crtc loop
   and plane loop.
3: Remove middleman DC interface and  call dc_commit_surfaces_to_stream
   directly to increase code clarity.

Remove it from atomic_commit.

Change-Id: I1337b7abe4a2c6812c7500a5bf22f6c6f01890ca
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c    | 207 ++++++++++-----------
 1 file changed, 99 insertions(+), 108 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index a929df2e690d..15204bf7d9a8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -683,9 +683,8 @@ struct amdgpu_connector *aconnector_from_drm_crtc_id(
 static void update_stream_scaling_settings(
 		const struct drm_display_mode *mode,
 		const struct dm_connector_state *dm_state,
-		const struct dc_stream *stream)
+		struct dc_stream *stream)
 {
-	struct amdgpu_device *adev = dm_state->base.crtc->dev->dev_private;
 	enum amdgpu_rmx_type rmx_type;
 
 	struct rect src = { 0 }; /* viewport in composition space*/
@@ -727,7 +726,8 @@ static void update_stream_scaling_settings(
 		dst.height -= dm_state->underscan_vborder;
 	}
 
-	adev->dm.dc->stream_funcs.stream_update_scaling(adev->dm.dc, stream, &src, &dst);
+	stream->src = src;
+	stream->dst = dst;
 
 	DRM_DEBUG_KMS("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
 			dst.x, dst.y, dst.width, dst.height);
@@ -1287,9 +1287,6 @@ int amdgpu_dm_connector_atomic_set_property(
 	struct dm_connector_state *dm_new_state =
 		to_dm_connector_state(connector_state);
 
-	struct drm_crtc_state *new_crtc_state;
-	struct drm_crtc *crtc;
-	int i;
 	int ret = -EINVAL;
 
 	if (property == dev->mode_config.scaling_mode_property) {
@@ -1335,34 +1332,6 @@ int amdgpu_dm_connector_atomic_set_property(
 		return ret;
 	}
 
-
-
-	for_each_crtc_in_state(
-		connector_state->state,
-		crtc,
-		new_crtc_state,
-		i) {
-
-		if (crtc == connector_state->crtc) {
-			struct drm_plane_state *plane_state;
-
-			/*
-			 * Bit of magic done here. We need to ensure
-			 * that planes get update after mode is set.
-			 * So, we need to add primary plane to state,
-			 * and this way atomic_update would be called
-			 * for it
-			 */
-			plane_state =
-				drm_atomic_get_plane_state(
-					connector_state->state,
-					crtc->primary);
-
-			if (!plane_state)
-				return -EINVAL;
-		}
-	}
-
 	return ret;
 }
 
@@ -2582,28 +2551,19 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state,
 		struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(crtc);
 		struct drm_framebuffer *fb = plane_state->fb;
 		struct drm_connector *connector;
-		struct dm_connector_state *dm_state = NULL;
-
-		enum dm_commit_action action;
+		struct dm_connector_state *con_state = NULL;
 		bool pflip_needed;
 
 		if (!fb || !crtc || !crtc->state->active)
 			continue;
 
-		action = get_dm_commit_action(crtc->state);
-
-		/*
-		 * TODO - TO decide if it's a flip or surface update
-		 * stop relying on allow_modeset flag and query DC
-		 * using dc_check_update_surfaces_for_stream.
-		 */
 		pflip_needed = !state->allow_modeset;
 		if (!pflip_needed) {
 			list_for_each_entry(connector,
 					    &dev->mode_config.connector_list,
 					    head) {
 				if (connector->state->crtc == crtc) {
-					dm_state = to_dm_connector_state(
+					con_state = to_dm_connector_state(
 							connector->state);
 					break;
 				}
@@ -2623,8 +2583,10 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state,
 			 * Also it should be needed when used with actual
 			 * drm_atomic_commit ioctl in future
 			 */
-			if (!dm_state)
+			if (!con_state)
 				continue;
+
+
 			if (crtc == pcrtc) {
 				add_surface(dm->dc, crtc, plane,
 					    &dc_surfaces_constructed[planes_count]);
@@ -2676,7 +2638,8 @@ void amdgpu_dm_atomic_commit_tail(
 	const struct dc_stream *new_stream;
 	unsigned long flags;
 	bool wait_for_vblank = true;
-
+	struct drm_connector *connector;
+	struct drm_connector_state *old_conn_state;
 
 	drm_atomic_helper_update_legacy_modeset_state(dev, state);
 
@@ -2756,21 +2719,6 @@ void amdgpu_dm_atomic_commit_tail(
 
 			break;
 		}
-
-		case DM_COMMIT_ACTION_NOTHING: {
-			struct dm_connector_state *dm_state = NULL;
-
-			if (!aconnector)
-				break;
-
-			dm_state = to_dm_connector_state(aconnector->base.state);
-
-			/* Scaling update */
-			update_stream_scaling_settings(&crtc->state->mode,
-					dm_state, acrtc->stream);
-
-			break;
-		}
 		case DM_COMMIT_ACTION_DPMS_OFF:
 		case DM_COMMIT_ACTION_RESET:
 			DRM_INFO("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
@@ -2778,9 +2726,48 @@ void amdgpu_dm_atomic_commit_tail(
 			if (acrtc->stream)
 				remove_stream(adev, acrtc);
 			break;
+
+		/*TODO retire */
+		case DM_COMMIT_ACTION_NOTHING:
+			continue;
 		} /* switch() */
 	} /* for_each_crtc_in_state() */
 
+	/* Handle scaling and undersacn changes*/
+	for_each_connector_in_state(state, connector, old_conn_state, i) {
+		struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
+		struct dm_connector_state *con_new_state =
+				to_dm_connector_state(aconnector->base.state);
+		struct dm_connector_state *con_old_state =
+				to_dm_connector_state(old_conn_state);
+		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(con_new_state->base.crtc);
+		const struct dc_stream_status *status = NULL;
+
+		/* Skip any modesets/resets */
+		if (!acrtc ||
+			get_dm_commit_action(acrtc->base.state) != DM_COMMIT_ACTION_NOTHING)
+			continue;
+
+		/* Skip any thing not scale or underscan chnages */
+		if (!is_scaling_state_different(con_new_state, con_old_state))
+			continue;
+
+		update_stream_scaling_settings(&con_new_state->base.crtc->mode,
+				con_new_state, (struct dc_stream *)acrtc->stream);
+
+		status = dc_stream_get_status(acrtc->stream);
+		WARN_ON(!status);
+		WARN_ON(!status->surface_count);
+
+		/*TODO How it works with MPO ?*/
+		if (!dc_commit_surfaces_to_stream(
+				dm->dc,
+				(const struct dc_surface **)status->surfaces,
+				status->surface_count,
+				acrtc->stream))
+			dm_error("%s: Failed to update stream scaling!\n", __func__);
+	}
+
 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 
 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
@@ -3118,6 +3105,8 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 	struct dc *dc = adev->dm.dc;
 	bool need_to_validate = false;
 	struct validate_context *context;
+	struct drm_connector *connector;
+	struct drm_connector_state *conn_state;
 	/*
 	 * This bool will be set for true for any modeset/reset
 	 * or surface update which implies non fast surfae update.
@@ -3203,52 +3192,6 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 			break;
 		}
 
-		case DM_COMMIT_ACTION_NOTHING: {
-			const struct drm_connector *drm_connector = NULL;
-			struct drm_connector_state *conn_state = NULL;
-			struct dm_connector_state *dm_state = NULL;
-			struct dm_connector_state *old_dm_state = NULL;
-			struct dc_stream *new_stream;
-
-			if (!aconnector)
-				break;
-
-			for_each_connector_in_state(
-				state, drm_connector, conn_state, j) {
-				if (&aconnector->base == drm_connector)
-					break;
-			}
-
-			old_dm_state = to_dm_connector_state(drm_connector->state);
-			dm_state = to_dm_connector_state(conn_state);
-
-			/* Support underscan adjustment*/
-			if (!is_scaling_state_different(dm_state, old_dm_state))
-				break;
-
-			new_stream = create_stream_for_sink(aconnector, &crtc_state->mode, dm_state);
-
-			if (!new_stream) {
-				DRM_ERROR("%s: Failed to create new stream for crtc %d\n",
-						__func__, acrtc->base.base.id);
-				break;
-			}
-
-			new_streams[new_stream_count] = new_stream;
-			set_count = update_in_val_sets_stream(
-					set,
-					crtc_set,
-					set_count,
-					acrtc->stream,
-					new_stream,
-					crtc);
-
-			new_stream_count++;
-			need_to_validate = true;
-			wait_for_prev_commits = true;
-
-			break;
-		}
 		case DM_COMMIT_ACTION_DPMS_OFF:
 		case DM_COMMIT_ACTION_RESET:
 			/* i.e. reset mode */
@@ -3260,6 +3203,10 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 				wait_for_prev_commits = true;
 			}
 			break;
+
+		/*TODO retire */
+		case DM_COMMIT_ACTION_NOTHING:
+			continue;
 		}
 
 		/*
@@ -3276,6 +3223,50 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 		ret = -EINVAL;
 	}
 
+	/* Check scaling and undersacn changes*/
+	for_each_connector_in_state(state, connector, conn_state, i) {
+		struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
+		struct dm_connector_state *con_old_state =
+				to_dm_connector_state(aconnector->base.state);
+		struct dm_connector_state *con_new_state =
+						to_dm_connector_state(conn_state);
+		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(con_new_state->base.crtc);
+		struct dc_stream *new_stream;
+
+		/* Skip any modesets/resets */
+		if (!acrtc ||
+			get_dm_commit_action(acrtc->base.state) != DM_COMMIT_ACTION_NOTHING)
+			continue;
+
+		/* Skip any thing not scale or underscan chnages */
+		if (!is_scaling_state_different(con_new_state, con_old_state))
+			continue;
+
+		new_stream = create_stream_for_sink(
+				aconnector,
+				&acrtc->base.state->mode,
+				con_new_state);
+
+		if (!new_stream) {
+			DRM_ERROR("%s: Failed to create new stream for crtc %d\n",
+					__func__, acrtc->base.base.id);
+			continue;
+		}
+
+		new_streams[new_stream_count] = new_stream;
+		set_count = update_in_val_sets_stream(
+				set,
+				crtc_set,
+				set_count,
+				acrtc->stream,
+				new_stream,
+				&acrtc->base);
+
+		new_stream_count++;
+		need_to_validate = true;
+		wait_for_prev_commits = true;
+	}
+
 	for (i = 0; i < set_count; i++) {
 		for_each_plane_in_state(state, plane, plane_state, j) {
 			struct drm_crtc *crtc = plane_state->crtc;
-- 
2.11.0

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[PATCH 05/19] drm/amd/display: Clean unused interface.

[Harry Wentland]

From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>

Change-Id: I65f1e3920bebeac06336add3a136b0ff452782c6
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 42 --------------------------------
 drivers/gpu/drm/amd/display/dc/dc.h      |  6 -----
 2 files changed, 48 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 4900e8073c69..f5349970b594 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -249,47 +249,6 @@ static void set_static_screen_events(struct dc *dc,
 	core_dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events);
 }
 
-/* This function is not expected to fail, proper implementation of
- * validation will prevent this from ever being called for unsupported
- * configurations.
- */
-static void stream_update_scaling(
-		const struct dc *dc,
-		const struct dc_stream *dc_stream,
-		const struct rect *src,
-		const struct rect *dst)
-{
-	struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
-	struct core_dc *core_dc = DC_TO_CORE(dc);
-	struct validate_context *cur_ctx = core_dc->current_context;
-	int i;
-
-	if (src)
-		stream->public.src = *src;
-
-	if (dst)
-		stream->public.dst = *dst;
-
-	for (i = 0; i < cur_ctx->stream_count; i++) {
-		struct core_stream *cur_stream = cur_ctx->streams[i];
-
-		if (stream == cur_stream) {
-			struct dc_stream_status *status = &cur_ctx->stream_status[i];
-
-			if (status->surface_count)
-				if (!dc_commit_surfaces_to_stream(
-						&core_dc->public,
-						status->surfaces,
-						status->surface_count,
-						&cur_stream->public))
-					/* Need to debug validation */
-					BREAK_TO_DEBUGGER();
-
-			return;
-		}
-	}
-}
-
 static void set_drive_settings(struct dc *dc,
 		struct link_training_settings *lt_settings,
 		const struct dc_link *link)
@@ -402,7 +361,6 @@ void set_dither_option(const struct dc_stream *dc_stream,
 
 static void allocate_dc_stream_funcs(struct core_dc *core_dc)
 {
-	core_dc->public.stream_funcs.stream_update_scaling = stream_update_scaling;
 	if (core_dc->hwss.set_drr != NULL) {
 		core_dc->public.stream_funcs.adjust_vmin_vmax =
 				stream_adjust_vmin_vmax;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 3b35487897b7..0d3b73a37df1 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -115,12 +115,6 @@ struct dc_stream_funcs {
 			unsigned int *v_pos,
 			unsigned int *nom_v_pos);
 
-
-	void (*stream_update_scaling)(const struct dc *dc,
-			const struct dc_stream *dc_stream,
-			const struct rect *src,
-			const struct rect *dst);
-
 	bool (*set_gamut_remap)(struct dc *dc,
 			const struct dc_stream *stream);
 
-- 
2.11.0

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[PATCH 06/19] drm/amd/display: Add disable_psr debug flag

[Harry Wentland]

From: Charlene Liu <charlene.liu@amd.com>

Change-Id: I09afa9c67b09ec3d9e547ce71963015d8eddd499
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 0d3b73a37df1..ce052d12a104 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -180,6 +180,7 @@ struct dc_debug {
 	bool disable_pplib_clock_request;
 	bool disable_clock_gate;
 	bool disable_dmcu;
+	bool disable_psr;
 	bool force_abm_enable;
 };
 
-- 
2.11.0

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[PATCH 07/19] drm/amd/display: Allow update stream without surface

[Harry Wentland]

From: Corbin McElhanney <corbin.mcelhanney@amd.com>

Passing NULL as surfaceUpdates to dc_update_surfaces_and_stream now
updates just the stream. Code that is dependent on srf_updates was moved
below the NULL check.

Change-Id: Iee54909c6c89c150b376aa85c95f0307d4fa91ab
Signed-off-by: Corbin McElhanney <corbin.mcelhanney@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 58 +++++++++++++++++---------------
 1 file changed, 31 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index f5349970b594..c33e31c9e3e1 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1223,33 +1223,7 @@ void dc_update_surfaces_and_stream(struct dc *dc,
 	if (!stream_status)
 		return; /* Cannot commit surface to stream that is not committed */
 
-	update_type = dc_check_update_surfaces_for_stream(
-			dc, srf_updates, surface_count, stream_update, stream_status);
-
-	if (update_type >= update_surface_trace_level)
-		update_surface_trace(dc, srf_updates, surface_count);
-
-	if (update_type >= UPDATE_TYPE_FULL) {
-		const struct dc_surface *new_surfaces[MAX_SURFACES] = { 0 };
-
-		for (i = 0; i < surface_count; i++)
-			new_surfaces[i] = srf_updates[i].surface;
-
-		/* initialize scratch memory for building context */
-		context = dm_alloc(sizeof(*context));
-		dc_resource_validate_ctx_copy_construct(
-				core_dc->current_context, context);
-
-		/* add surface to context */
-		if (!resource_attach_surfaces_to_context(
-				new_surfaces, surface_count, dc_stream,
-				context, core_dc->res_pool)) {
-			BREAK_TO_DEBUGGER();
-			goto fail;
-		}
-	} else {
-		context = core_dc->current_context;
-	}
+	context = core_dc->current_context;
 
 	/* update current stream with the new updates */
 	if (stream_update) {
@@ -1277,6 +1251,36 @@ void dc_update_surfaces_and_stream(struct dc *dc,
 		}
 	}
 
+	/* only proceed if we need to make a surface update */
+	if (!srf_updates)
+		return;
+
+	update_type = dc_check_update_surfaces_for_stream(
+			dc, srf_updates, surface_count, stream_update, stream_status);
+
+	if (update_type >= update_surface_trace_level)
+		update_surface_trace(dc, srf_updates, surface_count);
+
+	if (update_type >= UPDATE_TYPE_FULL) {
+		const struct dc_surface *new_surfaces[MAX_SURFACES] = { 0 };
+
+		for (i = 0; i < surface_count; i++)
+			new_surfaces[i] = srf_updates[i].surface;
+
+		/* initialize scratch memory for building context */
+		context = dm_alloc(sizeof(*context));
+		dc_resource_validate_ctx_copy_construct(
+				core_dc->current_context, context);
+
+		/* add surface to context */
+		if (!resource_attach_surfaces_to_context(
+				new_surfaces, surface_count, dc_stream,
+				context, core_dc->res_pool)) {
+			BREAK_TO_DEBUGGER();
+			goto fail;
+		}
+	}
+
 	/* save update parameters into surface */
 	for (i = 0; i < surface_count; i++) {
 		struct core_surface *surface =
-- 
2.11.0

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[PATCH 08/19] drm/amd/display: Add FORCE_HDR timing flag

[Harry Wentland]

From: Zeyu Fan <Zeyu.Fan@amd.com>

Change-Id: I486b2be53a380956b3405874ecb92d83b62135a0
Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 58a3bcd5131f..b6e677786cbc 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -635,6 +635,8 @@ struct dc_crtc_timing_flags {
 	uint32_t YCBCR420 :1; /* TODO: shouldn't need this flag, should be a separate pixel format */
 	uint32_t DTD_COUNTER :5; /* values 1 to 16 */
 
+	uint32_t FORCE_HDR :1;
+
 	/* HDMI 2.0 - Support scrambling for TMDS character
 	 * rates less than or equal to 340Mcsc */
 	uint32_t LTE_340MCSC_SCRAMBLE:1;
-- 
2.11.0

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[PATCH 09/19] drm/amd/display: Disable PSR entry abort to prevent intermittent freezes

[Harry Wentland]

From: Amy Zhang <Amy.Zhang@amd.com>

Change-Id: I8beaae4b027868ed3a088d89b2396b0097611830
Signed-off-by: Amy Zhang <Amy.Zhang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 59977640f938..79f3947a3ee1 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1550,6 +1550,11 @@ bool dc_link_setup_psr(const struct dc_link *dc_link,
 		 */
 		psr_context.psr_level.bits.SKIP_SMU_NOTIFICATION = 1;
 
+		/* Complete PSR entry before aborting to prevent intermittent
+		 * freezes on certain eDPs
+		 */
+		psr_context.psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
+
 		/* Controls additional delay after remote frame capture before
 		 * continuing power down, default = 0
 		 */
-- 
2.11.0

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[PATCH 10/19] drm/amd/display: fix NULL pointer in dm_commit_surfaces

[Harry Wentland]

From: Jerry Zuo <Jerry.Zuo@amd.com>

Check if adding surface is failed to prevent NULL pointer deref.

Change-Id: I804585bf126e74570875f4b8508358d3bad172a0
Signed-off-by: Jerry Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 15204bf7d9a8..543acb712edf 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -2590,6 +2590,10 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state,
 			if (crtc == pcrtc) {
 				add_surface(dm->dc, crtc, plane,
 					    &dc_surfaces_constructed[planes_count]);
+				if (dc_surfaces_constructed[planes_count] == NULL) {
+					dm_error("%s: Failed to add surface!\n", __func__);
+					continue;
+				}
 				dc_stream_attach = acrtc_attach->stream;
 				planes_count++;
 			}
-- 
2.11.0

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[PATCH 11/19] drm/amd/display: Get rid of get_dm_commit_action

[Harry Wentland]

From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>

Use drm_atomic_crtc_needs_modeset instead.

Change-Id: I296cd1c8f8a2e4239a3cb814805868c14bcd20ba
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c    | 127 +++++++--------------
 1 file changed, 44 insertions(+), 83 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 543acb712edf..aaa290bc425f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -2343,57 +2343,23 @@ int amdgpu_dm_encoder_init(
 	return res;
 }
 
-enum dm_commit_action {
-	DM_COMMIT_ACTION_NOTHING,
-	DM_COMMIT_ACTION_RESET,
-	DM_COMMIT_ACTION_DPMS_ON,
-	DM_COMMIT_ACTION_DPMS_OFF,
-	DM_COMMIT_ACTION_SET
-};
-
-static enum dm_commit_action get_dm_commit_action(struct drm_crtc_state *state)
+static bool modeset_required(struct drm_crtc_state *crtc_state)
 {
-	/* mode changed means either actually mode changed or enabled changed */
-	/* active changed means dpms changed */
-
-	DRM_DEBUG_KMS("crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
-			state->enable,
-			state->active,
-			state->planes_changed,
-			state->mode_changed,
-			state->active_changed,
-			state->connectors_changed);
-
-	if (state->mode_changed) {
-		/* if it is got disabled - call reset mode */
-		if (!state->enable)
-			return DM_COMMIT_ACTION_RESET;
+	if (!drm_atomic_crtc_needs_modeset(crtc_state))
+		return false;
 
-		if (state->active)
-			return DM_COMMIT_ACTION_SET;
-		else
-			return DM_COMMIT_ACTION_RESET;
-	} else {
-		/* ! mode_changed */
+	if (!crtc_state->enable)
+		return false;
 
-		/* if it is remain disable - skip it */
-		if (!state->enable)
-			return DM_COMMIT_ACTION_NOTHING;
+	return crtc_state->active;
+}
 
-		if (state->active && state->connectors_changed)
-			return DM_COMMIT_ACTION_SET;
+static bool modereset_required(struct drm_crtc_state *crtc_state)
+{
+	if (!drm_atomic_crtc_needs_modeset(crtc_state))
+		return false;
 
-		if (state->active_changed) {
-			if (state->active) {
-				return DM_COMMIT_ACTION_DPMS_ON;
-			} else {
-				return DM_COMMIT_ACTION_DPMS_OFF;
-			}
-		} else {
-			/* ! active_changed */
-			return DM_COMMIT_ACTION_NOTHING;
-		}
-	}
+	return !crtc_state->enable || !crtc_state->active;
 }
 
 static void manage_dm_interrupts(
@@ -2646,12 +2612,10 @@ void amdgpu_dm_atomic_commit_tail(
 	struct drm_connector_state *old_conn_state;
 
 	drm_atomic_helper_update_legacy_modeset_state(dev, state);
-
 	/* update changed items */
 	for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
 		struct amdgpu_crtc *acrtc;
 		struct amdgpu_connector *aconnector = NULL;
-		enum dm_commit_action action;
 		struct drm_crtc_state *new_state = crtc->state;
 
 		acrtc = to_amdgpu_crtc(crtc);
@@ -2662,15 +2626,23 @@ void amdgpu_dm_atomic_commit_tail(
 				crtc,
 				false);
 
+		DRM_DEBUG_KMS(
+			"amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
+			"planes_changed:%d, mode_changed:%d,active_changed:%d,"
+			"connectors_changed:%d\n",
+			acrtc->crtc_id,
+			new_state->enable,
+			new_state->active,
+			new_state->planes_changed,
+			new_state->mode_changed,
+			new_state->active_changed,
+			new_state->connectors_changed);
+
 		/* handles headless hotplug case, updating new_state and
 		 * aconnector as needed
 		 */
 
-		action = get_dm_commit_action(new_state);
-
-		switch (action) {
-		case DM_COMMIT_ACTION_DPMS_ON:
-		case DM_COMMIT_ACTION_SET: {
+		if (modeset_required(new_state)) {
 			struct dm_connector_state *dm_state = NULL;
 			new_stream = NULL;
 
@@ -2720,21 +2692,13 @@ void amdgpu_dm_atomic_commit_tail(
 			acrtc->enabled = true;
 			acrtc->hw_mode = crtc->state->mode;
 			crtc->hwmode = crtc->state->mode;
+		} else if (modereset_required(new_state)) {
 
-			break;
-		}
-		case DM_COMMIT_ACTION_DPMS_OFF:
-		case DM_COMMIT_ACTION_RESET:
 			DRM_INFO("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
 			/* i.e. reset mode */
 			if (acrtc->stream)
 				remove_stream(adev, acrtc);
-			break;
-
-		/*TODO retire */
-		case DM_COMMIT_ACTION_NOTHING:
-			continue;
-		} /* switch() */
+		}
 	} /* for_each_crtc_in_state() */
 
 	/* Handle scaling and undersacn changes*/
@@ -2748,8 +2712,7 @@ void amdgpu_dm_atomic_commit_tail(
 		const struct dc_stream_status *status = NULL;
 
 		/* Skip any modesets/resets */
-		if (!acrtc ||
-			get_dm_commit_action(acrtc->base.state) != DM_COMMIT_ACTION_NOTHING)
+		if (!acrtc || drm_atomic_crtc_needs_modeset(acrtc->base.state))
 			continue;
 
 		/* Skip any thing not scale or underscan chnages */
@@ -3145,17 +3108,25 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 	for_each_crtc_in_state(state, crtc, crtc_state, i) {
 		struct amdgpu_crtc *acrtc = NULL;
 		struct amdgpu_connector *aconnector = NULL;
-		enum dm_commit_action action;
 
 		acrtc = to_amdgpu_crtc(crtc);
 
 		aconnector = amdgpu_dm_find_first_crct_matching_connector(state, crtc, true);
 
-		action = get_dm_commit_action(crtc_state);
+		DRM_DEBUG_KMS(
+			"amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
+			"planes_changed:%d, mode_changed:%d,active_changed:%d,"
+			"connectors_changed:%d\n",
+			acrtc->crtc_id,
+			crtc_state->enable,
+			crtc_state->active,
+			crtc_state->planes_changed,
+			crtc_state->mode_changed,
+			crtc_state->active_changed,
+			crtc_state->connectors_changed);
+
+		if (modeset_required(crtc_state)) {
 
-		switch (action) {
-		case DM_COMMIT_ACTION_DPMS_ON:
-		case DM_COMMIT_ACTION_SET: {
 			struct dc_stream *new_stream = NULL;
 			struct drm_connector_state *conn_state = NULL;
 			struct dm_connector_state *dm_state = NULL;
@@ -3193,11 +3164,9 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 			new_stream_count++;
 			need_to_validate = true;
 			wait_for_prev_commits = true;
-			break;
-		}
 
-		case DM_COMMIT_ACTION_DPMS_OFF:
-		case DM_COMMIT_ACTION_RESET:
+		} else if (modereset_required(crtc_state)) {
+
 			/* i.e. reset mode */
 			if (acrtc->stream) {
 				set_count = remove_from_val_sets(
@@ -3206,11 +3175,6 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 						acrtc->stream);
 				wait_for_prev_commits = true;
 			}
-			break;
-
-		/*TODO retire */
-		case DM_COMMIT_ACTION_NOTHING:
-			continue;
 		}
 
 		/*
@@ -3238,8 +3202,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 		struct dc_stream *new_stream;
 
 		/* Skip any modesets/resets */
-		if (!acrtc ||
-			get_dm_commit_action(acrtc->base.state) != DM_COMMIT_ACTION_NOTHING)
+		if (!acrtc || drm_atomic_crtc_needs_modeset(acrtc->base.state))
 			continue;
 
 		/* Skip any thing not scale or underscan chnages */
@@ -3277,7 +3240,6 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 			struct drm_framebuffer *fb = plane_state->fb;
 			struct drm_connector *connector;
 			struct dm_connector_state *dm_state = NULL;
-			enum dm_commit_action action;
 			struct drm_crtc_state *crtc_state;
 			bool pflip_needed;
 
@@ -3286,7 +3248,6 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 				!crtc->state->planes_changed || !crtc->state->active)
 				continue;
 
-			action = get_dm_commit_action(crtc->state);
 
 			crtc_state = drm_atomic_get_crtc_state(state, crtc);
 			pflip_needed = !state->allow_modeset;
-- 
2.11.0

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[PATCH 12/19] drm/amd/display: Don't guard x86 in Makefile

[Harry Wentland]

make-kpkg doesn't seem to like it

Change-Id: Ia589318e8632de57286c4a3d63a0a92a6cb96af3
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/calcs/Makefile | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
index 2e4ce0918c02..a095472bf4b5 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
@@ -3,11 +3,9 @@
 # It calculates Bandwidth and Watermarks values for HW programming
 #
 
-ifeq ($(ARCH),x86)
 CFLAGS_dcn_calcs.o := -mhard-float -msse -mpreferred-stack-boundary=4
 CFLAGS_dcn_calc_auto.o := -mhard-float -msse -mpreferred-stack-boundary=4
 CFLAGS_dcn_calc_math.o := -mhard-float -msse -mpreferred-stack-boundary=4
-endif
 
 BW_CALCS = dce_calcs.o bw_fixed.o custom_float.o
 
-- 
2.11.0

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[PATCH 13/19] drm/amd/display: create_links bug with empty DDI slot

[Harry Wentland]

From: Hersen Wu <hersenxs.wu@amd.com>

Change-Id: Ia19bcb874b7ae22201f2b7cfef3c42c10276c6d5
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 7 ++++---
 drivers/gpu/drm/amd/display/dc/core/dc.c           | 3 +--
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index 682fc9b9b3f2..fcd3b72287c8 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -410,6 +410,9 @@ enum generic_id generic_id_from_bios_object_id(uint32_t bios_object_id)
 	return id;
 }
 
+/* BIOS oject table displaypath is per connector.
+ * There is extra path not for connector. BIOS fill its encoderid as 0
+ */
 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb)
 {
 	struct bios_parser *bp = BP_FROM_DCB(dcb);
@@ -417,9 +420,7 @@ static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb)
 	unsigned int i;
 
 	for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
-		if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0
-				&&
-		bp->object_info_tbl.v1_4->display_path[i].display_objid != 0)
+		if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0)
 			count++;
 	}
 	return count;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index c33e31c9e3e1..323a5e706908 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -97,6 +97,7 @@ static bool create_links(
 		struct core_link *link;
 
 		link_init_params.ctx = dc->ctx;
+		/* next BIOS object table connector */
 		link_init_params.connector_index = i;
 		link_init_params.link_index = dc->link_count;
 		link_init_params.dc = dc;
@@ -106,8 +107,6 @@ static bool create_links(
 			dc->links[dc->link_count] = link;
 			link->dc = dc;
 			++dc->link_count;
-		} else {
-			dm_error("DC: failed to create link!\n");
 		}
 	}
 
-- 
2.11.0

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[PATCH 14/19] drm/amd/display: re-order the luma chroma addres updation

[Harry Wentland]

From: Shirish S <shirish.s@amd.com>

The DCE engine triggers scan as soon as the luma
address is updated, since it is updated before chroma address
the chroma data is not scanned out properly or in order.
This patch fixes this by re-ordering the same.

BUG: SWDEV-119421
TEST: (On Chromium OS for Stoney Only)
    * Executed below tests to see YUV(underlay) & RGB planes on eDP
      plane_test --format XR24 --size 500x100 -p --format NV12 --size 500x500
    * Chroma data is scanned properly.

Change-Id: Ifc3e27a0cb88febbdbc95ebee1044daf18b50b2c
Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
index 9777a4d961d5..a06c6024deb4 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
@@ -137,12 +137,12 @@ static void program_addr(
 			addr->grph.addr);
 		break;
 	case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
-		program_pri_addr_l(
-			mem_input110,
-			addr->video_progressive.luma_addr);
 		program_pri_addr_c(
 			mem_input110,
 			addr->video_progressive.chroma_addr);
+		program_pri_addr_l(
+			mem_input110,
+			addr->video_progressive.luma_addr);
 		break;
 	default:
 		/* not supported */
-- 
2.11.0

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[PATCH 15/19] drm/amd/display: default spd packet to invalid

[Harry Wentland]

From: Jeff Smith <whydoubt@gmail.com>

Change-Id: I7ec74c131caa7d085415d5fd15c4e442a39b966a
Signed-off-by: Jeff Smith <whydoubt@gmail.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index ec5045734378..6202b4b3e597 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2172,6 +2172,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
 	info->avi.valid = false;
 	info->gamut.valid = false;
 	info->vendor.valid = false;
+	info->spd.valid = false;
 	info->hdrsmd.valid = false;
 	info->vsc.valid = false;
 
-- 
2.11.0

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[PATCH 16/19] drm/amd/display: update NV12/NV21 as the YUV format

[Harry Wentland]

From: Shirish S <shirish.s@amd.com>

This patch updates the YUV format supported to
NV12 and NV21 and hence updates the offsets.

BUG: SWDEV-119421
TEST: (On Chromium OS for Stoney Only)
    * Executed below tests to see YUV(underlay) & RGB planes on eDP
    plane_test --format XR24 --size 500x100 -p --format NV12 --size
    500x500

Change-Id: Ifcf0d58a409cfcf5450acd17534943f92216ad36
Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c    | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index aaa290bc425f..574806504bec 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -457,6 +457,7 @@ static void fill_plane_attributes_from_fb(
 {
 	uint64_t tiling_flags;
 	uint64_t fb_location = 0;
+	unsigned int awidth;
 	const struct drm_framebuffer *fb = &amdgpu_fb->base;
 	struct drm_format_name_buf format_name;
 
@@ -485,10 +486,10 @@ static void fill_plane_attributes_from_fb(
 	case DRM_FORMAT_ABGR2101010:
 		surface->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
 		break;
-	case DRM_FORMAT_YUV420:
+	case DRM_FORMAT_NV21:
 		surface->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
 		break;
-	case DRM_FORMAT_YVU420:
+	case DRM_FORMAT_NV12:
 		surface->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
 		break;
 	default:
@@ -511,24 +512,25 @@ static void fill_plane_attributes_from_fb(
 		surface->color_space = COLOR_SPACE_SRGB;
 
 	} else {
+		awidth = ALIGN(fb->width, 64);
 		surface->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
 		surface->address.video_progressive.luma_addr.low_part
 						= lower_32_bits(fb_location);
 		surface->address.video_progressive.chroma_addr.low_part
 						= lower_32_bits(fb_location) +
-							(fb->width * fb->height);
+							(awidth * fb->height);
 		surface->plane_size.video.luma_size.x = 0;
 		surface->plane_size.video.luma_size.y = 0;
-		surface->plane_size.video.luma_size.width = fb->width;
+		surface->plane_size.video.luma_size.width = awidth;
 		surface->plane_size.video.luma_size.height = fb->height;
 		/* TODO: unhardcode */
-		surface->plane_size.video.luma_pitch = ALIGN(fb->width, 64);
+		surface->plane_size.video.luma_pitch = awidth;
 
 		surface->plane_size.video.chroma_size.x = 0;
 		surface->plane_size.video.chroma_size.y = 0;
-		surface->plane_size.video.chroma_size.width = fb->width / 2;
-		surface->plane_size.video.chroma_size.height = fb->height / 2;
-		surface->plane_size.video.chroma_pitch = ALIGN(fb->width, 64) / 2;
+		surface->plane_size.video.chroma_size.width = awidth;
+		surface->plane_size.video.chroma_size.height = fb->height;
+		surface->plane_size.video.chroma_pitch = awidth / 2;
 
 		/* TODO: unhardcode */
 		surface->color_space = COLOR_SPACE_YCBCR709;
@@ -1833,8 +1835,8 @@ static uint32_t rgb_formats[] = {
 };
 
 static uint32_t yuv_formats[] = {
-	DRM_FORMAT_YUV420,
-	DRM_FORMAT_YVU420,
+	DRM_FORMAT_NV12,
+	DRM_FORMAT_NV21,
 };
 
 int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
-- 
2.11.0

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[PATCH 17/19] drm/amd/display: Don't commit surfaces if no stream

[Harry Wentland]

Change-Id: Id369865feb28818a62f8eb26ce4b2dee097a7bcb
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 574806504bec..939ea8df3440 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -2728,6 +2728,9 @@ void amdgpu_dm_atomic_commit_tail(
 		WARN_ON(!status);
 		WARN_ON(!status->surface_count);
 
+		if (!acrtc->stream)
+			continue;
+
 		/*TODO How it works with MPO ?*/
 		if (!dc_commit_surfaces_to_stream(
 				dm->dc,
@@ -2785,8 +2788,12 @@ void amdgpu_dm_atomic_commit_tail(
 	}
 
 	/* update planes when needed per crtc*/
-	for_each_crtc_in_state(state, pcrtc, old_crtc_state, j)
-		amdgpu_dm_commit_surfaces(state, dev, dm, pcrtc, &wait_for_vblank);
+	for_each_crtc_in_state(state, pcrtc, old_crtc_state, j) {
+		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(pcrtc);
+
+		if (acrtc->stream)
+			amdgpu_dm_commit_surfaces(state, dev, dm, pcrtc, &wait_for_vblank);
+	}
 
 	for (i = 0; i < new_crtcs_count; i++) {
 		/*
-- 
2.11.0

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[PATCH 18/19] drm/amd/display: enable static audio routing

[Harry Wentland]

From: Indrajit Das <indrajit-kumar.das@amd.com>

Change-Id: Ib61bf88eb16da50017944556995d3789735aea0c
Signed-off-by: Indrajit Das <indrajit-kumar.das@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 6202b4b3e597..50b0385bffce 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1278,7 +1278,7 @@ static struct audio *find_first_free_audio(
 {
 	int i;
 	for (i = 0; i < pool->audio_count; i++) {
-		if (res_ctx->is_audio_acquired[i] == false) {
+		if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
 			return pool->audios[i];
 		}
 	}
-- 
2.11.0

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[PATCH 19/19] drm/amd/display: stop adjusting scl taps when scl ratio is one on dcn

[Harry Wentland]

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

Change-Id: I7df3470eb793f91e9a3d765b476bf181a56663b3
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c
index 609805877508..d9815a991682 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c
@@ -851,14 +851,16 @@ static bool transform_get_optimal_number_of_taps(
 	else
 		scl_data->taps.h_taps_c = in_taps->h_taps_c;
 
-	if (IDENTITY_RATIO(scl_data->ratios.horz))
-		scl_data->taps.h_taps = 1;
-	if (IDENTITY_RATIO(scl_data->ratios.vert))
-		scl_data->taps.v_taps = 1;
-	if (IDENTITY_RATIO(scl_data->ratios.horz_c))
-		scl_data->taps.h_taps_c = 1;
-	if (IDENTITY_RATIO(scl_data->ratios.vert_c))
-		scl_data->taps.v_taps_c = 1;
+	if (!xfm->ctx->dc->debug.always_scale) {
+		if (IDENTITY_RATIO(scl_data->ratios.horz))
+			scl_data->taps.h_taps = 1;
+		if (IDENTITY_RATIO(scl_data->ratios.vert))
+			scl_data->taps.v_taps = 1;
+		if (IDENTITY_RATIO(scl_data->ratios.horz_c))
+			scl_data->taps.h_taps_c = 1;
+		if (IDENTITY_RATIO(scl_data->ratios.vert_c))
+			scl_data->taps.v_taps_c = 1;
+	}
 
 	return true;
 }
-- 
2.11.0

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Re: [PATCH 12/19] drm/amd/display: Don't guard x86 in Makefile

[Kai Wasserbäch]

[-- Attachment #1.1.1: Type: text/plain, Size: 1548 bytes --]

Hey Harry,
you should drop this patch and remove the addition from patch 3 AFAICT.


Cheers,
Kai

P.S.: IIRC the conclusion of the last discussion was, that this code is needed
on non-x86 hardware as well. Shouldn't there at least be some TODO added
somewhere in the DCN code or maybe now in the Kconfig option, stating that this
needs to be fixed for other arches?


Harry Wentland wrote on 31.05.2017 17:52:
> make-kpkg doesn't seem to like it
> 
> Change-Id: Ia589318e8632de57286c4a3d63a0a92a6cb96af3
> Signed-off-by: Harry Wentland <harry.wentland-5C7GfCeVMHo@public.gmane.org>
> Reviewed-by: Andrey Grodzovsky <Andrey.Grodzovsky-5C7GfCeVMHo@public.gmane.org>
> Acked-by: Harry Wentland <Harry.Wentland-5C7GfCeVMHo@public.gmane.org>
> ---
>  drivers/gpu/drm/amd/display/dc/calcs/Makefile | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> index 2e4ce0918c02..a095472bf4b5 100644
> --- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> @@ -3,11 +3,9 @@
>  # It calculates Bandwidth and Watermarks values for HW programming
>  #
>  
> -ifeq ($(ARCH),x86)
>  CFLAGS_dcn_calcs.o := -mhard-float -msse -mpreferred-stack-boundary=4
>  CFLAGS_dcn_calc_auto.o := -mhard-float -msse -mpreferred-stack-boundary=4
>  CFLAGS_dcn_calc_math.o := -mhard-float -msse -mpreferred-stack-boundary=4
> -endif
>  
>  BW_CALCS = dce_calcs.o bw_fixed.o custom_float.o


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[-- Attachment #2: Type: text/plain, Size: 154 bytes --]

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Re: [PATCH 04/19] drm/amd/display: Fix handling of scaling and underscan.

[Kai Wasserbäch]

[-- Attachment #1.1.1: Type: text/plain, Size: 11988 bytes --]

Hey Harry, hey Andrey,
Harry Wentland wrote on 31.05.2017 17:52:
> From: Andrey Grodzovsky <Andrey.Grodzovsky-5C7GfCeVMHo@public.gmane.org>
> 
> Summury of changes:

s/Summury/Summary/

> 1: Both in check and commit Connector properties were handled as

s/in// ?

>    part of for_each(crtc) loop while they shoud have been handled

s/part of/part of a/
s/shoud/should/

>    in a dedicated for_each(connector)
>    loop since they are connector properties. Moved.
> 
> 2: Removed hacky plane add in amdgpu_dm_connector_atomic_set_property
>    to force iteration on plane forconnector property. This was
>    causing double call to commit_surface_for_stream both in crtc loop
>    and plane loop.
> 3: Remove middleman DC interface and  call dc_commit_surfaces_to_stream
>    directly to increase code clarity.

This description makes it sound like three independent issues, that should be
split into their own patches. But I'm probably missing an interdependency here?
If so, it'd be awesome if this could be mentioned here.

Cheers&Thanks,
Kai


> Remove it from atomic_commit.
> 
> Change-Id: I1337b7abe4a2c6812c7500a5bf22f6c6f01890ca
> Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky-5C7GfCeVMHo@public.gmane.org>
> Reviewed-by: Harry Wentland <Harry.Wentland-5C7GfCeVMHo@public.gmane.org>
> ---
>  .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c    | 207 ++++++++++-----------
>  1 file changed, 99 insertions(+), 108 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
> index a929df2e690d..15204bf7d9a8 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
> @@ -683,9 +683,8 @@ struct amdgpu_connector *aconnector_from_drm_crtc_id(
>  static void update_stream_scaling_settings(
>  		const struct drm_display_mode *mode,
>  		const struct dm_connector_state *dm_state,
> -		const struct dc_stream *stream)
> +		struct dc_stream *stream)
>  {
> -	struct amdgpu_device *adev = dm_state->base.crtc->dev->dev_private;
>  	enum amdgpu_rmx_type rmx_type;
>  
>  	struct rect src = { 0 }; /* viewport in composition space*/
> @@ -727,7 +726,8 @@ static void update_stream_scaling_settings(
>  		dst.height -= dm_state->underscan_vborder;
>  	}
>  
> -	adev->dm.dc->stream_funcs.stream_update_scaling(adev->dm.dc, stream, &src, &dst);
> +	stream->src = src;
> +	stream->dst = dst;
>  
>  	DRM_DEBUG_KMS("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
>  			dst.x, dst.y, dst.width, dst.height);
> @@ -1287,9 +1287,6 @@ int amdgpu_dm_connector_atomic_set_property(
>  	struct dm_connector_state *dm_new_state =
>  		to_dm_connector_state(connector_state);
>  
> -	struct drm_crtc_state *new_crtc_state;
> -	struct drm_crtc *crtc;
> -	int i;
>  	int ret = -EINVAL;
>  
>  	if (property == dev->mode_config.scaling_mode_property) {
> @@ -1335,34 +1332,6 @@ int amdgpu_dm_connector_atomic_set_property(
>  		return ret;
>  	}
>  
> -
> -
> -	for_each_crtc_in_state(
> -		connector_state->state,
> -		crtc,
> -		new_crtc_state,
> -		i) {
> -
> -		if (crtc == connector_state->crtc) {
> -			struct drm_plane_state *plane_state;
> -
> -			/*
> -			 * Bit of magic done here. We need to ensure
> -			 * that planes get update after mode is set.
> -			 * So, we need to add primary plane to state,
> -			 * and this way atomic_update would be called
> -			 * for it
> -			 */
> -			plane_state =
> -				drm_atomic_get_plane_state(
> -					connector_state->state,
> -					crtc->primary);
> -
> -			if (!plane_state)
> -				return -EINVAL;
> -		}
> -	}
> -
>  	return ret;
>  }
>  
> @@ -2582,28 +2551,19 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state,
>  		struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(crtc);
>  		struct drm_framebuffer *fb = plane_state->fb;
>  		struct drm_connector *connector;
> -		struct dm_connector_state *dm_state = NULL;
> -
> -		enum dm_commit_action action;
> +		struct dm_connector_state *con_state = NULL;
>  		bool pflip_needed;
>  
>  		if (!fb || !crtc || !crtc->state->active)
>  			continue;
>  
> -		action = get_dm_commit_action(crtc->state);
> -
> -		/*
> -		 * TODO - TO decide if it's a flip or surface update
> -		 * stop relying on allow_modeset flag and query DC
> -		 * using dc_check_update_surfaces_for_stream.
> -		 */
>  		pflip_needed = !state->allow_modeset;
>  		if (!pflip_needed) {
>  			list_for_each_entry(connector,
>  					    &dev->mode_config.connector_list,
>  					    head) {
>  				if (connector->state->crtc == crtc) {
> -					dm_state = to_dm_connector_state(
> +					con_state = to_dm_connector_state(
>  							connector->state);
>  					break;
>  				}
> @@ -2623,8 +2583,10 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state,
>  			 * Also it should be needed when used with actual
>  			 * drm_atomic_commit ioctl in future
>  			 */
> -			if (!dm_state)
> +			if (!con_state)
>  				continue;
> +
> +
>  			if (crtc == pcrtc) {
>  				add_surface(dm->dc, crtc, plane,
>  					    &dc_surfaces_constructed[planes_count]);
> @@ -2676,7 +2638,8 @@ void amdgpu_dm_atomic_commit_tail(
>  	const struct dc_stream *new_stream;
>  	unsigned long flags;
>  	bool wait_for_vblank = true;
> -
> +	struct drm_connector *connector;
> +	struct drm_connector_state *old_conn_state;
>  
>  	drm_atomic_helper_update_legacy_modeset_state(dev, state);
>  
> @@ -2756,21 +2719,6 @@ void amdgpu_dm_atomic_commit_tail(
>  
>  			break;
>  		}
> -
> -		case DM_COMMIT_ACTION_NOTHING: {
> -			struct dm_connector_state *dm_state = NULL;
> -
> -			if (!aconnector)
> -				break;
> -
> -			dm_state = to_dm_connector_state(aconnector->base.state);
> -
> -			/* Scaling update */
> -			update_stream_scaling_settings(&crtc->state->mode,
> -					dm_state, acrtc->stream);
> -
> -			break;
> -		}
>  		case DM_COMMIT_ACTION_DPMS_OFF:
>  		case DM_COMMIT_ACTION_RESET:
>  			DRM_INFO("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
> @@ -2778,9 +2726,48 @@ void amdgpu_dm_atomic_commit_tail(
>  			if (acrtc->stream)
>  				remove_stream(adev, acrtc);
>  			break;
> +
> +		/*TODO retire */
> +		case DM_COMMIT_ACTION_NOTHING:
> +			continue;
>  		} /* switch() */
>  	} /* for_each_crtc_in_state() */
>  
> +	/* Handle scaling and undersacn changes*/
> +	for_each_connector_in_state(state, connector, old_conn_state, i) {
> +		struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
> +		struct dm_connector_state *con_new_state =
> +				to_dm_connector_state(aconnector->base.state);
> +		struct dm_connector_state *con_old_state =
> +				to_dm_connector_state(old_conn_state);
> +		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(con_new_state->base.crtc);
> +		const struct dc_stream_status *status = NULL;
> +
> +		/* Skip any modesets/resets */
> +		if (!acrtc ||
> +			get_dm_commit_action(acrtc->base.state) != DM_COMMIT_ACTION_NOTHING)
> +			continue;
> +
> +		/* Skip any thing not scale or underscan chnages */
> +		if (!is_scaling_state_different(con_new_state, con_old_state))
> +			continue;
> +
> +		update_stream_scaling_settings(&con_new_state->base.crtc->mode,
> +				con_new_state, (struct dc_stream *)acrtc->stream);
> +
> +		status = dc_stream_get_status(acrtc->stream);
> +		WARN_ON(!status);
> +		WARN_ON(!status->surface_count);
> +
> +		/*TODO How it works with MPO ?*/
> +		if (!dc_commit_surfaces_to_stream(
> +				dm->dc,
> +				(const struct dc_surface **)status->surfaces,
> +				status->surface_count,
> +				acrtc->stream))
> +			dm_error("%s: Failed to update stream scaling!\n", __func__);
> +	}
> +
>  	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
>  
>  		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
> @@ -3118,6 +3105,8 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
>  	struct dc *dc = adev->dm.dc;
>  	bool need_to_validate = false;
>  	struct validate_context *context;
> +	struct drm_connector *connector;
> +	struct drm_connector_state *conn_state;
>  	/*
>  	 * This bool will be set for true for any modeset/reset
>  	 * or surface update which implies non fast surfae update.
> @@ -3203,52 +3192,6 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
>  			break;
>  		}
>  
> -		case DM_COMMIT_ACTION_NOTHING: {
> -			const struct drm_connector *drm_connector = NULL;
> -			struct drm_connector_state *conn_state = NULL;
> -			struct dm_connector_state *dm_state = NULL;
> -			struct dm_connector_state *old_dm_state = NULL;
> -			struct dc_stream *new_stream;
> -
> -			if (!aconnector)
> -				break;
> -
> -			for_each_connector_in_state(
> -				state, drm_connector, conn_state, j) {
> -				if (&aconnector->base == drm_connector)
> -					break;
> -			}
> -
> -			old_dm_state = to_dm_connector_state(drm_connector->state);
> -			dm_state = to_dm_connector_state(conn_state);
> -
> -			/* Support underscan adjustment*/
> -			if (!is_scaling_state_different(dm_state, old_dm_state))
> -				break;
> -
> -			new_stream = create_stream_for_sink(aconnector, &crtc_state->mode, dm_state);
> -
> -			if (!new_stream) {
> -				DRM_ERROR("%s: Failed to create new stream for crtc %d\n",
> -						__func__, acrtc->base.base.id);
> -				break;
> -			}
> -
> -			new_streams[new_stream_count] = new_stream;
> -			set_count = update_in_val_sets_stream(
> -					set,
> -					crtc_set,
> -					set_count,
> -					acrtc->stream,
> -					new_stream,
> -					crtc);
> -
> -			new_stream_count++;
> -			need_to_validate = true;
> -			wait_for_prev_commits = true;
> -
> -			break;
> -		}
>  		case DM_COMMIT_ACTION_DPMS_OFF:
>  		case DM_COMMIT_ACTION_RESET:
>  			/* i.e. reset mode */
> @@ -3260,6 +3203,10 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
>  				wait_for_prev_commits = true;
>  			}
>  			break;
> +
> +		/*TODO retire */
> +		case DM_COMMIT_ACTION_NOTHING:
> +			continue;
>  		}
>  
>  		/*
> @@ -3276,6 +3223,50 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
>  		ret = -EINVAL;
>  	}
>  
> +	/* Check scaling and undersacn changes*/
> +	for_each_connector_in_state(state, connector, conn_state, i) {
> +		struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
> +		struct dm_connector_state *con_old_state =
> +				to_dm_connector_state(aconnector->base.state);
> +		struct dm_connector_state *con_new_state =
> +						to_dm_connector_state(conn_state);
> +		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(con_new_state->base.crtc);
> +		struct dc_stream *new_stream;
> +
> +		/* Skip any modesets/resets */
> +		if (!acrtc ||
> +			get_dm_commit_action(acrtc->base.state) != DM_COMMIT_ACTION_NOTHING)
> +			continue;
> +
> +		/* Skip any thing not scale or underscan chnages */
> +		if (!is_scaling_state_different(con_new_state, con_old_state))
> +			continue;
> +
> +		new_stream = create_stream_for_sink(
> +				aconnector,
> +				&acrtc->base.state->mode,
> +				con_new_state);
> +
> +		if (!new_stream) {
> +			DRM_ERROR("%s: Failed to create new stream for crtc %d\n",
> +					__func__, acrtc->base.base.id);
> +			continue;
> +		}
> +
> +		new_streams[new_stream_count] = new_stream;
> +		set_count = update_in_val_sets_stream(
> +				set,
> +				crtc_set,
> +				set_count,
> +				acrtc->stream,
> +				new_stream,
> +				&acrtc->base);
> +
> +		new_stream_count++;
> +		need_to_validate = true;
> +		wait_for_prev_commits = true;
> +	}
> +
>  	for (i = 0; i < set_count; i++) {
>  		for_each_plane_in_state(state, plane, plane_state, j) {
>  			struct drm_crtc *crtc = plane_state->crtc;
> 

-- 

Kai Wasserbäch (Kai Wasserbaech)

E-Mail: kai-1ZKVMVCtJ2dx9oSEVPI0kiST3g8Odh+X@public.gmane.org


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Re: [PATCH 03/19] drm/amd/display: Limit DCN to x86 arch

[zhoucm1]

On 2017年05月31日 23:52, Harry Wentland wrote:
> DCN bw calcs currently rely on the following gcc options:
>    -mhard-float -msse -mpreferred-stack-boundary=4
>
> We probably shouldn't really try building this on architectures
> other than x86.
Does it mean our card including DCN cannot run on other platform like ARM?

Regards,
David Zhou
>
> Change-Id: I63d214b2f6fe9b3fc0d59bd00563e0543f0baa8c
> CC: Alex Deucher <Alexander.Deucher@amd.com>
> CC: Christian König <christian.koenig@amd.com>
> CC: Michel Dänzer <michel.daenzer@amd.com>
> CC: Tony Cheng <Tony.Cheng@amd.com>
> CC: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
> Signed-off-by: Harry Wentland <harry.wentland@amd.com>
> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
> Acked-by: Harry Wentland <Harry.Wentland@amd.com>
> ---
>   drivers/gpu/drm/amd/display/Kconfig           | 2 +-
>   drivers/gpu/drm/amd/display/dc/calcs/Makefile | 2 ++
>   2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig
> index 2b8d77cebe03..62ea9f600374 100644
> --- a/drivers/gpu/drm/amd/display/Kconfig
> +++ b/drivers/gpu/drm/amd/display/Kconfig
> @@ -11,7 +11,7 @@ config DRM_AMD_DC
>   
>   config DRM_AMD_DC_DCN1_0
>           bool "DCN 1.0 Raven family"
> -        depends on DRM_AMD_DC
> +        depends on DRM_AMD_DC && X86
>           help
>               Choose this option if you want to have
>               RV family for display engine
> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> index a095472bf4b5..2e4ce0918c02 100644
> --- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> @@ -3,9 +3,11 @@
>   # It calculates Bandwidth and Watermarks values for HW programming
>   #
>   
> +ifeq ($(ARCH),x86)
>   CFLAGS_dcn_calcs.o := -mhard-float -msse -mpreferred-stack-boundary=4
>   CFLAGS_dcn_calc_auto.o := -mhard-float -msse -mpreferred-stack-boundary=4
>   CFLAGS_dcn_calc_math.o := -mhard-float -msse -mpreferred-stack-boundary=4
> +endif
>   
>   BW_CALCS = dce_calcs.o bw_fixed.o custom_float.o
>   

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Re: [PATCH 03/19] drm/amd/display: Limit DCN to x86 arch

[Christian König]

Am 01.06.2017 um 06:15 schrieb zhoucm1:
>
>
> On 2017年05月31日 23:52, Harry Wentland wrote:
>> DCN bw calcs currently rely on the following gcc options:
>>    -mhard-float -msse -mpreferred-stack-boundary=4
>>
>> We probably shouldn't really try building this on architectures
>> other than x86.
> Does it mean our card including DCN cannot run on other platform like 
> ARM?

Yeah, which is a bit problematic cause we need to support both ARM and 
PowerPC with the driver as well.

Regards,
Christian.

>
> Regards,
> David Zhou
>>
>> Change-Id: I63d214b2f6fe9b3fc0d59bd00563e0543f0baa8c
>> CC: Alex Deucher <Alexander.Deucher@amd.com>
>> CC: Christian König <christian.koenig@amd.com>
>> CC: Michel Dänzer <michel.daenzer@amd.com>
>> CC: Tony Cheng <Tony.Cheng@amd.com>
>> CC: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
>> Signed-off-by: Harry Wentland <harry.wentland@amd.com>
>> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
>> Acked-by: Harry Wentland <Harry.Wentland@amd.com>
>> ---
>>   drivers/gpu/drm/amd/display/Kconfig           | 2 +-
>>   drivers/gpu/drm/amd/display/dc/calcs/Makefile | 2 ++
>>   2 files changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/Kconfig 
>> b/drivers/gpu/drm/amd/display/Kconfig
>> index 2b8d77cebe03..62ea9f600374 100644
>> --- a/drivers/gpu/drm/amd/display/Kconfig
>> +++ b/drivers/gpu/drm/amd/display/Kconfig
>> @@ -11,7 +11,7 @@ config DRM_AMD_DC
>>     config DRM_AMD_DC_DCN1_0
>>           bool "DCN 1.0 Raven family"
>> -        depends on DRM_AMD_DC
>> +        depends on DRM_AMD_DC && X86
>>           help
>>               Choose this option if you want to have
>>               RV family for display engine
>> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile 
>> b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
>> index a095472bf4b5..2e4ce0918c02 100644
>> --- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
>> +++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
>> @@ -3,9 +3,11 @@
>>   # It calculates Bandwidth and Watermarks values for HW programming
>>   #
>>   +ifeq ($(ARCH),x86)
>>   CFLAGS_dcn_calcs.o := -mhard-float -msse -mpreferred-stack-boundary=4
>>   CFLAGS_dcn_calc_auto.o := -mhard-float -msse 
>> -mpreferred-stack-boundary=4
>>   CFLAGS_dcn_calc_math.o := -mhard-float -msse 
>> -mpreferred-stack-boundary=4
>> +endif
>>     BW_CALCS = dce_calcs.o bw_fixed.o custom_float.o
>

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Re: [PATCH 03/19] drm/amd/display: Limit DCN to x86 arch

[zhoucm1]

On 2017年06月01日 16:50, Christian König wrote:
> Am 01.06.2017 um 06:15 schrieb zhoucm1:
>>
>>
>> On 2017年05月31日 23:52, Harry Wentland wrote:
>>> DCN bw calcs currently rely on the following gcc options:
>>>    -mhard-float -msse -mpreferred-stack-boundary=4
>>>
>>> We probably shouldn't really try building this on architectures
>>> other than x86.
>> Does it mean our card including DCN cannot run on other platform like 
>> ARM?
>
> Yeah, which is a bit problematic cause we need to support both ARM and 
> PowerPC with the driver as well.
I often heard external people want to run our card on embed platform, 
ARM is most.

Regards,
David Zhou
>
> Regards,
> Christian.
>
>>
>> Regards,
>> David Zhou
>>>
>>> Change-Id: I63d214b2f6fe9b3fc0d59bd00563e0543f0baa8c
>>> CC: Alex Deucher <Alexander.Deucher@amd.com>
>>> CC: Christian König <christian.koenig@amd.com>
>>> CC: Michel Dänzer <michel.daenzer@amd.com>
>>> CC: Tony Cheng <Tony.Cheng@amd.com>
>>> CC: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
>>> Signed-off-by: Harry Wentland <harry.wentland@amd.com>
>>> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
>>> Acked-by: Harry Wentland <Harry.Wentland@amd.com>
>>> ---
>>>   drivers/gpu/drm/amd/display/Kconfig           | 2 +-
>>>   drivers/gpu/drm/amd/display/dc/calcs/Makefile | 2 ++
>>>   2 files changed, 3 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/display/Kconfig 
>>> b/drivers/gpu/drm/amd/display/Kconfig
>>> index 2b8d77cebe03..62ea9f600374 100644
>>> --- a/drivers/gpu/drm/amd/display/Kconfig
>>> +++ b/drivers/gpu/drm/amd/display/Kconfig
>>> @@ -11,7 +11,7 @@ config DRM_AMD_DC
>>>     config DRM_AMD_DC_DCN1_0
>>>           bool "DCN 1.0 Raven family"
>>> -        depends on DRM_AMD_DC
>>> +        depends on DRM_AMD_DC && X86
>>>           help
>>>               Choose this option if you want to have
>>>               RV family for display engine
>>> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile 
>>> b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
>>> index a095472bf4b5..2e4ce0918c02 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
>>> +++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
>>> @@ -3,9 +3,11 @@
>>>   # It calculates Bandwidth and Watermarks values for HW programming
>>>   #
>>>   +ifeq ($(ARCH),x86)
>>>   CFLAGS_dcn_calcs.o := -mhard-float -msse -mpreferred-stack-boundary=4
>>>   CFLAGS_dcn_calc_auto.o := -mhard-float -msse 
>>> -mpreferred-stack-boundary=4
>>>   CFLAGS_dcn_calc_math.o := -mhard-float -msse 
>>> -mpreferred-stack-boundary=4
>>> +endif
>>>     BW_CALCS = dce_calcs.o bw_fixed.o custom_float.o
>>
>

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Re: [PATCH 03/19] drm/amd/display: Limit DCN to x86 arch

[Alex Deucher]

On Thu, Jun 1, 2017 at 12:15 AM, zhoucm1 <david1.zhou@amd.com> wrote:
>
>
> On 2017年05月31日 23:52, Harry Wentland wrote:
>>
>> DCN bw calcs currently rely on the following gcc options:
>>    -mhard-float -msse -mpreferred-stack-boundary=4
>>
>> We probably shouldn't really try building this on architectures
>> other than x86.
>
> Does it mean our card including DCN cannot run on other platform like ARM?

The only DCN asics at the moment are APUs so they are only x86.

Alex

>
> Regards,
> David Zhou
>>
>>
>> Change-Id: I63d214b2f6fe9b3fc0d59bd00563e0543f0baa8c
>> CC: Alex Deucher <Alexander.Deucher@amd.com>
>> CC: Christian König <christian.koenig@amd.com>
>> CC: Michel Dänzer <michel.daenzer@amd.com>
>> CC: Tony Cheng <Tony.Cheng@amd.com>
>> CC: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
>> Signed-off-by: Harry Wentland <harry.wentland@amd.com>
>> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
>> Acked-by: Harry Wentland <Harry.Wentland@amd.com>
>> ---
>>   drivers/gpu/drm/amd/display/Kconfig           | 2 +-
>>   drivers/gpu/drm/amd/display/dc/calcs/Makefile | 2 ++
>>   2 files changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/Kconfig
>> b/drivers/gpu/drm/amd/display/Kconfig
>> index 2b8d77cebe03..62ea9f600374 100644
>> --- a/drivers/gpu/drm/amd/display/Kconfig
>> +++ b/drivers/gpu/drm/amd/display/Kconfig
>> @@ -11,7 +11,7 @@ config DRM_AMD_DC
>>     config DRM_AMD_DC_DCN1_0
>>           bool "DCN 1.0 Raven family"
>> -        depends on DRM_AMD_DC
>> +        depends on DRM_AMD_DC && X86
>>           help
>>               Choose this option if you want to have
>>               RV family for display engine
>> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
>> b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
>> index a095472bf4b5..2e4ce0918c02 100644
>> --- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
>> +++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
>> @@ -3,9 +3,11 @@
>>   # It calculates Bandwidth and Watermarks values for HW programming
>>   #
>>   +ifeq ($(ARCH),x86)
>>   CFLAGS_dcn_calcs.o := -mhard-float -msse -mpreferred-stack-boundary=4
>>   CFLAGS_dcn_calc_auto.o := -mhard-float -msse
>> -mpreferred-stack-boundary=4
>>   CFLAGS_dcn_calc_math.o := -mhard-float -msse
>> -mpreferred-stack-boundary=4
>> +endif
>>     BW_CALCS = dce_calcs.o bw_fixed.o custom_float.o
>>
>
>
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