* [PATCH v3 01/16] MIPS: lantiq: Use of_platform_default_populate instead of __dt_register_buses
2017-05-28 18:39 ` Hauke Mehrtens
@ 2017-05-28 18:39 ` Hauke Mehrtens
-1 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:39 UTC (permalink / raw)
To: ralf-6z/3iImG2C8G8FEW9MqTrA
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w,
robh-DgEjT+Ai2ygdnm+yROfE0A,
andy.shevchenko-Re5JQEeQqe8AvxtiuMwx3w,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ, Hauke Mehrtens
From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
This allows populating syscon devices which are using "simple-mfd"
instead of "simple-bus".
Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
arch/mips/lantiq/prom.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
index 96773bed8a8a..9ff7ccde9de0 100644
--- a/arch/mips/lantiq/prom.c
+++ b/arch/mips/lantiq/prom.c
@@ -117,7 +117,7 @@ void __init prom_init(void)
int __init plat_of_setup(void)
{
- return __dt_register_buses(soc_info.compatible, "simple-bus");
+ return of_platform_default_populate(NULL, NULL, NULL);
}
arch_initcall(plat_of_setup);
--
2.11.0
--
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^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v3 01/16] MIPS: lantiq: Use of_platform_default_populate instead of __dt_register_buses
@ 2017-05-28 18:39 ` Hauke Mehrtens
0 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:39 UTC (permalink / raw)
To: ralf
Cc: linux-mips, linux-mtd, linux-watchdog, devicetree,
martin.blumenstingl, john, linux-spi, hauke.mehrtens, robh,
andy.shevchenko, p.zabel, Hauke Mehrtens
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
This allows populating syscon devices which are using "simple-mfd"
instead of "simple-bus".
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
arch/mips/lantiq/prom.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
index 96773bed8a8a..9ff7ccde9de0 100644
--- a/arch/mips/lantiq/prom.c
+++ b/arch/mips/lantiq/prom.c
@@ -117,7 +117,7 @@ void __init prom_init(void)
int __init plat_of_setup(void)
{
- return __dt_register_buses(soc_info.compatible, "simple-bus");
+ return of_platform_default_populate(NULL, NULL, NULL);
}
arch_initcall(plat_of_setup);
--
2.11.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v3 02/16] mtd: lantiq-flash: drop check of boot select
2017-05-28 18:39 ` Hauke Mehrtens
@ 2017-05-28 18:39 ` Hauke Mehrtens
-1 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:39 UTC (permalink / raw)
To: ralf-6z/3iImG2C8G8FEW9MqTrA
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w,
robh-DgEjT+Ai2ygdnm+yROfE0A,
andy.shevchenko-Re5JQEeQqe8AvxtiuMwx3w,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ, Hauke Mehrtens
Do not check which flash type the SoC was booted from before
using this driver. Assume that the device tree is correct and use this
driver when it was added to device tree. This also removes a build
dependency to the SoC code.
Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
Acked-by: Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
drivers/mtd/maps/lantiq-flash.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/drivers/mtd/maps/lantiq-flash.c b/drivers/mtd/maps/lantiq-flash.c
index 3e33ab66eb24..77b1d8013295 100644
--- a/drivers/mtd/maps/lantiq-flash.c
+++ b/drivers/mtd/maps/lantiq-flash.c
@@ -114,12 +114,6 @@ ltq_mtd_probe(struct platform_device *pdev)
struct cfi_private *cfi;
int err;
- if (of_machine_is_compatible("lantiq,falcon") &&
- (ltq_boot_select() != BS_FLASH)) {
- dev_err(&pdev->dev, "invalid bootstrap options\n");
- return -ENODEV;
- }
-
ltq_mtd = devm_kzalloc(&pdev->dev, sizeof(struct ltq_mtd), GFP_KERNEL);
if (!ltq_mtd)
return -ENOMEM;
--
2.11.0
--
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^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v3 02/16] mtd: lantiq-flash: drop check of boot select
@ 2017-05-28 18:39 ` Hauke Mehrtens
0 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:39 UTC (permalink / raw)
To: ralf
Cc: linux-mips, linux-mtd, linux-watchdog, devicetree,
martin.blumenstingl, john, linux-spi, hauke.mehrtens, robh,
andy.shevchenko, p.zabel, Hauke Mehrtens
Do not check which flash type the SoC was booted from before
using this driver. Assume that the device tree is correct and use this
driver when it was added to device tree. This also removes a build
dependency to the SoC code.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Acked-by: Brian Norris <computersforpeace@gmail.com>
---
drivers/mtd/maps/lantiq-flash.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/drivers/mtd/maps/lantiq-flash.c b/drivers/mtd/maps/lantiq-flash.c
index 3e33ab66eb24..77b1d8013295 100644
--- a/drivers/mtd/maps/lantiq-flash.c
+++ b/drivers/mtd/maps/lantiq-flash.c
@@ -114,12 +114,6 @@ ltq_mtd_probe(struct platform_device *pdev)
struct cfi_private *cfi;
int err;
- if (of_machine_is_compatible("lantiq,falcon") &&
- (ltq_boot_select() != BS_FLASH)) {
- dev_err(&pdev->dev, "invalid bootstrap options\n");
- return -ENODEV;
- }
-
ltq_mtd = devm_kzalloc(&pdev->dev, sizeof(struct ltq_mtd), GFP_KERNEL);
if (!ltq_mtd)
return -ENOMEM;
--
2.11.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v3 03/16] mtd: spi-falcon: drop check of boot select
2017-05-28 18:39 ` Hauke Mehrtens
@ 2017-05-28 18:39 ` Hauke Mehrtens
-1 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:39 UTC (permalink / raw)
To: ralf-6z/3iImG2C8G8FEW9MqTrA
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w,
robh-DgEjT+Ai2ygdnm+yROfE0A,
andy.shevchenko-Re5JQEeQqe8AvxtiuMwx3w,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ, Hauke Mehrtens
Do not check which flash type the SoC was booted from before
using this driver. Assume that the device tree is correct and use this
driver when it was added to device tree. This also removes a build
dependency to the SoC code.
Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
drivers/spi/spi-falcon.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/drivers/spi/spi-falcon.c b/drivers/spi/spi-falcon.c
index 286b2c81fc6b..f8638e82e5db 100644
--- a/drivers/spi/spi-falcon.c
+++ b/drivers/spi/spi-falcon.c
@@ -395,11 +395,6 @@ static int falcon_sflash_probe(struct platform_device *pdev)
struct spi_master *master;
int ret;
- if (ltq_boot_select() != BS_SPI) {
- dev_err(&pdev->dev, "invalid bootstrap options\n");
- return -ENODEV;
- }
-
master = spi_alloc_master(&pdev->dev, sizeof(*priv));
if (!master)
return -ENOMEM;
--
2.11.0
--
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^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v3 03/16] mtd: spi-falcon: drop check of boot select
@ 2017-05-28 18:39 ` Hauke Mehrtens
0 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:39 UTC (permalink / raw)
To: ralf
Cc: linux-mips, linux-mtd, linux-watchdog, devicetree,
martin.blumenstingl, john, linux-spi, hauke.mehrtens, robh,
andy.shevchenko, p.zabel, Hauke Mehrtens
Do not check which flash type the SoC was booted from before
using this driver. Assume that the device tree is correct and use this
driver when it was added to device tree. This also removes a build
dependency to the SoC code.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
drivers/spi/spi-falcon.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/drivers/spi/spi-falcon.c b/drivers/spi/spi-falcon.c
index 286b2c81fc6b..f8638e82e5db 100644
--- a/drivers/spi/spi-falcon.c
+++ b/drivers/spi/spi-falcon.c
@@ -395,11 +395,6 @@ static int falcon_sflash_probe(struct platform_device *pdev)
struct spi_master *master;
int ret;
- if (ltq_boot_select() != BS_SPI) {
- dev_err(&pdev->dev, "invalid bootstrap options\n");
- return -ENODEV;
- }
-
master = spi_alloc_master(&pdev->dev, sizeof(*priv));
if (!master)
return -ENOMEM;
--
2.11.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v3 04/16] watchdog: lantiq: access boot cause register through regmap
2017-05-28 18:39 ` Hauke Mehrtens
@ 2017-05-28 18:39 ` Hauke Mehrtens
-1 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:39 UTC (permalink / raw)
To: ralf-6z/3iImG2C8G8FEW9MqTrA
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w,
robh-DgEjT+Ai2ygdnm+yROfE0A,
andy.shevchenko-Re5JQEeQqe8AvxtiuMwx3w,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ, Hauke Mehrtens
This patch avoids accessing the function ltq_reset_cause() and directly
accesses the register given over the syscon interface. The syscon
interface will be implemented for the xway SoCs for the falcon SoCs the
ltq_reset_cause() function never worked, because a wrong offset was used.
Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
Acked-by: Guenter Roeck <linux-cYGBoTPqujPR7s880joybQ@public.gmane.org>
---
drivers/watchdog/lantiq_wdt.c | 45 +++++++++++++++++++++++++++++++++++++++----
1 file changed, 41 insertions(+), 4 deletions(-)
diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c
index e0823677d8c1..c9ad8100ec3c 100644
--- a/drivers/watchdog/lantiq_wdt.c
+++ b/drivers/watchdog/lantiq_wdt.c
@@ -4,6 +4,7 @@
* by the Free Software Foundation.
*
* Copyright (C) 2010 John Crispin <john-Pj+rj9U5foFAfugRpC6u6w@public.gmane.org>
+ * Copyright (C) 2017 Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
* Based on EP93xx wdt driver
*/
@@ -17,6 +18,8 @@
#include <linux/uaccess.h>
#include <linux/clk.h>
#include <linux/io.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
#include <lantiq_soc.h>
@@ -186,6 +189,40 @@ static struct miscdevice ltq_wdt_miscdev = {
.fops = <q_wdt_fops,
};
+static void ltq_set_wdt_bootstatus(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct regmap *rcu_regmap;
+ u32 status_reg_offset;
+ u32 status_reg_mask;
+ u32 val;
+ int err;
+
+ rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "regmap");
+ if (IS_ERR_OR_NULL(rcu_regmap))
+ return;
+
+ err = device_property_read_u32(dev, "offset-status",
+ &status_reg_offset);
+ if (err) {
+ dev_err(&pdev->dev, "Failed to get RCU reg offset\n");
+ return;
+ }
+
+ err = device_property_read_u32(dev, "mask-status", &status_reg_mask);
+ if (err) {
+ dev_err(&pdev->dev, "Failed to get RCU reg offset\n");
+ return;
+ }
+
+ err = regmap_read(rcu_regmap, status_reg_offset, &val);
+ if (err)
+ return;
+
+ if (val & status_reg_mask)
+ ltq_wdt_bootstatus = WDIOF_CARDRESET;
+}
+
static int
ltq_wdt_probe(struct platform_device *pdev)
{
@@ -205,9 +242,7 @@ ltq_wdt_probe(struct platform_device *pdev)
ltq_io_region_clk_rate = clk_get_rate(clk);
clk_put(clk);
- /* find out if the watchdog caused the last reboot */
- if (ltq_reset_cause() == LTQ_RST_CAUSE_WDTRST)
- ltq_wdt_bootstatus = WDIOF_CARDRESET;
+ ltq_set_wdt_bootstatus(pdev);
dev_info(&pdev->dev, "Init done\n");
return misc_register(<q_wdt_miscdev);
@@ -222,7 +257,9 @@ ltq_wdt_remove(struct platform_device *pdev)
}
static const struct of_device_id ltq_wdt_match[] = {
- { .compatible = "lantiq,wdt" },
+ { .compatible = "lantiq,wdt"},
+ { .compatible = "lantiq,wdt-xrx100"},
+ { .compatible = "lantiq,wdt-falcon"},
{},
};
MODULE_DEVICE_TABLE(of, ltq_wdt_match);
--
2.11.0
--
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^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v3 04/16] watchdog: lantiq: access boot cause register through regmap
@ 2017-05-28 18:39 ` Hauke Mehrtens
0 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:39 UTC (permalink / raw)
To: ralf
Cc: linux-mips, linux-mtd, linux-watchdog, devicetree,
martin.blumenstingl, john, linux-spi, hauke.mehrtens, robh,
andy.shevchenko, p.zabel, Hauke Mehrtens
This patch avoids accessing the function ltq_reset_cause() and directly
accesses the register given over the syscon interface. The syscon
interface will be implemented for the xway SoCs for the falcon SoCs the
ltq_reset_cause() function never worked, because a wrong offset was used.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Acked-by: Guenter Roeck <linux@reck-us.net>
---
drivers/watchdog/lantiq_wdt.c | 45 +++++++++++++++++++++++++++++++++++++++----
1 file changed, 41 insertions(+), 4 deletions(-)
diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c
index e0823677d8c1..c9ad8100ec3c 100644
--- a/drivers/watchdog/lantiq_wdt.c
+++ b/drivers/watchdog/lantiq_wdt.c
@@ -4,6 +4,7 @@
* by the Free Software Foundation.
*
* Copyright (C) 2010 John Crispin <john@phrozen.org>
+ * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
* Based on EP93xx wdt driver
*/
@@ -17,6 +18,8 @@
#include <linux/uaccess.h>
#include <linux/clk.h>
#include <linux/io.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
#include <lantiq_soc.h>
@@ -186,6 +189,40 @@ static struct miscdevice ltq_wdt_miscdev = {
.fops = <q_wdt_fops,
};
+static void ltq_set_wdt_bootstatus(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct regmap *rcu_regmap;
+ u32 status_reg_offset;
+ u32 status_reg_mask;
+ u32 val;
+ int err;
+
+ rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "regmap");
+ if (IS_ERR_OR_NULL(rcu_regmap))
+ return;
+
+ err = device_property_read_u32(dev, "offset-status",
+ &status_reg_offset);
+ if (err) {
+ dev_err(&pdev->dev, "Failed to get RCU reg offset\n");
+ return;
+ }
+
+ err = device_property_read_u32(dev, "mask-status", &status_reg_mask);
+ if (err) {
+ dev_err(&pdev->dev, "Failed to get RCU reg offset\n");
+ return;
+ }
+
+ err = regmap_read(rcu_regmap, status_reg_offset, &val);
+ if (err)
+ return;
+
+ if (val & status_reg_mask)
+ ltq_wdt_bootstatus = WDIOF_CARDRESET;
+}
+
static int
ltq_wdt_probe(struct platform_device *pdev)
{
@@ -205,9 +242,7 @@ ltq_wdt_probe(struct platform_device *pdev)
ltq_io_region_clk_rate = clk_get_rate(clk);
clk_put(clk);
- /* find out if the watchdog caused the last reboot */
- if (ltq_reset_cause() == LTQ_RST_CAUSE_WDTRST)
- ltq_wdt_bootstatus = WDIOF_CARDRESET;
+ ltq_set_wdt_bootstatus(pdev);
dev_info(&pdev->dev, "Init done\n");
return misc_register(<q_wdt_miscdev);
@@ -222,7 +257,9 @@ ltq_wdt_remove(struct platform_device *pdev)
}
static const struct of_device_id ltq_wdt_match[] = {
- { .compatible = "lantiq,wdt" },
+ { .compatible = "lantiq,wdt"},
+ { .compatible = "lantiq,wdt-xrx100"},
+ { .compatible = "lantiq,wdt-falcon"},
{},
};
MODULE_DEVICE_TABLE(of, ltq_wdt_match);
--
2.11.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v3 05/16] watchdog: lantiq: add device tree binding documentation
2017-05-28 18:39 ` Hauke Mehrtens
@ 2017-05-28 18:39 ` Hauke Mehrtens
-1 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:39 UTC (permalink / raw)
To: ralf-6z/3iImG2C8G8FEW9MqTrA
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w,
robh-DgEjT+Ai2ygdnm+yROfE0A,
andy.shevchenko-Re5JQEeQqe8AvxtiuMwx3w,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ, Hauke Mehrtens
The binding was not documented before, add the documentation now.
Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
.../devicetree/bindings/watchdog/lantiq-wdt.txt | 28 ++++++++++++++++++++++
1 file changed, 28 insertions(+)
create mode 100644 Documentation/devicetree/bindings/watchdog/lantiq-wdt.txt
diff --git a/Documentation/devicetree/bindings/watchdog/lantiq-wdt.txt b/Documentation/devicetree/bindings/watchdog/lantiq-wdt.txt
new file mode 100644
index 000000000000..675c30e23b65
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/lantiq-wdt.txt
@@ -0,0 +1,28 @@
+Lantiq WTD watchdog binding
+============================
+
+This describes the binding of the Lantiq watchdog driver.
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible : Should be one of
+ "lantiq,wdt"
+ "lantiq,wdt-xrx100"
+ "lantiq,wdt-falcon"
+
+Optional properties:
+- regmap : A phandle to the RCU syscon
+- offset-status : Offset of the reset cause register
+- mask-status : Mask of the reset cause register value
+
+
+-------------------------------------------------------------------------------
+Example for the watchdog on the xRX200 SoCs:
+ watchdog@803F0 {
+ compatible = "lantiq,wdt-xrx200", "lantiq,wdt-xrx100";
+ reg = <0x803F0 0x10>;
+
+ regmap = <&rcu0>;
+ offset-status = <0x14>;
+ mask-status = <0x80000000>;
+ };
--
2.11.0
--
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^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v3 05/16] watchdog: lantiq: add device tree binding documentation
@ 2017-05-28 18:39 ` Hauke Mehrtens
0 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:39 UTC (permalink / raw)
To: ralf
Cc: linux-mips, linux-mtd, linux-watchdog, devicetree,
martin.blumenstingl, john, linux-spi, hauke.mehrtens, robh,
andy.shevchenko, p.zabel, Hauke Mehrtens
The binding was not documented before, add the documentation now.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
.../devicetree/bindings/watchdog/lantiq-wdt.txt | 28 ++++++++++++++++++++++
1 file changed, 28 insertions(+)
create mode 100644 Documentation/devicetree/bindings/watchdog/lantiq-wdt.txt
diff --git a/Documentation/devicetree/bindings/watchdog/lantiq-wdt.txt b/Documentation/devicetree/bindings/watchdog/lantiq-wdt.txt
new file mode 100644
index 000000000000..675c30e23b65
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/lantiq-wdt.txt
@@ -0,0 +1,28 @@
+Lantiq WTD watchdog binding
+============================
+
+This describes the binding of the Lantiq watchdog driver.
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible : Should be one of
+ "lantiq,wdt"
+ "lantiq,wdt-xrx100"
+ "lantiq,wdt-falcon"
+
+Optional properties:
+- regmap : A phandle to the RCU syscon
+- offset-status : Offset of the reset cause register
+- mask-status : Mask of the reset cause register value
+
+
+-------------------------------------------------------------------------------
+Example for the watchdog on the xRX200 SoCs:
+ watchdog@803F0 {
+ compatible = "lantiq,wdt-xrx200", "lantiq,wdt-xrx100";
+ reg = <0x803F0 0x10>;
+
+ regmap = <&rcu0>;
+ offset-status = <0x14>;
+ mask-status = <0x80000000>;
+ };
--
2.11.0
^ permalink raw reply related [flat|nested] 60+ messages in thread[parent not found: <20170528184006.31668-6-hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>]
* Re: [PATCH v3 05/16] watchdog: lantiq: add device tree binding documentation
2017-05-28 18:39 ` Hauke Mehrtens
@ 2017-05-31 20:00 ` Rob Herring
-1 siblings, 0 replies; 60+ messages in thread
From: Rob Herring @ 2017-05-31 20:00 UTC (permalink / raw)
To: Hauke Mehrtens
Cc: ralf-6z/3iImG2C8G8FEW9MqTrA, linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w,
andy.shevchenko-Re5JQEeQqe8AvxtiuMwx3w,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ
On Sun, May 28, 2017 at 08:39:55PM +0200, Hauke Mehrtens wrote:
> The binding was not documented before, add the documentation now.
>
> Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
> ---
> .../devicetree/bindings/watchdog/lantiq-wdt.txt | 28 ++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/watchdog/lantiq-wdt.txt
>
> diff --git a/Documentation/devicetree/bindings/watchdog/lantiq-wdt.txt b/Documentation/devicetree/bindings/watchdog/lantiq-wdt.txt
> new file mode 100644
> index 000000000000..675c30e23b65
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/watchdog/lantiq-wdt.txt
> @@ -0,0 +1,28 @@
> +Lantiq WTD watchdog binding
> +============================
> +
> +This describes the binding of the Lantiq watchdog driver.
> +
> +-------------------------------------------------------------------------------
> +Required properties:
> +- compatible : Should be one of
> + "lantiq,wdt"
> + "lantiq,wdt-xrx100"
> + "lantiq,wdt-falcon"
> +
> +Optional properties:
> +- regmap : A phandle to the RCU syscon
> +- offset-status : Offset of the reset cause register
> +- mask-status : Mask of the reset cause register value
These 2 should be implied by the compatible. But if already used in
upstream dts files, then it's okay.
> +
> +
> +-------------------------------------------------------------------------------
> +Example for the watchdog on the xRX200 SoCs:
> + watchdog@803F0 {
Lowercase hex please.
> + compatible = "lantiq,wdt-xrx200", "lantiq,wdt-xrx100";
Doesn't match the documentation.
> + reg = <0x803F0 0x10>;
Lowercase hex please.
> +
> + regmap = <&rcu0>;
> + offset-status = <0x14>;
> + mask-status = <0x80000000>;
> + };
> --
> 2.11.0
>
--
To unsubscribe from this list: send the line "unsubscribe linux-watchdog" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH v3 05/16] watchdog: lantiq: add device tree binding documentation
@ 2017-05-31 20:00 ` Rob Herring
0 siblings, 0 replies; 60+ messages in thread
From: Rob Herring @ 2017-05-31 20:00 UTC (permalink / raw)
To: Hauke Mehrtens
Cc: ralf, linux-mips, linux-mtd, linux-watchdog, devicetree,
martin.blumenstingl, john, linux-spi, hauke.mehrtens,
andy.shevchenko, p.zabel
On Sun, May 28, 2017 at 08:39:55PM +0200, Hauke Mehrtens wrote:
> The binding was not documented before, add the documentation now.
>
> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
> ---
> .../devicetree/bindings/watchdog/lantiq-wdt.txt | 28 ++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/watchdog/lantiq-wdt.txt
>
> diff --git a/Documentation/devicetree/bindings/watchdog/lantiq-wdt.txt b/Documentation/devicetree/bindings/watchdog/lantiq-wdt.txt
> new file mode 100644
> index 000000000000..675c30e23b65
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/watchdog/lantiq-wdt.txt
> @@ -0,0 +1,28 @@
> +Lantiq WTD watchdog binding
> +============================
> +
> +This describes the binding of the Lantiq watchdog driver.
> +
> +-------------------------------------------------------------------------------
> +Required properties:
> +- compatible : Should be one of
> + "lantiq,wdt"
> + "lantiq,wdt-xrx100"
> + "lantiq,wdt-falcon"
> +
> +Optional properties:
> +- regmap : A phandle to the RCU syscon
> +- offset-status : Offset of the reset cause register
> +- mask-status : Mask of the reset cause register value
These 2 should be implied by the compatible. But if already used in
upstream dts files, then it's okay.
> +
> +
> +-------------------------------------------------------------------------------
> +Example for the watchdog on the xRX200 SoCs:
> + watchdog@803F0 {
Lowercase hex please.
> + compatible = "lantiq,wdt-xrx200", "lantiq,wdt-xrx100";
Doesn't match the documentation.
> + reg = <0x803F0 0x10>;
Lowercase hex please.
> +
> + regmap = <&rcu0>;
> + offset-status = <0x14>;
> + mask-status = <0x80000000>;
> + };
> --
> 2.11.0
>
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH v3 05/16] watchdog: lantiq: add device tree binding documentation
2017-05-31 20:00 ` Rob Herring
@ 2017-05-31 20:11 ` Hauke Mehrtens
-1 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-31 20:11 UTC (permalink / raw)
To: Rob Herring
Cc: ralf-6z/3iImG2C8G8FEW9MqTrA, linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w,
andy.shevchenko-Re5JQEeQqe8AvxtiuMwx3w,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ
On 05/31/2017 10:00 PM, Rob Herring wrote:
> On Sun, May 28, 2017 at 08:39:55PM +0200, Hauke Mehrtens wrote:
>> The binding was not documented before, add the documentation now.
>>
>> Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
>> ---
>> .../devicetree/bindings/watchdog/lantiq-wdt.txt | 28 ++++++++++++++++++++++
>> 1 file changed, 28 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/watchdog/lantiq-wdt.txt
>>
>> diff --git a/Documentation/devicetree/bindings/watchdog/lantiq-wdt.txt b/Documentation/devicetree/bindings/watchdog/lantiq-wdt.txt
>> new file mode 100644
>> index 000000000000..675c30e23b65
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/watchdog/lantiq-wdt.txt
>> @@ -0,0 +1,28 @@
>> +Lantiq WTD watchdog binding
>> +============================
>> +
>> +This describes the binding of the Lantiq watchdog driver.
>> +
>> +-------------------------------------------------------------------------------
>> +Required properties:
>> +- compatible : Should be one of
>> + "lantiq,wdt"
>> + "lantiq,wdt-xrx100"
>> + "lantiq,wdt-falcon"
>> +
>> +Optional properties:
>> +- regmap : A phandle to the RCU syscon
>> +- offset-status : Offset of the reset cause register
>> +- mask-status : Mask of the reset cause register value
>
> These 2 should be implied by the compatible. But if already used in
> upstream dts files, then it's okay.
This is new.
Should I hard code the offsets of the register and the actual bits
depending on the compatible string in the driver instead of configuring
it in the device tree?
>> +
>> +
>> +-------------------------------------------------------------------------------
>> +Example for the watchdog on the xRX200 SoCs:
>> + watchdog@803F0 {
>
> Lowercase hex please.
>
>> + compatible = "lantiq,wdt-xrx200", "lantiq,wdt-xrx100";
>
> Doesn't match the documentation.
>
>> + reg = <0x803F0 0x10>;
>
> Lowercase hex please.
>
>> +
>> + regmap = <&rcu0>;
>> + offset-status = <0x14>;
>> + mask-status = <0x80000000>;
>> + };
>> --
>> 2.11.0
>>
--
To unsubscribe from this list: send the line "unsubscribe linux-watchdog" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH v3 05/16] watchdog: lantiq: add device tree binding documentation
@ 2017-05-31 20:11 ` Hauke Mehrtens
0 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-31 20:11 UTC (permalink / raw)
To: Rob Herring
Cc: ralf, linux-mips, linux-mtd, linux-watchdog, devicetree,
martin.blumenstingl, john, linux-spi, hauke.mehrtens,
andy.shevchenko, p.zabel
On 05/31/2017 10:00 PM, Rob Herring wrote:
> On Sun, May 28, 2017 at 08:39:55PM +0200, Hauke Mehrtens wrote:
>> The binding was not documented before, add the documentation now.
>>
>> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
>> ---
>> .../devicetree/bindings/watchdog/lantiq-wdt.txt | 28 ++++++++++++++++++++++
>> 1 file changed, 28 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/watchdog/lantiq-wdt.txt
>>
>> diff --git a/Documentation/devicetree/bindings/watchdog/lantiq-wdt.txt b/Documentation/devicetree/bindings/watchdog/lantiq-wdt.txt
>> new file mode 100644
>> index 000000000000..675c30e23b65
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/watchdog/lantiq-wdt.txt
>> @@ -0,0 +1,28 @@
>> +Lantiq WTD watchdog binding
>> +============================
>> +
>> +This describes the binding of the Lantiq watchdog driver.
>> +
>> +-------------------------------------------------------------------------------
>> +Required properties:
>> +- compatible : Should be one of
>> + "lantiq,wdt"
>> + "lantiq,wdt-xrx100"
>> + "lantiq,wdt-falcon"
>> +
>> +Optional properties:
>> +- regmap : A phandle to the RCU syscon
>> +- offset-status : Offset of the reset cause register
>> +- mask-status : Mask of the reset cause register value
>
> These 2 should be implied by the compatible. But if already used in
> upstream dts files, then it's okay.
This is new.
Should I hard code the offsets of the register and the actual bits
depending on the compatible string in the driver instead of configuring
it in the device tree?
>> +
>> +
>> +-------------------------------------------------------------------------------
>> +Example for the watchdog on the xRX200 SoCs:
>> + watchdog@803F0 {
>
> Lowercase hex please.
>
>> + compatible = "lantiq,wdt-xrx200", "lantiq,wdt-xrx100";
>
> Doesn't match the documentation.
>
>> + reg = <0x803F0 0x10>;
>
> Lowercase hex please.
>
>> +
>> + regmap = <&rcu0>;
>> + offset-status = <0x14>;
>> + mask-status = <0x80000000>;
>> + };
>> --
>> 2.11.0
>>
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v3 06/16] MIPS: lantiq: Enable MFD_SYSCON to be able to use it for the RCU MFD
2017-05-28 18:39 ` Hauke Mehrtens
@ 2017-05-28 18:39 ` Hauke Mehrtens
-1 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:39 UTC (permalink / raw)
To: ralf-6z/3iImG2C8G8FEW9MqTrA
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w,
robh-DgEjT+Ai2ygdnm+yROfE0A,
andy.shevchenko-Re5JQEeQqe8AvxtiuMwx3w,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ, Hauke Mehrtens
From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
arch/mips/lantiq/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig
index 177769dbb0e8..f5db4a426568 100644
--- a/arch/mips/lantiq/Kconfig
+++ b/arch/mips/lantiq/Kconfig
@@ -17,6 +17,7 @@ config SOC_XWAY
bool "XWAY"
select SOC_TYPE_XWAY
select HW_HAS_PCI
+ select MFD_SYSCON
config SOC_FALCON
bool "FALCON"
--
2.11.0
--
To unsubscribe from this list: send the line "unsubscribe linux-spi" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v3 06/16] MIPS: lantiq: Enable MFD_SYSCON to be able to use it for the RCU MFD
@ 2017-05-28 18:39 ` Hauke Mehrtens
0 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:39 UTC (permalink / raw)
To: ralf
Cc: linux-mips, linux-mtd, linux-watchdog, devicetree,
martin.blumenstingl, john, linux-spi, hauke.mehrtens, robh,
andy.shevchenko, p.zabel, Hauke Mehrtens
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
arch/mips/lantiq/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig
index 177769dbb0e8..f5db4a426568 100644
--- a/arch/mips/lantiq/Kconfig
+++ b/arch/mips/lantiq/Kconfig
@@ -17,6 +17,7 @@ config SOC_XWAY
bool "XWAY"
select SOC_TYPE_XWAY
select HW_HAS_PCI
+ select MFD_SYSCON
config SOC_FALCON
bool "FALCON"
--
2.11.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v3 07/16] Documentation: DT: MIPS: lantiq: Add docs for the RCU bindings
2017-05-28 18:39 ` Hauke Mehrtens
@ 2017-05-28 18:39 ` Hauke Mehrtens
-1 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:39 UTC (permalink / raw)
To: ralf-6z/3iImG2C8G8FEW9MqTrA
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w,
robh-DgEjT+Ai2ygdnm+yROfE0A,
andy.shevchenko-Re5JQEeQqe8AvxtiuMwx3w,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ, Hauke Mehrtens
From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
This adds the initial documentation for the RCU module (a MFD device
which provides USB PHYs, reset controllers and more).
The RCU register range is used for multiple purposes. Mostly one device
uses one or multiple register exclusively, but for some registers some
bits are for one driver and some other bits are for a different driver.
With this patch all accesses to the RCU registers will go through
syscon.
Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
.../devicetree/bindings/mips/lantiq/rcu.txt | 97 ++++++++++++++++++++++
1 file changed, 97 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu.txt
diff --git a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
new file mode 100644
index 000000000000..3e2461262218
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
@@ -0,0 +1,97 @@
+Lantiq XWAY SoC RCU binding
+===========================
+
+This binding describes the RCU (reset controller unit) multifunction device,
+where each sub-device has it's own set of registers.
+
+The RCU register range is used for multiple purposes. Mostly one device
+uses one or multiple register exclusively, but for some registers some
+bits are for one driver and some other bits are for a different driver.
+With this patch all accesses to the RCU registers will go through
+syscon.
+
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible : The first and second values must be: "simple-mfd", "syscon"
+- reg : The address and length of the system control registers
+
+
+-------------------------------------------------------------------------------
+Example of the RCU bindings on a xRX200 SoC:
+ rcu0: rcu@203000 {
+ compatible = "lantiq,rcu-xrx200", "simple-mfd", "syscon";
+ reg = <0x203000 0x100>;
+ big-endian;
+
+ gphy0: gphy@0 {
+ compatible = "lantiq,xrx200a2x-rcu-gphy";
+
+ regmap = <&rcu0>;
+ offset = <0x20>;
+ resets = <&reset0 31 30>, <&reset1 7 7>;
+ reset-names = "gphy", "gphy2";
+ lantiq,gphy-mode = <GPHY_MODE_GE>;
+ };
+
+ gphy1: gphy@1 {
+ compatible = "lantiq,xrx200a2x-rcu-gphy";
+
+ regmap = <&rcu0>;
+ offset = <0x68>;
+ resets = <&reset0 29 28>, <&reset1 6 6>;
+ reset-names = "gphy", "gphy2";
+ lantiq,gphy-mode = <GPHY_MODE_GE>;
+ };
+
+ reset0: reset-controller@0 {
+ compatible = "lantiq,rcu-reset";
+
+ regmap = <&rcu0>;
+ offset-set = <0x10>;
+ offset-status = <0x14>;
+ #reset-cells = <2>;
+ };
+
+ reset1: reset-controller@1 {
+ compatible = "lantiq,rcu-reset";
+
+ regmap = <&rcu0>;
+ offset-set = <0x48>;
+ offset-status = <0x24>;
+ #reset-cells = <2>;
+ };
+
+ usb_phy0: usb2-phy@0 {
+ compatible = "lantiq,xrx200-rcu-usb2-phy";
+ status = "disabled";
+
+ regmap = <&rcu0>;
+ offset-phy = <0x18>;
+ offset-ana = <0x38>;
+ resets = <&reset1 4 4>, <&reset0 4 4>;
+ reset-names = "phy", "ctrl";
+ #phy-cells = <0>;
+ };
+
+ usb_phy1: usb2-phy@1 {
+ compatible = "lantiq,xrx200-rcu-usb2-phy";
+ status = "disabled";
+
+ regmap = <&rcu0>;
+ offset-phy = <0x34>;
+ offset-ana = <0x3C>;
+ resets = <&reset1 5 4>, <&reset0 4 4>;
+ reset-names = "phy", "ctrl";
+ #phy-cells = <0>;
+ };
+
+ reboot {
+ compatible = "syscon-reboot";
+
+ regmap = <&rcu0>;
+ offset = <0x10>;
+ mask = <0x40000000>;
+ };
+ };
+
--
2.11.0
--
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^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v3 07/16] Documentation: DT: MIPS: lantiq: Add docs for the RCU bindings
@ 2017-05-28 18:39 ` Hauke Mehrtens
0 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:39 UTC (permalink / raw)
To: ralf
Cc: linux-mips, linux-mtd, linux-watchdog, devicetree,
martin.blumenstingl, john, linux-spi, hauke.mehrtens, robh,
andy.shevchenko, p.zabel, Hauke Mehrtens
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
This adds the initial documentation for the RCU module (a MFD device
which provides USB PHYs, reset controllers and more).
The RCU register range is used for multiple purposes. Mostly one device
uses one or multiple register exclusively, but for some registers some
bits are for one driver and some other bits are for a different driver.
With this patch all accesses to the RCU registers will go through
syscon.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
.../devicetree/bindings/mips/lantiq/rcu.txt | 97 ++++++++++++++++++++++
1 file changed, 97 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu.txt
diff --git a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
new file mode 100644
index 000000000000..3e2461262218
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
@@ -0,0 +1,97 @@
+Lantiq XWAY SoC RCU binding
+===========================
+
+This binding describes the RCU (reset controller unit) multifunction device,
+where each sub-device has it's own set of registers.
+
+The RCU register range is used for multiple purposes. Mostly one device
+uses one or multiple register exclusively, but for some registers some
+bits are for one driver and some other bits are for a different driver.
+With this patch all accesses to the RCU registers will go through
+syscon.
+
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible : The first and second values must be: "simple-mfd", "syscon"
+- reg : The address and length of the system control registers
+
+
+-------------------------------------------------------------------------------
+Example of the RCU bindings on a xRX200 SoC:
+ rcu0: rcu@203000 {
+ compatible = "lantiq,rcu-xrx200", "simple-mfd", "syscon";
+ reg = <0x203000 0x100>;
+ big-endian;
+
+ gphy0: gphy@0 {
+ compatible = "lantiq,xrx200a2x-rcu-gphy";
+
+ regmap = <&rcu0>;
+ offset = <0x20>;
+ resets = <&reset0 31 30>, <&reset1 7 7>;
+ reset-names = "gphy", "gphy2";
+ lantiq,gphy-mode = <GPHY_MODE_GE>;
+ };
+
+ gphy1: gphy@1 {
+ compatible = "lantiq,xrx200a2x-rcu-gphy";
+
+ regmap = <&rcu0>;
+ offset = <0x68>;
+ resets = <&reset0 29 28>, <&reset1 6 6>;
+ reset-names = "gphy", "gphy2";
+ lantiq,gphy-mode = <GPHY_MODE_GE>;
+ };
+
+ reset0: reset-controller@0 {
+ compatible = "lantiq,rcu-reset";
+
+ regmap = <&rcu0>;
+ offset-set = <0x10>;
+ offset-status = <0x14>;
+ #reset-cells = <2>;
+ };
+
+ reset1: reset-controller@1 {
+ compatible = "lantiq,rcu-reset";
+
+ regmap = <&rcu0>;
+ offset-set = <0x48>;
+ offset-status = <0x24>;
+ #reset-cells = <2>;
+ };
+
+ usb_phy0: usb2-phy@0 {
+ compatible = "lantiq,xrx200-rcu-usb2-phy";
+ status = "disabled";
+
+ regmap = <&rcu0>;
+ offset-phy = <0x18>;
+ offset-ana = <0x38>;
+ resets = <&reset1 4 4>, <&reset0 4 4>;
+ reset-names = "phy", "ctrl";
+ #phy-cells = <0>;
+ };
+
+ usb_phy1: usb2-phy@1 {
+ compatible = "lantiq,xrx200-rcu-usb2-phy";
+ status = "disabled";
+
+ regmap = <&rcu0>;
+ offset-phy = <0x34>;
+ offset-ana = <0x3C>;
+ resets = <&reset1 5 4>, <&reset0 4 4>;
+ reset-names = "phy", "ctrl";
+ #phy-cells = <0>;
+ };
+
+ reboot {
+ compatible = "syscon-reboot";
+
+ regmap = <&rcu0>;
+ offset = <0x10>;
+ mask = <0x40000000>;
+ };
+ };
+
--
2.11.0
^ permalink raw reply related [flat|nested] 60+ messages in thread[parent not found: <20170528184006.31668-8-hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>]
* Re: [PATCH v3 07/16] Documentation: DT: MIPS: lantiq: Add docs for the RCU bindings
2017-05-28 18:39 ` Hauke Mehrtens
@ 2017-05-31 20:05 ` Rob Herring
-1 siblings, 0 replies; 60+ messages in thread
From: Rob Herring @ 2017-05-31 20:05 UTC (permalink / raw)
To: Hauke Mehrtens
Cc: ralf-6z/3iImG2C8G8FEW9MqTrA, linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w,
andy.shevchenko-Re5JQEeQqe8AvxtiuMwx3w,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ
On Sun, May 28, 2017 at 08:39:57PM +0200, Hauke Mehrtens wrote:
> From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
>
> This adds the initial documentation for the RCU module (a MFD device
> which provides USB PHYs, reset controllers and more).
>
> The RCU register range is used for multiple purposes. Mostly one device
> uses one or multiple register exclusively, but for some registers some
> bits are for one driver and some other bits are for a different driver.
> With this patch all accesses to the RCU registers will go through
> syscon.
>
> Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
> ---
> .../devicetree/bindings/mips/lantiq/rcu.txt | 97 ++++++++++++++++++++++
> 1 file changed, 97 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu.txt
>
> diff --git a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
> new file mode 100644
> index 000000000000..3e2461262218
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
> @@ -0,0 +1,97 @@
> +Lantiq XWAY SoC RCU binding
> +===========================
> +
> +This binding describes the RCU (reset controller unit) multifunction device,
> +where each sub-device has it's own set of registers.
> +
> +The RCU register range is used for multiple purposes. Mostly one device
> +uses one or multiple register exclusively, but for some registers some
> +bits are for one driver and some other bits are for a different driver.
> +With this patch all accesses to the RCU registers will go through
> +syscon.
> +
> +
> +-------------------------------------------------------------------------------
> +Required properties:
> +- compatible : The first and second values must be: "simple-mfd", "syscon"
> +- reg : The address and length of the system control registers
> +
> +
> +-------------------------------------------------------------------------------
> +Example of the RCU bindings on a xRX200 SoC:
> + rcu0: rcu@203000 {
> + compatible = "lantiq,rcu-xrx200", "simple-mfd", "syscon";
> + reg = <0x203000 0x100>;
> + big-endian;
> +
> + gphy0: gphy@0 {
Unit address without reg address is not valid.
> + compatible = "lantiq,xrx200a2x-rcu-gphy";
> +
> + regmap = <&rcu0>;
> + offset = <0x20>;
Does reg not work instead?
> + resets = <&reset0 31 30>, <&reset1 7 7>;
> + reset-names = "gphy", "gphy2";
> + lantiq,gphy-mode = <GPHY_MODE_GE>;
> + };
> +
> + gphy1: gphy@1 {
> + compatible = "lantiq,xrx200a2x-rcu-gphy";
> +
> + regmap = <&rcu0>;
> + offset = <0x68>;
> + resets = <&reset0 29 28>, <&reset1 6 6>;
> + reset-names = "gphy", "gphy2";
> + lantiq,gphy-mode = <GPHY_MODE_GE>;
> + };
> +
> + reset0: reset-controller@0 {
> + compatible = "lantiq,rcu-reset";
> +
> + regmap = <&rcu0>;
> + offset-set = <0x10>;
> + offset-status = <0x14>;
> + #reset-cells = <2>;
> + };
> +
> + reset1: reset-controller@1 {
> + compatible = "lantiq,rcu-reset";
> +
> + regmap = <&rcu0>;
> + offset-set = <0x48>;
> + offset-status = <0x24>;
> + #reset-cells = <2>;
> + };
> +
> + usb_phy0: usb2-phy@0 {
> + compatible = "lantiq,xrx200-rcu-usb2-phy";
> + status = "disabled";
> +
> + regmap = <&rcu0>;
> + offset-phy = <0x18>;
> + offset-ana = <0x38>;
> + resets = <&reset1 4 4>, <&reset0 4 4>;
> + reset-names = "phy", "ctrl";
> + #phy-cells = <0>;
> + };
> +
> + usb_phy1: usb2-phy@1 {
> + compatible = "lantiq,xrx200-rcu-usb2-phy";
> + status = "disabled";
> +
> + regmap = <&rcu0>;
> + offset-phy = <0x34>;
> + offset-ana = <0x3C>;
> + resets = <&reset1 5 4>, <&reset0 4 4>;
> + reset-names = "phy", "ctrl";
> + #phy-cells = <0>;
> + };
> +
> + reboot {
> + compatible = "syscon-reboot";
> +
> + regmap = <&rcu0>;
> + offset = <0x10>;
> + mask = <0x40000000>;
> + };
> + };
> +
> --
> 2.11.0
>
--
To unsubscribe from this list: send the line "unsubscribe linux-spi" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH v3 07/16] Documentation: DT: MIPS: lantiq: Add docs for the RCU bindings
@ 2017-05-31 20:05 ` Rob Herring
0 siblings, 0 replies; 60+ messages in thread
From: Rob Herring @ 2017-05-31 20:05 UTC (permalink / raw)
To: Hauke Mehrtens
Cc: ralf, linux-mips, linux-mtd, linux-watchdog, devicetree,
martin.blumenstingl, john, linux-spi, hauke.mehrtens,
andy.shevchenko, p.zabel
On Sun, May 28, 2017 at 08:39:57PM +0200, Hauke Mehrtens wrote:
> From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>
> This adds the initial documentation for the RCU module (a MFD device
> which provides USB PHYs, reset controllers and more).
>
> The RCU register range is used for multiple purposes. Mostly one device
> uses one or multiple register exclusively, but for some registers some
> bits are for one driver and some other bits are for a different driver.
> With this patch all accesses to the RCU registers will go through
> syscon.
>
> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
> ---
> .../devicetree/bindings/mips/lantiq/rcu.txt | 97 ++++++++++++++++++++++
> 1 file changed, 97 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu.txt
>
> diff --git a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
> new file mode 100644
> index 000000000000..3e2461262218
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
> @@ -0,0 +1,97 @@
> +Lantiq XWAY SoC RCU binding
> +===========================
> +
> +This binding describes the RCU (reset controller unit) multifunction device,
> +where each sub-device has it's own set of registers.
> +
> +The RCU register range is used for multiple purposes. Mostly one device
> +uses one or multiple register exclusively, but for some registers some
> +bits are for one driver and some other bits are for a different driver.
> +With this patch all accesses to the RCU registers will go through
> +syscon.
> +
> +
> +-------------------------------------------------------------------------------
> +Required properties:
> +- compatible : The first and second values must be: "simple-mfd", "syscon"
> +- reg : The address and length of the system control registers
> +
> +
> +-------------------------------------------------------------------------------
> +Example of the RCU bindings on a xRX200 SoC:
> + rcu0: rcu@203000 {
> + compatible = "lantiq,rcu-xrx200", "simple-mfd", "syscon";
> + reg = <0x203000 0x100>;
> + big-endian;
> +
> + gphy0: gphy@0 {
Unit address without reg address is not valid.
> + compatible = "lantiq,xrx200a2x-rcu-gphy";
> +
> + regmap = <&rcu0>;
> + offset = <0x20>;
Does reg not work instead?
> + resets = <&reset0 31 30>, <&reset1 7 7>;
> + reset-names = "gphy", "gphy2";
> + lantiq,gphy-mode = <GPHY_MODE_GE>;
> + };
> +
> + gphy1: gphy@1 {
> + compatible = "lantiq,xrx200a2x-rcu-gphy";
> +
> + regmap = <&rcu0>;
> + offset = <0x68>;
> + resets = <&reset0 29 28>, <&reset1 6 6>;
> + reset-names = "gphy", "gphy2";
> + lantiq,gphy-mode = <GPHY_MODE_GE>;
> + };
> +
> + reset0: reset-controller@0 {
> + compatible = "lantiq,rcu-reset";
> +
> + regmap = <&rcu0>;
> + offset-set = <0x10>;
> + offset-status = <0x14>;
> + #reset-cells = <2>;
> + };
> +
> + reset1: reset-controller@1 {
> + compatible = "lantiq,rcu-reset";
> +
> + regmap = <&rcu0>;
> + offset-set = <0x48>;
> + offset-status = <0x24>;
> + #reset-cells = <2>;
> + };
> +
> + usb_phy0: usb2-phy@0 {
> + compatible = "lantiq,xrx200-rcu-usb2-phy";
> + status = "disabled";
> +
> + regmap = <&rcu0>;
> + offset-phy = <0x18>;
> + offset-ana = <0x38>;
> + resets = <&reset1 4 4>, <&reset0 4 4>;
> + reset-names = "phy", "ctrl";
> + #phy-cells = <0>;
> + };
> +
> + usb_phy1: usb2-phy@1 {
> + compatible = "lantiq,xrx200-rcu-usb2-phy";
> + status = "disabled";
> +
> + regmap = <&rcu0>;
> + offset-phy = <0x34>;
> + offset-ana = <0x3C>;
> + resets = <&reset1 5 4>, <&reset0 4 4>;
> + reset-names = "phy", "ctrl";
> + #phy-cells = <0>;
> + };
> +
> + reboot {
> + compatible = "syscon-reboot";
> +
> + regmap = <&rcu0>;
> + offset = <0x10>;
> + mask = <0x40000000>;
> + };
> + };
> +
> --
> 2.11.0
>
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH v3 07/16] Documentation: DT: MIPS: lantiq: Add docs for the RCU bindings
2017-05-31 20:05 ` Rob Herring
@ 2017-05-31 20:13 ` Hauke Mehrtens
-1 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-31 20:13 UTC (permalink / raw)
To: Rob Herring
Cc: ralf-6z/3iImG2C8G8FEW9MqTrA, linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w,
andy.shevchenko-Re5JQEeQqe8AvxtiuMwx3w,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ
On 05/31/2017 10:05 PM, Rob Herring wrote:
> On Sun, May 28, 2017 at 08:39:57PM +0200, Hauke Mehrtens wrote:
>> From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
>>
>> This adds the initial documentation for the RCU module (a MFD device
>> which provides USB PHYs, reset controllers and more).
>>
>> The RCU register range is used for multiple purposes. Mostly one device
>> uses one or multiple register exclusively, but for some registers some
>> bits are for one driver and some other bits are for a different driver.
>> With this patch all accesses to the RCU registers will go through
>> syscon.
>>
>> Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
>> ---
>> .../devicetree/bindings/mips/lantiq/rcu.txt | 97 ++++++++++++++++++++++
>> 1 file changed, 97 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu.txt
>>
>> diff --git a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
>> new file mode 100644
>> index 000000000000..3e2461262218
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
>> @@ -0,0 +1,97 @@
>> +Lantiq XWAY SoC RCU binding
>> +===========================
>> +
>> +This binding describes the RCU (reset controller unit) multifunction device,
>> +where each sub-device has it's own set of registers.
>> +
>> +The RCU register range is used for multiple purposes. Mostly one device
>> +uses one or multiple register exclusively, but for some registers some
>> +bits are for one driver and some other bits are for a different driver.
>> +With this patch all accesses to the RCU registers will go through
>> +syscon.
>> +
>> +
>> +-------------------------------------------------------------------------------
>> +Required properties:
>> +- compatible : The first and second values must be: "simple-mfd", "syscon"
>> +- reg : The address and length of the system control registers
>> +
>> +
>> +-------------------------------------------------------------------------------
>> +Example of the RCU bindings on a xRX200 SoC:
>> + rcu0: rcu@203000 {
>> + compatible = "lantiq,rcu-xrx200", "simple-mfd", "syscon";
>> + reg = <0x203000 0x100>;
>> + big-endian;
>> +
>> + gphy0: gphy@0 {
>
> Unit address without reg address is not valid.
>
>> + compatible = "lantiq,xrx200a2x-rcu-gphy";
>> +
>> + regmap = <&rcu0>;
>> + offset = <0x20>;
>
> Does reg not work instead?
Is it ok to access some registers in this range with a reg = <0x20 0x04>
setting and some others through syscon? This specific register is only
used by this gphy, but the reset controller shares the register with
some other drivers like the watchdog driver.
>> + resets = <&reset0 31 30>, <&reset1 7 7>;
>> + reset-names = "gphy", "gphy2";
>> + lantiq,gphy-mode = <GPHY_MODE_GE>;
>> + };
>> +
>> + gphy1: gphy@1 {
>> + compatible = "lantiq,xrx200a2x-rcu-gphy";
>> +
>> + regmap = <&rcu0>;
>> + offset = <0x68>;
>> + resets = <&reset0 29 28>, <&reset1 6 6>;
>> + reset-names = "gphy", "gphy2";
>> + lantiq,gphy-mode = <GPHY_MODE_GE>;
>> + };
>> +
>> + reset0: reset-controller@0 {
>> + compatible = "lantiq,rcu-reset";
>> +
>> + regmap = <&rcu0>;
>> + offset-set = <0x10>;
>> + offset-status = <0x14>;
>> + #reset-cells = <2>;
>> + };
>> +
>> + reset1: reset-controller@1 {
>> + compatible = "lantiq,rcu-reset";
>> +
>> + regmap = <&rcu0>;
>> + offset-set = <0x48>;
>> + offset-status = <0x24>;
>> + #reset-cells = <2>;
>> + };
>> +
>> + usb_phy0: usb2-phy@0 {
>> + compatible = "lantiq,xrx200-rcu-usb2-phy";
>> + status = "disabled";
>> +
>> + regmap = <&rcu0>;
>> + offset-phy = <0x18>;
>> + offset-ana = <0x38>;
>> + resets = <&reset1 4 4>, <&reset0 4 4>;
>> + reset-names = "phy", "ctrl";
>> + #phy-cells = <0>;
>> + };
>> +
>> + usb_phy1: usb2-phy@1 {
>> + compatible = "lantiq,xrx200-rcu-usb2-phy";
>> + status = "disabled";
>> +
>> + regmap = <&rcu0>;
>> + offset-phy = <0x34>;
>> + offset-ana = <0x3C>;
>> + resets = <&reset1 5 4>, <&reset0 4 4>;
>> + reset-names = "phy", "ctrl";
>> + #phy-cells = <0>;
>> + };
>> +
>> + reboot {
>> + compatible = "syscon-reboot";
>> +
>> + regmap = <&rcu0>;
>> + offset = <0x10>;
>> + mask = <0x40000000>;
>> + };
>> + };
>> +
>> --
>> 2.11.0
>>
--
To unsubscribe from this list: send the line "unsubscribe linux-watchdog" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH v3 07/16] Documentation: DT: MIPS: lantiq: Add docs for the RCU bindings
@ 2017-05-31 20:13 ` Hauke Mehrtens
0 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-31 20:13 UTC (permalink / raw)
To: Rob Herring
Cc: ralf, linux-mips, linux-mtd, linux-watchdog, devicetree,
martin.blumenstingl, john, linux-spi, hauke.mehrtens,
andy.shevchenko, p.zabel
On 05/31/2017 10:05 PM, Rob Herring wrote:
> On Sun, May 28, 2017 at 08:39:57PM +0200, Hauke Mehrtens wrote:
>> From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>>
>> This adds the initial documentation for the RCU module (a MFD device
>> which provides USB PHYs, reset controllers and more).
>>
>> The RCU register range is used for multiple purposes. Mostly one device
>> uses one or multiple register exclusively, but for some registers some
>> bits are for one driver and some other bits are for a different driver.
>> With this patch all accesses to the RCU registers will go through
>> syscon.
>>
>> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
>> ---
>> .../devicetree/bindings/mips/lantiq/rcu.txt | 97 ++++++++++++++++++++++
>> 1 file changed, 97 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu.txt
>>
>> diff --git a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
>> new file mode 100644
>> index 000000000000..3e2461262218
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
>> @@ -0,0 +1,97 @@
>> +Lantiq XWAY SoC RCU binding
>> +===========================
>> +
>> +This binding describes the RCU (reset controller unit) multifunction device,
>> +where each sub-device has it's own set of registers.
>> +
>> +The RCU register range is used for multiple purposes. Mostly one device
>> +uses one or multiple register exclusively, but for some registers some
>> +bits are for one driver and some other bits are for a different driver.
>> +With this patch all accesses to the RCU registers will go through
>> +syscon.
>> +
>> +
>> +-------------------------------------------------------------------------------
>> +Required properties:
>> +- compatible : The first and second values must be: "simple-mfd", "syscon"
>> +- reg : The address and length of the system control registers
>> +
>> +
>> +-------------------------------------------------------------------------------
>> +Example of the RCU bindings on a xRX200 SoC:
>> + rcu0: rcu@203000 {
>> + compatible = "lantiq,rcu-xrx200", "simple-mfd", "syscon";
>> + reg = <0x203000 0x100>;
>> + big-endian;
>> +
>> + gphy0: gphy@0 {
>
> Unit address without reg address is not valid.
>
>> + compatible = "lantiq,xrx200a2x-rcu-gphy";
>> +
>> + regmap = <&rcu0>;
>> + offset = <0x20>;
>
> Does reg not work instead?
Is it ok to access some registers in this range with a reg = <0x20 0x04>
setting and some others through syscon? This specific register is only
used by this gphy, but the reset controller shares the register with
some other drivers like the watchdog driver.
>> + resets = <&reset0 31 30>, <&reset1 7 7>;
>> + reset-names = "gphy", "gphy2";
>> + lantiq,gphy-mode = <GPHY_MODE_GE>;
>> + };
>> +
>> + gphy1: gphy@1 {
>> + compatible = "lantiq,xrx200a2x-rcu-gphy";
>> +
>> + regmap = <&rcu0>;
>> + offset = <0x68>;
>> + resets = <&reset0 29 28>, <&reset1 6 6>;
>> + reset-names = "gphy", "gphy2";
>> + lantiq,gphy-mode = <GPHY_MODE_GE>;
>> + };
>> +
>> + reset0: reset-controller@0 {
>> + compatible = "lantiq,rcu-reset";
>> +
>> + regmap = <&rcu0>;
>> + offset-set = <0x10>;
>> + offset-status = <0x14>;
>> + #reset-cells = <2>;
>> + };
>> +
>> + reset1: reset-controller@1 {
>> + compatible = "lantiq,rcu-reset";
>> +
>> + regmap = <&rcu0>;
>> + offset-set = <0x48>;
>> + offset-status = <0x24>;
>> + #reset-cells = <2>;
>> + };
>> +
>> + usb_phy0: usb2-phy@0 {
>> + compatible = "lantiq,xrx200-rcu-usb2-phy";
>> + status = "disabled";
>> +
>> + regmap = <&rcu0>;
>> + offset-phy = <0x18>;
>> + offset-ana = <0x38>;
>> + resets = <&reset1 4 4>, <&reset0 4 4>;
>> + reset-names = "phy", "ctrl";
>> + #phy-cells = <0>;
>> + };
>> +
>> + usb_phy1: usb2-phy@1 {
>> + compatible = "lantiq,xrx200-rcu-usb2-phy";
>> + status = "disabled";
>> +
>> + regmap = <&rcu0>;
>> + offset-phy = <0x34>;
>> + offset-ana = <0x3C>;
>> + resets = <&reset1 5 4>, <&reset0 4 4>;
>> + reset-names = "phy", "ctrl";
>> + #phy-cells = <0>;
>> + };
>> +
>> + reboot {
>> + compatible = "syscon-reboot";
>> +
>> + regmap = <&rcu0>;
>> + offset = <0x10>;
>> + mask = <0x40000000>;
>> + };
>> + };
>> +
>> --
>> 2.11.0
>>
^ permalink raw reply [flat|nested] 60+ messages in thread[parent not found: <6b8bb1cd-c090-435d-d150-d53edf04d2df-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>]
* Re: [PATCH v3 07/16] Documentation: DT: MIPS: lantiq: Add docs for the RCU bindings
2017-05-31 20:13 ` Hauke Mehrtens
@ 2017-05-31 21:04 ` Rob Herring
-1 siblings, 0 replies; 60+ messages in thread
From: Rob Herring @ 2017-05-31 21:04 UTC (permalink / raw)
To: Hauke Mehrtens
Cc: Ralf Baechle, Linux-MIPS,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, LINUX-WATCHDOG,
devicetree-u79uwXL29TY76Z2rM5mHXA, Martin Blumenstingl,
John Crispin, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w, Andy Shevchenko,
Philipp Zabel
On Wed, May 31, 2017 at 3:13 PM, Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org> wrote:
> On 05/31/2017 10:05 PM, Rob Herring wrote:
>> On Sun, May 28, 2017 at 08:39:57PM +0200, Hauke Mehrtens wrote:
>>> From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
>>>
>>> This adds the initial documentation for the RCU module (a MFD device
>>> which provides USB PHYs, reset controllers and more).
>>>
>>> The RCU register range is used for multiple purposes. Mostly one device
>>> uses one or multiple register exclusively, but for some registers some
>>> bits are for one driver and some other bits are for a different driver.
>>> With this patch all accesses to the RCU registers will go through
>>> syscon.
>>>
>>> Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
>>> ---
>>> .../devicetree/bindings/mips/lantiq/rcu.txt | 97 ++++++++++++++++++++++
>>> 1 file changed, 97 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
>>> new file mode 100644
>>> index 000000000000..3e2461262218
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
>>> @@ -0,0 +1,97 @@
>>> +Lantiq XWAY SoC RCU binding
>>> +===========================
>>> +
>>> +This binding describes the RCU (reset controller unit) multifunction device,
>>> +where each sub-device has it's own set of registers.
>>> +
>>> +The RCU register range is used for multiple purposes. Mostly one device
>>> +uses one or multiple register exclusively, but for some registers some
>>> +bits are for one driver and some other bits are for a different driver.
>>> +With this patch all accesses to the RCU registers will go through
>>> +syscon.
>>> +
>>> +
>>> +-------------------------------------------------------------------------------
>>> +Required properties:
>>> +- compatible : The first and second values must be: "simple-mfd", "syscon"
>>> +- reg : The address and length of the system control registers
>>> +
>>> +
>>> +-------------------------------------------------------------------------------
>>> +Example of the RCU bindings on a xRX200 SoC:
>>> + rcu0: rcu@203000 {
>>> + compatible = "lantiq,rcu-xrx200", "simple-mfd", "syscon";
>>> + reg = <0x203000 0x100>;
>>> + big-endian;
>>> +
>>> + gphy0: gphy@0 {
>>
>> Unit address without reg address is not valid.
>>
>>> + compatible = "lantiq,xrx200a2x-rcu-gphy";
>>> +
>>> + regmap = <&rcu0>;
>>> + offset = <0x20>;
>>
>> Does reg not work instead?
>
> Is it ok to access some registers in this range with a reg = <0x20 0x04>
> setting and some others through syscon? This specific register is only
> used by this gphy, but the reset controller shares the register with
> some other drivers like the watchdog driver.
Yes. The main thing is you need to use reg where you have unit addresses.
For the syscon-reboot, you could also just not describe in DT and have
the reset ctrlr driver register reboot driver. DT is not the only way
to instantiate drivers.
Rob
--
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^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH v3 07/16] Documentation: DT: MIPS: lantiq: Add docs for the RCU bindings
@ 2017-05-31 21:04 ` Rob Herring
0 siblings, 0 replies; 60+ messages in thread
From: Rob Herring @ 2017-05-31 21:04 UTC (permalink / raw)
To: Hauke Mehrtens
Cc: Ralf Baechle, Linux-MIPS, linux-mtd, LINUX-WATCHDOG, devicetree,
Martin Blumenstingl, John Crispin, linux-spi, hauke.mehrtens,
Andy Shevchenko, Philipp Zabel
On Wed, May 31, 2017 at 3:13 PM, Hauke Mehrtens <hauke@hauke-m.de> wrote:
> On 05/31/2017 10:05 PM, Rob Herring wrote:
>> On Sun, May 28, 2017 at 08:39:57PM +0200, Hauke Mehrtens wrote:
>>> From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>>>
>>> This adds the initial documentation for the RCU module (a MFD device
>>> which provides USB PHYs, reset controllers and more).
>>>
>>> The RCU register range is used for multiple purposes. Mostly one device
>>> uses one or multiple register exclusively, but for some registers some
>>> bits are for one driver and some other bits are for a different driver.
>>> With this patch all accesses to the RCU registers will go through
>>> syscon.
>>>
>>> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
>>> ---
>>> .../devicetree/bindings/mips/lantiq/rcu.txt | 97 ++++++++++++++++++++++
>>> 1 file changed, 97 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
>>> new file mode 100644
>>> index 000000000000..3e2461262218
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
>>> @@ -0,0 +1,97 @@
>>> +Lantiq XWAY SoC RCU binding
>>> +===========================
>>> +
>>> +This binding describes the RCU (reset controller unit) multifunction device,
>>> +where each sub-device has it's own set of registers.
>>> +
>>> +The RCU register range is used for multiple purposes. Mostly one device
>>> +uses one or multiple register exclusively, but for some registers some
>>> +bits are for one driver and some other bits are for a different driver.
>>> +With this patch all accesses to the RCU registers will go through
>>> +syscon.
>>> +
>>> +
>>> +-------------------------------------------------------------------------------
>>> +Required properties:
>>> +- compatible : The first and second values must be: "simple-mfd", "syscon"
>>> +- reg : The address and length of the system control registers
>>> +
>>> +
>>> +-------------------------------------------------------------------------------
>>> +Example of the RCU bindings on a xRX200 SoC:
>>> + rcu0: rcu@203000 {
>>> + compatible = "lantiq,rcu-xrx200", "simple-mfd", "syscon";
>>> + reg = <0x203000 0x100>;
>>> + big-endian;
>>> +
>>> + gphy0: gphy@0 {
>>
>> Unit address without reg address is not valid.
>>
>>> + compatible = "lantiq,xrx200a2x-rcu-gphy";
>>> +
>>> + regmap = <&rcu0>;
>>> + offset = <0x20>;
>>
>> Does reg not work instead?
>
> Is it ok to access some registers in this range with a reg = <0x20 0x04>
> setting and some others through syscon? This specific register is only
> used by this gphy, but the reset controller shares the register with
> some other drivers like the watchdog driver.
Yes. The main thing is you need to use reg where you have unit addresses.
For the syscon-reboot, you could also just not describe in DT and have
the reset ctrlr driver register reboot driver. DT is not the only way
to instantiate drivers.
Rob
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v3 08/16] MIPS: lantiq: Convert the fpi bus driver to a platform_driver
2017-05-28 18:39 ` Hauke Mehrtens
@ 2017-05-28 18:39 ` Hauke Mehrtens
-1 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:39 UTC (permalink / raw)
To: ralf-6z/3iImG2C8G8FEW9MqTrA
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w,
robh-DgEjT+Ai2ygdnm+yROfE0A,
andy.shevchenko-Re5JQEeQqe8AvxtiuMwx3w,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ, Hauke Mehrtens
From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
Instead of hacking the configuration of the FPI bus into the arch code
add an own bus driver for this internal bus. The FPI bus is the main
bus of the SoC. This bus driver makes sure the bus is configured
correctly before the child drivers are getting initialized. This driver
will probably also be used on different SoC later.
Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
.../devicetree/bindings/mips/lantiq/fpi-bus.txt | 33 ++++++++
MAINTAINERS | 1 +
arch/mips/lantiq/xway/reset.c | 4 -
arch/mips/lantiq/xway/sysctrl.c | 41 ----------
drivers/soc/Makefile | 1 +
drivers/soc/lantiq/Makefile | 1 +
drivers/soc/lantiq/fpi-bus.c | 91 ++++++++++++++++++++++
7 files changed, 127 insertions(+), 45 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mips/lantiq/fpi-bus.txt
create mode 100644 drivers/soc/lantiq/Makefile
create mode 100644 drivers/soc/lantiq/fpi-bus.c
diff --git a/Documentation/devicetree/bindings/mips/lantiq/fpi-bus.txt b/Documentation/devicetree/bindings/mips/lantiq/fpi-bus.txt
new file mode 100644
index 000000000000..52d4bb9d2ffa
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/lantiq/fpi-bus.txt
@@ -0,0 +1,33 @@
+Lantiq XWAY SoC FPI BUS binding
+============================
+
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible : Should be one of
+ "lantiq,fpi-xrx200"
+- reg : The address and length of the XBAR configuration register.
+ Address and length of the FPI bus itself
+
+Optional properties:
+- regmap : A phandle to the RCU syscon
+- offset-endianness : Offset of the endianness configuration register
+
+
+-------------------------------------------------------------------------------
+Example for the FPI on the xrx200 SoCs:
+ fpi@10000000 {
+ compatible = "lantiq,fpi-xrx200", "simple-bus";
+ ranges = <0x0 0x10000000 0xF000000>;
+ reg = <0x1F400000 0x1000>,
+ <0x10000000 0xF000000>;
+ regmap = <&rcu0>;
+ offset-endianness = <0x4c>;
+ big-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gptu@E100A00 {
+ ......
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 9e984645c4b0..f2c2acd6f73f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7441,6 +7441,7 @@ M: John Crispin <john-Pj+rj9U5foFAfugRpC6u6w@public.gmane.org>
L: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
S: Maintained
F: arch/mips/lantiq
+F: drivers/soc/lantiq
LAPB module
L: linux-x25-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index 83fd65d76e81..b6752c95a600 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -373,10 +373,6 @@ static int __init mips_reboot_setup(void)
of_machine_is_compatible("lantiq,vr9"))
ltq_usb_init();
- if (of_machine_is_compatible("lantiq,vr9"))
- ltq_rcu_w32(ltq_rcu_r32(RCU_AHB_ENDIAN) | RCU_VR9_BE_AHB1S,
- RCU_AHB_ENDIAN);
-
_machine_restart = ltq_machine_restart;
_machine_halt = ltq_machine_halt;
pm_power_off = ltq_machine_power_off;
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 95bec460b651..706639a343bc 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -145,15 +145,7 @@ static u32 pmu_clk_cr_b[] = {
#define pmu_w32(x, y) ltq_w32((x), pmu_membase + (y))
#define pmu_r32(x) ltq_r32(pmu_membase + (x))
-#define XBAR_ALWAYS_LAST 0x430
-#define XBAR_FPI_BURST_EN BIT(1)
-#define XBAR_AHB_BURST_EN BIT(2)
-
-#define xbar_w32(x, y) ltq_w32((x), ltq_xbar_membase + (y))
-#define xbar_r32(x) ltq_r32(ltq_xbar_membase + (x))
-
static void __iomem *pmu_membase;
-static void __iomem *ltq_xbar_membase;
void __iomem *ltq_cgu_membase;
void __iomem *ltq_ebu_membase;
@@ -293,16 +285,6 @@ static void pci_ext_disable(struct clk *clk)
ltq_cgu_w32((1 << 31) | (1 << 30), pcicr);
}
-static void xbar_fpi_burst_disable(void)
-{
- u32 reg;
-
- /* bit 1 as 1 --burst; bit 1 as 0 -- single */
- reg = xbar_r32(XBAR_ALWAYS_LAST);
- reg &= ~XBAR_FPI_BURST_EN;
- xbar_w32(reg, XBAR_ALWAYS_LAST);
-}
-
/* enable a clockout source */
static int clkout_enable(struct clk *clk)
{
@@ -459,26 +441,6 @@ void __init ltq_soc_init(void)
if (!pmu_membase || !ltq_cgu_membase || !ltq_ebu_membase)
panic("Failed to remap core resources");
- if (of_machine_is_compatible("lantiq,vr9")) {
- struct resource res_xbar;
- struct device_node *np_xbar =
- of_find_compatible_node(NULL, NULL,
- "lantiq,xbar-xway");
-
- if (!np_xbar)
- panic("Failed to load xbar nodes from devicetree");
- if (of_address_to_resource(np_xbar, 0, &res_xbar))
- panic("Failed to get xbar resources");
- if (!request_mem_region(res_xbar.start, resource_size(&res_xbar),
- res_xbar.name))
- panic("Failed to get xbar resources");
-
- ltq_xbar_membase = ioremap_nocache(res_xbar.start,
- resource_size(&res_xbar));
- if (!ltq_xbar_membase)
- panic("Failed to remap xbar resources");
- }
-
/* make sure to unprotect the memory region where flash is located */
ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
@@ -605,7 +567,4 @@ void __init ltq_soc_init(void)
clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
}
-
- if (of_machine_is_compatible("lantiq,vr9"))
- xbar_fpi_burst_disable();
}
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 824b44281efa..009b5de74a24 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_ARCH_DOVE) += dove/
obj-$(CONFIG_MACH_DOVE) += dove/
obj-y += fsl/
obj-$(CONFIG_ARCH_MXC) += imx/
+obj-$(CONFIG_SOC_XWAY) += lantiq/
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_ARCH_QCOM) += qcom/
obj-$(CONFIG_ARCH_RENESAS) += renesas/
diff --git a/drivers/soc/lantiq/Makefile b/drivers/soc/lantiq/Makefile
new file mode 100644
index 000000000000..35aa86bd1023
--- /dev/null
+++ b/drivers/soc/lantiq/Makefile
@@ -0,0 +1 @@
+obj-y += fpi-bus.o
diff --git a/drivers/soc/lantiq/fpi-bus.c b/drivers/soc/lantiq/fpi-bus.c
new file mode 100644
index 000000000000..71b13c6c2553
--- /dev/null
+++ b/drivers/soc/lantiq/fpi-bus.c
@@ -0,0 +1,91 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2011-2015 John Crispin <blogic-Pj+rj9U5foFAfugRpC6u6w@public.gmane.org>
+ * Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
+ * Copyright (C) 2017 Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
+ */
+
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/regmap.h>
+
+#include <lantiq_soc.h>
+
+#define XBAR_ALWAYS_LAST 0x430
+#define XBAR_FPI_BURST_EN BIT(1)
+#define XBAR_AHB_BURST_EN BIT(2)
+
+#define RCU_VR9_BE_AHB1S 0x00000008
+
+static int ltq_fpi_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct resource *res_xbar;
+ struct regmap *rcu_regmap;
+ void __iomem *xbar_membase;
+ u32 rcu_ahb_endianness_reg_offset;
+ u32 rcu_ahb_endianness_val;
+ int ret;
+
+ res_xbar = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ xbar_membase = devm_ioremap_resource(dev, res_xbar);
+ if (IS_ERR(xbar_membase))
+ return PTR_ERR(xbar_membase);
+
+ /* RCU configuration is optional */
+ rcu_regmap = syscon_regmap_lookup_by_phandle(np, "regmap");
+ if (!IS_ERR_OR_NULL(rcu_regmap)) {
+ ret = device_property_read_u32(dev, "offset-endianness",
+ &rcu_ahb_endianness_reg_offset);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to get RCU reg offset\n");
+ return -EINVAL;
+ }
+
+ if (of_device_is_big_endian(np))
+ rcu_ahb_endianness_val = RCU_VR9_BE_AHB1S;
+ else
+ rcu_ahb_endianness_val = 0;
+
+ if (regmap_update_bits(rcu_regmap,
+ rcu_ahb_endianness_reg_offset,
+ RCU_VR9_BE_AHB1S,
+ rcu_ahb_endianness_val))
+ dev_warn(&pdev->dev,
+ "Failed to configure RCU AHB endianness\n");
+ }
+
+ /* disable fpi burst */
+ ltq_w32_mask(XBAR_FPI_BURST_EN, 0, xbar_membase + XBAR_ALWAYS_LAST);
+
+ return of_platform_populate(dev->of_node, NULL, NULL, dev);
+}
+
+static const struct of_device_id ltq_fpi_match[] = {
+ { .compatible = "lantiq,fpi-xrx200" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, ltq_fpi_match);
+
+static struct platform_driver ltq_fpi_driver = {
+ .probe = ltq_fpi_probe,
+ .driver = {
+ .name = "fpi-xway",
+ .of_match_table = ltq_fpi_match,
+ },
+};
+
+module_platform_driver(ltq_fpi_driver);
+
+MODULE_DESCRIPTION("Lantiq FPI bus driver");
+MODULE_LICENSE("GPL");
--
2.11.0
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^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v3 08/16] MIPS: lantiq: Convert the fpi bus driver to a platform_driver
@ 2017-05-28 18:39 ` Hauke Mehrtens
0 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:39 UTC (permalink / raw)
To: ralf
Cc: linux-mips, linux-mtd, linux-watchdog, devicetree,
martin.blumenstingl, john, linux-spi, hauke.mehrtens, robh,
andy.shevchenko, p.zabel, Hauke Mehrtens
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Instead of hacking the configuration of the FPI bus into the arch code
add an own bus driver for this internal bus. The FPI bus is the main
bus of the SoC. This bus driver makes sure the bus is configured
correctly before the child drivers are getting initialized. This driver
will probably also be used on different SoC later.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
.../devicetree/bindings/mips/lantiq/fpi-bus.txt | 33 ++++++++
MAINTAINERS | 1 +
arch/mips/lantiq/xway/reset.c | 4 -
arch/mips/lantiq/xway/sysctrl.c | 41 ----------
drivers/soc/Makefile | 1 +
drivers/soc/lantiq/Makefile | 1 +
drivers/soc/lantiq/fpi-bus.c | 91 ++++++++++++++++++++++
7 files changed, 127 insertions(+), 45 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mips/lantiq/fpi-bus.txt
create mode 100644 drivers/soc/lantiq/Makefile
create mode 100644 drivers/soc/lantiq/fpi-bus.c
diff --git a/Documentation/devicetree/bindings/mips/lantiq/fpi-bus.txt b/Documentation/devicetree/bindings/mips/lantiq/fpi-bus.txt
new file mode 100644
index 000000000000..52d4bb9d2ffa
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/lantiq/fpi-bus.txt
@@ -0,0 +1,33 @@
+Lantiq XWAY SoC FPI BUS binding
+============================
+
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible : Should be one of
+ "lantiq,fpi-xrx200"
+- reg : The address and length of the XBAR configuration register.
+ Address and length of the FPI bus itself
+
+Optional properties:
+- regmap : A phandle to the RCU syscon
+- offset-endianness : Offset of the endianness configuration register
+
+
+-------------------------------------------------------------------------------
+Example for the FPI on the xrx200 SoCs:
+ fpi@10000000 {
+ compatible = "lantiq,fpi-xrx200", "simple-bus";
+ ranges = <0x0 0x10000000 0xF000000>;
+ reg = <0x1F400000 0x1000>,
+ <0x10000000 0xF000000>;
+ regmap = <&rcu0>;
+ offset-endianness = <0x4c>;
+ big-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gptu@E100A00 {
+ ......
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 9e984645c4b0..f2c2acd6f73f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7441,6 +7441,7 @@ M: John Crispin <john@phrozen.org>
L: linux-mips@linux-mips.org
S: Maintained
F: arch/mips/lantiq
+F: drivers/soc/lantiq
LAPB module
L: linux-x25@vger.kernel.org
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index 83fd65d76e81..b6752c95a600 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -373,10 +373,6 @@ static int __init mips_reboot_setup(void)
of_machine_is_compatible("lantiq,vr9"))
ltq_usb_init();
- if (of_machine_is_compatible("lantiq,vr9"))
- ltq_rcu_w32(ltq_rcu_r32(RCU_AHB_ENDIAN) | RCU_VR9_BE_AHB1S,
- RCU_AHB_ENDIAN);
-
_machine_restart = ltq_machine_restart;
_machine_halt = ltq_machine_halt;
pm_power_off = ltq_machine_power_off;
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 95bec460b651..706639a343bc 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -145,15 +145,7 @@ static u32 pmu_clk_cr_b[] = {
#define pmu_w32(x, y) ltq_w32((x), pmu_membase + (y))
#define pmu_r32(x) ltq_r32(pmu_membase + (x))
-#define XBAR_ALWAYS_LAST 0x430
-#define XBAR_FPI_BURST_EN BIT(1)
-#define XBAR_AHB_BURST_EN BIT(2)
-
-#define xbar_w32(x, y) ltq_w32((x), ltq_xbar_membase + (y))
-#define xbar_r32(x) ltq_r32(ltq_xbar_membase + (x))
-
static void __iomem *pmu_membase;
-static void __iomem *ltq_xbar_membase;
void __iomem *ltq_cgu_membase;
void __iomem *ltq_ebu_membase;
@@ -293,16 +285,6 @@ static void pci_ext_disable(struct clk *clk)
ltq_cgu_w32((1 << 31) | (1 << 30), pcicr);
}
-static void xbar_fpi_burst_disable(void)
-{
- u32 reg;
-
- /* bit 1 as 1 --burst; bit 1 as 0 -- single */
- reg = xbar_r32(XBAR_ALWAYS_LAST);
- reg &= ~XBAR_FPI_BURST_EN;
- xbar_w32(reg, XBAR_ALWAYS_LAST);
-}
-
/* enable a clockout source */
static int clkout_enable(struct clk *clk)
{
@@ -459,26 +441,6 @@ void __init ltq_soc_init(void)
if (!pmu_membase || !ltq_cgu_membase || !ltq_ebu_membase)
panic("Failed to remap core resources");
- if (of_machine_is_compatible("lantiq,vr9")) {
- struct resource res_xbar;
- struct device_node *np_xbar =
- of_find_compatible_node(NULL, NULL,
- "lantiq,xbar-xway");
-
- if (!np_xbar)
- panic("Failed to load xbar nodes from devicetree");
- if (of_address_to_resource(np_xbar, 0, &res_xbar))
- panic("Failed to get xbar resources");
- if (!request_mem_region(res_xbar.start, resource_size(&res_xbar),
- res_xbar.name))
- panic("Failed to get xbar resources");
-
- ltq_xbar_membase = ioremap_nocache(res_xbar.start,
- resource_size(&res_xbar));
- if (!ltq_xbar_membase)
- panic("Failed to remap xbar resources");
- }
-
/* make sure to unprotect the memory region where flash is located */
ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
@@ -605,7 +567,4 @@ void __init ltq_soc_init(void)
clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
}
-
- if (of_machine_is_compatible("lantiq,vr9"))
- xbar_fpi_burst_disable();
}
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 824b44281efa..009b5de74a24 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_ARCH_DOVE) += dove/
obj-$(CONFIG_MACH_DOVE) += dove/
obj-y += fsl/
obj-$(CONFIG_ARCH_MXC) += imx/
+obj-$(CONFIG_SOC_XWAY) += lantiq/
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_ARCH_QCOM) += qcom/
obj-$(CONFIG_ARCH_RENESAS) += renesas/
diff --git a/drivers/soc/lantiq/Makefile b/drivers/soc/lantiq/Makefile
new file mode 100644
index 000000000000..35aa86bd1023
--- /dev/null
+++ b/drivers/soc/lantiq/Makefile
@@ -0,0 +1 @@
+obj-y += fpi-bus.o
diff --git a/drivers/soc/lantiq/fpi-bus.c b/drivers/soc/lantiq/fpi-bus.c
new file mode 100644
index 000000000000..71b13c6c2553
--- /dev/null
+++ b/drivers/soc/lantiq/fpi-bus.c
@@ -0,0 +1,91 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2011-2015 John Crispin <blogic@phrozen.org>
+ * Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
+ */
+
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/regmap.h>
+
+#include <lantiq_soc.h>
+
+#define XBAR_ALWAYS_LAST 0x430
+#define XBAR_FPI_BURST_EN BIT(1)
+#define XBAR_AHB_BURST_EN BIT(2)
+
+#define RCU_VR9_BE_AHB1S 0x00000008
+
+static int ltq_fpi_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct resource *res_xbar;
+ struct regmap *rcu_regmap;
+ void __iomem *xbar_membase;
+ u32 rcu_ahb_endianness_reg_offset;
+ u32 rcu_ahb_endianness_val;
+ int ret;
+
+ res_xbar = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ xbar_membase = devm_ioremap_resource(dev, res_xbar);
+ if (IS_ERR(xbar_membase))
+ return PTR_ERR(xbar_membase);
+
+ /* RCU configuration is optional */
+ rcu_regmap = syscon_regmap_lookup_by_phandle(np, "regmap");
+ if (!IS_ERR_OR_NULL(rcu_regmap)) {
+ ret = device_property_read_u32(dev, "offset-endianness",
+ &rcu_ahb_endianness_reg_offset);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to get RCU reg offset\n");
+ return -EINVAL;
+ }
+
+ if (of_device_is_big_endian(np))
+ rcu_ahb_endianness_val = RCU_VR9_BE_AHB1S;
+ else
+ rcu_ahb_endianness_val = 0;
+
+ if (regmap_update_bits(rcu_regmap,
+ rcu_ahb_endianness_reg_offset,
+ RCU_VR9_BE_AHB1S,
+ rcu_ahb_endianness_val))
+ dev_warn(&pdev->dev,
+ "Failed to configure RCU AHB endianness\n");
+ }
+
+ /* disable fpi burst */
+ ltq_w32_mask(XBAR_FPI_BURST_EN, 0, xbar_membase + XBAR_ALWAYS_LAST);
+
+ return of_platform_populate(dev->of_node, NULL, NULL, dev);
+}
+
+static const struct of_device_id ltq_fpi_match[] = {
+ { .compatible = "lantiq,fpi-xrx200" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, ltq_fpi_match);
+
+static struct platform_driver ltq_fpi_driver = {
+ .probe = ltq_fpi_probe,
+ .driver = {
+ .name = "fpi-xway",
+ .of_match_table = ltq_fpi_match,
+ },
+};
+
+module_platform_driver(ltq_fpi_driver);
+
+MODULE_DESCRIPTION("Lantiq FPI bus driver");
+MODULE_LICENSE("GPL");
--
2.11.0
^ permalink raw reply related [flat|nested] 60+ messages in thread[parent not found: <20170528184006.31668-9-hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>]
* Re: [PATCH v3 08/16] MIPS: lantiq: Convert the fpi bus driver to a platform_driver
2017-05-28 18:39 ` Hauke Mehrtens
@ 2017-05-30 18:23 ` Andy Shevchenko
-1 siblings, 0 replies; 60+ messages in thread
From: Andy Shevchenko @ 2017-05-30 18:23 UTC (permalink / raw)
To: Hauke Mehrtens
Cc: Ralf Baechle, Linux MIPS Mailing List,
open list:MEMORY TECHNOLOGY...,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA, devicetree,
martin.blumenstingl, john, linux-spi, hauke.mehrtens,
Rob Herring, Philipp Zabel
On Sun, May 28, 2017 at 9:39 PM, Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org> wrote:
> From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
>
> Instead of hacking the configuration of the FPI bus into the arch code
> add an own bus driver for this internal bus. The FPI bus is the main
> bus of the SoC. This bus driver makes sure the bus is configured
> correctly before the child drivers are getting initialized. This driver
> will probably also be used on different SoC later.
> +Optional properties:
> +- regmap : A phandle to the RCU syscon
> +- offset-endianness : Offset of the endianness configuration register
Shouldn't be one of
big-endian;
little-endian;
native-endian;
?
For what purpose that register is used?
Is it configurable in RTL? IOW why you need to have it in DT?
> + offset-endianness = <0x4c>;
> + big-endian;
> + /* RCU configuration is optional */
> + rcu_regmap = syscon_regmap_lookup_by_phandle(np, "regmap");
> + if (!IS_ERR_OR_NULL(rcu_regmap)) {
_OR_NULL is suspicious. You are doing something wrong.
--
With Best Regards,
Andy Shevchenko
--
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^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH v3 08/16] MIPS: lantiq: Convert the fpi bus driver to a platform_driver
@ 2017-05-30 18:23 ` Andy Shevchenko
0 siblings, 0 replies; 60+ messages in thread
From: Andy Shevchenko @ 2017-05-30 18:23 UTC (permalink / raw)
To: Hauke Mehrtens
Cc: Ralf Baechle, Linux MIPS Mailing List,
open list:MEMORY TECHNOLOGY...,
linux-watchdog, devicetree, martin.blumenstingl, john, linux-spi,
hauke.mehrtens, Rob Herring, Philipp Zabel
On Sun, May 28, 2017 at 9:39 PM, Hauke Mehrtens <hauke@hauke-m.de> wrote:
> From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>
> Instead of hacking the configuration of the FPI bus into the arch code
> add an own bus driver for this internal bus. The FPI bus is the main
> bus of the SoC. This bus driver makes sure the bus is configured
> correctly before the child drivers are getting initialized. This driver
> will probably also be used on different SoC later.
> +Optional properties:
> +- regmap : A phandle to the RCU syscon
> +- offset-endianness : Offset of the endianness configuration register
Shouldn't be one of
big-endian;
little-endian;
native-endian;
?
For what purpose that register is used?
Is it configurable in RTL? IOW why you need to have it in DT?
> + offset-endianness = <0x4c>;
> + big-endian;
> + /* RCU configuration is optional */
> + rcu_regmap = syscon_regmap_lookup_by_phandle(np, "regmap");
> + if (!IS_ERR_OR_NULL(rcu_regmap)) {
_OR_NULL is suspicious. You are doing something wrong.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 60+ messages in thread[parent not found: <CAHp75VcU3cF07GQG5vPV9uhmpOzO2aGD8Fj9-Do4yN3BXNN1Rg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH v3 08/16] MIPS: lantiq: Convert the fpi bus driver to a platform_driver
2017-05-30 18:23 ` Andy Shevchenko
(?)
@ 2017-05-30 22:02 ` Hauke Mehrtens
-1 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-30 22:02 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Ralf Baechle, Linux MIPS Mailing List,
open list:MEMORY TECHNOLOGY...,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA, devicetree,
martin.blumenstingl, john, linux-spi, hauke.mehrtens,
Rob Herring, Philipp Zabel
On 05/30/2017 08:23 PM, Andy Shevchenko wrote:
> On Sun, May 28, 2017 at 9:39 PM, Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org> wrote:
>> From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
>>
>> Instead of hacking the configuration of the FPI bus into the arch code
>> add an own bus driver for this internal bus. The FPI bus is the main
>> bus of the SoC. This bus driver makes sure the bus is configured
>> correctly before the child drivers are getting initialized. This driver
>> will probably also be used on different SoC later.
>
>> +Optional properties:
>> +- regmap : A phandle to the RCU syscon
>
>> +- offset-endianness : Offset of the endianness configuration register
>
> Shouldn't be one of
>
> big-endian;
> little-endian;
> native-endian;
>
> ?
The offset-endianness is the offset of the endianes register in the RCU
register range which is accessed through the syscon. For the SoCs where
I checked it is the same value. I should add a documentation of big-endian.
> For what purpose that register is used?
> Is it configurable in RTL? IOW why you need to have it in DT?
>
>> + offset-endianness = <0x4c>;
>> + big-endian;
>
>> + /* RCU configuration is optional */
>> + rcu_regmap = syscon_regmap_lookup_by_phandle(np, "regmap");
>
>> + if (!IS_ERR_OR_NULL(rcu_regmap)) {
>
> _OR_NULL is suspicious. You are doing something wrong.
>
This is only needed for some SoCs, some chips do not have this register.
Should I do this based on the compatibility string?
Hauke
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^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH v3 08/16] MIPS: lantiq: Convert the fpi bus driver to a platform_driver
@ 2017-05-30 22:02 ` Hauke Mehrtens
0 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-30 22:02 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Ralf Baechle, Linux MIPS Mailing List,
open list:MEMORY TECHNOLOGY...,
linux-watchdog, devicetree, martin.blumenstingl, john, linux-spi,
hauke.mehrtens, Rob Herring, Philipp Zabel
On 05/30/2017 08:23 PM, Andy Shevchenko wrote:
> On Sun, May 28, 2017 at 9:39 PM, Hauke Mehrtens <hauke@hauke-m.de> wrote:
>> From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>>
>> Instead of hacking the configuration of the FPI bus into the arch code
>> add an own bus driver for this internal bus. The FPI bus is the main
>> bus of the SoC. This bus driver makes sure the bus is configured
>> correctly before the child drivers are getting initialized. This driver
>> will probably also be used on different SoC later.
>
>> +Optional properties:
>> +- regmap : A phandle to the RCU syscon
>
>> +- offset-endianness : Offset of the endianness configuration register
>
> Shouldn't be one of
>
> big-endian;
> little-endian;
> native-endian;
>
> ?
The offset-endianness is the offset of the endianes register in the RCU
register range which is accessed through the syscon. For the SoCs where
I checked it is the same value. I should add a documentation of big-endian.
> For what purpose that register is used?
> Is it configurable in RTL? IOW why you need to have it in DT?
>
>> + offset-endianness = <0x4c>;
>> + big-endian;
>
>> + /* RCU configuration is optional */
>> + rcu_regmap = syscon_regmap_lookup_by_phandle(np, "regmap");
>
>> + if (!IS_ERR_OR_NULL(rcu_regmap)) {
>
> _OR_NULL is suspicious. You are doing something wrong.
>
This is only needed for some SoCs, some chips do not have this register.
Should I do this based on the compatibility string?
Hauke
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH v3 08/16] MIPS: lantiq: Convert the fpi bus driver to a platform_driver
@ 2017-05-30 22:02 ` Hauke Mehrtens
0 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-30 22:02 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Ralf Baechle, Linux MIPS Mailing List,
open list:MEMORY TECHNOLOGY...,
linux-watchdog, devicetree, martin.blumenstingl, john, linux-spi,
hauke.mehrtens, Rob Herring, Philipp Zabel
On 05/30/2017 08:23 PM, Andy Shevchenko wrote:
> On Sun, May 28, 2017 at 9:39 PM, Hauke Mehrtens <hauke@hauke-m.de> wrote:
>> From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>>
>> Instead of hacking the configuration of the FPI bus into the arch code
>> add an own bus driver for this internal bus. The FPI bus is the main
>> bus of the SoC. This bus driver makes sure the bus is configured
>> correctly before the child drivers are getting initialized. This driver
>> will probably also be used on different SoC later.
>
>> +Optional properties:
>> +- regmap : A phandle to the RCU syscon
>
>> +- offset-endianness : Offset of the endianness configuration register
>
> Shouldn't be one of
>
> big-endian;
> little-endian;
> native-endian;
>
> ?
The offset-endianness is the offset of the endianes register in the RCU
register range which is accessed through the syscon. For the SoCs where
I checked it is the same value. I should add a documentation of big-endian.
> For what purpose that register is used?
> Is it configurable in RTL? IOW why you need to have it in DT?
>
>> + offset-endianness = <0x4c>;
>> + big-endian;
>
>> + /* RCU configuration is optional */
>> + rcu_regmap = syscon_regmap_lookup_by_phandle(np, "regmap");
>
>> + if (!IS_ERR_OR_NULL(rcu_regmap)) {
>
> _OR_NULL is suspicious. You are doing something wrong.
>
This is only needed for some SoCs, some chips do not have this register.
Should I do this based on the compatibility string?
Hauke
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^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [PATCH v3 08/16] MIPS: lantiq: Convert the fpi bus driver to a platform_driver
2017-05-28 18:39 ` Hauke Mehrtens
@ 2017-05-31 20:54 ` Rob Herring
-1 siblings, 0 replies; 60+ messages in thread
From: Rob Herring @ 2017-05-31 20:54 UTC (permalink / raw)
To: Hauke Mehrtens
Cc: ralf-6z/3iImG2C8G8FEW9MqTrA, linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w,
andy.shevchenko-Re5JQEeQqe8AvxtiuMwx3w,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ
On Sun, May 28, 2017 at 08:39:58PM +0200, Hauke Mehrtens wrote:
> From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
>
> Instead of hacking the configuration of the FPI bus into the arch code
> add an own bus driver for this internal bus. The FPI bus is the main
> bus of the SoC. This bus driver makes sure the bus is configured
> correctly before the child drivers are getting initialized. This driver
> will probably also be used on different SoC later.
>
> Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> ---
> .../devicetree/bindings/mips/lantiq/fpi-bus.txt | 33 ++++++++
> MAINTAINERS | 1 +
> arch/mips/lantiq/xway/reset.c | 4 -
> arch/mips/lantiq/xway/sysctrl.c | 41 ----------
> drivers/soc/Makefile | 1 +
> drivers/soc/lantiq/Makefile | 1 +
> drivers/soc/lantiq/fpi-bus.c | 91 ++++++++++++++++++++++
> 7 files changed, 127 insertions(+), 45 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/mips/lantiq/fpi-bus.txt
> create mode 100644 drivers/soc/lantiq/Makefile
> create mode 100644 drivers/soc/lantiq/fpi-bus.c
>
> diff --git a/Documentation/devicetree/bindings/mips/lantiq/fpi-bus.txt b/Documentation/devicetree/bindings/mips/lantiq/fpi-bus.txt
> new file mode 100644
> index 000000000000..52d4bb9d2ffa
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mips/lantiq/fpi-bus.txt
> @@ -0,0 +1,33 @@
> +Lantiq XWAY SoC FPI BUS binding
> +============================
> +
> +
> +-------------------------------------------------------------------------------
> +Required properties:
> +- compatible : Should be one of
> + "lantiq,fpi-xrx200"
> +- reg : The address and length of the XBAR configuration register.
> + Address and length of the FPI bus itself
> +
> +Optional properties:
> +- regmap : A phandle to the RCU syscon
> +- offset-endianness : Offset of the endianness configuration register
> +
> +
> +-------------------------------------------------------------------------------
> +Example for the FPI on the xrx200 SoCs:
> + fpi@10000000 {
> + compatible = "lantiq,fpi-xrx200", "simple-bus";
> + ranges = <0x0 0x10000000 0xF000000>;
lowercase hex please.
> + reg = <0x1F400000 0x1000>,
> + <0x10000000 0xF000000>;
> + regmap = <&rcu0>;
> + offset-endianness = <0x4c>;
Presumably, this is for endianness of the children. So this needs to be
configured before probing the children. If so, then you should not call
this a "simple-bus".
> + big-endian;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + gptu@E100A00 {
lowercase hex.
> + ......
> + };
> + };
--
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^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH v3 08/16] MIPS: lantiq: Convert the fpi bus driver to a platform_driver
@ 2017-05-31 20:54 ` Rob Herring
0 siblings, 0 replies; 60+ messages in thread
From: Rob Herring @ 2017-05-31 20:54 UTC (permalink / raw)
To: Hauke Mehrtens
Cc: ralf, linux-mips, linux-mtd, linux-watchdog, devicetree,
martin.blumenstingl, john, linux-spi, hauke.mehrtens,
andy.shevchenko, p.zabel
On Sun, May 28, 2017 at 08:39:58PM +0200, Hauke Mehrtens wrote:
> From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>
> Instead of hacking the configuration of the FPI bus into the arch code
> add an own bus driver for this internal bus. The FPI bus is the main
> bus of the SoC. This bus driver makes sure the bus is configured
> correctly before the child drivers are getting initialized. This driver
> will probably also be used on different SoC later.
>
> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
> .../devicetree/bindings/mips/lantiq/fpi-bus.txt | 33 ++++++++
> MAINTAINERS | 1 +
> arch/mips/lantiq/xway/reset.c | 4 -
> arch/mips/lantiq/xway/sysctrl.c | 41 ----------
> drivers/soc/Makefile | 1 +
> drivers/soc/lantiq/Makefile | 1 +
> drivers/soc/lantiq/fpi-bus.c | 91 ++++++++++++++++++++++
> 7 files changed, 127 insertions(+), 45 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/mips/lantiq/fpi-bus.txt
> create mode 100644 drivers/soc/lantiq/Makefile
> create mode 100644 drivers/soc/lantiq/fpi-bus.c
>
> diff --git a/Documentation/devicetree/bindings/mips/lantiq/fpi-bus.txt b/Documentation/devicetree/bindings/mips/lantiq/fpi-bus.txt
> new file mode 100644
> index 000000000000..52d4bb9d2ffa
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mips/lantiq/fpi-bus.txt
> @@ -0,0 +1,33 @@
> +Lantiq XWAY SoC FPI BUS binding
> +============================
> +
> +
> +-------------------------------------------------------------------------------
> +Required properties:
> +- compatible : Should be one of
> + "lantiq,fpi-xrx200"
> +- reg : The address and length of the XBAR configuration register.
> + Address and length of the FPI bus itself
> +
> +Optional properties:
> +- regmap : A phandle to the RCU syscon
> +- offset-endianness : Offset of the endianness configuration register
> +
> +
> +-------------------------------------------------------------------------------
> +Example for the FPI on the xrx200 SoCs:
> + fpi@10000000 {
> + compatible = "lantiq,fpi-xrx200", "simple-bus";
> + ranges = <0x0 0x10000000 0xF000000>;
lowercase hex please.
> + reg = <0x1F400000 0x1000>,
> + <0x10000000 0xF000000>;
> + regmap = <&rcu0>;
> + offset-endianness = <0x4c>;
Presumably, this is for endianness of the children. So this needs to be
configured before probing the children. If so, then you should not call
this a "simple-bus".
> + big-endian;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + gptu@E100A00 {
lowercase hex.
> + ......
> + };
> + };
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v3 09/16] MIPS: lantiq: remove ltq_reset_cause() and ltq_boot_select()
2017-05-28 18:39 ` Hauke Mehrtens
@ 2017-05-28 18:39 ` Hauke Mehrtens
-1 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:39 UTC (permalink / raw)
To: ralf-6z/3iImG2C8G8FEW9MqTrA
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w,
robh-DgEjT+Ai2ygdnm+yROfE0A,
andy.shevchenko-Re5JQEeQqe8AvxtiuMwx3w,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ, Hauke Mehrtens
Do not export the ltq_reset_cause() and ltq_boot_select() function any
more. ltq_reset_cause() was accessed by the watchdog driver before to
see why the last reset happened, this is now done through direct access
of the register over regmap. The bits in this register are anyway
different between the xrx200 and the falcon SoC.
ltq_boot_select() is not used any more and was used by the flash
drivers to check if the system was booted from this flash type, now the
drivers should depend on the device tree only.
Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
Acked-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
arch/mips/include/asm/mach-lantiq/lantiq.h | 4 ----
arch/mips/lantiq/falcon/reset.c | 22 ----------------------
arch/mips/lantiq/xway/reset.c | 19 -------------------
3 files changed, 45 deletions(-)
diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
index 8064d7a4b33d..fa045b4c0cdd 100644
--- a/arch/mips/include/asm/mach-lantiq/lantiq.h
+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
@@ -44,10 +44,6 @@ extern struct clk *clk_get_fpi(void);
extern struct clk *clk_get_io(void);
extern struct clk *clk_get_ppe(void);
-/* find out what bootsource we have */
-extern unsigned char ltq_boot_select(void);
-/* find out what caused the last cpu reset */
-extern int ltq_reset_cause(void);
/* find out the soc type */
extern int ltq_soc_type(void);
diff --git a/arch/mips/lantiq/falcon/reset.c b/arch/mips/lantiq/falcon/reset.c
index 7a535d72f541..722114d7409d 100644
--- a/arch/mips/lantiq/falcon/reset.c
+++ b/arch/mips/lantiq/falcon/reset.c
@@ -15,28 +15,6 @@
#include <lantiq_soc.h>
-/* CPU0 Reset Source Register */
-#define SYS1_CPU0RS 0x0040
-/* reset cause mask */
-#define CPU0RS_MASK 0x0003
-/* CPU0 Boot Mode Register */
-#define SYS1_BM 0x00a0
-/* boot mode mask */
-#define BM_MASK 0x0005
-
-/* allow platform code to find out what surce we booted from */
-unsigned char ltq_boot_select(void)
-{
- return ltq_sys1_r32(SYS1_BM) & BM_MASK;
-}
-
-/* allow the watchdog driver to find out what the boot reason was */
-int ltq_reset_cause(void)
-{
- return ltq_sys1_r32(SYS1_CPU0RS) & CPU0RS_MASK;
-}
-EXPORT_SYMBOL_GPL(ltq_reset_cause);
-
#define BOOT_REG_BASE (KSEG1 | 0x1F200000)
#define BOOT_PW1_REG (BOOT_REG_BASE | 0x20)
#define BOOT_PW2_REG (BOOT_REG_BASE | 0x24)
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index b6752c95a600..2dedcf939901 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -119,25 +119,6 @@ static void ltq_rcu_w32_mask(uint32_t clr, uint32_t set, uint32_t reg_off)
spin_unlock_irqrestore(<q_rcu_lock, flags);
}
-/* This function is used by the watchdog driver */
-int ltq_reset_cause(void)
-{
- u32 val = ltq_rcu_r32(RCU_RST_STAT);
- return val >> RCU_STAT_SHIFT;
-}
-EXPORT_SYMBOL_GPL(ltq_reset_cause);
-
-/* allow platform code to find out what source we booted from */
-unsigned char ltq_boot_select(void)
-{
- u32 val = ltq_rcu_r32(RCU_RST_STAT);
-
- if (of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200"))
- return RCU_BOOT_SEL_XRX200(val);
-
- return RCU_BOOT_SEL(val);
-}
-
struct ltq_gphy_reset {
u32 rd;
u32 addr;
--
2.11.0
--
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^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v3 09/16] MIPS: lantiq: remove ltq_reset_cause() and ltq_boot_select()
@ 2017-05-28 18:39 ` Hauke Mehrtens
0 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:39 UTC (permalink / raw)
To: ralf
Cc: linux-mips, linux-mtd, linux-watchdog, devicetree,
martin.blumenstingl, john, linux-spi, hauke.mehrtens, robh,
andy.shevchenko, p.zabel, Hauke Mehrtens
Do not export the ltq_reset_cause() and ltq_boot_select() function any
more. ltq_reset_cause() was accessed by the watchdog driver before to
see why the last reset happened, this is now done through direct access
of the register over regmap. The bits in this register are anyway
different between the xrx200 and the falcon SoC.
ltq_boot_select() is not used any more and was used by the flash
drivers to check if the system was booted from this flash type, now the
drivers should depend on the device tree only.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
arch/mips/include/asm/mach-lantiq/lantiq.h | 4 ----
arch/mips/lantiq/falcon/reset.c | 22 ----------------------
arch/mips/lantiq/xway/reset.c | 19 -------------------
3 files changed, 45 deletions(-)
diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
index 8064d7a4b33d..fa045b4c0cdd 100644
--- a/arch/mips/include/asm/mach-lantiq/lantiq.h
+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
@@ -44,10 +44,6 @@ extern struct clk *clk_get_fpi(void);
extern struct clk *clk_get_io(void);
extern struct clk *clk_get_ppe(void);
-/* find out what bootsource we have */
-extern unsigned char ltq_boot_select(void);
-/* find out what caused the last cpu reset */
-extern int ltq_reset_cause(void);
/* find out the soc type */
extern int ltq_soc_type(void);
diff --git a/arch/mips/lantiq/falcon/reset.c b/arch/mips/lantiq/falcon/reset.c
index 7a535d72f541..722114d7409d 100644
--- a/arch/mips/lantiq/falcon/reset.c
+++ b/arch/mips/lantiq/falcon/reset.c
@@ -15,28 +15,6 @@
#include <lantiq_soc.h>
-/* CPU0 Reset Source Register */
-#define SYS1_CPU0RS 0x0040
-/* reset cause mask */
-#define CPU0RS_MASK 0x0003
-/* CPU0 Boot Mode Register */
-#define SYS1_BM 0x00a0
-/* boot mode mask */
-#define BM_MASK 0x0005
-
-/* allow platform code to find out what surce we booted from */
-unsigned char ltq_boot_select(void)
-{
- return ltq_sys1_r32(SYS1_BM) & BM_MASK;
-}
-
-/* allow the watchdog driver to find out what the boot reason was */
-int ltq_reset_cause(void)
-{
- return ltq_sys1_r32(SYS1_CPU0RS) & CPU0RS_MASK;
-}
-EXPORT_SYMBOL_GPL(ltq_reset_cause);
-
#define BOOT_REG_BASE (KSEG1 | 0x1F200000)
#define BOOT_PW1_REG (BOOT_REG_BASE | 0x20)
#define BOOT_PW2_REG (BOOT_REG_BASE | 0x24)
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index b6752c95a600..2dedcf939901 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -119,25 +119,6 @@ static void ltq_rcu_w32_mask(uint32_t clr, uint32_t set, uint32_t reg_off)
spin_unlock_irqrestore(<q_rcu_lock, flags);
}
-/* This function is used by the watchdog driver */
-int ltq_reset_cause(void)
-{
- u32 val = ltq_rcu_r32(RCU_RST_STAT);
- return val >> RCU_STAT_SHIFT;
-}
-EXPORT_SYMBOL_GPL(ltq_reset_cause);
-
-/* allow platform code to find out what source we booted from */
-unsigned char ltq_boot_select(void)
-{
- u32 val = ltq_rcu_r32(RCU_RST_STAT);
-
- if (of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200"))
- return RCU_BOOT_SEL_XRX200(val);
-
- return RCU_BOOT_SEL(val);
-}
-
struct ltq_gphy_reset {
u32 rd;
u32 addr;
--
2.11.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v3 10/16] reset: Add a reset controller driver for the Lantiq XWAY based SoCs
2017-05-28 18:39 ` Hauke Mehrtens
@ 2017-05-28 18:40 ` Hauke Mehrtens
-1 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:40 UTC (permalink / raw)
To: ralf-6z/3iImG2C8G8FEW9MqTrA
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w,
robh-DgEjT+Ai2ygdnm+yROfE0A,
andy.shevchenko-Re5JQEeQqe8AvxtiuMwx3w,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ, Hauke Mehrtens
From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
The reset controllers (on xRX200 and newer SoCs have two of them) are
provided by the RCU module. This was initially implemented as a simple
reset controller. However, the RCU module provides more functionality
(ethernet GPHYs, USB PHY, etc.), which makes it a MFD device.
The old reset controller driver implementation from
arch/mips/lantiq/xway/reset.c did not honor this fact.
For some devices the request and the status bits are different.
Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
Cc: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
.../devicetree/bindings/reset/lantiq,reset.txt | 30 +++
drivers/reset/Kconfig | 6 +
drivers/reset/Makefile | 1 +
drivers/reset/reset-lantiq.c | 205 +++++++++++++++++++++
4 files changed, 242 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/lantiq,reset.txt
create mode 100644 drivers/reset/reset-lantiq.c
diff --git a/Documentation/devicetree/bindings/reset/lantiq,reset.txt b/Documentation/devicetree/bindings/reset/lantiq,reset.txt
new file mode 100644
index 000000000000..00cc3d4c68c4
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/lantiq,reset.txt
@@ -0,0 +1,30 @@
+Lantiq XWAY SoC RCU reset controller binding
+============================================
+
+This binding describes a reset-controller found on the RCU module on Lantiq
+XWAY SoCs.
+
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible : Should be one of
+ "lantiq,reset-danube"
+ "lantiq,reset-xrx200"
+- regmap : A phandle to the RCU syscon
+- offset-set : Offset of the reset set register
+- offset-status : Offset of the reset status register
+- #reset-cells : Specifies the number of cells needed to encode the
+ reset line, should be 2.
+ The first cell takes the reset set bit and the
+ second cell takes the status bit.
+
+-------------------------------------------------------------------------------
+Example for the reset-controllers on the xRX200 SoCs:
+ reset0: reset-controller@0 {
+ compatible = "lantiq,reset-xrx200";
+
+ regmap = <&rcu0>;
+ offset-set = <0x10>;
+ offset-status = <0x14>;
+ #reset-cells = <2>;
+ };
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index d21c07ccc94e..1742c2293bc3 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -41,6 +41,12 @@ config RESET_IMX7
help
This enables the reset controller driver for i.MX7 SoCs.
+config RESET_LANTIQ
+ bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
+ default SOC_TYPE_XWAY
+ help
+ This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
+
config RESET_LPC18XX
bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
default ARCH_LPC18XX
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 02a74db94339..112dba1db6b9 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
+obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
diff --git a/drivers/reset/reset-lantiq.c b/drivers/reset/reset-lantiq.c
new file mode 100644
index 000000000000..798bf648f36d
--- /dev/null
+++ b/drivers/reset/reset-lantiq.c
@@ -0,0 +1,205 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2010 John Crispin <blogic-Pj+rj9U5foFAfugRpC6u6w@public.gmane.org>
+ * Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
+ * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
+ * Copyright (C) 2017 Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
+ */
+
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+
+#define LANTIQ_RCU_RESET_TIMEOUT 10000
+
+struct lantiq_rcu_reset_priv {
+ struct reset_controller_dev rcdev;
+ struct device *dev;
+ struct regmap *regmap;
+ u32 reset_offset;
+ u32 status_offset;
+};
+
+static struct lantiq_rcu_reset_priv *to_lantiq_rcu_reset_priv(
+ struct reset_controller_dev *rcdev)
+{
+ return container_of(rcdev, struct lantiq_rcu_reset_priv, rcdev);
+}
+
+static int lantiq_rcu_reset_status(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct lantiq_rcu_reset_priv *priv = to_lantiq_rcu_reset_priv(rcdev);
+ unsigned int status = (id >> 8) & 0x1f;
+ u32 val;
+ int ret;
+
+ ret = regmap_read(priv->regmap, priv->status_offset, &val);
+ if (ret)
+ return ret;
+
+ return !!(val & BIT(status));
+}
+
+static int lantiq_rcu_reset_update(struct reset_controller_dev *rcdev,
+ unsigned long id, bool assert)
+{
+ struct lantiq_rcu_reset_priv *priv = to_lantiq_rcu_reset_priv(rcdev);
+ int ret, retry = LANTIQ_RCU_RESET_TIMEOUT;
+ unsigned int set = id & 0x1f;
+ u32 val;
+
+ if (assert)
+ val = BIT(set);
+ else
+ val = 0;
+
+ ret = regmap_update_bits(priv->regmap, priv->reset_offset, BIT(set),
+ val);
+ if (ret) {
+ dev_err(priv->dev, "Failed to set reset bit %u\n", set);
+ return ret;
+ }
+
+ do {
+ ret = lantiq_rcu_reset_status(rcdev, id);
+ if (ret < 0)
+ return ret;
+ if (ret == assert)
+ break;
+ usleep_range(20, 40);
+ } while (--retry);
+ if (!retry) {
+ dev_err(priv->dev, "Failed to %s bit %u\n",
+ assert ? "assert" : "deassert", set);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int lantiq_rcu_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ return lantiq_rcu_reset_update(rcdev, id, true);
+}
+
+static int lantiq_rcu_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ return lantiq_rcu_reset_update(rcdev, id, false);
+}
+
+static int lantiq_rcu_reset_reset(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ int ret;
+
+ ret = lantiq_rcu_reset_assert(rcdev, id);
+ if (ret)
+ return ret;
+
+ return lantiq_rcu_reset_deassert(rcdev, id);
+}
+
+static const struct reset_control_ops lantiq_rcu_reset_ops = {
+ .assert = lantiq_rcu_reset_assert,
+ .deassert = lantiq_rcu_reset_deassert,
+ .status = lantiq_rcu_reset_status,
+ .reset = lantiq_rcu_reset_reset,
+};
+
+static int lantiq_rcu_reset_of_probe(struct platform_device *pdev,
+ struct lantiq_rcu_reset_priv *priv)
+{
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ priv->regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "regmap");
+ if (IS_ERR(priv->regmap)) {
+ dev_err(&pdev->dev, "Failed to lookup RCU regmap\n");
+ return PTR_ERR(priv->regmap);
+ }
+
+ ret = device_property_read_u32(dev, "offset-set", &priv->reset_offset);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to get RCU reset offset\n");
+ return -EINVAL;
+ }
+
+ ret = device_property_read_u32(dev, "offset-status",
+ &priv->status_offset);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to get RCU status offset\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int lantiq_rcu_reset_xlate(struct reset_controller_dev *rcdev,
+ const struct of_phandle_args *reset_spec)
+{
+ unsigned int status, set;
+
+ set = reset_spec->args[0];
+ status = reset_spec->args[1];
+
+ if (set >= rcdev->nr_resets || status >= rcdev->nr_resets)
+ return -EINVAL;
+
+ return (status << 8) | set;
+}
+
+static int lantiq_rcu_reset_probe(struct platform_device *pdev)
+{
+ struct lantiq_rcu_reset_priv *priv;
+ int err;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = &pdev->dev;
+ platform_set_drvdata(pdev, priv);
+
+ err = lantiq_rcu_reset_of_probe(pdev, priv);
+ if (err)
+ return err;
+
+ priv->rcdev.ops = &lantiq_rcu_reset_ops;
+ priv->rcdev.owner = THIS_MODULE;
+ priv->rcdev.of_node = pdev->dev.of_node;
+ priv->rcdev.nr_resets = 32;
+ priv->rcdev.of_xlate = lantiq_rcu_reset_xlate;
+ priv->rcdev.of_reset_n_cells = 2;
+
+ return reset_controller_register(&priv->rcdev);
+}
+
+static const struct of_device_id lantiq_rcu_reset_dt_ids[] = {
+ { .compatible = "lantiq,reset-danube", },
+ { .compatible = "lantiq,reset-xrx200", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, lantiq_rcu_reset_dt_ids);
+
+static struct platform_driver lantiq_rcu_reset_driver = {
+ .probe = lantiq_rcu_reset_probe,
+ .driver = {
+ .name = "lantiq-reset",
+ .of_match_table = lantiq_rcu_reset_dt_ids,
+ },
+};
+module_platform_driver(lantiq_rcu_reset_driver);
+
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>");
+MODULE_DESCRIPTION("Lantiq XWAY RCU Reset Controller Driver");
+MODULE_LICENSE("GPL");
--
2.11.0
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^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v3 10/16] reset: Add a reset controller driver for the Lantiq XWAY based SoCs
@ 2017-05-28 18:40 ` Hauke Mehrtens
0 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:40 UTC (permalink / raw)
To: ralf
Cc: linux-mips, linux-mtd, linux-watchdog, devicetree,
martin.blumenstingl, john, linux-spi, hauke.mehrtens, robh,
andy.shevchenko, p.zabel, Hauke Mehrtens
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
The reset controllers (on xRX200 and newer SoCs have two of them) are
provided by the RCU module. This was initially implemented as a simple
reset controller. However, the RCU module provides more functionality
(ethernet GPHYs, USB PHY, etc.), which makes it a MFD device.
The old reset controller driver implementation from
arch/mips/lantiq/xway/reset.c did not honor this fact.
For some devices the request and the status bits are different.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
---
.../devicetree/bindings/reset/lantiq,reset.txt | 30 +++
drivers/reset/Kconfig | 6 +
drivers/reset/Makefile | 1 +
drivers/reset/reset-lantiq.c | 205 +++++++++++++++++++++
4 files changed, 242 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/lantiq,reset.txt
create mode 100644 drivers/reset/reset-lantiq.c
diff --git a/Documentation/devicetree/bindings/reset/lantiq,reset.txt b/Documentation/devicetree/bindings/reset/lantiq,reset.txt
new file mode 100644
index 000000000000..00cc3d4c68c4
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/lantiq,reset.txt
@@ -0,0 +1,30 @@
+Lantiq XWAY SoC RCU reset controller binding
+============================================
+
+This binding describes a reset-controller found on the RCU module on Lantiq
+XWAY SoCs.
+
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible : Should be one of
+ "lantiq,reset-danube"
+ "lantiq,reset-xrx200"
+- regmap : A phandle to the RCU syscon
+- offset-set : Offset of the reset set register
+- offset-status : Offset of the reset status register
+- #reset-cells : Specifies the number of cells needed to encode the
+ reset line, should be 2.
+ The first cell takes the reset set bit and the
+ second cell takes the status bit.
+
+-------------------------------------------------------------------------------
+Example for the reset-controllers on the xRX200 SoCs:
+ reset0: reset-controller@0 {
+ compatible = "lantiq,reset-xrx200";
+
+ regmap = <&rcu0>;
+ offset-set = <0x10>;
+ offset-status = <0x14>;
+ #reset-cells = <2>;
+ };
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index d21c07ccc94e..1742c2293bc3 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -41,6 +41,12 @@ config RESET_IMX7
help
This enables the reset controller driver for i.MX7 SoCs.
+config RESET_LANTIQ
+ bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
+ default SOC_TYPE_XWAY
+ help
+ This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
+
config RESET_LPC18XX
bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
default ARCH_LPC18XX
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 02a74db94339..112dba1db6b9 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
+obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
diff --git a/drivers/reset/reset-lantiq.c b/drivers/reset/reset-lantiq.c
new file mode 100644
index 000000000000..798bf648f36d
--- /dev/null
+++ b/drivers/reset/reset-lantiq.c
@@ -0,0 +1,205 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2010 John Crispin <blogic@phrozen.org>
+ * Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
+ * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
+ */
+
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+
+#define LANTIQ_RCU_RESET_TIMEOUT 10000
+
+struct lantiq_rcu_reset_priv {
+ struct reset_controller_dev rcdev;
+ struct device *dev;
+ struct regmap *regmap;
+ u32 reset_offset;
+ u32 status_offset;
+};
+
+static struct lantiq_rcu_reset_priv *to_lantiq_rcu_reset_priv(
+ struct reset_controller_dev *rcdev)
+{
+ return container_of(rcdev, struct lantiq_rcu_reset_priv, rcdev);
+}
+
+static int lantiq_rcu_reset_status(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct lantiq_rcu_reset_priv *priv = to_lantiq_rcu_reset_priv(rcdev);
+ unsigned int status = (id >> 8) & 0x1f;
+ u32 val;
+ int ret;
+
+ ret = regmap_read(priv->regmap, priv->status_offset, &val);
+ if (ret)
+ return ret;
+
+ return !!(val & BIT(status));
+}
+
+static int lantiq_rcu_reset_update(struct reset_controller_dev *rcdev,
+ unsigned long id, bool assert)
+{
+ struct lantiq_rcu_reset_priv *priv = to_lantiq_rcu_reset_priv(rcdev);
+ int ret, retry = LANTIQ_RCU_RESET_TIMEOUT;
+ unsigned int set = id & 0x1f;
+ u32 val;
+
+ if (assert)
+ val = BIT(set);
+ else
+ val = 0;
+
+ ret = regmap_update_bits(priv->regmap, priv->reset_offset, BIT(set),
+ val);
+ if (ret) {
+ dev_err(priv->dev, "Failed to set reset bit %u\n", set);
+ return ret;
+ }
+
+ do {
+ ret = lantiq_rcu_reset_status(rcdev, id);
+ if (ret < 0)
+ return ret;
+ if (ret == assert)
+ break;
+ usleep_range(20, 40);
+ } while (--retry);
+ if (!retry) {
+ dev_err(priv->dev, "Failed to %s bit %u\n",
+ assert ? "assert" : "deassert", set);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int lantiq_rcu_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ return lantiq_rcu_reset_update(rcdev, id, true);
+}
+
+static int lantiq_rcu_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ return lantiq_rcu_reset_update(rcdev, id, false);
+}
+
+static int lantiq_rcu_reset_reset(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ int ret;
+
+ ret = lantiq_rcu_reset_assert(rcdev, id);
+ if (ret)
+ return ret;
+
+ return lantiq_rcu_reset_deassert(rcdev, id);
+}
+
+static const struct reset_control_ops lantiq_rcu_reset_ops = {
+ .assert = lantiq_rcu_reset_assert,
+ .deassert = lantiq_rcu_reset_deassert,
+ .status = lantiq_rcu_reset_status,
+ .reset = lantiq_rcu_reset_reset,
+};
+
+static int lantiq_rcu_reset_of_probe(struct platform_device *pdev,
+ struct lantiq_rcu_reset_priv *priv)
+{
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ priv->regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "regmap");
+ if (IS_ERR(priv->regmap)) {
+ dev_err(&pdev->dev, "Failed to lookup RCU regmap\n");
+ return PTR_ERR(priv->regmap);
+ }
+
+ ret = device_property_read_u32(dev, "offset-set", &priv->reset_offset);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to get RCU reset offset\n");
+ return -EINVAL;
+ }
+
+ ret = device_property_read_u32(dev, "offset-status",
+ &priv->status_offset);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to get RCU status offset\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int lantiq_rcu_reset_xlate(struct reset_controller_dev *rcdev,
+ const struct of_phandle_args *reset_spec)
+{
+ unsigned int status, set;
+
+ set = reset_spec->args[0];
+ status = reset_spec->args[1];
+
+ if (set >= rcdev->nr_resets || status >= rcdev->nr_resets)
+ return -EINVAL;
+
+ return (status << 8) | set;
+}
+
+static int lantiq_rcu_reset_probe(struct platform_device *pdev)
+{
+ struct lantiq_rcu_reset_priv *priv;
+ int err;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = &pdev->dev;
+ platform_set_drvdata(pdev, priv);
+
+ err = lantiq_rcu_reset_of_probe(pdev, priv);
+ if (err)
+ return err;
+
+ priv->rcdev.ops = &lantiq_rcu_reset_ops;
+ priv->rcdev.owner = THIS_MODULE;
+ priv->rcdev.of_node = pdev->dev.of_node;
+ priv->rcdev.nr_resets = 32;
+ priv->rcdev.of_xlate = lantiq_rcu_reset_xlate;
+ priv->rcdev.of_reset_n_cells = 2;
+
+ return reset_controller_register(&priv->rcdev);
+}
+
+static const struct of_device_id lantiq_rcu_reset_dt_ids[] = {
+ { .compatible = "lantiq,reset-danube", },
+ { .compatible = "lantiq,reset-xrx200", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, lantiq_rcu_reset_dt_ids);
+
+static struct platform_driver lantiq_rcu_reset_driver = {
+ .probe = lantiq_rcu_reset_probe,
+ .driver = {
+ .name = "lantiq-reset",
+ .of_match_table = lantiq_rcu_reset_dt_ids,
+ },
+};
+module_platform_driver(lantiq_rcu_reset_driver);
+
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
+MODULE_DESCRIPTION("Lantiq XWAY RCU Reset Controller Driver");
+MODULE_LICENSE("GPL");
--
2.11.0
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [PATCH v3 10/16] reset: Add a reset controller driver for the Lantiq XWAY based SoCs
2017-05-28 18:40 ` Hauke Mehrtens
@ 2017-05-29 10:20 ` Philipp Zabel
-1 siblings, 0 replies; 60+ messages in thread
From: Philipp Zabel @ 2017-05-29 10:20 UTC (permalink / raw)
To: Hauke Mehrtens
Cc: ralf, linux-mips, linux-mtd, linux-watchdog, devicetree,
martin.blumenstingl, john, linux-spi, hauke.mehrtens, robh,
andy.shevchenko
Hi Hauke,
On Sun, 2017-05-28 at 20:40 +0200, Hauke Mehrtens wrote:
[...]
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/lantiq,reset.txt
> @@ -0,0 +1,30 @@
> +Lantiq XWAY SoC RCU reset controller binding
> +============================================
> +
> +This binding describes a reset-controller found on the RCU module on Lantiq
> +XWAY SoCs.
> +
> +
> +-------------------------------------------------------------------------------
> +Required properties:
> +- compatible : Should be one of
> + "lantiq,reset-danube"
> + "lantiq,reset-xrx200"
> +- regmap : A phandle to the RCU syscon
> +- offset-set : Offset of the reset set register
> +- offset-status : Offset of the reset status register
> +- #reset-cells : Specifies the number of cells needed to encode the
> + reset line, should be 2.
> + The first cell takes the reset set bit and the
> + second cell takes the status bit.
> +
> +-------------------------------------------------------------------------------
> +Example for the reset-controllers on the xRX200 SoCs:
> + reset0: reset-controller@0 {
> + compatible = "lantiq,reset-xrx200";
> +
> + regmap = <&rcu0>;
Why not place these nodes as children of &rcu0 ? This property would be
superfluous then.
> + offset-set = <0x10>;
> + offset-status = <0x14>;
> + #reset-cells = <2>;
> + };
[...]
> --- /dev/null
> +++ b/drivers/reset/reset-lantiq.c
> @@ -0,0 +1,205 @@
[...]
> +static int lantiq_rcu_reset_update(struct reset_controller_dev *rcdev,
> + unsigned long id, bool assert)
> +{
> + struct lantiq_rcu_reset_priv *priv = to_lantiq_rcu_reset_priv(rcdev);
> + int ret, retry = LANTIQ_RCU_RESET_TIMEOUT;
> + unsigned int set = id & 0x1f;
> + u32 val;
> +
> + if (assert)
> + val = BIT(set);
> + else
> + val = 0;
> +
> + ret = regmap_update_bits(priv->regmap, priv->reset_offset, BIT(set),
> + val);
> + if (ret) {
> + dev_err(priv->dev, "Failed to set reset bit %u\n", set);
> + return ret;
> + }
> +
> + do {
> + ret = lantiq_rcu_reset_status(rcdev, id);
> + if (ret < 0)
> + return ret;
> + if (ret == assert)
> + break;
> + usleep_range(20, 40);
> + } while (--retry);
How about wrapping this in a lantiq_rcu_poll_status(_timeout) function?
I still think this is a case where regmap_read_poll_timeout could be
used.
[...]
> +static int lantiq_rcu_reset_of_probe(struct platform_device *pdev,
> + struct lantiq_rcu_reset_priv *priv)
> +{
> + struct device *dev = &pdev->dev;
> + int ret;
> +
> + priv->regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "regmap");
Why not use syscon_node_to_regmap(dev->of_node->parent) ?
regards
Philipp
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH v3 10/16] reset: Add a reset controller driver for the Lantiq XWAY based SoCs
@ 2017-05-29 10:20 ` Philipp Zabel
0 siblings, 0 replies; 60+ messages in thread
From: Philipp Zabel @ 2017-05-29 10:20 UTC (permalink / raw)
To: Hauke Mehrtens
Cc: ralf, linux-mips, linux-mtd, linux-watchdog, devicetree,
martin.blumenstingl, john, linux-spi, hauke.mehrtens, robh,
andy.shevchenko
Hi Hauke,
On Sun, 2017-05-28 at 20:40 +0200, Hauke Mehrtens wrote:
[...]
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/lantiq,reset.txt
> @@ -0,0 +1,30 @@
> +Lantiq XWAY SoC RCU reset controller binding
> +============================================
> +
> +This binding describes a reset-controller found on the RCU module on Lantiq
> +XWAY SoCs.
> +
> +
> +-------------------------------------------------------------------------------
> +Required properties:
> +- compatible : Should be one of
> + "lantiq,reset-danube"
> + "lantiq,reset-xrx200"
> +- regmap : A phandle to the RCU syscon
> +- offset-set : Offset of the reset set register
> +- offset-status : Offset of the reset status register
> +- #reset-cells : Specifies the number of cells needed to encode the
> + reset line, should be 2.
> + The first cell takes the reset set bit and the
> + second cell takes the status bit.
> +
> +-------------------------------------------------------------------------------
> +Example for the reset-controllers on the xRX200 SoCs:
> + reset0: reset-controller@0 {
> + compatible = "lantiq,reset-xrx200";
> +
> + regmap = <&rcu0>;
Why not place these nodes as children of &rcu0 ? This property would be
superfluous then.
> + offset-set = <0x10>;
> + offset-status = <0x14>;
> + #reset-cells = <2>;
> + };
[...]
> --- /dev/null
> +++ b/drivers/reset/reset-lantiq.c
> @@ -0,0 +1,205 @@
[...]
> +static int lantiq_rcu_reset_update(struct reset_controller_dev *rcdev,
> + unsigned long id, bool assert)
> +{
> + struct lantiq_rcu_reset_priv *priv = to_lantiq_rcu_reset_priv(rcdev);
> + int ret, retry = LANTIQ_RCU_RESET_TIMEOUT;
> + unsigned int set = id & 0x1f;
> + u32 val;
> +
> + if (assert)
> + val = BIT(set);
> + else
> + val = 0;
> +
> + ret = regmap_update_bits(priv->regmap, priv->reset_offset, BIT(set),
> + val);
> + if (ret) {
> + dev_err(priv->dev, "Failed to set reset bit %u\n", set);
> + return ret;
> + }
> +
> + do {
> + ret = lantiq_rcu_reset_status(rcdev, id);
> + if (ret < 0)
> + return ret;
> + if (ret == assert)
> + break;
> + usleep_range(20, 40);
> + } while (--retry);
How about wrapping this in a lantiq_rcu_poll_status(_timeout) function?
I still think this is a case where regmap_read_poll_timeout could be
used.
[...]
> +static int lantiq_rcu_reset_of_probe(struct platform_device *pdev,
> + struct lantiq_rcu_reset_priv *priv)
> +{
> + struct device *dev = &pdev->dev;
> + int ret;
> +
> + priv->regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "regmap");
Why not use syscon_node_to_regmap(dev->of_node->parent) ?
regards
Philipp
^ permalink raw reply [flat|nested] 60+ messages in thread[parent not found: <1496053214.17695.49.camel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>]
* Re: [PATCH v3 10/16] reset: Add a reset controller driver for the Lantiq XWAY based SoCs
2017-05-29 10:20 ` Philipp Zabel
@ 2017-05-31 20:58 ` Rob Herring
-1 siblings, 0 replies; 60+ messages in thread
From: Rob Herring @ 2017-05-31 20:58 UTC (permalink / raw)
To: Philipp Zabel
Cc: Hauke Mehrtens, ralf-6z/3iImG2C8G8FEW9MqTrA,
linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w,
andy.shevchenko-Re5JQEeQqe8AvxtiuMwx3w
On Mon, May 29, 2017 at 12:20:14PM +0200, Philipp Zabel wrote:
> Hi Hauke,
>
> On Sun, 2017-05-28 at 20:40 +0200, Hauke Mehrtens wrote:
> [...]
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/reset/lantiq,reset.txt
> > @@ -0,0 +1,30 @@
> > +Lantiq XWAY SoC RCU reset controller binding
> > +============================================
> > +
> > +This binding describes a reset-controller found on the RCU module on Lantiq
> > +XWAY SoCs.
> > +
> > +
> > +-------------------------------------------------------------------------------
> > +Required properties:
> > +- compatible : Should be one of
> > + "lantiq,reset-danube"
> > + "lantiq,reset-xrx200"
> > +- regmap : A phandle to the RCU syscon
> > +- offset-set : Offset of the reset set register
> > +- offset-status : Offset of the reset status register
> > +- #reset-cells : Specifies the number of cells needed to encode the
> > + reset line, should be 2.
> > + The first cell takes the reset set bit and the
> > + second cell takes the status bit.
> > +
> > +-------------------------------------------------------------------------------
> > +Example for the reset-controllers on the xRX200 SoCs:
> > + reset0: reset-controller@0 {
> > + compatible = "lantiq,reset-xrx200";
> > +
> > + regmap = <&rcu0>;
>
> Why not place these nodes as children of &rcu0 ? This property would be
> superfluous then.
They are children. So it should be removed and made clear that these are
child nodes of rcu (here and in other patches in this series).
Rob
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^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH v3 10/16] reset: Add a reset controller driver for the Lantiq XWAY based SoCs
@ 2017-05-31 20:58 ` Rob Herring
0 siblings, 0 replies; 60+ messages in thread
From: Rob Herring @ 2017-05-31 20:58 UTC (permalink / raw)
To: Philipp Zabel
Cc: Hauke Mehrtens, ralf, linux-mips, linux-mtd, linux-watchdog,
devicetree, martin.blumenstingl, john, linux-spi, hauke.mehrtens,
andy.shevchenko
On Mon, May 29, 2017 at 12:20:14PM +0200, Philipp Zabel wrote:
> Hi Hauke,
>
> On Sun, 2017-05-28 at 20:40 +0200, Hauke Mehrtens wrote:
> [...]
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/reset/lantiq,reset.txt
> > @@ -0,0 +1,30 @@
> > +Lantiq XWAY SoC RCU reset controller binding
> > +============================================
> > +
> > +This binding describes a reset-controller found on the RCU module on Lantiq
> > +XWAY SoCs.
> > +
> > +
> > +-------------------------------------------------------------------------------
> > +Required properties:
> > +- compatible : Should be one of
> > + "lantiq,reset-danube"
> > + "lantiq,reset-xrx200"
> > +- regmap : A phandle to the RCU syscon
> > +- offset-set : Offset of the reset set register
> > +- offset-status : Offset of the reset status register
> > +- #reset-cells : Specifies the number of cells needed to encode the
> > + reset line, should be 2.
> > + The first cell takes the reset set bit and the
> > + second cell takes the status bit.
> > +
> > +-------------------------------------------------------------------------------
> > +Example for the reset-controllers on the xRX200 SoCs:
> > + reset0: reset-controller@0 {
> > + compatible = "lantiq,reset-xrx200";
> > +
> > + regmap = <&rcu0>;
>
> Why not place these nodes as children of &rcu0 ? This property would be
> superfluous then.
They are children. So it should be removed and made clear that these are
child nodes of rcu (here and in other patches in this series).
Rob
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v3 11/16] MIPS: lantiq: remove old reset controller implementation
2017-05-28 18:39 ` Hauke Mehrtens
@ 2017-05-28 18:40 ` Hauke Mehrtens
-1 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:40 UTC (permalink / raw)
To: ralf-6z/3iImG2C8G8FEW9MqTrA
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w,
robh-DgEjT+Ai2ygdnm+yROfE0A,
andy.shevchenko-Re5JQEeQqe8AvxtiuMwx3w,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ, Hauke Mehrtens
This code is now replaced by a reset controller in drivers/reset/reset-
lantiq-rcu.c. The old code was never used anyway.
Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
arch/mips/lantiq/xway/reset.c | 68 -------------------------------------------
1 file changed, 68 deletions(-)
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index 2dedcf939901..5cb9309b0047 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -194,74 +194,6 @@ int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr)
return 0;
}
-/* reset a io domain for u micro seconds */
-void ltq_reset_once(unsigned int module, ulong u)
-{
- ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | module, RCU_RST_REQ);
- udelay(u);
- ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~module, RCU_RST_REQ);
-}
-
-static int ltq_assert_device(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
- u32 val;
-
- if (id < 8)
- return -1;
-
- val = ltq_rcu_r32(RCU_RST_REQ);
- val |= BIT(id);
- ltq_rcu_w32(val, RCU_RST_REQ);
-
- return 0;
-}
-
-static int ltq_deassert_device(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
- u32 val;
-
- if (id < 8)
- return -1;
-
- val = ltq_rcu_r32(RCU_RST_REQ);
- val &= ~BIT(id);
- ltq_rcu_w32(val, RCU_RST_REQ);
-
- return 0;
-}
-
-static int ltq_reset_device(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
- ltq_assert_device(rcdev, id);
- return ltq_deassert_device(rcdev, id);
-}
-
-static const struct reset_control_ops reset_ops = {
- .reset = ltq_reset_device,
- .assert = ltq_assert_device,
- .deassert = ltq_deassert_device,
-};
-
-static struct reset_controller_dev reset_dev = {
- .ops = &reset_ops,
- .owner = THIS_MODULE,
- .nr_resets = 32,
- .of_reset_n_cells = 1,
-};
-
-void ltq_rst_init(void)
-{
- reset_dev.of_node = of_find_compatible_node(NULL, NULL,
- "lantiq,xway-reset");
- if (!reset_dev.of_node)
- pr_err("Failed to find reset controller node");
- else
- reset_controller_register(&reset_dev);
-}
-
static void ltq_machine_restart(char *command)
{
u32 val = ltq_rcu_r32(RCU_RST_REQ);
--
2.11.0
--
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^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v3 11/16] MIPS: lantiq: remove old reset controller implementation
@ 2017-05-28 18:40 ` Hauke Mehrtens
0 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:40 UTC (permalink / raw)
To: ralf
Cc: linux-mips, linux-mtd, linux-watchdog, devicetree,
martin.blumenstingl, john, linux-spi, hauke.mehrtens, robh,
andy.shevchenko, p.zabel, Hauke Mehrtens
This code is now replaced by a reset controller in drivers/reset/reset-
lantiq-rcu.c. The old code was never used anyway.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
arch/mips/lantiq/xway/reset.c | 68 -------------------------------------------
1 file changed, 68 deletions(-)
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index 2dedcf939901..5cb9309b0047 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -194,74 +194,6 @@ int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr)
return 0;
}
-/* reset a io domain for u micro seconds */
-void ltq_reset_once(unsigned int module, ulong u)
-{
- ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | module, RCU_RST_REQ);
- udelay(u);
- ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~module, RCU_RST_REQ);
-}
-
-static int ltq_assert_device(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
- u32 val;
-
- if (id < 8)
- return -1;
-
- val = ltq_rcu_r32(RCU_RST_REQ);
- val |= BIT(id);
- ltq_rcu_w32(val, RCU_RST_REQ);
-
- return 0;
-}
-
-static int ltq_deassert_device(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
- u32 val;
-
- if (id < 8)
- return -1;
-
- val = ltq_rcu_r32(RCU_RST_REQ);
- val &= ~BIT(id);
- ltq_rcu_w32(val, RCU_RST_REQ);
-
- return 0;
-}
-
-static int ltq_reset_device(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
- ltq_assert_device(rcdev, id);
- return ltq_deassert_device(rcdev, id);
-}
-
-static const struct reset_control_ops reset_ops = {
- .reset = ltq_reset_device,
- .assert = ltq_assert_device,
- .deassert = ltq_deassert_device,
-};
-
-static struct reset_controller_dev reset_dev = {
- .ops = &reset_ops,
- .owner = THIS_MODULE,
- .nr_resets = 32,
- .of_reset_n_cells = 1,
-};
-
-void ltq_rst_init(void)
-{
- reset_dev.of_node = of_find_compatible_node(NULL, NULL,
- "lantiq,xway-reset");
- if (!reset_dev.of_node)
- pr_err("Failed to find reset controller node");
- else
- reset_controller_register(&reset_dev);
-}
-
static void ltq_machine_restart(char *command)
{
u32 val = ltq_rcu_r32(RCU_RST_REQ);
--
2.11.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v3 12/16] MIPS: lantiq: Add a GPHY driver which uses the RCU syscon-mfd
2017-05-28 18:39 ` Hauke Mehrtens
@ 2017-05-28 18:40 ` Hauke Mehrtens
-1 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:40 UTC (permalink / raw)
To: ralf-6z/3iImG2C8G8FEW9MqTrA
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w,
robh-DgEjT+Ai2ygdnm+yROfE0A,
andy.shevchenko-Re5JQEeQqe8AvxtiuMwx3w,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ, Hauke Mehrtens
From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
Compared to the old xrx200_phy_fw driver the new version has multiple
enhancements. The name of the firmware files does not have to be added
to all .dts files anymore - one now configures the GPHY mode (FE or GE)
instead. Each GPHY can now also boot separate firmware (thus mixing of
GE and FE GPHYs is now possible).
The new implementation is based on the RCU syscon-mfd and uses the
reeset_controller framework instead of raw RCU register reads/writes.
Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
.../devicetree/bindings/mips/lantiq/rcu-gphy.txt | 38 +++
arch/mips/lantiq/xway/sysctrl.c | 6 +-
drivers/soc/lantiq/Makefile | 1 +
drivers/soc/lantiq/gphy.c | 277 +++++++++++++++++++++
include/dt-bindings/mips/lantiq_rcu_gphy.h | 15 ++
5 files changed, 335 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
create mode 100644 drivers/soc/lantiq/gphy.c
create mode 100644 include/dt-bindings/mips/lantiq_rcu_gphy.h
diff --git a/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt b/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
new file mode 100644
index 000000000000..529b97d7e350
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
@@ -0,0 +1,38 @@
+Lantiq XWAY SoC GPHY binding
+============================
+
+This binding describes a software-defined ethernet PHY, provided by the RCU
+module on newer Lantiq XWAY SoCs (xRX200 and newer).
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible : Should be one of
+ "lantiq,xrx200a1x-rcu-gphy"
+ "lantiq,xrx200a2x-rcu-gphy"
+ "lantiq,xrx300-rcu-gphy"
+ "lantiq,xrx330-rcu-gphy"
+- regmap : A phandle to the RCU syscon
+- offset : Offset of the GPHY FW load address register
+- resets : Must reference the RCU GPHY reset bit
+- reset-names : One entry, value must be "gphy" or optional "gphy2"
+- clocks : A reference to the (PMU) GPHY clock gate
+
+Optional properties:
+- lantiq,gphy-mode : GPHY_MODE_GE (default) or GPHY_MODE_FE as defined in
+ <dt-bindings/mips/lantiq_xway_gphy.h>
+
+
+-------------------------------------------------------------------------------
+Example for the GPHys on the xRX200 SoCs:
+
+#include <dt-bindings/mips/lantiq_rcu_gphy.h>
+ gphy0: gphy@0 {
+ compatible = "lantiq,xrx200a2x-rcu-gphy";
+
+ regmap = <&rcu0>;
+ offset = <0x20>;
+ resets = <&reset0 31 30>, <&reset1 7 7>;
+ reset-names = "gphy", "gphy2";
+ clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
+ lantiq,gphy-mode = <GPHY_MODE_GE>
+ };
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 706639a343bc..0789c48ef779 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -518,7 +518,8 @@ void __init ltq_soc_init(void)
clkdev_add_pmu("1e108000.eth", NULL, 0, 0, PMU_SWITCH |
PMU_PPE_DP | PMU_PPE_TC);
clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
- clkdev_add_pmu("1f203000.rcu", "gphy", 1, 0, PMU_GPHY);
+ clkdev_add_pmu("1f203000.rcu:gphy@0", NULL, 1, 0, PMU_GPHY);
+ clkdev_add_pmu("1f203000.rcu:gphy@1", NULL, 1, 0, PMU_GPHY);
clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
clkdev_add_pmu("1e116000.mei", "afe", 1, 2, PMU_ANALOG_DSL_AFE);
clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
@@ -541,7 +542,8 @@ void __init ltq_soc_init(void)
PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
PMU_PPE_QSB | PMU_PPE_TOP);
- clkdev_add_pmu("1f203000.rcu", "gphy", 0, 0, PMU_GPHY);
+ clkdev_add_pmu("1f203000.rcu:gphy@0", NULL, 0, 0, PMU_GPHY);
+ clkdev_add_pmu("1f203000.rcu:gphy@1", NULL, 0, 0, PMU_GPHY);
clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
diff --git a/drivers/soc/lantiq/Makefile b/drivers/soc/lantiq/Makefile
index 35aa86bd1023..be9e866d53e5 100644
--- a/drivers/soc/lantiq/Makefile
+++ b/drivers/soc/lantiq/Makefile
@@ -1 +1,2 @@
obj-y += fpi-bus.o
+obj-$(CONFIG_XRX200_PHY_FW) += gphy.o
diff --git a/drivers/soc/lantiq/gphy.c b/drivers/soc/lantiq/gphy.c
new file mode 100644
index 000000000000..59b179166a82
--- /dev/null
+++ b/drivers/soc/lantiq/gphy.c
@@ -0,0 +1,277 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2012 John Crispin <blogic-Pj+rj9U5foFAfugRpC6u6w@public.gmane.org>
+ * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
+ * Copyright (C) 2017 Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/firmware.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/reboot.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/of_platform.h>
+#include <linux/property.h>
+#include <dt-bindings/mips/lantiq_rcu_gphy.h>
+
+#include <lantiq_soc.h>
+
+#define XRX200_GPHY_FW_ALIGN (16 * 1024)
+
+struct xway_gphy_priv {
+ struct clk *gphy_clk_gate;
+ struct reset_control *gphy_reset;
+ struct reset_control *gphy_reset2;
+ struct regmap *regmap;
+ struct notifier_block gphy_reboot_nb;
+ u32 reg_offset;
+ char *fw_name;
+ dma_addr_t dma_addr;
+ void *fw_addr;
+ size_t size;
+};
+
+struct xway_gphy_match_data {
+ char *fe_firmware_name;
+ char *ge_firmware_name;
+};
+
+static const struct xway_gphy_match_data xrx200a1x_gphy_data = {
+ .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin",
+ .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin",
+};
+
+static const struct xway_gphy_match_data xrx200a2x_gphy_data = {
+ .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin",
+ .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin",
+};
+
+static const struct xway_gphy_match_data xrx300_gphy_data = {
+ .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin",
+ .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin",
+};
+
+static const struct of_device_id xway_gphy_match[] = {
+ { .compatible = "lantiq,xrx200a1x-rcu-gphy", .data = &xrx200a1x_gphy_data },
+ { .compatible = "lantiq,xrx200a2x-rcu-gphy", .data = &xrx200a2x_gphy_data },
+ { .compatible = "lantiq,xrx300-rcu-gphy", .data = &xrx300_gphy_data },
+ { .compatible = "lantiq,xrx330-rcu-gphy", .data = &xrx300_gphy_data },
+ {},
+};
+MODULE_DEVICE_TABLE(of, xway_gphy_match);
+
+static struct xway_gphy_priv *to_xway_gphy_priv(struct notifier_block *nb)
+{
+ return container_of(nb, struct xway_gphy_priv, gphy_reboot_nb);
+}
+
+static int xway_gphy_reboot_notify(struct notifier_block *reboot_nb,
+ unsigned long code, void *unused)
+{
+ struct xway_gphy_priv *priv = to_xway_gphy_priv(reboot_nb);
+
+ if (priv) {
+ reset_control_assert(priv->gphy_reset);
+ reset_control_assert(priv->gphy_reset2);
+ }
+
+ return NOTIFY_DONE;
+}
+
+static int xway_gphy_load(struct platform_device *pdev,
+ struct xway_gphy_priv *priv,
+ dma_addr_t *dev_addr)
+{
+ const struct firmware *fw;
+ void *fw_addr_align;
+ int ret;
+
+ ret = request_firmware(&fw, priv->fw_name, &pdev->dev);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to load firmware: %s, error: %i\n",
+ priv->fw_name, ret);
+ return ret;
+ }
+
+ /*
+ * GPHY cores need the firmware code in a persistent and contiguous
+ * memory area with a 16 kB boundary aligned start address.
+ */
+ priv->size = fw->size + XRX200_GPHY_FW_ALIGN;
+
+ priv->fw_addr = dma_alloc_coherent(&pdev->dev, priv->size,
+ &priv->dma_addr, GFP_KERNEL);
+ if (priv->fw_addr) {
+ fw_addr_align = PTR_ALIGN(priv->fw_addr, XRX200_GPHY_FW_ALIGN);
+ *dev_addr = ALIGN(priv->dma_addr, XRX200_GPHY_FW_ALIGN);
+ memcpy(fw_addr_align, fw->data, fw->size);
+ } else {
+ dev_err(&pdev->dev, "failed to alloc firmware memory\n");
+ ret = -ENOMEM;
+ }
+
+ release_firmware(fw);
+
+ return ret;
+}
+
+static int xway_gphy_of_probe(struct platform_device *pdev,
+ struct xway_gphy_priv *priv)
+{
+ struct device *dev = &pdev->dev;
+ const struct of_device_id *match = of_match_node(xway_gphy_match,
+ dev->of_node);
+ const struct xway_gphy_match_data *gphy_fw_name_cfg;
+ u32 gphy_mode;
+ int ret;
+
+ gphy_fw_name_cfg = match->data;
+
+ priv->gphy_clk_gate = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(priv->gphy_clk_gate)) {
+ dev_err(&pdev->dev, "Failed to lookup gate clock\n");
+ return PTR_ERR(priv->gphy_clk_gate);
+ }
+
+ priv->regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "regmap");
+ if (IS_ERR(priv->regmap)) {
+ dev_err(&pdev->dev, "Failed to lookup RCU regmap\n");
+ return PTR_ERR(priv->regmap);
+ }
+
+ ret = device_property_read_u32(dev, "offset", &priv->reg_offset);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to get RCU reg offset\n");
+ return -EINVAL;
+ }
+
+ priv->gphy_reset = devm_reset_control_get(&pdev->dev, "gphy");
+ if (IS_ERR(priv->gphy_reset)) {
+ if (PTR_ERR(priv->gphy_reset) != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "Failed to lookup gphy reset\n");
+ return PTR_ERR(priv->gphy_reset);
+ }
+
+ priv->gphy_reset2 = devm_reset_control_get_optional(&pdev->dev,
+ "gphy2");
+ if (IS_ERR(priv->gphy_reset2))
+ return PTR_ERR(priv->gphy_reset2);
+
+ ret = device_property_read_u32(dev, "lantiq,gphy-mode", &gphy_mode);
+ /* Default to GE mode */
+ if (ret)
+ gphy_mode = GPHY_MODE_GE;
+
+ switch (gphy_mode) {
+ case GPHY_MODE_FE:
+ priv->fw_name = gphy_fw_name_cfg->fe_firmware_name;
+ break;
+ case GPHY_MODE_GE:
+ priv->fw_name = gphy_fw_name_cfg->ge_firmware_name;
+ break;
+ default:
+ dev_err(&pdev->dev, "Unknown GPHY mode %d\n", gphy_mode);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int xway_gphy_probe(struct platform_device *pdev)
+{
+ struct xway_gphy_priv *priv;
+ dma_addr_t fw_addr = 0;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ ret = xway_gphy_of_probe(pdev, priv);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(priv->gphy_clk_gate);
+ if (ret)
+ return ret;
+
+ ret = xway_gphy_load(pdev, priv, &fw_addr);
+ if (ret)
+ return ret;
+
+ reset_control_assert(priv->gphy_reset);
+ reset_control_assert(priv->gphy_reset2);
+
+ ret = regmap_write(priv->regmap, priv->reg_offset, fw_addr);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to configure FW addr\n");
+ return ret;
+ }
+
+ reset_control_deassert(priv->gphy_reset);
+ reset_control_deassert(priv->gphy_reset2);
+
+ /* assert the gphy reset because it can hang after a reboot: */
+ priv->gphy_reboot_nb.notifier_call = xway_gphy_reboot_notify;
+ priv->gphy_reboot_nb.priority = -1;
+
+ ret = register_reboot_notifier(&priv->gphy_reboot_nb);
+ if (ret)
+ dev_warn(&pdev->dev, "Failed to register reboot notifier\n");
+
+ platform_set_drvdata(pdev, priv);
+
+ return ret;
+}
+
+static int xway_gphy_remove(struct platform_device *pdev)
+{
+ struct xway_gphy_priv *priv = platform_get_drvdata(pdev);
+ int ret;
+
+ reset_control_assert(priv->gphy_reset);
+ reset_control_assert(priv->gphy_reset2);
+
+ ret = regmap_write(priv->regmap, priv->reg_offset, 0);
+ if (ret)
+ dev_err(&pdev->dev, "Failed to configure FW addr\n");
+
+ clk_disable_unprepare(priv->gphy_clk_gate);
+
+ dma_free_coherent(&pdev->dev, priv->size, priv->fw_addr,
+ priv->dma_addr);
+
+ ret = unregister_reboot_notifier(&priv->gphy_reboot_nb);
+ if (ret)
+ dev_warn(&pdev->dev, "Failed to unregister reboot notifier\n");
+
+ return 0;
+}
+
+static struct platform_driver xway_gphy_driver = {
+ .probe = xway_gphy_probe,
+ .remove = xway_gphy_remove,
+ .driver = {
+ .name = "xway-rcu-gphy",
+ .of_match_table = xway_gphy_match,
+ },
+};
+
+module_platform_driver(xway_gphy_driver);
+
+MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin");
+MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin");
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>");
+MODULE_DESCRIPTION("Lantiq XWAY GPHY Firmware Loader");
+MODULE_LICENSE("GPL");
diff --git a/include/dt-bindings/mips/lantiq_rcu_gphy.h b/include/dt-bindings/mips/lantiq_rcu_gphy.h
new file mode 100644
index 000000000000..fa1a63773342
--- /dev/null
+++ b/include/dt-bindings/mips/lantiq_rcu_gphy.h
@@ -0,0 +1,15 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
+ * Copyright (C) 2017 Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
+ */
+#ifndef _DT_BINDINGS_MIPS_LANTIQ_RCU_GPHY_H
+#define _DT_BINDINGS_MIPS_LANTIQ_RCU_GPHY_H
+
+#define GPHY_MODE_GE 1
+#define GPHY_MODE_FE 2
+
+#endif /* _DT_BINDINGS_MIPS_LANTIQ_RCU_GPHY_H */
--
2.11.0
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^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v3 12/16] MIPS: lantiq: Add a GPHY driver which uses the RCU syscon-mfd
@ 2017-05-28 18:40 ` Hauke Mehrtens
0 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:40 UTC (permalink / raw)
To: ralf
Cc: linux-mips, linux-mtd, linux-watchdog, devicetree,
martin.blumenstingl, john, linux-spi, hauke.mehrtens, robh,
andy.shevchenko, p.zabel, Hauke Mehrtens
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Compared to the old xrx200_phy_fw driver the new version has multiple
enhancements. The name of the firmware files does not have to be added
to all .dts files anymore - one now configures the GPHY mode (FE or GE)
instead. Each GPHY can now also boot separate firmware (thus mixing of
GE and FE GPHYs is now possible).
The new implementation is based on the RCU syscon-mfd and uses the
reeset_controller framework instead of raw RCU register reads/writes.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
.../devicetree/bindings/mips/lantiq/rcu-gphy.txt | 38 +++
arch/mips/lantiq/xway/sysctrl.c | 6 +-
drivers/soc/lantiq/Makefile | 1 +
drivers/soc/lantiq/gphy.c | 277 +++++++++++++++++++++
include/dt-bindings/mips/lantiq_rcu_gphy.h | 15 ++
5 files changed, 335 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
create mode 100644 drivers/soc/lantiq/gphy.c
create mode 100644 include/dt-bindings/mips/lantiq_rcu_gphy.h
diff --git a/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt b/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
new file mode 100644
index 000000000000..529b97d7e350
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
@@ -0,0 +1,38 @@
+Lantiq XWAY SoC GPHY binding
+============================
+
+This binding describes a software-defined ethernet PHY, provided by the RCU
+module on newer Lantiq XWAY SoCs (xRX200 and newer).
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible : Should be one of
+ "lantiq,xrx200a1x-rcu-gphy"
+ "lantiq,xrx200a2x-rcu-gphy"
+ "lantiq,xrx300-rcu-gphy"
+ "lantiq,xrx330-rcu-gphy"
+- regmap : A phandle to the RCU syscon
+- offset : Offset of the GPHY FW load address register
+- resets : Must reference the RCU GPHY reset bit
+- reset-names : One entry, value must be "gphy" or optional "gphy2"
+- clocks : A reference to the (PMU) GPHY clock gate
+
+Optional properties:
+- lantiq,gphy-mode : GPHY_MODE_GE (default) or GPHY_MODE_FE as defined in
+ <dt-bindings/mips/lantiq_xway_gphy.h>
+
+
+-------------------------------------------------------------------------------
+Example for the GPHys on the xRX200 SoCs:
+
+#include <dt-bindings/mips/lantiq_rcu_gphy.h>
+ gphy0: gphy@0 {
+ compatible = "lantiq,xrx200a2x-rcu-gphy";
+
+ regmap = <&rcu0>;
+ offset = <0x20>;
+ resets = <&reset0 31 30>, <&reset1 7 7>;
+ reset-names = "gphy", "gphy2";
+ clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
+ lantiq,gphy-mode = <GPHY_MODE_GE>
+ };
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 706639a343bc..0789c48ef779 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -518,7 +518,8 @@ void __init ltq_soc_init(void)
clkdev_add_pmu("1e108000.eth", NULL, 0, 0, PMU_SWITCH |
PMU_PPE_DP | PMU_PPE_TC);
clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
- clkdev_add_pmu("1f203000.rcu", "gphy", 1, 0, PMU_GPHY);
+ clkdev_add_pmu("1f203000.rcu:gphy@0", NULL, 1, 0, PMU_GPHY);
+ clkdev_add_pmu("1f203000.rcu:gphy@1", NULL, 1, 0, PMU_GPHY);
clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
clkdev_add_pmu("1e116000.mei", "afe", 1, 2, PMU_ANALOG_DSL_AFE);
clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
@@ -541,7 +542,8 @@ void __init ltq_soc_init(void)
PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
PMU_PPE_QSB | PMU_PPE_TOP);
- clkdev_add_pmu("1f203000.rcu", "gphy", 0, 0, PMU_GPHY);
+ clkdev_add_pmu("1f203000.rcu:gphy@0", NULL, 0, 0, PMU_GPHY);
+ clkdev_add_pmu("1f203000.rcu:gphy@1", NULL, 0, 0, PMU_GPHY);
clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
diff --git a/drivers/soc/lantiq/Makefile b/drivers/soc/lantiq/Makefile
index 35aa86bd1023..be9e866d53e5 100644
--- a/drivers/soc/lantiq/Makefile
+++ b/drivers/soc/lantiq/Makefile
@@ -1 +1,2 @@
obj-y += fpi-bus.o
+obj-$(CONFIG_XRX200_PHY_FW) += gphy.o
diff --git a/drivers/soc/lantiq/gphy.c b/drivers/soc/lantiq/gphy.c
new file mode 100644
index 000000000000..59b179166a82
--- /dev/null
+++ b/drivers/soc/lantiq/gphy.c
@@ -0,0 +1,277 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2012 John Crispin <blogic@phrozen.org>
+ * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/firmware.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/reboot.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/of_platform.h>
+#include <linux/property.h>
+#include <dt-bindings/mips/lantiq_rcu_gphy.h>
+
+#include <lantiq_soc.h>
+
+#define XRX200_GPHY_FW_ALIGN (16 * 1024)
+
+struct xway_gphy_priv {
+ struct clk *gphy_clk_gate;
+ struct reset_control *gphy_reset;
+ struct reset_control *gphy_reset2;
+ struct regmap *regmap;
+ struct notifier_block gphy_reboot_nb;
+ u32 reg_offset;
+ char *fw_name;
+ dma_addr_t dma_addr;
+ void *fw_addr;
+ size_t size;
+};
+
+struct xway_gphy_match_data {
+ char *fe_firmware_name;
+ char *ge_firmware_name;
+};
+
+static const struct xway_gphy_match_data xrx200a1x_gphy_data = {
+ .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin",
+ .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin",
+};
+
+static const struct xway_gphy_match_data xrx200a2x_gphy_data = {
+ .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin",
+ .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin",
+};
+
+static const struct xway_gphy_match_data xrx300_gphy_data = {
+ .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin",
+ .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin",
+};
+
+static const struct of_device_id xway_gphy_match[] = {
+ { .compatible = "lantiq,xrx200a1x-rcu-gphy", .data = &xrx200a1x_gphy_data },
+ { .compatible = "lantiq,xrx200a2x-rcu-gphy", .data = &xrx200a2x_gphy_data },
+ { .compatible = "lantiq,xrx300-rcu-gphy", .data = &xrx300_gphy_data },
+ { .compatible = "lantiq,xrx330-rcu-gphy", .data = &xrx300_gphy_data },
+ {},
+};
+MODULE_DEVICE_TABLE(of, xway_gphy_match);
+
+static struct xway_gphy_priv *to_xway_gphy_priv(struct notifier_block *nb)
+{
+ return container_of(nb, struct xway_gphy_priv, gphy_reboot_nb);
+}
+
+static int xway_gphy_reboot_notify(struct notifier_block *reboot_nb,
+ unsigned long code, void *unused)
+{
+ struct xway_gphy_priv *priv = to_xway_gphy_priv(reboot_nb);
+
+ if (priv) {
+ reset_control_assert(priv->gphy_reset);
+ reset_control_assert(priv->gphy_reset2);
+ }
+
+ return NOTIFY_DONE;
+}
+
+static int xway_gphy_load(struct platform_device *pdev,
+ struct xway_gphy_priv *priv,
+ dma_addr_t *dev_addr)
+{
+ const struct firmware *fw;
+ void *fw_addr_align;
+ int ret;
+
+ ret = request_firmware(&fw, priv->fw_name, &pdev->dev);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to load firmware: %s, error: %i\n",
+ priv->fw_name, ret);
+ return ret;
+ }
+
+ /*
+ * GPHY cores need the firmware code in a persistent and contiguous
+ * memory area with a 16 kB boundary aligned start address.
+ */
+ priv->size = fw->size + XRX200_GPHY_FW_ALIGN;
+
+ priv->fw_addr = dma_alloc_coherent(&pdev->dev, priv->size,
+ &priv->dma_addr, GFP_KERNEL);
+ if (priv->fw_addr) {
+ fw_addr_align = PTR_ALIGN(priv->fw_addr, XRX200_GPHY_FW_ALIGN);
+ *dev_addr = ALIGN(priv->dma_addr, XRX200_GPHY_FW_ALIGN);
+ memcpy(fw_addr_align, fw->data, fw->size);
+ } else {
+ dev_err(&pdev->dev, "failed to alloc firmware memory\n");
+ ret = -ENOMEM;
+ }
+
+ release_firmware(fw);
+
+ return ret;
+}
+
+static int xway_gphy_of_probe(struct platform_device *pdev,
+ struct xway_gphy_priv *priv)
+{
+ struct device *dev = &pdev->dev;
+ const struct of_device_id *match = of_match_node(xway_gphy_match,
+ dev->of_node);
+ const struct xway_gphy_match_data *gphy_fw_name_cfg;
+ u32 gphy_mode;
+ int ret;
+
+ gphy_fw_name_cfg = match->data;
+
+ priv->gphy_clk_gate = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(priv->gphy_clk_gate)) {
+ dev_err(&pdev->dev, "Failed to lookup gate clock\n");
+ return PTR_ERR(priv->gphy_clk_gate);
+ }
+
+ priv->regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "regmap");
+ if (IS_ERR(priv->regmap)) {
+ dev_err(&pdev->dev, "Failed to lookup RCU regmap\n");
+ return PTR_ERR(priv->regmap);
+ }
+
+ ret = device_property_read_u32(dev, "offset", &priv->reg_offset);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to get RCU reg offset\n");
+ return -EINVAL;
+ }
+
+ priv->gphy_reset = devm_reset_control_get(&pdev->dev, "gphy");
+ if (IS_ERR(priv->gphy_reset)) {
+ if (PTR_ERR(priv->gphy_reset) != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "Failed to lookup gphy reset\n");
+ return PTR_ERR(priv->gphy_reset);
+ }
+
+ priv->gphy_reset2 = devm_reset_control_get_optional(&pdev->dev,
+ "gphy2");
+ if (IS_ERR(priv->gphy_reset2))
+ return PTR_ERR(priv->gphy_reset2);
+
+ ret = device_property_read_u32(dev, "lantiq,gphy-mode", &gphy_mode);
+ /* Default to GE mode */
+ if (ret)
+ gphy_mode = GPHY_MODE_GE;
+
+ switch (gphy_mode) {
+ case GPHY_MODE_FE:
+ priv->fw_name = gphy_fw_name_cfg->fe_firmware_name;
+ break;
+ case GPHY_MODE_GE:
+ priv->fw_name = gphy_fw_name_cfg->ge_firmware_name;
+ break;
+ default:
+ dev_err(&pdev->dev, "Unknown GPHY mode %d\n", gphy_mode);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int xway_gphy_probe(struct platform_device *pdev)
+{
+ struct xway_gphy_priv *priv;
+ dma_addr_t fw_addr = 0;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ ret = xway_gphy_of_probe(pdev, priv);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(priv->gphy_clk_gate);
+ if (ret)
+ return ret;
+
+ ret = xway_gphy_load(pdev, priv, &fw_addr);
+ if (ret)
+ return ret;
+
+ reset_control_assert(priv->gphy_reset);
+ reset_control_assert(priv->gphy_reset2);
+
+ ret = regmap_write(priv->regmap, priv->reg_offset, fw_addr);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to configure FW addr\n");
+ return ret;
+ }
+
+ reset_control_deassert(priv->gphy_reset);
+ reset_control_deassert(priv->gphy_reset2);
+
+ /* assert the gphy reset because it can hang after a reboot: */
+ priv->gphy_reboot_nb.notifier_call = xway_gphy_reboot_notify;
+ priv->gphy_reboot_nb.priority = -1;
+
+ ret = register_reboot_notifier(&priv->gphy_reboot_nb);
+ if (ret)
+ dev_warn(&pdev->dev, "Failed to register reboot notifier\n");
+
+ platform_set_drvdata(pdev, priv);
+
+ return ret;
+}
+
+static int xway_gphy_remove(struct platform_device *pdev)
+{
+ struct xway_gphy_priv *priv = platform_get_drvdata(pdev);
+ int ret;
+
+ reset_control_assert(priv->gphy_reset);
+ reset_control_assert(priv->gphy_reset2);
+
+ ret = regmap_write(priv->regmap, priv->reg_offset, 0);
+ if (ret)
+ dev_err(&pdev->dev, "Failed to configure FW addr\n");
+
+ clk_disable_unprepare(priv->gphy_clk_gate);
+
+ dma_free_coherent(&pdev->dev, priv->size, priv->fw_addr,
+ priv->dma_addr);
+
+ ret = unregister_reboot_notifier(&priv->gphy_reboot_nb);
+ if (ret)
+ dev_warn(&pdev->dev, "Failed to unregister reboot notifier\n");
+
+ return 0;
+}
+
+static struct platform_driver xway_gphy_driver = {
+ .probe = xway_gphy_probe,
+ .remove = xway_gphy_remove,
+ .driver = {
+ .name = "xway-rcu-gphy",
+ .of_match_table = xway_gphy_match,
+ },
+};
+
+module_platform_driver(xway_gphy_driver);
+
+MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin");
+MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin");
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
+MODULE_DESCRIPTION("Lantiq XWAY GPHY Firmware Loader");
+MODULE_LICENSE("GPL");
diff --git a/include/dt-bindings/mips/lantiq_rcu_gphy.h b/include/dt-bindings/mips/lantiq_rcu_gphy.h
new file mode 100644
index 000000000000..fa1a63773342
--- /dev/null
+++ b/include/dt-bindings/mips/lantiq_rcu_gphy.h
@@ -0,0 +1,15 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
+ */
+#ifndef _DT_BINDINGS_MIPS_LANTIQ_RCU_GPHY_H
+#define _DT_BINDINGS_MIPS_LANTIQ_RCU_GPHY_H
+
+#define GPHY_MODE_GE 1
+#define GPHY_MODE_FE 2
+
+#endif /* _DT_BINDINGS_MIPS_LANTIQ_RCU_GPHY_H */
--
2.11.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v3 13/16] MIPS: lantiq: remove old GPHY loader code
2017-05-28 18:39 ` Hauke Mehrtens
@ 2017-05-28 18:40 ` Hauke Mehrtens
-1 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:40 UTC (permalink / raw)
To: ralf-6z/3iImG2C8G8FEW9MqTrA
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w,
robh-DgEjT+Ai2ygdnm+yROfE0A,
andy.shevchenko-Re5JQEeQqe8AvxtiuMwx3w,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ, Hauke Mehrtens
The GPHY loader was replaced by a new more flexible driver. Remove the
old driver.
Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
arch/mips/lantiq/xway/Makefile | 2 -
arch/mips/lantiq/xway/reset.c | 106 -------------------------------
arch/mips/lantiq/xway/xrx200_phy_fw.c | 113 ----------------------------------
3 files changed, 221 deletions(-)
delete mode 100644 arch/mips/lantiq/xway/xrx200_phy_fw.c
diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
index a2edc538f477..6daf3149e7ca 100644
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
@@ -1,5 +1,3 @@
obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o
obj-y += vmmc.o
-
-obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index 5cb9309b0047..be5fd29de523 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -27,18 +27,6 @@
#define RCU_RST_REQ 0x0010
/* reset status register */
#define RCU_RST_STAT 0x0014
-/* vr9 gphy registers */
-#define RCU_GFS_ADD0_XRX200 0x0020
-#define RCU_GFS_ADD1_XRX200 0x0068
-/* xRX300 gphy registers */
-#define RCU_GFS_ADD0_XRX300 0x0020
-#define RCU_GFS_ADD1_XRX300 0x0058
-#define RCU_GFS_ADD2_XRX300 0x00AC
-/* xRX330 gphy registers */
-#define RCU_GFS_ADD0_XRX330 0x0020
-#define RCU_GFS_ADD1_XRX330 0x0058
-#define RCU_GFS_ADD2_XRX330 0x00AC
-#define RCU_GFS_ADD3_XRX330 0x0264
/* xbar BE flag */
#define RCU_AHB_ENDIAN 0x004C
@@ -48,15 +36,6 @@
#define RCU_RD_GPHY0_XRX200 BIT(31)
#define RCU_RD_SRST BIT(30)
#define RCU_RD_GPHY1_XRX200 BIT(29)
-/* xRX300 bits */
-#define RCU_RD_GPHY0_XRX300 BIT(31)
-#define RCU_RD_GPHY1_XRX300 BIT(29)
-#define RCU_RD_GPHY2_XRX300 BIT(28)
-/* xRX330 bits */
-#define RCU_RD_GPHY0_XRX330 BIT(31)
-#define RCU_RD_GPHY1_XRX330 BIT(29)
-#define RCU_RD_GPHY2_XRX330 BIT(28)
-#define RCU_RD_GPHY3_XRX330 BIT(10)
/* reset cause */
#define RCU_STAT_SHIFT 26
@@ -98,7 +77,6 @@
/* remapped base addr of the reset control unit */
static void __iomem *ltq_rcu_membase;
static struct device_node *ltq_rcu_np;
-static DEFINE_SPINLOCK(ltq_rcu_lock);
static void ltq_rcu_w32(uint32_t val, uint32_t reg_off)
{
@@ -110,90 +88,6 @@ static uint32_t ltq_rcu_r32(uint32_t reg_off)
return ltq_r32(ltq_rcu_membase + reg_off);
}
-static void ltq_rcu_w32_mask(uint32_t clr, uint32_t set, uint32_t reg_off)
-{
- unsigned long flags;
-
- spin_lock_irqsave(<q_rcu_lock, flags);
- ltq_rcu_w32((ltq_rcu_r32(reg_off) & ~(clr)) | (set), reg_off);
- spin_unlock_irqrestore(<q_rcu_lock, flags);
-}
-
-struct ltq_gphy_reset {
- u32 rd;
- u32 addr;
-};
-
-/* reset / boot a gphy */
-static struct ltq_gphy_reset xrx200_gphy[] = {
- {RCU_RD_GPHY0_XRX200, RCU_GFS_ADD0_XRX200},
- {RCU_RD_GPHY1_XRX200, RCU_GFS_ADD1_XRX200},
-};
-
-/* reset / boot a gphy */
-static struct ltq_gphy_reset xrx300_gphy[] = {
- {RCU_RD_GPHY0_XRX300, RCU_GFS_ADD0_XRX300},
- {RCU_RD_GPHY1_XRX300, RCU_GFS_ADD1_XRX300},
- {RCU_RD_GPHY2_XRX300, RCU_GFS_ADD2_XRX300},
-};
-
-/* reset / boot a gphy */
-static struct ltq_gphy_reset xrx330_gphy[] = {
- {RCU_RD_GPHY0_XRX330, RCU_GFS_ADD0_XRX330},
- {RCU_RD_GPHY1_XRX330, RCU_GFS_ADD1_XRX330},
- {RCU_RD_GPHY2_XRX330, RCU_GFS_ADD2_XRX330},
- {RCU_RD_GPHY3_XRX330, RCU_GFS_ADD3_XRX330},
-};
-
-static void xrx200_gphy_boot_addr(struct ltq_gphy_reset *phy_regs,
- dma_addr_t dev_addr)
-{
- ltq_rcu_w32_mask(0, phy_regs->rd, RCU_RST_REQ);
- ltq_rcu_w32(dev_addr, phy_regs->addr);
- ltq_rcu_w32_mask(phy_regs->rd, 0, RCU_RST_REQ);
-}
-
-/* reset and boot a gphy. these phys only exist on xrx200 SoC */
-int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr)
-{
- struct clk *clk;
-
- if (!of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200")) {
- dev_err(dev, "this SoC has no GPHY\n");
- return -EINVAL;
- }
-
- if (of_machine_is_compatible("lantiq,vr9")) {
- clk = clk_get_sys("1f203000.rcu", "gphy");
- if (IS_ERR(clk))
- return PTR_ERR(clk);
- clk_enable(clk);
- }
-
- dev_info(dev, "booting GPHY%u firmware at %X\n", id, dev_addr);
-
- if (of_machine_is_compatible("lantiq,vr9")) {
- if (id >= ARRAY_SIZE(xrx200_gphy)) {
- dev_err(dev, "%u is an invalid gphy id\n", id);
- return -EINVAL;
- }
- xrx200_gphy_boot_addr(&xrx200_gphy[id], dev_addr);
- } else if (of_machine_is_compatible("lantiq,ar10")) {
- if (id >= ARRAY_SIZE(xrx300_gphy)) {
- dev_err(dev, "%u is an invalid gphy id\n", id);
- return -EINVAL;
- }
- xrx200_gphy_boot_addr(&xrx300_gphy[id], dev_addr);
- } else if (of_machine_is_compatible("lantiq,grx390")) {
- if (id >= ARRAY_SIZE(xrx330_gphy)) {
- dev_err(dev, "%u is an invalid gphy id\n", id);
- return -EINVAL;
- }
- xrx200_gphy_boot_addr(&xrx330_gphy[id], dev_addr);
- }
- return 0;
-}
-
static void ltq_machine_restart(char *command)
{
u32 val = ltq_rcu_r32(RCU_RST_REQ);
diff --git a/arch/mips/lantiq/xway/xrx200_phy_fw.c b/arch/mips/lantiq/xway/xrx200_phy_fw.c
deleted file mode 100644
index f0a0f2d431b2..000000000000
--- a/arch/mips/lantiq/xway/xrx200_phy_fw.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * Lantiq XRX200 PHY Firmware Loader
- * Author: John Crispin
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- * Copyright (C) 2012 John Crispin <john-Pj+rj9U5foFAfugRpC6u6w@public.gmane.org>
- */
-
-#include <linux/delay.h>
-#include <linux/dma-mapping.h>
-#include <linux/firmware.h>
-#include <linux/of_platform.h>
-
-#include <lantiq_soc.h>
-
-#define XRX200_GPHY_FW_ALIGN (16 * 1024)
-
-static dma_addr_t xway_gphy_load(struct platform_device *pdev)
-{
- const struct firmware *fw;
- dma_addr_t dev_addr = 0;
- const char *fw_name;
- void *fw_addr;
- size_t size;
-
- if (of_get_property(pdev->dev.of_node, "firmware1", NULL) ||
- of_get_property(pdev->dev.of_node, "firmware2", NULL)) {
- switch (ltq_soc_type()) {
- case SOC_TYPE_VR9:
- if (of_property_read_string(pdev->dev.of_node,
- "firmware1", &fw_name)) {
- dev_err(&pdev->dev,
- "failed to load firmware filename\n");
- return 0;
- }
- break;
- case SOC_TYPE_VR9_2:
- if (of_property_read_string(pdev->dev.of_node,
- "firmware2", &fw_name)) {
- dev_err(&pdev->dev,
- "failed to load firmware filename\n");
- return 0;
- }
- break;
- }
- } else if (of_property_read_string(pdev->dev.of_node,
- "firmware", &fw_name)) {
- dev_err(&pdev->dev, "failed to load firmware filename\n");
- return 0;
- }
-
- dev_info(&pdev->dev, "requesting %s\n", fw_name);
- if (request_firmware(&fw, fw_name, &pdev->dev)) {
- dev_err(&pdev->dev, "failed to load firmware: %s\n", fw_name);
- return 0;
- }
-
- /*
- * GPHY cores need the firmware code in a persistent and contiguous
- * memory area with a 16 kB boundary aligned start address
- */
- size = fw->size + XRX200_GPHY_FW_ALIGN;
-
- fw_addr = dma_alloc_coherent(&pdev->dev, size, &dev_addr, GFP_KERNEL);
- if (fw_addr) {
- fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN);
- dev_addr = ALIGN(dev_addr, XRX200_GPHY_FW_ALIGN);
- memcpy(fw_addr, fw->data, fw->size);
- } else {
- dev_err(&pdev->dev, "failed to alloc firmware memory\n");
- }
-
- release_firmware(fw);
- return dev_addr;
-}
-
-static int xway_phy_fw_probe(struct platform_device *pdev)
-{
- dma_addr_t fw_addr;
- struct property *pp;
- unsigned char *phyids;
- int i, ret = 0;
-
- fw_addr = xway_gphy_load(pdev);
- if (!fw_addr)
- return -EINVAL;
- pp = of_find_property(pdev->dev.of_node, "phys", NULL);
- if (!pp)
- return -ENOENT;
- phyids = pp->value;
- for (i = 0; i < pp->length && !ret; i++)
- ret = xrx200_gphy_boot(&pdev->dev, phyids[i], fw_addr);
- if (!ret)
- mdelay(100);
- return ret;
-}
-
-static const struct of_device_id xway_phy_match[] = {
- { .compatible = "lantiq,phy-xrx200" },
- {},
-};
-
-static struct platform_driver xway_phy_driver = {
- .probe = xway_phy_fw_probe,
- .driver = {
- .name = "phy-xrx200",
- .of_match_table = xway_phy_match,
- },
-};
-builtin_platform_driver(xway_phy_driver);
--
2.11.0
--
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^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v3 13/16] MIPS: lantiq: remove old GPHY loader code
@ 2017-05-28 18:40 ` Hauke Mehrtens
0 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:40 UTC (permalink / raw)
To: ralf
Cc: linux-mips, linux-mtd, linux-watchdog, devicetree,
martin.blumenstingl, john, linux-spi, hauke.mehrtens, robh,
andy.shevchenko, p.zabel, Hauke Mehrtens
The GPHY loader was replaced by a new more flexible driver. Remove the
old driver.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
arch/mips/lantiq/xway/Makefile | 2 -
arch/mips/lantiq/xway/reset.c | 106 -------------------------------
arch/mips/lantiq/xway/xrx200_phy_fw.c | 113 ----------------------------------
3 files changed, 221 deletions(-)
delete mode 100644 arch/mips/lantiq/xway/xrx200_phy_fw.c
diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
index a2edc538f477..6daf3149e7ca 100644
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
@@ -1,5 +1,3 @@
obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o
obj-y += vmmc.o
-
-obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index 5cb9309b0047..be5fd29de523 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -27,18 +27,6 @@
#define RCU_RST_REQ 0x0010
/* reset status register */
#define RCU_RST_STAT 0x0014
-/* vr9 gphy registers */
-#define RCU_GFS_ADD0_XRX200 0x0020
-#define RCU_GFS_ADD1_XRX200 0x0068
-/* xRX300 gphy registers */
-#define RCU_GFS_ADD0_XRX300 0x0020
-#define RCU_GFS_ADD1_XRX300 0x0058
-#define RCU_GFS_ADD2_XRX300 0x00AC
-/* xRX330 gphy registers */
-#define RCU_GFS_ADD0_XRX330 0x0020
-#define RCU_GFS_ADD1_XRX330 0x0058
-#define RCU_GFS_ADD2_XRX330 0x00AC
-#define RCU_GFS_ADD3_XRX330 0x0264
/* xbar BE flag */
#define RCU_AHB_ENDIAN 0x004C
@@ -48,15 +36,6 @@
#define RCU_RD_GPHY0_XRX200 BIT(31)
#define RCU_RD_SRST BIT(30)
#define RCU_RD_GPHY1_XRX200 BIT(29)
-/* xRX300 bits */
-#define RCU_RD_GPHY0_XRX300 BIT(31)
-#define RCU_RD_GPHY1_XRX300 BIT(29)
-#define RCU_RD_GPHY2_XRX300 BIT(28)
-/* xRX330 bits */
-#define RCU_RD_GPHY0_XRX330 BIT(31)
-#define RCU_RD_GPHY1_XRX330 BIT(29)
-#define RCU_RD_GPHY2_XRX330 BIT(28)
-#define RCU_RD_GPHY3_XRX330 BIT(10)
/* reset cause */
#define RCU_STAT_SHIFT 26
@@ -98,7 +77,6 @@
/* remapped base addr of the reset control unit */
static void __iomem *ltq_rcu_membase;
static struct device_node *ltq_rcu_np;
-static DEFINE_SPINLOCK(ltq_rcu_lock);
static void ltq_rcu_w32(uint32_t val, uint32_t reg_off)
{
@@ -110,90 +88,6 @@ static uint32_t ltq_rcu_r32(uint32_t reg_off)
return ltq_r32(ltq_rcu_membase + reg_off);
}
-static void ltq_rcu_w32_mask(uint32_t clr, uint32_t set, uint32_t reg_off)
-{
- unsigned long flags;
-
- spin_lock_irqsave(<q_rcu_lock, flags);
- ltq_rcu_w32((ltq_rcu_r32(reg_off) & ~(clr)) | (set), reg_off);
- spin_unlock_irqrestore(<q_rcu_lock, flags);
-}
-
-struct ltq_gphy_reset {
- u32 rd;
- u32 addr;
-};
-
-/* reset / boot a gphy */
-static struct ltq_gphy_reset xrx200_gphy[] = {
- {RCU_RD_GPHY0_XRX200, RCU_GFS_ADD0_XRX200},
- {RCU_RD_GPHY1_XRX200, RCU_GFS_ADD1_XRX200},
-};
-
-/* reset / boot a gphy */
-static struct ltq_gphy_reset xrx300_gphy[] = {
- {RCU_RD_GPHY0_XRX300, RCU_GFS_ADD0_XRX300},
- {RCU_RD_GPHY1_XRX300, RCU_GFS_ADD1_XRX300},
- {RCU_RD_GPHY2_XRX300, RCU_GFS_ADD2_XRX300},
-};
-
-/* reset / boot a gphy */
-static struct ltq_gphy_reset xrx330_gphy[] = {
- {RCU_RD_GPHY0_XRX330, RCU_GFS_ADD0_XRX330},
- {RCU_RD_GPHY1_XRX330, RCU_GFS_ADD1_XRX330},
- {RCU_RD_GPHY2_XRX330, RCU_GFS_ADD2_XRX330},
- {RCU_RD_GPHY3_XRX330, RCU_GFS_ADD3_XRX330},
-};
-
-static void xrx200_gphy_boot_addr(struct ltq_gphy_reset *phy_regs,
- dma_addr_t dev_addr)
-{
- ltq_rcu_w32_mask(0, phy_regs->rd, RCU_RST_REQ);
- ltq_rcu_w32(dev_addr, phy_regs->addr);
- ltq_rcu_w32_mask(phy_regs->rd, 0, RCU_RST_REQ);
-}
-
-/* reset and boot a gphy. these phys only exist on xrx200 SoC */
-int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr)
-{
- struct clk *clk;
-
- if (!of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200")) {
- dev_err(dev, "this SoC has no GPHY\n");
- return -EINVAL;
- }
-
- if (of_machine_is_compatible("lantiq,vr9")) {
- clk = clk_get_sys("1f203000.rcu", "gphy");
- if (IS_ERR(clk))
- return PTR_ERR(clk);
- clk_enable(clk);
- }
-
- dev_info(dev, "booting GPHY%u firmware at %X\n", id, dev_addr);
-
- if (of_machine_is_compatible("lantiq,vr9")) {
- if (id >= ARRAY_SIZE(xrx200_gphy)) {
- dev_err(dev, "%u is an invalid gphy id\n", id);
- return -EINVAL;
- }
- xrx200_gphy_boot_addr(&xrx200_gphy[id], dev_addr);
- } else if (of_machine_is_compatible("lantiq,ar10")) {
- if (id >= ARRAY_SIZE(xrx300_gphy)) {
- dev_err(dev, "%u is an invalid gphy id\n", id);
- return -EINVAL;
- }
- xrx200_gphy_boot_addr(&xrx300_gphy[id], dev_addr);
- } else if (of_machine_is_compatible("lantiq,grx390")) {
- if (id >= ARRAY_SIZE(xrx330_gphy)) {
- dev_err(dev, "%u is an invalid gphy id\n", id);
- return -EINVAL;
- }
- xrx200_gphy_boot_addr(&xrx330_gphy[id], dev_addr);
- }
- return 0;
-}
-
static void ltq_machine_restart(char *command)
{
u32 val = ltq_rcu_r32(RCU_RST_REQ);
diff --git a/arch/mips/lantiq/xway/xrx200_phy_fw.c b/arch/mips/lantiq/xway/xrx200_phy_fw.c
deleted file mode 100644
index f0a0f2d431b2..000000000000
--- a/arch/mips/lantiq/xway/xrx200_phy_fw.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * Lantiq XRX200 PHY Firmware Loader
- * Author: John Crispin
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- * Copyright (C) 2012 John Crispin <john@phrozen.org>
- */
-
-#include <linux/delay.h>
-#include <linux/dma-mapping.h>
-#include <linux/firmware.h>
-#include <linux/of_platform.h>
-
-#include <lantiq_soc.h>
-
-#define XRX200_GPHY_FW_ALIGN (16 * 1024)
-
-static dma_addr_t xway_gphy_load(struct platform_device *pdev)
-{
- const struct firmware *fw;
- dma_addr_t dev_addr = 0;
- const char *fw_name;
- void *fw_addr;
- size_t size;
-
- if (of_get_property(pdev->dev.of_node, "firmware1", NULL) ||
- of_get_property(pdev->dev.of_node, "firmware2", NULL)) {
- switch (ltq_soc_type()) {
- case SOC_TYPE_VR9:
- if (of_property_read_string(pdev->dev.of_node,
- "firmware1", &fw_name)) {
- dev_err(&pdev->dev,
- "failed to load firmware filename\n");
- return 0;
- }
- break;
- case SOC_TYPE_VR9_2:
- if (of_property_read_string(pdev->dev.of_node,
- "firmware2", &fw_name)) {
- dev_err(&pdev->dev,
- "failed to load firmware filename\n");
- return 0;
- }
- break;
- }
- } else if (of_property_read_string(pdev->dev.of_node,
- "firmware", &fw_name)) {
- dev_err(&pdev->dev, "failed to load firmware filename\n");
- return 0;
- }
-
- dev_info(&pdev->dev, "requesting %s\n", fw_name);
- if (request_firmware(&fw, fw_name, &pdev->dev)) {
- dev_err(&pdev->dev, "failed to load firmware: %s\n", fw_name);
- return 0;
- }
-
- /*
- * GPHY cores need the firmware code in a persistent and contiguous
- * memory area with a 16 kB boundary aligned start address
- */
- size = fw->size + XRX200_GPHY_FW_ALIGN;
-
- fw_addr = dma_alloc_coherent(&pdev->dev, size, &dev_addr, GFP_KERNEL);
- if (fw_addr) {
- fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN);
- dev_addr = ALIGN(dev_addr, XRX200_GPHY_FW_ALIGN);
- memcpy(fw_addr, fw->data, fw->size);
- } else {
- dev_err(&pdev->dev, "failed to alloc firmware memory\n");
- }
-
- release_firmware(fw);
- return dev_addr;
-}
-
-static int xway_phy_fw_probe(struct platform_device *pdev)
-{
- dma_addr_t fw_addr;
- struct property *pp;
- unsigned char *phyids;
- int i, ret = 0;
-
- fw_addr = xway_gphy_load(pdev);
- if (!fw_addr)
- return -EINVAL;
- pp = of_find_property(pdev->dev.of_node, "phys", NULL);
- if (!pp)
- return -ENOENT;
- phyids = pp->value;
- for (i = 0; i < pp->length && !ret; i++)
- ret = xrx200_gphy_boot(&pdev->dev, phyids[i], fw_addr);
- if (!ret)
- mdelay(100);
- return ret;
-}
-
-static const struct of_device_id xway_phy_match[] = {
- { .compatible = "lantiq,phy-xrx200" },
- {},
-};
-
-static struct platform_driver xway_phy_driver = {
- .probe = xway_phy_fw_probe,
- .driver = {
- .name = "phy-xrx200",
- .of_match_table = xway_phy_match,
- },
-};
-builtin_platform_driver(xway_phy_driver);
--
2.11.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v3 14/16] phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module
2017-05-28 18:39 ` Hauke Mehrtens
@ 2017-05-28 18:40 ` Hauke Mehrtens
-1 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:40 UTC (permalink / raw)
To: ralf-6z/3iImG2C8G8FEW9MqTrA
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w,
robh-DgEjT+Ai2ygdnm+yROfE0A,
andy.shevchenko-Re5JQEeQqe8AvxtiuMwx3w,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ, Hauke Mehrtens,
Kishon Vijay Abraham I
From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
This driver starts the DWC2 core(s) built into the XWAY SoCs and provides
the PHY interfaces for each core. The phy instances can be passed to the
dwc2 driver, which already supports the generic phy interface.
Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
Cc: Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>
---
.../bindings/phy/phy-lantiq-rcu-usb2.txt | 42 ++++
arch/mips/lantiq/xway/sysctrl.c | 24 +-
drivers/phy/Kconfig | 8 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-lantiq-rcu-usb2.c | 275 +++++++++++++++++++++
5 files changed, 338 insertions(+), 12 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
create mode 100644 drivers/phy/phy-lantiq-rcu-usb2.c
diff --git a/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
new file mode 100644
index 000000000000..7bdde5051c2d
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
@@ -0,0 +1,42 @@
+Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding
+===========================================
+
+This binding describes the USB PHY hardware provided by the RCU module on the
+Lantiq XWAY SoCs.
+
+
+-------------------------------------------------------------------------------
+Required properties (controller (parent) node):
+- compatible : Should be one of
+ "lantiq,ase-rcu-usb2-phy"
+ "lantiq,danube-rcu-usb2-phy"
+ "lantiq,xrx100-rcu-usb2-phy"
+ "lantiq,xrx200-rcu-usb2-phy"
+ "lantiq,xrx300-rcu-usb2-phy"
+- regmap : A phandle to the RCU module
+- offset-phy : Offset of the USB PHY configuration register
+- offset-ana : Offset of the USB Analog configuration register
+- clocks : References to the (PMU) "ctrl" and "phy" clk gates.
+- clock-names : Must be one of the following:
+ "ctrl"
+ "phy"
+- resets : References to the RCU USB configuration reset bits.
+- reset-names : Must be one of the following:
+ "phy" (optional)
+ "ctrl" (shared)
+
+-------------------------------------------------------------------------------
+Example for the USB PHYs on an xRX200 SoC:
+ usb_phy0: usb2-phy@0 {
+ compatible = "lantiq,xrx200-rcu-usb2-phy";
+
+ regmap = <&rcu0>;
+ offset-phy = <0x18>;
+ offset-ana = <0x38>;
+ clocks = <&pmu PMU_GATE_USB0_CTRL>,
+ <&pmu PMU_GATE_USB0_PHY>;
+ clock-names = "ctrl", "phy";
+ resets = <&reset1 4 4>, <&reset0 4 4>;
+ reset-names = "phy", "ctrl";
+ #phy-cells = <0>;
+ };
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 0789c48ef779..4f45bef613f7 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -469,8 +469,8 @@ void __init ltq_soc_init(void)
if (of_machine_is_compatible("lantiq,grx390") ||
of_machine_is_compatible("lantiq,ar10")) {
- clkdev_add_pmu("1e101000.usb", "phy", 1, 2, PMU_ANALOG_USB0_P);
- clkdev_add_pmu("1e106000.usb", "phy", 1, 2, PMU_ANALOG_USB1_P);
+ clkdev_add_pmu("1f203000.rcu:usb2-phy@0", "phy", 1, 2, PMU_ANALOG_USB0_P);
+ clkdev_add_pmu("1f203000.rcu:usb2-phy@1", "phy", 1, 2, PMU_ANALOG_USB1_P);
/* rc 0 */
clkdev_add_pmu("1d900000.pcie", "phy", 1, 2, PMU_ANALOG_PCIE0_P);
clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
@@ -490,8 +490,8 @@ void __init ltq_soc_init(void)
else
clkdev_add_static(CLOCK_133M, CLOCK_133M,
CLOCK_133M, CLOCK_133M);
- clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
- clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
+ clkdev_add_pmu("1f203000.rcu:usb2-phy@0", "ctrl", 1, 0, PMU_USB0);
+ clkdev_add_pmu("1f203000.rcu:usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
clkdev_add_pmu("1e180000.etop", "ppe", 1, 0, PMU_PPE);
clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY);
clkdev_add_pmu("1e180000.etop", "ephy", 1, 0, PMU_EPHY);
@@ -526,10 +526,10 @@ void __init ltq_soc_init(void)
} else if (of_machine_is_compatible("lantiq,vr9")) {
clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
- clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
- clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0 | PMU_AHBM);
- clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);
- clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1 | PMU_AHBM);
+ clkdev_add_pmu("1f203000.rcu:usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
+ clkdev_add_pmu("1f203000.rcu:usb2-phy@0", "ctrl", 1, 0, PMU_USB0 | PMU_AHBM);
+ clkdev_add_pmu("1f203000.rcu:usb2-phy@1", "phy", 1, 0, PMU_USB1_P);
+ clkdev_add_pmu("1f203000.rcu:usb2-phy@1", "ctrl", 1, 0, PMU_USB1 | PMU_AHBM);
clkdev_add_pmu("1d900000.pcie", "phy", 1, 1, PMU1_PCIE_PHY);
clkdev_add_pmu("1d900000.pcie", "bus", 1, 0, PMU_PCIE_CLK);
clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
@@ -550,8 +550,8 @@ void __init ltq_soc_init(void)
} else if (of_machine_is_compatible("lantiq,ar9")) {
clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
ltq_ar9_fpi_hz(), CLOCK_250M);
- clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
- clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
+ clkdev_add_pmu("1f203000.rcu:usb2-phy@0", "ctrl", 1, 0, PMU_USB0);
+ clkdev_add_pmu("1f203000.rcu:usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1);
clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);
clkdev_add_pmu("1e180000.etop", "switch", 1, 0, PMU_SWITCH);
@@ -562,8 +562,8 @@ void __init ltq_soc_init(void)
} else {
clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
- clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
- clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
+ clkdev_add_pmu("1f203000.rcu:usb2-phy@0", "ctrl", 1, 0, PMU_USB0);
+ clkdev_add_pmu("1f203000.rcu:usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index afaf7b643eeb..f7f6bfca20fc 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -507,6 +507,14 @@ config PHY_CYGNUS_PCIE
Enable this to support the Broadcom Cygnus PCIe PHY.
If unsure, say N.
+config PHY_LANTIQ_RCU_USB2
+ tristate "Lantiq XWAY SoC RCU based USB PHY"
+ depends on SOC_TYPE_XWAY
+ depends on OF
+ select GENERIC_PHY
+ help
+ Support for the USB PHY(s) on the Lantiq XWAY family SoCs.
+
source "drivers/phy/tegra/Kconfig"
config PHY_NS2_PCIE
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index f8047b4639fa..d6ba19233001 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -61,6 +61,7 @@ obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o
obj-$(CONFIG_PHY_BRCM_SATA) += phy-brcm-sata.o
obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o
+obj-$(CONFIG_PHY_LANTIQ_RCU_USB2) += phy-lantiq-rcu-usb2.o
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o
obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o
diff --git a/drivers/phy/phy-lantiq-rcu-usb2.c b/drivers/phy/phy-lantiq-rcu-usb2.c
new file mode 100644
index 000000000000..d7a456403f8f
--- /dev/null
+++ b/drivers/phy/phy-lantiq-rcu-usb2.c
@@ -0,0 +1,275 @@
+/*
+ * Lantiq XWAY SoC RCU module based USB 1.1/2.0 PHY driver
+ *
+ * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
+ * Copyright (C) 2017 Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+/* Transmitter HS Pre-Emphasis Enable */
+#define RCU_CFG1_TX_PEE BIT(0)
+/* Disconnect Threshold */
+#define RCU_CFG1_DIS_THR_MASK 0x00038000
+#define RCU_CFG1_DIS_THR_SHIFT 15
+
+struct ltq_rcu_usb2_bits {
+ u8 hostmode;
+ u8 slave_endianness;
+ u8 host_endianness;
+ bool have_ana_cfg;
+};
+
+struct ltq_rcu_usb2_priv {
+ struct regmap *regmap;
+ u32 phy_reg_offset;
+ u32 ana_cfg1_reg_offset;
+ const struct ltq_rcu_usb2_bits *reg_bits;
+ struct device *dev;
+ struct phy *phy;
+ struct clk *ctrl_gate_clk;
+ struct clk *phy_gate_clk;
+ struct reset_control *ctrl_reset;
+ struct reset_control *phy_reset;
+};
+
+static const struct ltq_rcu_usb2_bits xway_rcu_usb2_reg_bits = {
+ .hostmode = 11,
+ .slave_endianness = 9,
+ .host_endianness = 10,
+ .have_ana_cfg = false,
+};
+
+static const struct ltq_rcu_usb2_bits xrx100_rcu_usb2_reg_bits = {
+ .hostmode = 11,
+ .slave_endianness = 17,
+ .host_endianness = 10,
+ .have_ana_cfg = false,
+};
+
+static const struct ltq_rcu_usb2_bits xrx200_rcu_usb2_reg_bits = {
+ .hostmode = 11,
+ .slave_endianness = 9,
+ .host_endianness = 10,
+ .have_ana_cfg = true,
+};
+
+static const struct of_device_id ltq_rcu_usb2_phy_of_match[] = {
+ {
+ .compatible = "lantiq,ase-rcu-usb2-phy",
+ .data = &xway_rcu_usb2_reg_bits,
+ },
+ {
+ .compatible = "lantiq,danube-rcu-usb2-phy",
+ .data = &xway_rcu_usb2_reg_bits,
+ },
+ {
+ .compatible = "lantiq,xrx100-rcu-usb2-phy",
+ .data = &xrx100_rcu_usb2_reg_bits,
+ },
+ {
+ .compatible = "lantiq,xrx200-rcu-usb2-phy",
+ .data = &xrx200_rcu_usb2_reg_bits,
+ },
+ {
+ .compatible = "lantiq,xrx300-rcu-usb2-phy",
+ .data = &xrx200_rcu_usb2_reg_bits,
+ },
+ { },
+};
+MODULE_DEVICE_TABLE(of, ltq_rcu_usb2_phy_of_match);
+
+
+static int ltq_rcu_usb2_phy_power_on(struct phy *phy)
+{
+ struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy);
+
+ reset_control_deassert(priv->phy_reset);
+
+ return 0;
+}
+
+static int ltq_rcu_usb2_phy_power_off(struct phy *phy)
+{
+ struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy);
+
+ reset_control_assert(priv->phy_reset);
+
+ return 0;
+}
+
+static struct phy_ops ltq_rcu_usb2_phy_ops = {
+ .power_on = ltq_rcu_usb2_phy_power_on,
+ .power_off = ltq_rcu_usb2_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static void ltq_rcu_usb2_start_cores(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct ltq_rcu_usb2_priv *priv = dev_get_drvdata(dev);
+
+ /* Power on the USB core. */
+ if (clk_prepare_enable(priv->ctrl_gate_clk)) {
+ dev_err(dev, "failed to enable CTRL gate\n");
+ return;
+ }
+
+ /*
+ * Power on the USB PHY. We have to do it early because
+ * otherwise the second core won't turn on properly.
+ */
+ if (clk_prepare_enable(priv->phy_gate_clk)) {
+ dev_err(dev, "failed to enable PHY gate\n");
+ return;
+ }
+
+ if (priv->reg_bits->have_ana_cfg) {
+ regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset,
+ RCU_CFG1_TX_PEE, RCU_CFG1_TX_PEE);
+ regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset,
+ RCU_CFG1_DIS_THR_MASK, 7 << RCU_CFG1_DIS_THR_SHIFT);
+ }
+
+ /* Configure core to host mode */
+ regmap_update_bits(priv->regmap, priv->phy_reg_offset,
+ BIT(priv->reg_bits->hostmode), 0);
+
+ /* Select DMA endianness (Host-endian: big-endian) */
+ regmap_update_bits(priv->regmap, priv->phy_reg_offset,
+ BIT(priv->reg_bits->slave_endianness), 0);
+ regmap_update_bits(priv->regmap, priv->phy_reg_offset,
+ BIT(priv->reg_bits->host_endianness),
+ BIT(priv->reg_bits->host_endianness));
+
+ /* Reset USB core throgh reset controller */
+ reset_control_deassert(priv->ctrl_reset);
+
+ reset_control_assert(priv->phy_reset);
+}
+
+static int ltq_rcu_usb2_of_probe(struct device_node *phynode,
+ struct ltq_rcu_usb2_priv *priv)
+{
+ struct device *dev = priv->dev;
+ const struct of_device_id *match =
+ of_match_node(ltq_rcu_usb2_phy_of_match, phynode);
+ int ret;
+
+ if (!match) {
+ dev_err(dev, "Not a compatible Lantiq RCU USB PHY\n");
+ return -EINVAL;
+ }
+
+ priv->reg_bits = match->data;
+
+ priv->regmap = syscon_regmap_lookup_by_phandle(phynode, "regmap");
+ if (IS_ERR(priv->regmap)) {
+ dev_err(dev, "Failed to lookup RCU regmap\n");
+ return PTR_ERR(priv->regmap);
+ }
+
+ priv->ctrl_gate_clk = devm_clk_get(dev, "ctrl");
+ if (IS_ERR(priv->ctrl_gate_clk)) {
+ dev_err(dev, "Unable to get USB ctrl gate clk\n");
+ return PTR_ERR(priv->ctrl_gate_clk);
+ }
+
+ priv->phy_gate_clk = devm_clk_get(dev, "phy");
+ if (IS_ERR(priv->phy_gate_clk)) {
+ dev_err(dev, "Unable to get USB phy gate clk\n");
+ return PTR_ERR(priv->phy_gate_clk);
+ }
+
+ priv->ctrl_reset = devm_reset_control_get_shared(dev, "ctrl");
+ if (IS_ERR(priv->ctrl_reset)) {
+ if (PTR_ERR(priv->ctrl_reset) != -EPROBE_DEFER)
+ dev_err(dev, "failed to get 'ctrl' reset\n");
+ return PTR_ERR(priv->ctrl_reset);
+ }
+
+ priv->phy_reset = devm_reset_control_get_optional(dev, "phy");
+ if (IS_ERR(priv->phy_reset))
+ return PTR_ERR(priv->phy_reset);
+
+ ret = device_property_read_u32(dev, "offset-phy",
+ &priv->phy_reg_offset);
+ if (ret) {
+ dev_err(dev, "Failed to get RCU PHY reg offset\n");
+ return ret;
+ }
+
+ if (priv->reg_bits->have_ana_cfg) {
+ ret = device_property_read_u32(dev, "offset-ana",
+ &priv->ana_cfg1_reg_offset);
+ if (ret) {
+ dev_dbg(dev, "Failed to get RCU ANA CFG1 reg offset\n");
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int ltq_rcu_usb2_phy_probe(struct platform_device *pdev)
+{
+ struct device_node *child, *np = pdev->dev.of_node;
+ struct ltq_rcu_usb2_priv *priv;
+ struct phy_provider *provider;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = &pdev->dev;
+ dev_set_drvdata(priv->dev, priv);
+
+ ret = ltq_rcu_usb2_of_probe(np, priv);
+ if (ret)
+ return ret;
+
+ priv->phy = devm_phy_create(&pdev->dev, child,
+ <q_rcu_usb2_phy_ops);
+ if (IS_ERR(priv->phy)) {
+ dev_err(&pdev->dev, "failed to create PHY\n");
+ return PTR_ERR(priv->phy);
+ }
+
+ phy_set_drvdata(priv->phy, priv);
+
+ ltq_rcu_usb2_start_cores(pdev);
+
+ provider = devm_of_phy_provider_register(&pdev->dev,
+ of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(provider);
+}
+
+static struct platform_driver ltq_rcu_usb2_phy_driver = {
+ .probe = ltq_rcu_usb2_phy_probe,
+ .driver = {
+ .name = "lantiq-rcu-usb2-phy",
+ .of_match_table = ltq_rcu_usb2_phy_of_match,
+ }
+};
+module_platform_driver(ltq_rcu_usb2_phy_driver);
+
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>");
+MODULE_DESCRIPTION("Lantiq XWAY USB2 PHY driver");
+MODULE_LICENSE("GPL v2");
--
2.11.0
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^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v3 14/16] phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module
@ 2017-05-28 18:40 ` Hauke Mehrtens
0 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:40 UTC (permalink / raw)
To: ralf
Cc: linux-mips, linux-mtd, linux-watchdog, devicetree,
martin.blumenstingl, john, linux-spi, hauke.mehrtens, robh,
andy.shevchenko, p.zabel, Hauke Mehrtens, Kishon Vijay Abraham I
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
This driver starts the DWC2 core(s) built into the XWAY SoCs and provides
the PHY interfaces for each core. The phy instances can be passed to the
dwc2 driver, which already supports the generic phy interface.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
---
.../bindings/phy/phy-lantiq-rcu-usb2.txt | 42 ++++
arch/mips/lantiq/xway/sysctrl.c | 24 +-
drivers/phy/Kconfig | 8 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-lantiq-rcu-usb2.c | 275 +++++++++++++++++++++
5 files changed, 338 insertions(+), 12 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
create mode 100644 drivers/phy/phy-lantiq-rcu-usb2.c
diff --git a/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
new file mode 100644
index 000000000000..7bdde5051c2d
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
@@ -0,0 +1,42 @@
+Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding
+===========================================
+
+This binding describes the USB PHY hardware provided by the RCU module on the
+Lantiq XWAY SoCs.
+
+
+-------------------------------------------------------------------------------
+Required properties (controller (parent) node):
+- compatible : Should be one of
+ "lantiq,ase-rcu-usb2-phy"
+ "lantiq,danube-rcu-usb2-phy"
+ "lantiq,xrx100-rcu-usb2-phy"
+ "lantiq,xrx200-rcu-usb2-phy"
+ "lantiq,xrx300-rcu-usb2-phy"
+- regmap : A phandle to the RCU module
+- offset-phy : Offset of the USB PHY configuration register
+- offset-ana : Offset of the USB Analog configuration register
+- clocks : References to the (PMU) "ctrl" and "phy" clk gates.
+- clock-names : Must be one of the following:
+ "ctrl"
+ "phy"
+- resets : References to the RCU USB configuration reset bits.
+- reset-names : Must be one of the following:
+ "phy" (optional)
+ "ctrl" (shared)
+
+-------------------------------------------------------------------------------
+Example for the USB PHYs on an xRX200 SoC:
+ usb_phy0: usb2-phy@0 {
+ compatible = "lantiq,xrx200-rcu-usb2-phy";
+
+ regmap = <&rcu0>;
+ offset-phy = <0x18>;
+ offset-ana = <0x38>;
+ clocks = <&pmu PMU_GATE_USB0_CTRL>,
+ <&pmu PMU_GATE_USB0_PHY>;
+ clock-names = "ctrl", "phy";
+ resets = <&reset1 4 4>, <&reset0 4 4>;
+ reset-names = "phy", "ctrl";
+ #phy-cells = <0>;
+ };
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 0789c48ef779..4f45bef613f7 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -469,8 +469,8 @@ void __init ltq_soc_init(void)
if (of_machine_is_compatible("lantiq,grx390") ||
of_machine_is_compatible("lantiq,ar10")) {
- clkdev_add_pmu("1e101000.usb", "phy", 1, 2, PMU_ANALOG_USB0_P);
- clkdev_add_pmu("1e106000.usb", "phy", 1, 2, PMU_ANALOG_USB1_P);
+ clkdev_add_pmu("1f203000.rcu:usb2-phy@0", "phy", 1, 2, PMU_ANALOG_USB0_P);
+ clkdev_add_pmu("1f203000.rcu:usb2-phy@1", "phy", 1, 2, PMU_ANALOG_USB1_P);
/* rc 0 */
clkdev_add_pmu("1d900000.pcie", "phy", 1, 2, PMU_ANALOG_PCIE0_P);
clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
@@ -490,8 +490,8 @@ void __init ltq_soc_init(void)
else
clkdev_add_static(CLOCK_133M, CLOCK_133M,
CLOCK_133M, CLOCK_133M);
- clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
- clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
+ clkdev_add_pmu("1f203000.rcu:usb2-phy@0", "ctrl", 1, 0, PMU_USB0);
+ clkdev_add_pmu("1f203000.rcu:usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
clkdev_add_pmu("1e180000.etop", "ppe", 1, 0, PMU_PPE);
clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY);
clkdev_add_pmu("1e180000.etop", "ephy", 1, 0, PMU_EPHY);
@@ -526,10 +526,10 @@ void __init ltq_soc_init(void)
} else if (of_machine_is_compatible("lantiq,vr9")) {
clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
- clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
- clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0 | PMU_AHBM);
- clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);
- clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1 | PMU_AHBM);
+ clkdev_add_pmu("1f203000.rcu:usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
+ clkdev_add_pmu("1f203000.rcu:usb2-phy@0", "ctrl", 1, 0, PMU_USB0 | PMU_AHBM);
+ clkdev_add_pmu("1f203000.rcu:usb2-phy@1", "phy", 1, 0, PMU_USB1_P);
+ clkdev_add_pmu("1f203000.rcu:usb2-phy@1", "ctrl", 1, 0, PMU_USB1 | PMU_AHBM);
clkdev_add_pmu("1d900000.pcie", "phy", 1, 1, PMU1_PCIE_PHY);
clkdev_add_pmu("1d900000.pcie", "bus", 1, 0, PMU_PCIE_CLK);
clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
@@ -550,8 +550,8 @@ void __init ltq_soc_init(void)
} else if (of_machine_is_compatible("lantiq,ar9")) {
clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
ltq_ar9_fpi_hz(), CLOCK_250M);
- clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
- clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
+ clkdev_add_pmu("1f203000.rcu:usb2-phy@0", "ctrl", 1, 0, PMU_USB0);
+ clkdev_add_pmu("1f203000.rcu:usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1);
clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);
clkdev_add_pmu("1e180000.etop", "switch", 1, 0, PMU_SWITCH);
@@ -562,8 +562,8 @@ void __init ltq_soc_init(void)
} else {
clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
- clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
- clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
+ clkdev_add_pmu("1f203000.rcu:usb2-phy@0", "ctrl", 1, 0, PMU_USB0);
+ clkdev_add_pmu("1f203000.rcu:usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index afaf7b643eeb..f7f6bfca20fc 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -507,6 +507,14 @@ config PHY_CYGNUS_PCIE
Enable this to support the Broadcom Cygnus PCIe PHY.
If unsure, say N.
+config PHY_LANTIQ_RCU_USB2
+ tristate "Lantiq XWAY SoC RCU based USB PHY"
+ depends on SOC_TYPE_XWAY
+ depends on OF
+ select GENERIC_PHY
+ help
+ Support for the USB PHY(s) on the Lantiq XWAY family SoCs.
+
source "drivers/phy/tegra/Kconfig"
config PHY_NS2_PCIE
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index f8047b4639fa..d6ba19233001 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -61,6 +61,7 @@ obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o
obj-$(CONFIG_PHY_BRCM_SATA) += phy-brcm-sata.o
obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o
+obj-$(CONFIG_PHY_LANTIQ_RCU_USB2) += phy-lantiq-rcu-usb2.o
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o
obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o
diff --git a/drivers/phy/phy-lantiq-rcu-usb2.c b/drivers/phy/phy-lantiq-rcu-usb2.c
new file mode 100644
index 000000000000..d7a456403f8f
--- /dev/null
+++ b/drivers/phy/phy-lantiq-rcu-usb2.c
@@ -0,0 +1,275 @@
+/*
+ * Lantiq XWAY SoC RCU module based USB 1.1/2.0 PHY driver
+ *
+ * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+/* Transmitter HS Pre-Emphasis Enable */
+#define RCU_CFG1_TX_PEE BIT(0)
+/* Disconnect Threshold */
+#define RCU_CFG1_DIS_THR_MASK 0x00038000
+#define RCU_CFG1_DIS_THR_SHIFT 15
+
+struct ltq_rcu_usb2_bits {
+ u8 hostmode;
+ u8 slave_endianness;
+ u8 host_endianness;
+ bool have_ana_cfg;
+};
+
+struct ltq_rcu_usb2_priv {
+ struct regmap *regmap;
+ u32 phy_reg_offset;
+ u32 ana_cfg1_reg_offset;
+ const struct ltq_rcu_usb2_bits *reg_bits;
+ struct device *dev;
+ struct phy *phy;
+ struct clk *ctrl_gate_clk;
+ struct clk *phy_gate_clk;
+ struct reset_control *ctrl_reset;
+ struct reset_control *phy_reset;
+};
+
+static const struct ltq_rcu_usb2_bits xway_rcu_usb2_reg_bits = {
+ .hostmode = 11,
+ .slave_endianness = 9,
+ .host_endianness = 10,
+ .have_ana_cfg = false,
+};
+
+static const struct ltq_rcu_usb2_bits xrx100_rcu_usb2_reg_bits = {
+ .hostmode = 11,
+ .slave_endianness = 17,
+ .host_endianness = 10,
+ .have_ana_cfg = false,
+};
+
+static const struct ltq_rcu_usb2_bits xrx200_rcu_usb2_reg_bits = {
+ .hostmode = 11,
+ .slave_endianness = 9,
+ .host_endianness = 10,
+ .have_ana_cfg = true,
+};
+
+static const struct of_device_id ltq_rcu_usb2_phy_of_match[] = {
+ {
+ .compatible = "lantiq,ase-rcu-usb2-phy",
+ .data = &xway_rcu_usb2_reg_bits,
+ },
+ {
+ .compatible = "lantiq,danube-rcu-usb2-phy",
+ .data = &xway_rcu_usb2_reg_bits,
+ },
+ {
+ .compatible = "lantiq,xrx100-rcu-usb2-phy",
+ .data = &xrx100_rcu_usb2_reg_bits,
+ },
+ {
+ .compatible = "lantiq,xrx200-rcu-usb2-phy",
+ .data = &xrx200_rcu_usb2_reg_bits,
+ },
+ {
+ .compatible = "lantiq,xrx300-rcu-usb2-phy",
+ .data = &xrx200_rcu_usb2_reg_bits,
+ },
+ { },
+};
+MODULE_DEVICE_TABLE(of, ltq_rcu_usb2_phy_of_match);
+
+
+static int ltq_rcu_usb2_phy_power_on(struct phy *phy)
+{
+ struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy);
+
+ reset_control_deassert(priv->phy_reset);
+
+ return 0;
+}
+
+static int ltq_rcu_usb2_phy_power_off(struct phy *phy)
+{
+ struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy);
+
+ reset_control_assert(priv->phy_reset);
+
+ return 0;
+}
+
+static struct phy_ops ltq_rcu_usb2_phy_ops = {
+ .power_on = ltq_rcu_usb2_phy_power_on,
+ .power_off = ltq_rcu_usb2_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static void ltq_rcu_usb2_start_cores(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct ltq_rcu_usb2_priv *priv = dev_get_drvdata(dev);
+
+ /* Power on the USB core. */
+ if (clk_prepare_enable(priv->ctrl_gate_clk)) {
+ dev_err(dev, "failed to enable CTRL gate\n");
+ return;
+ }
+
+ /*
+ * Power on the USB PHY. We have to do it early because
+ * otherwise the second core won't turn on properly.
+ */
+ if (clk_prepare_enable(priv->phy_gate_clk)) {
+ dev_err(dev, "failed to enable PHY gate\n");
+ return;
+ }
+
+ if (priv->reg_bits->have_ana_cfg) {
+ regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset,
+ RCU_CFG1_TX_PEE, RCU_CFG1_TX_PEE);
+ regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset,
+ RCU_CFG1_DIS_THR_MASK, 7 << RCU_CFG1_DIS_THR_SHIFT);
+ }
+
+ /* Configure core to host mode */
+ regmap_update_bits(priv->regmap, priv->phy_reg_offset,
+ BIT(priv->reg_bits->hostmode), 0);
+
+ /* Select DMA endianness (Host-endian: big-endian) */
+ regmap_update_bits(priv->regmap, priv->phy_reg_offset,
+ BIT(priv->reg_bits->slave_endianness), 0);
+ regmap_update_bits(priv->regmap, priv->phy_reg_offset,
+ BIT(priv->reg_bits->host_endianness),
+ BIT(priv->reg_bits->host_endianness));
+
+ /* Reset USB core throgh reset controller */
+ reset_control_deassert(priv->ctrl_reset);
+
+ reset_control_assert(priv->phy_reset);
+}
+
+static int ltq_rcu_usb2_of_probe(struct device_node *phynode,
+ struct ltq_rcu_usb2_priv *priv)
+{
+ struct device *dev = priv->dev;
+ const struct of_device_id *match =
+ of_match_node(ltq_rcu_usb2_phy_of_match, phynode);
+ int ret;
+
+ if (!match) {
+ dev_err(dev, "Not a compatible Lantiq RCU USB PHY\n");
+ return -EINVAL;
+ }
+
+ priv->reg_bits = match->data;
+
+ priv->regmap = syscon_regmap_lookup_by_phandle(phynode, "regmap");
+ if (IS_ERR(priv->regmap)) {
+ dev_err(dev, "Failed to lookup RCU regmap\n");
+ return PTR_ERR(priv->regmap);
+ }
+
+ priv->ctrl_gate_clk = devm_clk_get(dev, "ctrl");
+ if (IS_ERR(priv->ctrl_gate_clk)) {
+ dev_err(dev, "Unable to get USB ctrl gate clk\n");
+ return PTR_ERR(priv->ctrl_gate_clk);
+ }
+
+ priv->phy_gate_clk = devm_clk_get(dev, "phy");
+ if (IS_ERR(priv->phy_gate_clk)) {
+ dev_err(dev, "Unable to get USB phy gate clk\n");
+ return PTR_ERR(priv->phy_gate_clk);
+ }
+
+ priv->ctrl_reset = devm_reset_control_get_shared(dev, "ctrl");
+ if (IS_ERR(priv->ctrl_reset)) {
+ if (PTR_ERR(priv->ctrl_reset) != -EPROBE_DEFER)
+ dev_err(dev, "failed to get 'ctrl' reset\n");
+ return PTR_ERR(priv->ctrl_reset);
+ }
+
+ priv->phy_reset = devm_reset_control_get_optional(dev, "phy");
+ if (IS_ERR(priv->phy_reset))
+ return PTR_ERR(priv->phy_reset);
+
+ ret = device_property_read_u32(dev, "offset-phy",
+ &priv->phy_reg_offset);
+ if (ret) {
+ dev_err(dev, "Failed to get RCU PHY reg offset\n");
+ return ret;
+ }
+
+ if (priv->reg_bits->have_ana_cfg) {
+ ret = device_property_read_u32(dev, "offset-ana",
+ &priv->ana_cfg1_reg_offset);
+ if (ret) {
+ dev_dbg(dev, "Failed to get RCU ANA CFG1 reg offset\n");
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int ltq_rcu_usb2_phy_probe(struct platform_device *pdev)
+{
+ struct device_node *child, *np = pdev->dev.of_node;
+ struct ltq_rcu_usb2_priv *priv;
+ struct phy_provider *provider;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = &pdev->dev;
+ dev_set_drvdata(priv->dev, priv);
+
+ ret = ltq_rcu_usb2_of_probe(np, priv);
+ if (ret)
+ return ret;
+
+ priv->phy = devm_phy_create(&pdev->dev, child,
+ <q_rcu_usb2_phy_ops);
+ if (IS_ERR(priv->phy)) {
+ dev_err(&pdev->dev, "failed to create PHY\n");
+ return PTR_ERR(priv->phy);
+ }
+
+ phy_set_drvdata(priv->phy, priv);
+
+ ltq_rcu_usb2_start_cores(pdev);
+
+ provider = devm_of_phy_provider_register(&pdev->dev,
+ of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(provider);
+}
+
+static struct platform_driver ltq_rcu_usb2_phy_driver = {
+ .probe = ltq_rcu_usb2_phy_probe,
+ .driver = {
+ .name = "lantiq-rcu-usb2-phy",
+ .of_match_table = ltq_rcu_usb2_phy_of_match,
+ }
+};
+module_platform_driver(ltq_rcu_usb2_phy_driver);
+
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
+MODULE_DESCRIPTION("Lantiq XWAY USB2 PHY driver");
+MODULE_LICENSE("GPL v2");
--
2.11.0
^ permalink raw reply related [flat|nested] 60+ messages in thread[parent not found: <20170528184006.31668-15-hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>]
* Re: [PATCH v3 14/16] phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module
2017-05-28 18:40 ` Hauke Mehrtens
@ 2017-05-30 18:31 ` Andy Shevchenko
-1 siblings, 0 replies; 60+ messages in thread
From: Andy Shevchenko @ 2017-05-30 18:31 UTC (permalink / raw)
To: Hauke Mehrtens
Cc: Ralf Baechle, Linux MIPS Mailing List,
open list:MEMORY TECHNOLOGY...,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA, devicetree,
martin.blumenstingl, john, linux-spi, hauke.mehrtens,
Rob Herring, Philipp Zabel, Kishon Vijay Abraham I
On Sun, May 28, 2017 at 9:40 PM, Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org> wrote:
> This driver starts the DWC2 core(s) built into the XWAY SoCs and provides
> the PHY interfaces for each core. The phy instances can be passed to the
> dwc2 driver, which already supports the generic phy interface.
> +static void ltq_rcu_usb2_start_cores(struct platform_device *pdev)
It should return int. See below.
> +{
> + /* Power on the USB core. */
> + if (clk_prepare_enable(priv->ctrl_gate_clk)) {
You basically shadow the error, why?
> + dev_err(dev, "failed to enable CTRL gate\n");
> + return;
> + }
> + if (clk_prepare_enable(priv->phy_gate_clk)) {
> + dev_err(dev, "failed to enable PHY gate\n");
> + return;
> + }
Ditto.
> +static int ltq_rcu_usb2_of_probe(struct device_node *phynode,
> + struct ltq_rcu_usb2_priv *priv)
> +{
> + struct device *dev = priv->dev;
> + const struct of_device_id *match =
> + of_match_node(ltq_rcu_usb2_phy_of_match, phynode);
> + int ret;
> +
> + if (!match) {
> + dev_err(dev, "Not a compatible Lantiq RCU USB PHY\n");
> + return -EINVAL;
> + }
Can it ever happen?
> +
> + priv->reg_bits = match->data;
I think there is a helper to get driver data directly from node.
> + if (priv->reg_bits->have_ana_cfg) {
> + ret = device_property_read_u32(dev, "offset-ana",
> + &priv->ana_cfg1_reg_offset);
> + if (ret) {
> + dev_dbg(dev, "Failed to get RCU ANA CFG1 reg offset\n");
> + return ret;
> + }
> + }
ret = device_property_...(...);
if (ret && priv->reg_bits->have_ana_cfg) {
...
return ret;
}
?
> + priv->dev = &pdev->dev;
> + dev_set_drvdata(priv->dev, priv);
Move this to the end of function. Ideally it should be run if and only
if the function returns 0.
> + provider = devm_of_phy_provider_register(&pdev->dev,
> + of_phy_simple_xlate);
> +
> + return PTR_ERR_OR_ZERO(provider);
I would do explicitly, though it's up to you and maintainer.
if (IS_ERR(provider))
return PTR_ERR();
return 0;
--
With Best Regards,
Andy Shevchenko
--
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^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH v3 14/16] phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module
@ 2017-05-30 18:31 ` Andy Shevchenko
0 siblings, 0 replies; 60+ messages in thread
From: Andy Shevchenko @ 2017-05-30 18:31 UTC (permalink / raw)
To: Hauke Mehrtens
Cc: Ralf Baechle, Linux MIPS Mailing List,
open list:MEMORY TECHNOLOGY...,
linux-watchdog, devicetree, martin.blumenstingl, john, linux-spi,
hauke.mehrtens, Rob Herring, Philipp Zabel,
Kishon Vijay Abraham I
On Sun, May 28, 2017 at 9:40 PM, Hauke Mehrtens <hauke@hauke-m.de> wrote:
> This driver starts the DWC2 core(s) built into the XWAY SoCs and provides
> the PHY interfaces for each core. The phy instances can be passed to the
> dwc2 driver, which already supports the generic phy interface.
> +static void ltq_rcu_usb2_start_cores(struct platform_device *pdev)
It should return int. See below.
> +{
> + /* Power on the USB core. */
> + if (clk_prepare_enable(priv->ctrl_gate_clk)) {
You basically shadow the error, why?
> + dev_err(dev, "failed to enable CTRL gate\n");
> + return;
> + }
> + if (clk_prepare_enable(priv->phy_gate_clk)) {
> + dev_err(dev, "failed to enable PHY gate\n");
> + return;
> + }
Ditto.
> +static int ltq_rcu_usb2_of_probe(struct device_node *phynode,
> + struct ltq_rcu_usb2_priv *priv)
> +{
> + struct device *dev = priv->dev;
> + const struct of_device_id *match =
> + of_match_node(ltq_rcu_usb2_phy_of_match, phynode);
> + int ret;
> +
> + if (!match) {
> + dev_err(dev, "Not a compatible Lantiq RCU USB PHY\n");
> + return -EINVAL;
> + }
Can it ever happen?
> +
> + priv->reg_bits = match->data;
I think there is a helper to get driver data directly from node.
> + if (priv->reg_bits->have_ana_cfg) {
> + ret = device_property_read_u32(dev, "offset-ana",
> + &priv->ana_cfg1_reg_offset);
> + if (ret) {
> + dev_dbg(dev, "Failed to get RCU ANA CFG1 reg offset\n");
> + return ret;
> + }
> + }
ret = device_property_...(...);
if (ret && priv->reg_bits->have_ana_cfg) {
...
return ret;
}
?
> + priv->dev = &pdev->dev;
> + dev_set_drvdata(priv->dev, priv);
Move this to the end of function. Ideally it should be run if and only
if the function returns 0.
> + provider = devm_of_phy_provider_register(&pdev->dev,
> + of_phy_simple_xlate);
> +
> + return PTR_ERR_OR_ZERO(provider);
I would do explicitly, though it's up to you and maintainer.
if (IS_ERR(provider))
return PTR_ERR();
return 0;
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 60+ messages in thread[parent not found: <CAHp75Ve9bV99=WCzmXU-Rth-gar5gqvy4taZ7NMQQHGKcVbHHw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH v3 14/16] phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module
2017-05-30 18:31 ` Andy Shevchenko
(?)
@ 2017-05-30 20:21 ` Hauke Mehrtens
-1 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-30 20:21 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Ralf Baechle, Linux MIPS Mailing List,
open list:MEMORY TECHNOLOGY...,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA, devicetree,
martin.blumenstingl, john, linux-spi, hauke.mehrtens,
Rob Herring, Philipp Zabel, Kishon Vijay Abraham I
On 05/30/2017 08:31 PM, Andy Shevchenko wrote:
> On Sun, May 28, 2017 at 9:40 PM, Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org> wrote:
>> This driver starts the DWC2 core(s) built into the XWAY SoCs and provides
>> the PHY interfaces for each core. The phy instances can be passed to the
>> dwc2 driver, which already supports the generic phy interface.
>
>> +static void ltq_rcu_usb2_start_cores(struct platform_device *pdev)
>
> It should return int. See below.
>
>> +{
>
>> + /* Power on the USB core. */
>> + if (clk_prepare_enable(priv->ctrl_gate_clk)) {
>
> You basically shadow the error, why?
Thanks for the hint I changed it.
>> + dev_err(dev, "failed to enable CTRL gate\n");
>> + return;
>> + }
>
>> + if (clk_prepare_enable(priv->phy_gate_clk)) {
>> + dev_err(dev, "failed to enable PHY gate\n");
>> + return;
>> + }
>
> Ditto.
same here.
>> +static int ltq_rcu_usb2_of_probe(struct device_node *phynode,
>> + struct ltq_rcu_usb2_priv *priv)
>> +{
>> + struct device *dev = priv->dev;
>> + const struct of_device_id *match =
>> + of_match_node(ltq_rcu_usb2_phy_of_match, phynode);
>> + int ret;
>> +
>
>> + if (!match) {
>> + dev_err(dev, "Not a compatible Lantiq RCU USB PHY\n");
>> + return -EINVAL;
>> + }
>
> Can it ever happen?
As long as this device gets probed by device tree this can not happen,
so I will remove it.
>> +
>> + priv->reg_bits = match->data;
>
> I think there is a helper to get driver data directly from node.
Thanks for the hint, there is of_device_get_match_data() which does this.
>> + if (priv->reg_bits->have_ana_cfg) {
>> + ret = device_property_read_u32(dev, "offset-ana",
>> + &priv->ana_cfg1_reg_offset);
>> + if (ret) {
>> + dev_dbg(dev, "Failed to get RCU ANA CFG1 reg offset\n");
>> + return ret;
>> + }
>> + }
>
> ret = device_property_...(...);
> if (ret && priv->reg_bits->have_ana_cfg) {
> ...
> return ret;
> }
>
> ?
Yes, that should look better, I will change it.
>
>
>> + priv->dev = &pdev->dev;
>
>> + dev_set_drvdata(priv->dev, priv);
>
> Move this to the end of function. Ideally it should be run if and only
> if the function returns 0.
Done
>> + provider = devm_of_phy_provider_register(&pdev->dev,
>> + of_phy_simple_xlate);
>> +
>> + return PTR_ERR_OR_ZERO(provider);
>
> I would do explicitly, though it's up to you and maintainer.
>
> if (IS_ERR(provider))
> return PTR_ERR();
>
> return 0;
I do not care, but this was I can call dev_set_drvdata() when this is
really returning 0.
Hauke
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^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH v3 14/16] phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module
@ 2017-05-30 20:21 ` Hauke Mehrtens
0 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-30 20:21 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Ralf Baechle, Linux MIPS Mailing List,
open list:MEMORY TECHNOLOGY...,
linux-watchdog, devicetree, martin.blumenstingl, john, linux-spi,
hauke.mehrtens, Rob Herring, Philipp Zabel,
Kishon Vijay Abraham I
On 05/30/2017 08:31 PM, Andy Shevchenko wrote:
> On Sun, May 28, 2017 at 9:40 PM, Hauke Mehrtens <hauke@hauke-m.de> wrote:
>> This driver starts the DWC2 core(s) built into the XWAY SoCs and provides
>> the PHY interfaces for each core. The phy instances can be passed to the
>> dwc2 driver, which already supports the generic phy interface.
>
>> +static void ltq_rcu_usb2_start_cores(struct platform_device *pdev)
>
> It should return int. See below.
>
>> +{
>
>> + /* Power on the USB core. */
>> + if (clk_prepare_enable(priv->ctrl_gate_clk)) {
>
> You basically shadow the error, why?
Thanks for the hint I changed it.
>> + dev_err(dev, "failed to enable CTRL gate\n");
>> + return;
>> + }
>
>> + if (clk_prepare_enable(priv->phy_gate_clk)) {
>> + dev_err(dev, "failed to enable PHY gate\n");
>> + return;
>> + }
>
> Ditto.
same here.
>> +static int ltq_rcu_usb2_of_probe(struct device_node *phynode,
>> + struct ltq_rcu_usb2_priv *priv)
>> +{
>> + struct device *dev = priv->dev;
>> + const struct of_device_id *match =
>> + of_match_node(ltq_rcu_usb2_phy_of_match, phynode);
>> + int ret;
>> +
>
>> + if (!match) {
>> + dev_err(dev, "Not a compatible Lantiq RCU USB PHY\n");
>> + return -EINVAL;
>> + }
>
> Can it ever happen?
As long as this device gets probed by device tree this can not happen,
so I will remove it.
>> +
>> + priv->reg_bits = match->data;
>
> I think there is a helper to get driver data directly from node.
Thanks for the hint, there is of_device_get_match_data() which does this.
>> + if (priv->reg_bits->have_ana_cfg) {
>> + ret = device_property_read_u32(dev, "offset-ana",
>> + &priv->ana_cfg1_reg_offset);
>> + if (ret) {
>> + dev_dbg(dev, "Failed to get RCU ANA CFG1 reg offset\n");
>> + return ret;
>> + }
>> + }
>
> ret = device_property_...(...);
> if (ret && priv->reg_bits->have_ana_cfg) {
> ...
> return ret;
> }
>
> ?
Yes, that should look better, I will change it.
>
>
>> + priv->dev = &pdev->dev;
>
>> + dev_set_drvdata(priv->dev, priv);
>
> Move this to the end of function. Ideally it should be run if and only
> if the function returns 0.
Done
>> + provider = devm_of_phy_provider_register(&pdev->dev,
>> + of_phy_simple_xlate);
>> +
>> + return PTR_ERR_OR_ZERO(provider);
>
> I would do explicitly, though it's up to you and maintainer.
>
> if (IS_ERR(provider))
> return PTR_ERR();
>
> return 0;
I do not care, but this was I can call dev_set_drvdata() when this is
really returning 0.
Hauke
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH v3 14/16] phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module
@ 2017-05-30 20:21 ` Hauke Mehrtens
0 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-30 20:21 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Ralf Baechle, Linux MIPS Mailing List,
open list:MEMORY TECHNOLOGY...,
linux-watchdog, devicetree, martin.blumenstingl, john, linux-spi,
hauke.mehrtens, Rob Herring, Philipp Zabel,
Kishon Vijay Abraham I
On 05/30/2017 08:31 PM, Andy Shevchenko wrote:
> On Sun, May 28, 2017 at 9:40 PM, Hauke Mehrtens <hauke@hauke-m.de> wrote:
>> This driver starts the DWC2 core(s) built into the XWAY SoCs and provides
>> the PHY interfaces for each core. The phy instances can be passed to the
>> dwc2 driver, which already supports the generic phy interface.
>
>> +static void ltq_rcu_usb2_start_cores(struct platform_device *pdev)
>
> It should return int. See below.
>
>> +{
>
>> + /* Power on the USB core. */
>> + if (clk_prepare_enable(priv->ctrl_gate_clk)) {
>
> You basically shadow the error, why?
Thanks for the hint I changed it.
>> + dev_err(dev, "failed to enable CTRL gate\n");
>> + return;
>> + }
>
>> + if (clk_prepare_enable(priv->phy_gate_clk)) {
>> + dev_err(dev, "failed to enable PHY gate\n");
>> + return;
>> + }
>
> Ditto.
same here.
>> +static int ltq_rcu_usb2_of_probe(struct device_node *phynode,
>> + struct ltq_rcu_usb2_priv *priv)
>> +{
>> + struct device *dev = priv->dev;
>> + const struct of_device_id *match =
>> + of_match_node(ltq_rcu_usb2_phy_of_match, phynode);
>> + int ret;
>> +
>
>> + if (!match) {
>> + dev_err(dev, "Not a compatible Lantiq RCU USB PHY\n");
>> + return -EINVAL;
>> + }
>
> Can it ever happen?
As long as this device gets probed by device tree this can not happen,
so I will remove it.
>> +
>> + priv->reg_bits = match->data;
>
> I think there is a helper to get driver data directly from node.
Thanks for the hint, there is of_device_get_match_data() which does this.
>> + if (priv->reg_bits->have_ana_cfg) {
>> + ret = device_property_read_u32(dev, "offset-ana",
>> + &priv->ana_cfg1_reg_offset);
>> + if (ret) {
>> + dev_dbg(dev, "Failed to get RCU ANA CFG1 reg offset\n");
>> + return ret;
>> + }
>> + }
>
> ret = device_property_...(...);
> if (ret && priv->reg_bits->have_ana_cfg) {
> ...
> return ret;
> }
>
> ?
Yes, that should look better, I will change it.
>
>
>> + priv->dev = &pdev->dev;
>
>> + dev_set_drvdata(priv->dev, priv);
>
> Move this to the end of function. Ideally it should be run if and only
> if the function returns 0.
Done
>> + provider = devm_of_phy_provider_register(&pdev->dev,
>> + of_phy_simple_xlate);
>> +
>> + return PTR_ERR_OR_ZERO(provider);
>
> I would do explicitly, though it's up to you and maintainer.
>
> if (IS_ERR(provider))
> return PTR_ERR();
>
> return 0;
I do not care, but this was I can call dev_set_drvdata() when this is
really returning 0.
Hauke
--
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^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v3 15/16] MIPS: lantiq: remove old USB PHY initialisation
2017-05-28 18:39 ` Hauke Mehrtens
@ 2017-05-28 18:40 ` Hauke Mehrtens
-1 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:40 UTC (permalink / raw)
To: ralf-6z/3iImG2C8G8FEW9MqTrA
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w,
robh-DgEjT+Ai2ygdnm+yROfE0A,
andy.shevchenko-Re5JQEeQqe8AvxtiuMwx3w,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ, Hauke Mehrtens
This is now done in a PHY driver.
Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
arch/mips/lantiq/xway/reset.c | 43 -------------------------------------------
1 file changed, 43 deletions(-)
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index be5fd29de523..04cd9a7c04a3 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -114,45 +114,6 @@ static void ltq_machine_power_off(void)
unreachable();
}
-static void ltq_usb_init(void)
-{
- /* Power for USB cores 1 & 2 */
- ltq_pmu_enable(PMU_AHBM);
- ltq_pmu_enable(PMU_USB0);
- ltq_pmu_enable(PMU_USB1);
-
- ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1A) | BIT(0), RCU_CFG1A);
- ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1B) | BIT(0), RCU_CFG1B);
-
- /* Enable USB PHY power for cores 1 & 2 */
- ltq_pmu_enable(PMU_USB0_P);
- ltq_pmu_enable(PMU_USB1_P);
-
- /* Configure cores to host mode */
- ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
- RCU_USB1CFG);
- ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT,
- RCU_USB2CFG);
-
- /* Select DMA endianness (Host-endian: big-endian) */
- ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT)
- | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
- ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT)
- | RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG);
-
- /* Hard reset USB state machines */
- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) | USBRESET_BIT, RCU_USBRESET);
- udelay(50 * 1000);
- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) & ~USBRESET_BIT, RCU_USBRESET);
-
- /* Soft reset USB state machines */
- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
- | USB1RESET_BIT | USB2RESET_BIT, RCU_USBRESET2);
- udelay(50 * 1000);
- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
- & ~(USB1RESET_BIT | USB2RESET_BIT), RCU_USBRESET2);
-}
-
static int __init mips_reboot_setup(void)
{
struct resource res;
@@ -176,10 +137,6 @@ static int __init mips_reboot_setup(void)
if (!ltq_rcu_membase)
panic("Failed to remap core memory");
- if (of_machine_is_compatible("lantiq,ar9") ||
- of_machine_is_compatible("lantiq,vr9"))
- ltq_usb_init();
-
_machine_restart = ltq_machine_restart;
_machine_halt = ltq_machine_halt;
pm_power_off = ltq_machine_power_off;
--
2.11.0
--
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^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v3 15/16] MIPS: lantiq: remove old USB PHY initialisation
@ 2017-05-28 18:40 ` Hauke Mehrtens
0 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:40 UTC (permalink / raw)
To: ralf
Cc: linux-mips, linux-mtd, linux-watchdog, devicetree,
martin.blumenstingl, john, linux-spi, hauke.mehrtens, robh,
andy.shevchenko, p.zabel, Hauke Mehrtens
This is now done in a PHY driver.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
arch/mips/lantiq/xway/reset.c | 43 -------------------------------------------
1 file changed, 43 deletions(-)
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index be5fd29de523..04cd9a7c04a3 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -114,45 +114,6 @@ static void ltq_machine_power_off(void)
unreachable();
}
-static void ltq_usb_init(void)
-{
- /* Power for USB cores 1 & 2 */
- ltq_pmu_enable(PMU_AHBM);
- ltq_pmu_enable(PMU_USB0);
- ltq_pmu_enable(PMU_USB1);
-
- ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1A) | BIT(0), RCU_CFG1A);
- ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1B) | BIT(0), RCU_CFG1B);
-
- /* Enable USB PHY power for cores 1 & 2 */
- ltq_pmu_enable(PMU_USB0_P);
- ltq_pmu_enable(PMU_USB1_P);
-
- /* Configure cores to host mode */
- ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
- RCU_USB1CFG);
- ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT,
- RCU_USB2CFG);
-
- /* Select DMA endianness (Host-endian: big-endian) */
- ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT)
- | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
- ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT)
- | RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG);
-
- /* Hard reset USB state machines */
- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) | USBRESET_BIT, RCU_USBRESET);
- udelay(50 * 1000);
- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) & ~USBRESET_BIT, RCU_USBRESET);
-
- /* Soft reset USB state machines */
- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
- | USB1RESET_BIT | USB2RESET_BIT, RCU_USBRESET2);
- udelay(50 * 1000);
- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
- & ~(USB1RESET_BIT | USB2RESET_BIT), RCU_USBRESET2);
-}
-
static int __init mips_reboot_setup(void)
{
struct resource res;
@@ -176,10 +137,6 @@ static int __init mips_reboot_setup(void)
if (!ltq_rcu_membase)
panic("Failed to remap core memory");
- if (of_machine_is_compatible("lantiq,ar9") ||
- of_machine_is_compatible("lantiq,vr9"))
- ltq_usb_init();
-
_machine_restart = ltq_machine_restart;
_machine_halt = ltq_machine_halt;
pm_power_off = ltq_machine_power_off;
--
2.11.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v3 16/16] MIPS: lantiq: Remove the arch/mips/lantiq/xway/reset.c implementation
2017-05-28 18:39 ` Hauke Mehrtens
@ 2017-05-28 18:40 ` Hauke Mehrtens
-1 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:40 UTC (permalink / raw)
To: ralf-6z/3iImG2C8G8FEW9MqTrA
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg,
john-Pj+rj9U5foFAfugRpC6u6w, linux-spi-u79uwXL29TY76Z2rM5mHXA,
hauke.mehrtens-ral2JQCrhuEAvxtiuMwx3w,
robh-DgEjT+Ai2ygdnm+yROfE0A,
andy.shevchenko-Re5JQEeQqe8AvxtiuMwx3w,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ, Hauke Mehrtens
From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
The RCU register are now access through separates drivers. remove the
last pieces of the old implementation.
The GPHY reset bits are now set by the GPHY driver which registers a
reboot notifier. The reboot is triggered by a syscon-reboot driver and
the MIPS specific parts are done by the generic MIPS implementation in
arch/mips/kernel/reset.c.
Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
arch/mips/lantiq/Kconfig | 1 +
arch/mips/lantiq/xway/Makefile | 2 +-
arch/mips/lantiq/xway/reset.c | 147 -----------------------------------------
3 files changed, 2 insertions(+), 148 deletions(-)
delete mode 100644 arch/mips/lantiq/xway/reset.c
diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig
index f5db4a426568..35bc69b78268 100644
--- a/arch/mips/lantiq/Kconfig
+++ b/arch/mips/lantiq/Kconfig
@@ -18,6 +18,7 @@ config SOC_XWAY
select SOC_TYPE_XWAY
select HW_HAS_PCI
select MFD_SYSCON
+ select MFD_CORE
config SOC_FALCON
bool "FALCON"
diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
index 6daf3149e7ca..fbb0747c70b7 100644
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
@@ -1,3 +1,3 @@
-obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o
+obj-y := prom.o sysctrl.o clk.o dma.o gptu.o dcdc.o
obj-y += vmmc.o
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
deleted file mode 100644
index 04cd9a7c04a3..000000000000
--- a/arch/mips/lantiq/xway/reset.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- * Copyright (C) 2010 John Crispin <john-Pj+rj9U5foFAfugRpC6u6w@public.gmane.org>
- * Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
- */
-
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/ioport.h>
-#include <linux/pm.h>
-#include <linux/export.h>
-#include <linux/delay.h>
-#include <linux/of_address.h>
-#include <linux/of_platform.h>
-#include <linux/reset-controller.h>
-
-#include <asm/reboot.h>
-
-#include <lantiq_soc.h>
-
-#include "../prom.h"
-
-/* reset request register */
-#define RCU_RST_REQ 0x0010
-/* reset status register */
-#define RCU_RST_STAT 0x0014
-
-/* xbar BE flag */
-#define RCU_AHB_ENDIAN 0x004C
-#define RCU_VR9_BE_AHB1S 0x00000008
-
-/* reboot bit */
-#define RCU_RD_GPHY0_XRX200 BIT(31)
-#define RCU_RD_SRST BIT(30)
-#define RCU_RD_GPHY1_XRX200 BIT(29)
-
-/* reset cause */
-#define RCU_STAT_SHIFT 26
-/* boot selection */
-#define RCU_BOOT_SEL(x) ((x >> 18) & 0x7)
-#define RCU_BOOT_SEL_XRX200(x) (((x >> 17) & 0xf) | ((x >> 8) & 0x10))
-
-/* dwc2 USB configuration registers */
-#define RCU_USB1CFG 0x0018
-#define RCU_USB2CFG 0x0034
-
-/* USB DMA endianness bits */
-#define RCU_USBCFG_HDSEL_BIT BIT(11)
-#define RCU_USBCFG_HOST_END_BIT BIT(10)
-#define RCU_USBCFG_SLV_END_BIT BIT(9)
-
-/* USB reset bits */
-#define RCU_USBRESET 0x0010
-
-#define USBRESET_BIT BIT(4)
-
-#define RCU_USBRESET2 0x0048
-
-#define USB1RESET_BIT BIT(4)
-#define USB2RESET_BIT BIT(5)
-
-#define RCU_CFG1A 0x0038
-#define RCU_CFG1B 0x003C
-
-/* USB PMU devices */
-#define PMU_AHBM BIT(15)
-#define PMU_USB0 BIT(6)
-#define PMU_USB1 BIT(27)
-
-/* USB PHY PMU devices */
-#define PMU_USB0_P BIT(0)
-#define PMU_USB1_P BIT(26)
-
-/* remapped base addr of the reset control unit */
-static void __iomem *ltq_rcu_membase;
-static struct device_node *ltq_rcu_np;
-
-static void ltq_rcu_w32(uint32_t val, uint32_t reg_off)
-{
- ltq_w32(val, ltq_rcu_membase + reg_off);
-}
-
-static uint32_t ltq_rcu_r32(uint32_t reg_off)
-{
- return ltq_r32(ltq_rcu_membase + reg_off);
-}
-
-static void ltq_machine_restart(char *command)
-{
- u32 val = ltq_rcu_r32(RCU_RST_REQ);
-
- if (of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200"))
- val |= RCU_RD_GPHY1_XRX200 | RCU_RD_GPHY0_XRX200;
-
- val |= RCU_RD_SRST;
-
- local_irq_disable();
- ltq_rcu_w32(val, RCU_RST_REQ);
- unreachable();
-}
-
-static void ltq_machine_halt(void)
-{
- local_irq_disable();
- unreachable();
-}
-
-static void ltq_machine_power_off(void)
-{
- local_irq_disable();
- unreachable();
-}
-
-static int __init mips_reboot_setup(void)
-{
- struct resource res;
-
- ltq_rcu_np = of_find_compatible_node(NULL, NULL, "lantiq,rcu-xway");
- if (!ltq_rcu_np)
- ltq_rcu_np = of_find_compatible_node(NULL, NULL,
- "lantiq,rcu-xrx200");
-
- /* check if all the reset register range is available */
- if (!ltq_rcu_np)
- panic("Failed to load reset resources from devicetree");
-
- if (of_address_to_resource(ltq_rcu_np, 0, &res))
- panic("Failed to get rcu memory range");
-
- if (!request_mem_region(res.start, resource_size(&res), res.name))
- pr_err("Failed to request rcu memory");
-
- ltq_rcu_membase = ioremap_nocache(res.start, resource_size(&res));
- if (!ltq_rcu_membase)
- panic("Failed to remap core memory");
-
- _machine_restart = ltq_machine_restart;
- _machine_halt = ltq_machine_halt;
- pm_power_off = ltq_machine_power_off;
-
- return 0;
-}
-
-arch_initcall(mips_reboot_setup);
--
2.11.0
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v3 16/16] MIPS: lantiq: Remove the arch/mips/lantiq/xway/reset.c implementation
@ 2017-05-28 18:40 ` Hauke Mehrtens
0 siblings, 0 replies; 60+ messages in thread
From: Hauke Mehrtens @ 2017-05-28 18:40 UTC (permalink / raw)
To: ralf
Cc: linux-mips, linux-mtd, linux-watchdog, devicetree,
martin.blumenstingl, john, linux-spi, hauke.mehrtens, robh,
andy.shevchenko, p.zabel, Hauke Mehrtens
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
The RCU register are now access through separates drivers. remove the
last pieces of the old implementation.
The GPHY reset bits are now set by the GPHY driver which registers a
reboot notifier. The reboot is triggered by a syscon-reboot driver and
the MIPS specific parts are done by the generic MIPS implementation in
arch/mips/kernel/reset.c.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
arch/mips/lantiq/Kconfig | 1 +
arch/mips/lantiq/xway/Makefile | 2 +-
arch/mips/lantiq/xway/reset.c | 147 -----------------------------------------
3 files changed, 2 insertions(+), 148 deletions(-)
delete mode 100644 arch/mips/lantiq/xway/reset.c
diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig
index f5db4a426568..35bc69b78268 100644
--- a/arch/mips/lantiq/Kconfig
+++ b/arch/mips/lantiq/Kconfig
@@ -18,6 +18,7 @@ config SOC_XWAY
select SOC_TYPE_XWAY
select HW_HAS_PCI
select MFD_SYSCON
+ select MFD_CORE
config SOC_FALCON
bool "FALCON"
diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
index 6daf3149e7ca..fbb0747c70b7 100644
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
@@ -1,3 +1,3 @@
-obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o
+obj-y := prom.o sysctrl.o clk.o dma.o gptu.o dcdc.o
obj-y += vmmc.o
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
deleted file mode 100644
index 04cd9a7c04a3..000000000000
--- a/arch/mips/lantiq/xway/reset.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- * Copyright (C) 2010 John Crispin <john@phrozen.org>
- * Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
- */
-
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/ioport.h>
-#include <linux/pm.h>
-#include <linux/export.h>
-#include <linux/delay.h>
-#include <linux/of_address.h>
-#include <linux/of_platform.h>
-#include <linux/reset-controller.h>
-
-#include <asm/reboot.h>
-
-#include <lantiq_soc.h>
-
-#include "../prom.h"
-
-/* reset request register */
-#define RCU_RST_REQ 0x0010
-/* reset status register */
-#define RCU_RST_STAT 0x0014
-
-/* xbar BE flag */
-#define RCU_AHB_ENDIAN 0x004C
-#define RCU_VR9_BE_AHB1S 0x00000008
-
-/* reboot bit */
-#define RCU_RD_GPHY0_XRX200 BIT(31)
-#define RCU_RD_SRST BIT(30)
-#define RCU_RD_GPHY1_XRX200 BIT(29)
-
-/* reset cause */
-#define RCU_STAT_SHIFT 26
-/* boot selection */
-#define RCU_BOOT_SEL(x) ((x >> 18) & 0x7)
-#define RCU_BOOT_SEL_XRX200(x) (((x >> 17) & 0xf) | ((x >> 8) & 0x10))
-
-/* dwc2 USB configuration registers */
-#define RCU_USB1CFG 0x0018
-#define RCU_USB2CFG 0x0034
-
-/* USB DMA endianness bits */
-#define RCU_USBCFG_HDSEL_BIT BIT(11)
-#define RCU_USBCFG_HOST_END_BIT BIT(10)
-#define RCU_USBCFG_SLV_END_BIT BIT(9)
-
-/* USB reset bits */
-#define RCU_USBRESET 0x0010
-
-#define USBRESET_BIT BIT(4)
-
-#define RCU_USBRESET2 0x0048
-
-#define USB1RESET_BIT BIT(4)
-#define USB2RESET_BIT BIT(5)
-
-#define RCU_CFG1A 0x0038
-#define RCU_CFG1B 0x003C
-
-/* USB PMU devices */
-#define PMU_AHBM BIT(15)
-#define PMU_USB0 BIT(6)
-#define PMU_USB1 BIT(27)
-
-/* USB PHY PMU devices */
-#define PMU_USB0_P BIT(0)
-#define PMU_USB1_P BIT(26)
-
-/* remapped base addr of the reset control unit */
-static void __iomem *ltq_rcu_membase;
-static struct device_node *ltq_rcu_np;
-
-static void ltq_rcu_w32(uint32_t val, uint32_t reg_off)
-{
- ltq_w32(val, ltq_rcu_membase + reg_off);
-}
-
-static uint32_t ltq_rcu_r32(uint32_t reg_off)
-{
- return ltq_r32(ltq_rcu_membase + reg_off);
-}
-
-static void ltq_machine_restart(char *command)
-{
- u32 val = ltq_rcu_r32(RCU_RST_REQ);
-
- if (of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200"))
- val |= RCU_RD_GPHY1_XRX200 | RCU_RD_GPHY0_XRX200;
-
- val |= RCU_RD_SRST;
-
- local_irq_disable();
- ltq_rcu_w32(val, RCU_RST_REQ);
- unreachable();
-}
-
-static void ltq_machine_halt(void)
-{
- local_irq_disable();
- unreachable();
-}
-
-static void ltq_machine_power_off(void)
-{
- local_irq_disable();
- unreachable();
-}
-
-static int __init mips_reboot_setup(void)
-{
- struct resource res;
-
- ltq_rcu_np = of_find_compatible_node(NULL, NULL, "lantiq,rcu-xway");
- if (!ltq_rcu_np)
- ltq_rcu_np = of_find_compatible_node(NULL, NULL,
- "lantiq,rcu-xrx200");
-
- /* check if all the reset register range is available */
- if (!ltq_rcu_np)
- panic("Failed to load reset resources from devicetree");
-
- if (of_address_to_resource(ltq_rcu_np, 0, &res))
- panic("Failed to get rcu memory range");
-
- if (!request_mem_region(res.start, resource_size(&res), res.name))
- pr_err("Failed to request rcu memory");
-
- ltq_rcu_membase = ioremap_nocache(res.start, resource_size(&res));
- if (!ltq_rcu_membase)
- panic("Failed to remap core memory");
-
- _machine_restart = ltq_machine_restart;
- _machine_halt = ltq_machine_halt;
- pm_power_off = ltq_machine_power_off;
-
- return 0;
-}
-
-arch_initcall(mips_reboot_setup);
--
2.11.0
^ permalink raw reply related [flat|nested] 60+ messages in thread