* [PATCH] drm/i915/glk: Fix dotclock calculation in skl_check_pipe_max_pixel_rate
@ 2017-06-01 10:34 Maarten Lankhorst
2017-06-01 10:50 ` ✓ Fi.CI.BAT: success for " Patchwork
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Maarten Lankhorst @ 2017-06-01 10:34 UTC (permalink / raw)
To: intel-gfx
Seems that GLK has a dotclock that's twice the display clock.
skl_max_scale checks for IS_GEMINILAKE, so perform the same check here.
While at it, change the DRM_ERROR to DEBUG_KMS.
Fixes: 73b0ca8ec76d ("drm/i915/skl+: consider max supported plane pixel
rate while scaling")
Cc: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2042f6512e6e..88c8a3511e24 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4122,7 +4122,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
struct drm_plane *plane;
const struct drm_plane_state *pstate;
struct intel_plane_state *intel_pstate;
- int crtc_clock, cdclk;
+ int crtc_clock, dotclk;
uint32_t pipe_max_pixel_rate;
uint_fixed_16_16_t pipe_downscale;
uint_fixed_16_16_t max_downscale = u32_to_fixed_16_16(1);
@@ -4157,11 +4157,15 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
pipe_downscale = mul_fixed16(pipe_downscale, max_downscale);
crtc_clock = crtc_state->adjusted_mode.crtc_clock;
- cdclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
- pipe_max_pixel_rate = div_round_up_u32_fixed16(cdclk, pipe_downscale);
+ dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
+
+ if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev)))
+ dotclk *= 2;
+
+ pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale);
if (pipe_max_pixel_rate < crtc_clock) {
- DRM_ERROR("Max supported pixel clock with scaling exceeded\n");
+ DRM_DEBUG_KMS("Max supported pixel clock with scaling exceeded\n");
return -EINVAL;
}
--
2.11.0
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/glk: Fix dotclock calculation in skl_check_pipe_max_pixel_rate
2017-06-01 10:34 [PATCH] drm/i915/glk: Fix dotclock calculation in skl_check_pipe_max_pixel_rate Maarten Lankhorst
@ 2017-06-01 10:50 ` Patchwork
2017-06-01 10:52 ` [PATCH] " Mahesh Kumar
2017-06-01 13:52 ` Ville Syrjälä
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2017-06-01 10:50 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/glk: Fix dotclock calculation in skl_check_pipe_max_pixel_rate
URL : https://patchwork.freedesktop.org/series/25155/
State : success
== Summary ==
Series 25155v1 drm/i915/glk: Fix dotclock calculation in skl_check_pipe_max_pixel_rate
https://patchwork.freedesktop.org/api/1.0/series/25155/revisions/1/mbox/
Test kms_busy:
Subgroup basic-flip-default-a:
pass -> DMESG-WARN (fi-skl-6700hq) fdo#101144 +1
fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144
fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time:443s
fi-bdw-gvtdvm total:278 pass:256 dwarn:8 dfail:0 fail:0 skip:14 time:434s
fi-bsw-n3050 total:278 pass:242 dwarn:0 dfail:0 fail:0 skip:36 time:576s
fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time:515s
fi-byt-j1900 total:278 pass:254 dwarn:0 dfail:0 fail:0 skip:24 time:493s
fi-byt-n2820 total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:476s
fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:430s
fi-hsw-4770r total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:410s
fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time:416s
fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:490s
fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:464s
fi-kbl-7500u total:278 pass:255 dwarn:5 dfail:0 fail:0 skip:18 time:470s
fi-kbl-7560u total:278 pass:263 dwarn:5 dfail:0 fail:0 skip:10 time:568s
fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:457s
fi-skl-6700hq total:278 pass:228 dwarn:1 dfail:0 fail:27 skip:22 time:404s
fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 time:465s
fi-skl-6770hq total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:502s
fi-skl-gvtdvm total:278 pass:265 dwarn:0 dfail:0 fail:0 skip:13 time:436s
fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:538s
fi-snb-2600 total:278 pass:249 dwarn:0 dfail:0 fail:0 skip:29 time:402s
b0d30ff104856c5c49eee882d77aac32928f9724 drm-tip: 2017y-06m-01d-09h-45m-19s UTC integration manifest
50ad41b drm/i915/glk: Fix dotclock calculation in skl_check_pipe_max_pixel_rate
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4854/
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915/glk: Fix dotclock calculation in skl_check_pipe_max_pixel_rate
2017-06-01 10:34 [PATCH] drm/i915/glk: Fix dotclock calculation in skl_check_pipe_max_pixel_rate Maarten Lankhorst
2017-06-01 10:50 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2017-06-01 10:52 ` Mahesh Kumar
2017-06-01 10:54 ` Maarten Lankhorst
2017-06-01 13:52 ` Ville Syrjälä
2 siblings, 1 reply; 6+ messages in thread
From: Mahesh Kumar @ 2017-06-01 10:52 UTC (permalink / raw)
To: Maarten Lankhorst, intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 2094 bytes --]
hmm... didn't considered 2 pixels per clock.
thanks.
Reviewed-by: Mahesh Kumar <mahesh1.kumar@intel.com>
On Thursday 01 June 2017 04:04 PM, Maarten Lankhorst wrote:
> Seems that GLK has a dotclock that's twice the display clock.
> skl_max_scale checks for IS_GEMINILAKE, so perform the same check here.
>
> While at it, change the DRM_ERROR to DEBUG_KMS.
>
> Fixes: 73b0ca8ec76d ("drm/i915/skl+: consider max supported plane pixel
> rate while scaling")
> Cc: Mahesh Kumar <mahesh1.kumar@intel.com>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 2042f6512e6e..88c8a3511e24 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4122,7 +4122,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
> struct drm_plane *plane;
> const struct drm_plane_state *pstate;
> struct intel_plane_state *intel_pstate;
> - int crtc_clock, cdclk;
> + int crtc_clock, dotclk;
> uint32_t pipe_max_pixel_rate;
> uint_fixed_16_16_t pipe_downscale;
> uint_fixed_16_16_t max_downscale = u32_to_fixed_16_16(1);
> @@ -4157,11 +4157,15 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
> pipe_downscale = mul_fixed16(pipe_downscale, max_downscale);
>
> crtc_clock = crtc_state->adjusted_mode.crtc_clock;
> - cdclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
> - pipe_max_pixel_rate = div_round_up_u32_fixed16(cdclk, pipe_downscale);
> + dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
> +
> + if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev)))
> + dotclk *= 2;
> +
> + pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale);
>
> if (pipe_max_pixel_rate < crtc_clock) {
> - DRM_ERROR("Max supported pixel clock with scaling exceeded\n");
> + DRM_DEBUG_KMS("Max supported pixel clock with scaling exceeded\n");
> return -EINVAL;
> }
>
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915/glk: Fix dotclock calculation in skl_check_pipe_max_pixel_rate
2017-06-01 10:52 ` [PATCH] " Mahesh Kumar
@ 2017-06-01 10:54 ` Maarten Lankhorst
0 siblings, 0 replies; 6+ messages in thread
From: Maarten Lankhorst @ 2017-06-01 10:54 UTC (permalink / raw)
To: Mahesh Kumar, intel-gfx
Op 01-06-17 om 12:52 schreef Mahesh Kumar:
>
> hmm... didn't considered 2 pixels per clock.
>
> thanks.
>
> Reviewed-by: Mahesh Kumar <mahesh1.kumar@intel.com>
>
Thanks, fix pushed. :)
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915/glk: Fix dotclock calculation in skl_check_pipe_max_pixel_rate
2017-06-01 10:34 [PATCH] drm/i915/glk: Fix dotclock calculation in skl_check_pipe_max_pixel_rate Maarten Lankhorst
2017-06-01 10:50 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-06-01 10:52 ` [PATCH] " Mahesh Kumar
@ 2017-06-01 13:52 ` Ville Syrjälä
2017-06-01 17:41 ` Maarten Lankhorst
2 siblings, 1 reply; 6+ messages in thread
From: Ville Syrjälä @ 2017-06-01 13:52 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
On Thu, Jun 01, 2017 at 12:34:13PM +0200, Maarten Lankhorst wrote:
> Seems that GLK has a dotclock that's twice the display clock.
> skl_max_scale checks for IS_GEMINILAKE, so perform the same check here.
>
> While at it, change the DRM_ERROR to DEBUG_KMS.
>
> Fixes: 73b0ca8ec76d ("drm/i915/skl+: consider max supported plane pixel
> rate while scaling")
> Cc: Mahesh Kumar <mahesh1.kumar@intel.com>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 2042f6512e6e..88c8a3511e24 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4122,7 +4122,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
> struct drm_plane *plane;
> const struct drm_plane_state *pstate;
> struct intel_plane_state *intel_pstate;
> - int crtc_clock, cdclk;
> + int crtc_clock, dotclk;
> uint32_t pipe_max_pixel_rate;
> uint_fixed_16_16_t pipe_downscale;
> uint_fixed_16_16_t max_downscale = u32_to_fixed_16_16(1);
> @@ -4157,11 +4157,15 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
> pipe_downscale = mul_fixed16(pipe_downscale, max_downscale);
>
> crtc_clock = crtc_state->adjusted_mode.crtc_clock;
> - cdclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
> - pipe_max_pixel_rate = div_round_up_u32_fixed16(cdclk, pipe_downscale);
> + dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
dotclk = cdclk. That statement doesn't make sense. It should be called
max_dotclk or something like that.
> +
> + if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev)))
> + dotclk *= 2;
> +
> + pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale);
>
> if (pipe_max_pixel_rate < crtc_clock) {
> - DRM_ERROR("Max supported pixel clock with scaling exceeded\n");
> + DRM_DEBUG_KMS("Max supported pixel clock with scaling exceeded\n");
> return -EINVAL;
> }
>
> --
> 2.11.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915/glk: Fix dotclock calculation in skl_check_pipe_max_pixel_rate
2017-06-01 13:52 ` Ville Syrjälä
@ 2017-06-01 17:41 ` Maarten Lankhorst
0 siblings, 0 replies; 6+ messages in thread
From: Maarten Lankhorst @ 2017-06-01 17:41 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
Op 01-06-17 om 15:52 schreef Ville Syrjälä:
> On Thu, Jun 01, 2017 at 12:34:13PM +0200, Maarten Lankhorst wrote:
>> Seems that GLK has a dotclock that's twice the display clock.
>> skl_max_scale checks for IS_GEMINILAKE, so perform the same check here.
>>
>> While at it, change the DRM_ERROR to DEBUG_KMS.
>>
>> Fixes: 73b0ca8ec76d ("drm/i915/skl+: consider max supported plane pixel
>> rate while scaling")
>> Cc: Mahesh Kumar <mahesh1.kumar@intel.com>
>> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++----
>> 1 file changed, 8 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 2042f6512e6e..88c8a3511e24 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -4122,7 +4122,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
>> struct drm_plane *plane;
>> const struct drm_plane_state *pstate;
>> struct intel_plane_state *intel_pstate;
>> - int crtc_clock, cdclk;
>> + int crtc_clock, dotclk;
>> uint32_t pipe_max_pixel_rate;
>> uint_fixed_16_16_t pipe_downscale;
>> uint_fixed_16_16_t max_downscale = u32_to_fixed_16_16(1);
>> @@ -4157,11 +4157,15 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
>> pipe_downscale = mul_fixed16(pipe_downscale, max_downscale);
>>
>> crtc_clock = crtc_state->adjusted_mode.crtc_clock;
>> - cdclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
>> - pipe_max_pixel_rate = div_round_up_u32_fixed16(cdclk, pipe_downscale);
>> + dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
> dotclk = cdclk. That statement doesn't make sense. It should be called
> max_dotclk or something like that.
R-B if you want to rename it to max_dotclk. :)
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^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2017-06-01 17:42 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2017-06-01 10:34 [PATCH] drm/i915/glk: Fix dotclock calculation in skl_check_pipe_max_pixel_rate Maarten Lankhorst
2017-06-01 10:50 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-06-01 10:52 ` [PATCH] " Mahesh Kumar
2017-06-01 10:54 ` Maarten Lankhorst
2017-06-01 13:52 ` Ville Syrjälä
2017-06-01 17:41 ` Maarten Lankhorst
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