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From: David Gibson <david@gibson.dropbear.id.au>
To: Aaron Larson <alarson@ddci.com>
Cc: agraf@suse.de, qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Subject: Re: [Qemu-devel] [PATCH] target-ppc: Fix openpic timer read register offset
Date: Mon, 5 Jun 2017 10:55:34 +1000	[thread overview]
Message-ID: <20170605005534.GX13397@umbus.fritz.box> (raw)
In-Reply-To: <201706021132.v52BWx1t027533@linux03a.ddci.com>

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On Fri, Jun 02, 2017 at 04:32:59AM -0700, Aaron Larson wrote:
> 
> openpic_tmr_read() is incorrectly computing register offset of the
> TCCR, TBCR, TVPR, and TDR registers when accessing the open pic timer
> registers.  Specifically the offset of timer registers for
> openpic_tmr_read() is not accounting for the timer frequency reporting
> register (TFFR) which is the first register in the "tmr" memory
> region.
> 
> openpic_tmr_write() *is* correctly computing the offset by adding
> 0x10f0 to the address prior to computing the register index.  This
> patch instead subtracts 0x10 in both the read and write routines and
> eliminates some other gratuitous differences between the functions.
> 
> Signed-off-by: Aaron Larson <alarson@ddci.com>

Applied to ppc-for-2.10.  It looks saner than the existing code, but I
don't know openpic well enough to really review it; so I'm trusting
you on that.

> ---
>  hw/intc/openpic.c | 22 ++++++++++------------
>  1 file changed, 10 insertions(+), 12 deletions(-)
> 
> diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c
> index 4349e45..f966d06 100644
> --- a/hw/intc/openpic.c
> +++ b/hw/intc/openpic.c
> @@ -796,27 +796,24 @@ static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len)
>  }
>  
>  static void openpic_tmr_write(void *opaque, hwaddr addr, uint64_t val,
> -                                unsigned len)
> +                              unsigned len)
>  {
>      OpenPICState *opp = opaque;
>      int idx;
>  
> -    addr += 0x10f0;
> -
>      DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n",
> -            __func__, addr, val);
> +            __func__, (addr + 0x10f0), val);
>      if (addr & 0xF) {
>          return;
>      }
>  
> -    if (addr == 0x10f0) {
> +    if (addr == 0) {
>          /* TFRR */
>          opp->tfrr = val;
>          return;
>      }
> -
> +    addr -= 0x10;  /* correct for TFRR */
>      idx = (addr >> 6) & 0x3;
> -    addr = addr & 0x30;
>  
>      switch (addr & 0x30) {
>      case 0x00: /* TCCR */
> @@ -844,16 +841,17 @@ static uint64_t openpic_tmr_read(void *opaque, hwaddr addr, unsigned len)
>      uint32_t retval = -1;
>      int idx;
>  
> -    DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr);
> +    DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr + 0x10f0);
>      if (addr & 0xF) {
>          goto out;
>      }
> -    idx = (addr >> 6) & 0x3;
> -    if (addr == 0x0) {
> +    if (addr == 0) {
>          /* TFRR */
>          retval = opp->tfrr;
>          goto out;
>      }
> +    addr -= 0x10;  /* correct for TFRR */
> +    idx = (addr >> 6) & 0x3;
>      switch (addr & 0x30) {
>      case 0x00: /* TCCR */
>          retval = opp->timers[idx].tccr;
> @@ -861,10 +859,10 @@ static uint64_t openpic_tmr_read(void *opaque, hwaddr addr, unsigned len)
>      case 0x10: /* TBCR */
>          retval = opp->timers[idx].tbcr;
>          break;
> -    case 0x20: /* TIPV */
> +    case 0x20: /* TVPR */
>          retval = read_IRQreg_ivpr(opp, opp->irq_tim0 + idx);
>          break;
> -    case 0x30: /* TIDE (TIDR) */
> +    case 0x30: /* TDR */
>          retval = read_IRQreg_idr(opp, opp->irq_tim0 + idx);
>          break;
>      }

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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  reply	other threads:[~2017-06-05  0:55 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-06-02 11:32 [Qemu-devel] [PATCH] target-ppc: Fix openpic timer read register offset Aaron Larson
2017-06-05  0:55 ` David Gibson [this message]
2017-06-05 13:39   ` alarson

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