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From: alarson@ddci.com
To: David Gibson <david@gibson.dropbear.id.au>
Cc: agraf@suse.de, qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Subject: Re: [Qemu-devel] [PATCH] target-ppc: Fix openpic timer read register offset
Date: Mon, 5 Jun 2017 08:39:37 -0500	[thread overview]
Message-ID: <OF8290D871.96947387-ON86258136.004AB4CA-86258136.004B0887@ddci.com> (raw)
In-Reply-To: <20170605005534.GX13397@umbus.fritz.box>

David Gibson <david@gibson.dropbear.id.au> wrote on 06/04/2017 07:55:34 
PM:

> From: David Gibson <david@gibson.dropbear.id.au>
> To: Aaron Larson <alarson@ddci.com>
> Cc: agraf@suse.de, qemu-devel@nongnu.org, qemu-ppc@nongnu.org
> Date: 06/04/2017 07:55 PM
> Subject: Re: [PATCH] target-ppc: Fix openpic timer read register offset
> 
> On Fri, Jun 02, 2017 at 04:32:59AM -0700, Aaron Larson wrote:
> > 
> > openpic_tmr_read() is incorrectly computing register offset of the
> > TCCR, TBCR, TVPR, and TDR registers when accessing the open pic timer
> > registers.  ...
> 
> Applied to ppc-for-2.10.  It looks saner than the existing code, but I
> don't know openpic well enough to really review it; so I'm trusting
> you on that.

Thanks David, I'll have an updated timer patch out later today for the
timer that actually times.  I'm reasonably sure the resulting code is
correct because we have the same binary working on real hardware and
on QEMU.

      reply	other threads:[~2017-06-05 13:39 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-06-02 11:32 [Qemu-devel] [PATCH] target-ppc: Fix openpic timer read register offset Aaron Larson
2017-06-05  0:55 ` David Gibson
2017-06-05 13:39   ` alarson [this message]

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