* [PATCH 0/2] arm64/kvm: use SYS_REG_DESC() for VGIC-v3 @ 2017-06-05 13:19 ` Mark Rutland 0 siblings, 0 replies; 10+ messages in thread From: Mark Rutland @ 2017-06-05 13:19 UTC (permalink / raw) To: linux-arm-kernel; +Cc: marc.zyngier, catalin.marinas, will.deacon, kvmarm While looking around, I spotted that the VGIC-v3 code still uses open-coded SYS encodings. These patches migrate said code to use common <asm/sysreg.h> mnemonics, as we do for the rest of the AArch64 sysregs. This is based on Marc's kvm-arm64/gicv3-cpuif-mediated-access branch [1]. Thanks, Mark. [1] git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git kvm-arm64/gicv3-cpuif-mediated-access Mark Rutland (2): arm64/kvm: sysreg: fix typo'd SYS_ICC_IGRPEN*_EL1 arm64/kvm: vgic: use SYS_DESC() arch/arm64/include/asm/arch_gicv3.h | 2 +- arch/arm64/include/asm/sysreg.h | 12 ++++++++-- arch/arm64/kvm/vgic-sys-reg-v3.c | 45 +++++++++++++------------------------ virt/kvm/arm/hyp/vgic-v3-sr.c | 4 ++-- 4 files changed, 28 insertions(+), 35 deletions(-) -- 1.9.1 ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 0/2] arm64/kvm: use SYS_REG_DESC() for VGIC-v3 @ 2017-06-05 13:19 ` Mark Rutland 0 siblings, 0 replies; 10+ messages in thread From: Mark Rutland @ 2017-06-05 13:19 UTC (permalink / raw) To: linux-arm-kernel While looking around, I spotted that the VGIC-v3 code still uses open-coded SYS encodings. These patches migrate said code to use common <asm/sysreg.h> mnemonics, as we do for the rest of the AArch64 sysregs. This is based on Marc's kvm-arm64/gicv3-cpuif-mediated-access branch [1]. Thanks, Mark. [1] git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git kvm-arm64/gicv3-cpuif-mediated-access Mark Rutland (2): arm64/kvm: sysreg: fix typo'd SYS_ICC_IGRPEN*_EL1 arm64/kvm: vgic: use SYS_DESC() arch/arm64/include/asm/arch_gicv3.h | 2 +- arch/arm64/include/asm/sysreg.h | 12 ++++++++-- arch/arm64/kvm/vgic-sys-reg-v3.c | 45 +++++++++++++------------------------ virt/kvm/arm/hyp/vgic-v3-sr.c | 4 ++-- 4 files changed, 28 insertions(+), 35 deletions(-) -- 1.9.1 ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 1/2] arm64/kvm: sysreg: fix typo'd SYS_ICC_IGRPEN*_EL1 2017-06-05 13:19 ` Mark Rutland @ 2017-06-05 13:20 ` Mark Rutland -1 siblings, 0 replies; 10+ messages in thread From: Mark Rutland @ 2017-06-05 13:20 UTC (permalink / raw) To: linux-arm-kernel; +Cc: marc.zyngier, catalin.marinas, will.deacon, kvmarm Per ARM DDI 0487B.a, the registers are named ICC_IGRPEN*_EL1 rather than ICC_GRPEN*_EL1. Correct our mnemonics and comments to match, before we add more GICv3 register definitions. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Christoffer Dall <christoffer.dall@linaro.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: kvmarm@lists.cs.columbia.edu --- arch/arm64/include/asm/arch_gicv3.h | 2 +- arch/arm64/include/asm/sysreg.h | 4 ++-- arch/arm64/kvm/vgic-sys-reg-v3.c | 2 +- virt/kvm/arm/hyp/vgic-v3-sr.c | 4 ++-- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h index 1a98bc8..8cef47f 100644 --- a/arch/arm64/include/asm/arch_gicv3.h +++ b/arch/arm64/include/asm/arch_gicv3.h @@ -89,7 +89,7 @@ static inline void gic_write_ctlr(u32 val) static inline void gic_write_grpen1(u32 val) { - write_sysreg_s(val, SYS_ICC_GRPEN1_EL1); + write_sysreg_s(val, SYS_ICC_IGRPEN1_EL1); isb(); } diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index c4d48e4..b9e88ac 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -195,8 +195,8 @@ #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3) #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4) #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5) -#define SYS_ICC_GRPEN0_EL1 sys_reg(3, 0, 12, 12, 6) -#define SYS_ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) +#define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6) +#define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) #define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1) #define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4) diff --git a/arch/arm64/kvm/vgic-sys-reg-v3.c b/arch/arm64/kvm/vgic-sys-reg-v3.c index 79f37e3..8daa883 100644 --- a/arch/arm64/kvm/vgic-sys-reg-v3.c +++ b/arch/arm64/kvm/vgic-sys-reg-v3.c @@ -296,7 +296,7 @@ static bool access_gic_sre(struct kvm_vcpu *vcpu, struct sys_reg_params *p, { Op0(3), Op1(0), CRn(12), CRm(12), Op2(5), access_gic_sre }, /* ICC_IGRPEN0_EL1 */ { Op0(3), Op1(0), CRn(12), CRm(12), Op2(6), access_gic_grpen0 }, - /* ICC_GRPEN1_EL1 */ + /* ICC_IGRPEN1_EL1 */ { Op0(3), Op1(0), CRn(12), CRm(12), Op2(7), access_gic_grpen1 }, }; diff --git a/virt/kvm/arm/hyp/vgic-v3-sr.c b/virt/kvm/arm/hyp/vgic-v3-sr.c index 3c6b7d4..163beab 100644 --- a/virt/kvm/arm/hyp/vgic-v3-sr.c +++ b/virt/kvm/arm/hyp/vgic-v3-sr.c @@ -972,7 +972,7 @@ int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu) case SYS_ICC_EOIR1_EL1: fn = __vgic_v3_write_eoir; break; - case SYS_ICC_GRPEN1_EL1: + case SYS_ICC_IGRPEN1_EL1: if (is_read) fn = __vgic_v3_read_igrpen1; else @@ -1016,7 +1016,7 @@ int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu) case SYS_ICC_HPPIR1_EL1: fn = __vgic_v3_read_hppir; break; - case SYS_ICC_GRPEN0_EL1: + case SYS_ICC_IGRPEN0_EL1: if (is_read) fn = __vgic_v3_read_igrpen0; else -- 1.9.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 1/2] arm64/kvm: sysreg: fix typo'd SYS_ICC_IGRPEN*_EL1 @ 2017-06-05 13:20 ` Mark Rutland 0 siblings, 0 replies; 10+ messages in thread From: Mark Rutland @ 2017-06-05 13:20 UTC (permalink / raw) To: linux-arm-kernel Per ARM DDI 0487B.a, the registers are named ICC_IGRPEN*_EL1 rather than ICC_GRPEN*_EL1. Correct our mnemonics and comments to match, before we add more GICv3 register definitions. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Christoffer Dall <christoffer.dall@linaro.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: kvmarm at lists.cs.columbia.edu --- arch/arm64/include/asm/arch_gicv3.h | 2 +- arch/arm64/include/asm/sysreg.h | 4 ++-- arch/arm64/kvm/vgic-sys-reg-v3.c | 2 +- virt/kvm/arm/hyp/vgic-v3-sr.c | 4 ++-- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h index 1a98bc8..8cef47f 100644 --- a/arch/arm64/include/asm/arch_gicv3.h +++ b/arch/arm64/include/asm/arch_gicv3.h @@ -89,7 +89,7 @@ static inline void gic_write_ctlr(u32 val) static inline void gic_write_grpen1(u32 val) { - write_sysreg_s(val, SYS_ICC_GRPEN1_EL1); + write_sysreg_s(val, SYS_ICC_IGRPEN1_EL1); isb(); } diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index c4d48e4..b9e88ac 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -195,8 +195,8 @@ #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3) #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4) #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5) -#define SYS_ICC_GRPEN0_EL1 sys_reg(3, 0, 12, 12, 6) -#define SYS_ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) +#define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6) +#define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) #define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1) #define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4) diff --git a/arch/arm64/kvm/vgic-sys-reg-v3.c b/arch/arm64/kvm/vgic-sys-reg-v3.c index 79f37e3..8daa883 100644 --- a/arch/arm64/kvm/vgic-sys-reg-v3.c +++ b/arch/arm64/kvm/vgic-sys-reg-v3.c @@ -296,7 +296,7 @@ static bool access_gic_sre(struct kvm_vcpu *vcpu, struct sys_reg_params *p, { Op0(3), Op1(0), CRn(12), CRm(12), Op2(5), access_gic_sre }, /* ICC_IGRPEN0_EL1 */ { Op0(3), Op1(0), CRn(12), CRm(12), Op2(6), access_gic_grpen0 }, - /* ICC_GRPEN1_EL1 */ + /* ICC_IGRPEN1_EL1 */ { Op0(3), Op1(0), CRn(12), CRm(12), Op2(7), access_gic_grpen1 }, }; diff --git a/virt/kvm/arm/hyp/vgic-v3-sr.c b/virt/kvm/arm/hyp/vgic-v3-sr.c index 3c6b7d4..163beab 100644 --- a/virt/kvm/arm/hyp/vgic-v3-sr.c +++ b/virt/kvm/arm/hyp/vgic-v3-sr.c @@ -972,7 +972,7 @@ int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu) case SYS_ICC_EOIR1_EL1: fn = __vgic_v3_write_eoir; break; - case SYS_ICC_GRPEN1_EL1: + case SYS_ICC_IGRPEN1_EL1: if (is_read) fn = __vgic_v3_read_igrpen1; else @@ -1016,7 +1016,7 @@ int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu) case SYS_ICC_HPPIR1_EL1: fn = __vgic_v3_read_hppir; break; - case SYS_ICC_GRPEN0_EL1: + case SYS_ICC_IGRPEN0_EL1: if (is_read) fn = __vgic_v3_read_igrpen0; else -- 1.9.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/2] arm64/kvm: vgic: use SYS_DESC() 2017-06-05 13:19 ` Mark Rutland @ 2017-06-05 13:20 ` Mark Rutland -1 siblings, 0 replies; 10+ messages in thread From: Mark Rutland @ 2017-06-05 13:20 UTC (permalink / raw) To: linux-arm-kernel; +Cc: marc.zyngier, catalin.marinas, will.deacon, kvmarm Almost all of the arm64 KVM code uses the sysreg mnemonics for AArch64 register descriptions. Move the last straggler over. To match what we do for SYS_ICH_AP*R*_EL2, the SYS_ICC_AP*R*_EL1 mnemonics are expanded in <asm/sysreg.h>. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Christoffer Dall <christoffer.dall@linaro.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: kvmarm@lists.cs.columbia.edu --- arch/arm64/include/asm/sysreg.h | 8 +++++++ arch/arm64/kvm/vgic-sys-reg-v3.c | 45 ++++++++++++++-------------------------- 2 files changed, 23 insertions(+), 30 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index b9e88ac..932029d 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -185,7 +185,15 @@ #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2) #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3) #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n) +#define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0) +#define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1) +#define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2) +#define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3) #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n) +#define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0) +#define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1) +#define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2) +#define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3) #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1) #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3) #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) diff --git a/arch/arm64/kvm/vgic-sys-reg-v3.c b/arch/arm64/kvm/vgic-sys-reg-v3.c index 8daa883..158da1f 100644 --- a/arch/arm64/kvm/vgic-sys-reg-v3.c +++ b/arch/arm64/kvm/vgic-sys-reg-v3.c @@ -268,36 +268,21 @@ static bool access_gic_sre(struct kvm_vcpu *vcpu, struct sys_reg_params *p, return true; } static const struct sys_reg_desc gic_v3_icc_reg_descs[] = { - /* ICC_PMR_EL1 */ - { Op0(3), Op1(0), CRn(4), CRm(6), Op2(0), access_gic_pmr }, - /* ICC_BPR0_EL1 */ - { Op0(3), Op1(0), CRn(12), CRm(8), Op2(3), access_gic_bpr0 }, - /* ICC_AP0R0_EL1 */ - { Op0(3), Op1(0), CRn(12), CRm(8), Op2(4), access_gic_ap0r }, - /* ICC_AP0R1_EL1 */ - { Op0(3), Op1(0), CRn(12), CRm(8), Op2(5), access_gic_ap0r }, - /* ICC_AP0R2_EL1 */ - { Op0(3), Op1(0), CRn(12), CRm(8), Op2(6), access_gic_ap0r }, - /* ICC_AP0R3_EL1 */ - { Op0(3), Op1(0), CRn(12), CRm(8), Op2(7), access_gic_ap0r }, - /* ICC_AP1R0_EL1 */ - { Op0(3), Op1(0), CRn(12), CRm(9), Op2(0), access_gic_ap1r }, - /* ICC_AP1R1_EL1 */ - { Op0(3), Op1(0), CRn(12), CRm(9), Op2(1), access_gic_ap1r }, - /* ICC_AP1R2_EL1 */ - { Op0(3), Op1(0), CRn(12), CRm(9), Op2(2), access_gic_ap1r }, - /* ICC_AP1R3_EL1 */ - { Op0(3), Op1(0), CRn(12), CRm(9), Op2(3), access_gic_ap1r }, - /* ICC_BPR1_EL1 */ - { Op0(3), Op1(0), CRn(12), CRm(12), Op2(3), access_gic_bpr1 }, - /* ICC_CTLR_EL1 */ - { Op0(3), Op1(0), CRn(12), CRm(12), Op2(4), access_gic_ctlr }, - /* ICC_SRE_EL1 */ - { Op0(3), Op1(0), CRn(12), CRm(12), Op2(5), access_gic_sre }, - /* ICC_IGRPEN0_EL1 */ - { Op0(3), Op1(0), CRn(12), CRm(12), Op2(6), access_gic_grpen0 }, - /* ICC_IGRPEN1_EL1 */ - { Op0(3), Op1(0), CRn(12), CRm(12), Op2(7), access_gic_grpen1 }, + { SYS_DESC(SYS_ICC_PMR_EL1), access_gic_pmr }, + { SYS_DESC(SYS_ICC_BPR0_EL1), access_gic_bpr0 }, + { SYS_DESC(SYS_ICC_AP0R0_EL1), access_gic_ap0r }, + { SYS_DESC(SYS_ICC_AP0R1_EL1), access_gic_ap0r }, + { SYS_DESC(SYS_ICC_AP0R2_EL1), access_gic_ap0r }, + { SYS_DESC(SYS_ICC_AP0R3_EL1), access_gic_ap0r }, + { SYS_DESC(SYS_ICC_AP1R0_EL1), access_gic_ap1r }, + { SYS_DESC(SYS_ICC_AP1R1_EL1), access_gic_ap1r }, + { SYS_DESC(SYS_ICC_AP1R2_EL1), access_gic_ap1r }, + { SYS_DESC(SYS_ICC_AP1R3_EL1), access_gic_ap1r }, + { SYS_DESC(SYS_ICC_BPR1_EL1), access_gic_bpr1 }, + { SYS_DESC(SYS_ICC_CTLR_EL1), access_gic_ctlr }, + { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, + { SYS_DESC(SYS_ICC_IGRPEN0_EL1), access_gic_grpen0 }, + { SYS_DESC(SYS_ICC_IGRPEN1_EL1), access_gic_grpen1 }, }; int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, bool is_write, u64 id, -- 1.9.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/2] arm64/kvm: vgic: use SYS_DESC() @ 2017-06-05 13:20 ` Mark Rutland 0 siblings, 0 replies; 10+ messages in thread From: Mark Rutland @ 2017-06-05 13:20 UTC (permalink / raw) To: linux-arm-kernel Almost all of the arm64 KVM code uses the sysreg mnemonics for AArch64 register descriptions. Move the last straggler over. To match what we do for SYS_ICH_AP*R*_EL2, the SYS_ICC_AP*R*_EL1 mnemonics are expanded in <asm/sysreg.h>. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Christoffer Dall <christoffer.dall@linaro.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: kvmarm at lists.cs.columbia.edu --- arch/arm64/include/asm/sysreg.h | 8 +++++++ arch/arm64/kvm/vgic-sys-reg-v3.c | 45 ++++++++++++++-------------------------- 2 files changed, 23 insertions(+), 30 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index b9e88ac..932029d 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -185,7 +185,15 @@ #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2) #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3) #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n) +#define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0) +#define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1) +#define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2) +#define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3) #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n) +#define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0) +#define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1) +#define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2) +#define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3) #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1) #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3) #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) diff --git a/arch/arm64/kvm/vgic-sys-reg-v3.c b/arch/arm64/kvm/vgic-sys-reg-v3.c index 8daa883..158da1f 100644 --- a/arch/arm64/kvm/vgic-sys-reg-v3.c +++ b/arch/arm64/kvm/vgic-sys-reg-v3.c @@ -268,36 +268,21 @@ static bool access_gic_sre(struct kvm_vcpu *vcpu, struct sys_reg_params *p, return true; } static const struct sys_reg_desc gic_v3_icc_reg_descs[] = { - /* ICC_PMR_EL1 */ - { Op0(3), Op1(0), CRn(4), CRm(6), Op2(0), access_gic_pmr }, - /* ICC_BPR0_EL1 */ - { Op0(3), Op1(0), CRn(12), CRm(8), Op2(3), access_gic_bpr0 }, - /* ICC_AP0R0_EL1 */ - { Op0(3), Op1(0), CRn(12), CRm(8), Op2(4), access_gic_ap0r }, - /* ICC_AP0R1_EL1 */ - { Op0(3), Op1(0), CRn(12), CRm(8), Op2(5), access_gic_ap0r }, - /* ICC_AP0R2_EL1 */ - { Op0(3), Op1(0), CRn(12), CRm(8), Op2(6), access_gic_ap0r }, - /* ICC_AP0R3_EL1 */ - { Op0(3), Op1(0), CRn(12), CRm(8), Op2(7), access_gic_ap0r }, - /* ICC_AP1R0_EL1 */ - { Op0(3), Op1(0), CRn(12), CRm(9), Op2(0), access_gic_ap1r }, - /* ICC_AP1R1_EL1 */ - { Op0(3), Op1(0), CRn(12), CRm(9), Op2(1), access_gic_ap1r }, - /* ICC_AP1R2_EL1 */ - { Op0(3), Op1(0), CRn(12), CRm(9), Op2(2), access_gic_ap1r }, - /* ICC_AP1R3_EL1 */ - { Op0(3), Op1(0), CRn(12), CRm(9), Op2(3), access_gic_ap1r }, - /* ICC_BPR1_EL1 */ - { Op0(3), Op1(0), CRn(12), CRm(12), Op2(3), access_gic_bpr1 }, - /* ICC_CTLR_EL1 */ - { Op0(3), Op1(0), CRn(12), CRm(12), Op2(4), access_gic_ctlr }, - /* ICC_SRE_EL1 */ - { Op0(3), Op1(0), CRn(12), CRm(12), Op2(5), access_gic_sre }, - /* ICC_IGRPEN0_EL1 */ - { Op0(3), Op1(0), CRn(12), CRm(12), Op2(6), access_gic_grpen0 }, - /* ICC_IGRPEN1_EL1 */ - { Op0(3), Op1(0), CRn(12), CRm(12), Op2(7), access_gic_grpen1 }, + { SYS_DESC(SYS_ICC_PMR_EL1), access_gic_pmr }, + { SYS_DESC(SYS_ICC_BPR0_EL1), access_gic_bpr0 }, + { SYS_DESC(SYS_ICC_AP0R0_EL1), access_gic_ap0r }, + { SYS_DESC(SYS_ICC_AP0R1_EL1), access_gic_ap0r }, + { SYS_DESC(SYS_ICC_AP0R2_EL1), access_gic_ap0r }, + { SYS_DESC(SYS_ICC_AP0R3_EL1), access_gic_ap0r }, + { SYS_DESC(SYS_ICC_AP1R0_EL1), access_gic_ap1r }, + { SYS_DESC(SYS_ICC_AP1R1_EL1), access_gic_ap1r }, + { SYS_DESC(SYS_ICC_AP1R2_EL1), access_gic_ap1r }, + { SYS_DESC(SYS_ICC_AP1R3_EL1), access_gic_ap1r }, + { SYS_DESC(SYS_ICC_BPR1_EL1), access_gic_bpr1 }, + { SYS_DESC(SYS_ICC_CTLR_EL1), access_gic_ctlr }, + { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, + { SYS_DESC(SYS_ICC_IGRPEN0_EL1), access_gic_grpen0 }, + { SYS_DESC(SYS_ICC_IGRPEN1_EL1), access_gic_grpen1 }, }; int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, bool is_write, u64 id, -- 1.9.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 0/2] arm64/kvm: use SYS_REG_DESC() for VGIC-v3 2017-06-05 13:19 ` Mark Rutland @ 2017-06-06 13:46 ` Christoffer Dall -1 siblings, 0 replies; 10+ messages in thread From: Christoffer Dall @ 2017-06-06 13:46 UTC (permalink / raw) To: Mark Rutland Cc: marc.zyngier, catalin.marinas, will.deacon, linux-arm-kernel, kvmarm Hi Mark, On Mon, Jun 05, 2017 at 02:19:59PM +0100, Mark Rutland wrote: > While looking around, I spotted that the VGIC-v3 code still uses open-coded SYS > encodings. These patches migrate said code to use common <asm/sysreg.h> > mnemonics, as we do for the rest of the AArch64 sysregs. > > This is based on Marc's kvm-arm64/gicv3-cpuif-mediated-access branch [1]. Patches look good to me. I can apply them after we apply [1] if Catalin/Will are ok with this. Thanks, -Christoffer > > [1] git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git kvm-arm64/gicv3-cpuif-mediated-access > > Mark Rutland (2): > arm64/kvm: sysreg: fix typo'd SYS_ICC_IGRPEN*_EL1 > arm64/kvm: vgic: use SYS_DESC() > > arch/arm64/include/asm/arch_gicv3.h | 2 +- > arch/arm64/include/asm/sysreg.h | 12 ++++++++-- > arch/arm64/kvm/vgic-sys-reg-v3.c | 45 +++++++++++++------------------------ > virt/kvm/arm/hyp/vgic-v3-sr.c | 4 ++-- > 4 files changed, 28 insertions(+), 35 deletions(-) > > -- > 1.9.1 > ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 0/2] arm64/kvm: use SYS_REG_DESC() for VGIC-v3 @ 2017-06-06 13:46 ` Christoffer Dall 0 siblings, 0 replies; 10+ messages in thread From: Christoffer Dall @ 2017-06-06 13:46 UTC (permalink / raw) To: linux-arm-kernel Hi Mark, On Mon, Jun 05, 2017 at 02:19:59PM +0100, Mark Rutland wrote: > While looking around, I spotted that the VGIC-v3 code still uses open-coded SYS > encodings. These patches migrate said code to use common <asm/sysreg.h> > mnemonics, as we do for the rest of the AArch64 sysregs. > > This is based on Marc's kvm-arm64/gicv3-cpuif-mediated-access branch [1]. Patches look good to me. I can apply them after we apply [1] if Catalin/Will are ok with this. Thanks, -Christoffer > > [1] git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git kvm-arm64/gicv3-cpuif-mediated-access > > Mark Rutland (2): > arm64/kvm: sysreg: fix typo'd SYS_ICC_IGRPEN*_EL1 > arm64/kvm: vgic: use SYS_DESC() > > arch/arm64/include/asm/arch_gicv3.h | 2 +- > arch/arm64/include/asm/sysreg.h | 12 ++++++++-- > arch/arm64/kvm/vgic-sys-reg-v3.c | 45 +++++++++++++------------------------ > virt/kvm/arm/hyp/vgic-v3-sr.c | 4 ++-- > 4 files changed, 28 insertions(+), 35 deletions(-) > > -- > 1.9.1 > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 0/2] arm64/kvm: use SYS_REG_DESC() for VGIC-v3 2017-06-06 13:46 ` Christoffer Dall @ 2017-06-06 14:46 ` Will Deacon -1 siblings, 0 replies; 10+ messages in thread From: Will Deacon @ 2017-06-06 14:46 UTC (permalink / raw) To: Christoffer Dall; +Cc: marc.zyngier, catalin.marinas, linux-arm-kernel, kvmarm On Tue, Jun 06, 2017 at 03:46:34PM +0200, Christoffer Dall wrote: > Hi Mark, > > On Mon, Jun 05, 2017 at 02:19:59PM +0100, Mark Rutland wrote: > > While looking around, I spotted that the VGIC-v3 code still uses open-coded SYS > > encodings. These patches migrate said code to use common <asm/sysreg.h> > > mnemonics, as we do for the rest of the AArch64 sysregs. > > > > This is based on Marc's kvm-arm64/gicv3-cpuif-mediated-access branch [1]. > > Patches look good to me. I can apply them after we apply [1] if > Catalin/Will are ok with this. Fine by me. Acked-by: Will Deacon <will.deacon@arm.com> if you need it. Will ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 0/2] arm64/kvm: use SYS_REG_DESC() for VGIC-v3 @ 2017-06-06 14:46 ` Will Deacon 0 siblings, 0 replies; 10+ messages in thread From: Will Deacon @ 2017-06-06 14:46 UTC (permalink / raw) To: linux-arm-kernel On Tue, Jun 06, 2017 at 03:46:34PM +0200, Christoffer Dall wrote: > Hi Mark, > > On Mon, Jun 05, 2017 at 02:19:59PM +0100, Mark Rutland wrote: > > While looking around, I spotted that the VGIC-v3 code still uses open-coded SYS > > encodings. These patches migrate said code to use common <asm/sysreg.h> > > mnemonics, as we do for the rest of the AArch64 sysregs. > > > > This is based on Marc's kvm-arm64/gicv3-cpuif-mediated-access branch [1]. > > Patches look good to me. I can apply them after we apply [1] if > Catalin/Will are ok with this. Fine by me. Acked-by: Will Deacon <will.deacon@arm.com> if you need it. Will ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2017-06-06 14:46 UTC | newest] Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2017-06-05 13:19 [PATCH 0/2] arm64/kvm: use SYS_REG_DESC() for VGIC-v3 Mark Rutland 2017-06-05 13:19 ` Mark Rutland 2017-06-05 13:20 ` [PATCH 1/2] arm64/kvm: sysreg: fix typo'd SYS_ICC_IGRPEN*_EL1 Mark Rutland 2017-06-05 13:20 ` Mark Rutland 2017-06-05 13:20 ` [PATCH 2/2] arm64/kvm: vgic: use SYS_DESC() Mark Rutland 2017-06-05 13:20 ` Mark Rutland 2017-06-06 13:46 ` [PATCH 0/2] arm64/kvm: use SYS_REG_DESC() for VGIC-v3 Christoffer Dall 2017-06-06 13:46 ` Christoffer Dall 2017-06-06 14:46 ` Will Deacon 2017-06-06 14:46 ` Will Deacon
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