[PATCH 00/27] DC Linux Patches Jun 9, 2017

[PATCH 00/27] DC Linux Patches Jun 9, 2017

[Harry Wentland]

 * Universal cursor plane
 * Bunch of Raven fixes
 * Couple of fixes for IGT

Amy Zhang (3):
  drm/amd/display: Add function to get PSR state
  drm/amd/display: Refactor to call set PSR wait loop in dce_dmcu
    instead of dce_clocks
  drm/amd/display: Fix DRR Enable on Desktop

Andrey Grodzovsky (2):
  drm/amd/display: Universal cursor plane hook-up.
  drm/amd/display: Remove redundant member from amdgpu_plane.

Anthony Koo (1):
  drm/amd/display: Temporary disable BTR FreeSync support for now

Charlene Liu (1):
  drm/amd/display: fix single link black screen

Corbin McElhanney (2):
  drm/amd/display: Don't update surface if dimensions are 0
  drm/amd/display: Add assertion for invalid surface dimensions

Dmytro Laktyushkin (8):
  drm/amd/display: allow taking split pipes during resource mapping
  drm/amd/display: fix surface attachment handling of pipe split
  drm/amd/display: fix mpo + split pipe aquisition failure
  drm/amd/display: clean up mpc programing during fe reset
  drm/amd/display: fix mpc alpha programming
  drm/amd/display: propagate surface alpha setting from OS to DC
  drm/amd/display: fix enable_optc_clock reg_wait timeouts
  drm/amd/display: add bw logging for dcn

Harry Wentland (1):
  drm/amd/display: No need to get property before set

Hersen Wu (2):
  drm/amd/display: Enable DCN clock gating
  drm/amd/display: remove disable_clk_gate debug flag for DCN

Leo (Sunpeng) Li (1):
  drm/amd/display: Remove unsupported RGB formats

Tony Cheng (1):
  drm/amd/display: disable forced stutter disable after programming
    watermark

Vitaly Prosyak (1):
  drm/amd/display: RV stereo support

Yongqiang Sun (2):
  drm/amd/display: Use surface update inuse for pending check.
  drm/amd/display: disable dcc when reset front end.

Zeyu Fan (2):
  drm/amd/display: Add function to log connectivity
  drm/amd/display: Call program_gamut explicitly instead of entire
    set_plane

 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  |   2 +-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c  |   6 +
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c    | 274 +++++--------
 .../gpu/drm/amd/display/dc/basics/log_helpers.c    |   3 +
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c   | 138 +++++++
 drivers/gpu/drm/amd/display/dc/core/dc.c           |  26 +-
 drivers/gpu/drm/amd/display/dc/core/dc_debug.c     |  42 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link.c      |  65 +--
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  |  90 +++--
 drivers/gpu/drm/amd/display/dc/dc.h                |  29 +-
 drivers/gpu/drm/amd/display/dc/dc_helper.c         |   8 +-
 drivers/gpu/drm/amd/display/dc/dc_types.h          | 103 ++++-
 drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c    |  41 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c      |  64 +++
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h      |   8 +
 .../amd/display/dc/dce110/dce110_hw_sequencer.c    |  42 ++
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 435 ++++++++++++++-------
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c |  30 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h |  38 ++
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c   | 201 ++++------
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h   |   6 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |   7 +-
 .../amd/display/dc/dcn10/dcn10_timing_generator.c  | 192 +++++----
 .../amd/display/dc/dcn10/dcn10_timing_generator.h  |   5 +
 drivers/gpu/drm/amd/display/dc/dm_helpers.h        |   4 +
 drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h       |   4 +
 .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h   | 101 -----
 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h  |   3 +
 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h        |  19 +-
 .../drm/amd/display/dc/inc/hw/timing_generator.h   |  12 +
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |   7 +
 .../gpu/drm/amd/display/include/logger_interface.h |   4 +
 .../drm/amd/display/modules/freesync/freesync.c    | 102 +++--
 .../gpu/drm/amd/display/modules/inc/mod_freesync.h |   3 +-
 34 files changed, 1305 insertions(+), 809 deletions(-)

-- 
2.11.0

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[PATCH 01/27] drm/amd/display: allow taking split pipes during resource mapping

[Harry Wentland]

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

Change-Id: I77bed9c869b8edfd9dfde6855b1d27f0850df2d8
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 43 +++++++++++++++++++++--
 1 file changed, 41 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 50b0385bffce..feb0f5d385b2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1406,6 +1406,42 @@ static void calculate_phy_pix_clks(struct validate_context *context)
 	}
 }
 
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+static int acquire_first_split_pipe(
+		struct resource_context *res_ctx,
+		const struct resource_pool *pool,
+		struct core_stream *stream)
+{
+	int i;
+
+	for (i = 0; i < pool->pipe_count; i++) {
+		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
+
+		if (pipe_ctx->top_pipe &&
+				pipe_ctx->top_pipe->surface == pipe_ctx->surface) {
+			int mpc_idx = pipe_ctx->mpc_idx;
+
+			pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
+			pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
+
+			memset(pipe_ctx, 0, sizeof(*pipe_ctx));
+			pipe_ctx->tg = pool->timing_generators[i];
+			pipe_ctx->mi = pool->mis[i];
+			pipe_ctx->ipp = pool->ipps[i];
+			pipe_ctx->xfm = pool->transforms[i];
+			pipe_ctx->opp = pool->opps[i];
+			pipe_ctx->dis_clk = pool->display_clock;
+			pipe_ctx->pipe_idx = i;
+			pipe_ctx->mpc_idx = mpc_idx;
+
+			pipe_ctx->stream = stream;
+			return i;
+		}
+	}
+	return -1;
+}
+#endif
+
 enum dc_status resource_map_pool_resources(
 		const struct core_dc *dc,
 		struct validate_context *context,
@@ -1477,8 +1513,11 @@ enum dc_status resource_map_pool_resources(
 		if (old_context && resource_is_stream_unchanged(old_context, stream))
 			continue;
 		/* acquire new resources */
-		pipe_idx = acquire_first_free_pipe(
-				&context->res_ctx, pool, stream);
+		pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+		if (pipe_idx < 0)
+			acquire_first_split_pipe(&context->res_ctx, pool, stream);
+#endif
 		if (pipe_idx < 0)
 			return DC_NO_CONTROLLER_RESOURCE;
 
-- 
2.11.0

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[PATCH 02/27] drm/amd/display: fix surface attachment handling of pipe split

[Harry Wentland]

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

Change-Id: I5f81333e21658cdd1a5c9932cfc91d6e9a56ec02
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 35 +++++++----------------
 1 file changed, 10 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index feb0f5d385b2..c97d0d1d471e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -894,24 +894,6 @@ enum dc_status resource_build_scaling_params_for_context(
 	return DC_OK;
 }
 
-static void detach_surfaces_for_stream(
-		struct validate_context *context,
-		const struct resource_pool *pool,
-		const struct dc_stream *dc_stream)
-{
-	int i;
-	struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
-
-	for (i = 0; i < pool->pipe_count; i++) {
-		struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i];
-		if (cur_pipe->stream == stream) {
-			cur_pipe->surface = NULL;
-			cur_pipe->top_pipe = NULL;
-			cur_pipe->bottom_pipe = NULL;
-		}
-	}
-}
-
 struct pipe_ctx *find_idle_secondary_pipe(
 		struct resource_context *res_ctx,
 		const struct resource_pool *pool)
@@ -1004,9 +986,11 @@ static void release_free_pipes_for_stream(
 	struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
 
 	for (i = MAX_PIPES - 1; i >= 0; i--) {
+		/* never release the topmost pipe*/
 		if (res_ctx->pipe_ctx[i].stream == stream &&
+				res_ctx->pipe_ctx[i].top_pipe &&
 				!res_ctx->pipe_ctx[i].surface) {
-			res_ctx->pipe_ctx[i].stream = NULL;
+			memset(&res_ctx->pipe_ctx[i], 0, sizeof(struct pipe_ctx));
 		}
 	}
 }
@@ -1021,6 +1005,7 @@ bool resource_attach_surfaces_to_context(
 	int i;
 	struct pipe_ctx *tail_pipe;
 	struct dc_stream_status *stream_status = NULL;
+	struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
 
 
 	if (surface_count > MAX_SURFACE_NUM) {
@@ -1043,7 +1028,12 @@ bool resource_attach_surfaces_to_context(
 	for (i = 0; i < surface_count; i++)
 		dc_surface_retain(surfaces[i]);
 
-	detach_surfaces_for_stream(context, pool, dc_stream);
+	/* detach surfaces from pipes */
+	for (i = 0; i < pool->pipe_count; i++)
+		if (context->res_ctx.pipe_ctx[i].stream == stream) {
+			context->res_ctx.pipe_ctx[i].surface = NULL;
+			context->res_ctx.pipe_ctx[i].bottom_pipe = NULL;
+		}
 
 	/* release existing surfaces*/
 	for (i = 0; i < stream_status->surface_count; i++)
@@ -1052,11 +1042,6 @@ bool resource_attach_surfaces_to_context(
 	for (i = surface_count; i < stream_status->surface_count; i++)
 		stream_status->surfaces[i] = NULL;
 
-	stream_status->surface_count = 0;
-
-	if (surface_count == 0)
-		return true;
-
 	tail_pipe = NULL;
 	for (i = 0; i < surface_count; i++) {
 		struct core_surface *surface = DC_SURFACE_TO_CORE(surfaces[i]);
-- 
2.11.0

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[PATCH 03/27] drm/amd/display: fix mpo + split pipe aquisition failure

[Harry Wentland]

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

Change-Id: Ic0d15333971c33102b887b8c425b6c4231d03d8b
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 80 +++++++++++++----------
 1 file changed, 44 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index c97d0d1d471e..236c8e9c0f6a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -995,6 +995,43 @@ static void release_free_pipes_for_stream(
 	}
 }
 
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+static int acquire_first_split_pipe(
+		struct resource_context *res_ctx,
+		const struct resource_pool *pool,
+		struct core_stream *stream)
+{
+	int i;
+
+	for (i = 0; i < pool->pipe_count; i++) {
+		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
+
+		if (pipe_ctx->top_pipe &&
+				pipe_ctx->top_pipe->surface == pipe_ctx->surface) {
+			int mpc_idx = pipe_ctx->mpc_idx;
+
+			pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
+			if (pipe_ctx->bottom_pipe)
+				pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
+
+			memset(pipe_ctx, 0, sizeof(*pipe_ctx));
+			pipe_ctx->tg = pool->timing_generators[i];
+			pipe_ctx->mi = pool->mis[i];
+			pipe_ctx->ipp = pool->ipps[i];
+			pipe_ctx->xfm = pool->transforms[i];
+			pipe_ctx->opp = pool->opps[i];
+			pipe_ctx->dis_clk = pool->display_clock;
+			pipe_ctx->pipe_idx = i;
+			pipe_ctx->mpc_idx = mpc_idx;
+
+			pipe_ctx->stream = stream;
+			return i;
+		}
+	}
+	return -1;
+}
+#endif
+
 bool resource_attach_surfaces_to_context(
 		const struct dc_surface * const *surfaces,
 		int surface_count,
@@ -1048,6 +1085,13 @@ bool resource_attach_surfaces_to_context(
 		struct pipe_ctx *free_pipe = acquire_free_pipe_for_stream(
 				context, pool, dc_stream);
 
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+		if (!free_pipe) {
+			int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
+			if (pipe_idx >= 0)
+				free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
+		}
+#endif
 		if (!free_pipe) {
 			stream_status->surfaces[i] = NULL;
 			return false;
@@ -1391,42 +1435,6 @@ static void calculate_phy_pix_clks(struct validate_context *context)
 	}
 }
 
-#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-static int acquire_first_split_pipe(
-		struct resource_context *res_ctx,
-		const struct resource_pool *pool,
-		struct core_stream *stream)
-{
-	int i;
-
-	for (i = 0; i < pool->pipe_count; i++) {
-		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
-
-		if (pipe_ctx->top_pipe &&
-				pipe_ctx->top_pipe->surface == pipe_ctx->surface) {
-			int mpc_idx = pipe_ctx->mpc_idx;
-
-			pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
-			pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
-
-			memset(pipe_ctx, 0, sizeof(*pipe_ctx));
-			pipe_ctx->tg = pool->timing_generators[i];
-			pipe_ctx->mi = pool->mis[i];
-			pipe_ctx->ipp = pool->ipps[i];
-			pipe_ctx->xfm = pool->transforms[i];
-			pipe_ctx->opp = pool->opps[i];
-			pipe_ctx->dis_clk = pool->display_clock;
-			pipe_ctx->pipe_idx = i;
-			pipe_ctx->mpc_idx = mpc_idx;
-
-			pipe_ctx->stream = stream;
-			return i;
-		}
-	}
-	return -1;
-}
-#endif
-
 enum dc_status resource_map_pool_resources(
 		const struct core_dc *dc,
 		struct validate_context *context,
-- 
2.11.0

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[PATCH 04/27] drm/amd/display: Universal cursor plane hook-up.

[Harry Wentland]

From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>

Switch from legacy cursor to DRM cursor plane. Cursor
is not an actual plane but more of a subplane of each
pipe. Bind a DRM cursor plane instance to each CRTC.
Eliminate seperate FB object allocation for cursor and
clean  dm_crtc_cursor_set.

Change-Id: I1d716ffe1427c27ef070acabd850f6fd56864415
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c    | 242 ++++++++-------------
 1 file changed, 91 insertions(+), 151 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 939ea8df3440..75102fd1f1f7 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -137,127 +137,27 @@ static void dm_set_cursor(
 	}
 }
 
-static int dm_crtc_unpin_cursor_bo_old(
-	struct amdgpu_crtc *amdgpu_crtc)
-{
-	struct amdgpu_bo *robj;
-	int ret = 0;
-
-	if (NULL != amdgpu_crtc && NULL != amdgpu_crtc->cursor_bo) {
-		robj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
-
-		ret = amdgpu_bo_reserve(robj, false);
-
-		if (likely(ret == 0)) {
-			ret = amdgpu_bo_unpin(robj);
-
-			if (unlikely(ret != 0)) {
-				DRM_ERROR(
-					"%s: unpin failed (ret=%d), bo %p\n",
-					__func__,
-					ret,
-					amdgpu_crtc->cursor_bo);
-			}
-
-			amdgpu_bo_unreserve(robj);
-		} else {
-			DRM_ERROR(
-				"%s: reserve failed (ret=%d), bo %p\n",
-				__func__,
-				ret,
-				amdgpu_crtc->cursor_bo);
-		}
-
-		drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
-		amdgpu_crtc->cursor_bo = NULL;
-	}
-
-	return ret;
-}
-
-static int dm_crtc_pin_cursor_bo_new(
-	struct drm_crtc *crtc,
-	struct drm_file *file_priv,
-	uint32_t handle,
-	struct amdgpu_bo **ret_obj)
-{
-	struct amdgpu_crtc *amdgpu_crtc;
-	struct amdgpu_bo *robj;
-	struct drm_gem_object *obj;
-	int ret = -EINVAL;
-
-	if (NULL != crtc) {
-		struct drm_device *dev = crtc->dev;
-		struct amdgpu_device *adev = dev->dev_private;
-		uint64_t gpu_addr;
-
-		amdgpu_crtc = to_amdgpu_crtc(crtc);
-
-		obj = drm_gem_object_lookup(file_priv, handle);
-
-		if (!obj) {
-			DRM_ERROR(
-				"Cannot find cursor object %x for crtc %d\n",
-				handle,
-				amdgpu_crtc->crtc_id);
-			goto release;
-		}
-		robj = gem_to_amdgpu_bo(obj);
-
-		ret  = amdgpu_bo_reserve(robj, false);
-
-		if (unlikely(ret != 0)) {
-			drm_gem_object_unreference_unlocked(obj);
-		DRM_ERROR("dm_crtc_pin_cursor_bo_new ret %x, handle %x\n",
-				 ret, handle);
-			goto release;
-		}
-
-		ret = amdgpu_bo_pin_restricted(robj, AMDGPU_GEM_DOMAIN_VRAM, 0,
-						adev->mc.visible_vram_size,
-						&gpu_addr);
-
-		if (ret == 0) {
-			amdgpu_crtc->cursor_addr = gpu_addr;
-			*ret_obj  = robj;
-		}
-		amdgpu_bo_unreserve(robj);
-		if (ret)
-			drm_gem_object_unreference_unlocked(obj);
-
-	}
-release:
-
-	return ret;
-}
-
 static int dm_crtc_cursor_set(
 	struct drm_crtc *crtc,
-	struct drm_file *file_priv,
-	uint32_t handle,
+	uint64_t address,
 	uint32_t width,
 	uint32_t height)
 {
-	struct amdgpu_bo *new_cursor_bo;
 	struct dc_cursor_position position;
 
 	int ret;
 
 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
-
 	ret		= EINVAL;
-	new_cursor_bo	= NULL;
 
 	DRM_DEBUG_KMS(
-	"%s: crtc_id=%d with handle %d and size %d to %d, bo_object %p\n",
+		"%s: crtc_id=%d with size %d to %d \n",
 		__func__,
 		amdgpu_crtc->crtc_id,
-		handle,
 		width,
-		height,
-		amdgpu_crtc->cursor_bo);
+		height);
 
-	if (!handle) {
+	if (!address) {
 		/* turn off cursor */
 		position.enable = false;
 		position.x = 0;
@@ -269,8 +169,6 @@ static int dm_crtc_cursor_set(
 				amdgpu_crtc->stream,
 				&position);
 		}
-		/*unpin old cursor buffer and update cache*/
-		ret = dm_crtc_unpin_cursor_bo_old(amdgpu_crtc);
 		goto release;
 
 	}
@@ -284,21 +182,9 @@ static int dm_crtc_cursor_set(
 			height);
 		goto release;
 	}
-	/*try to pin new cursor bo*/
-	ret = dm_crtc_pin_cursor_bo_new(crtc, file_priv, handle, &new_cursor_bo);
-	/*if map not successful then return an error*/
-	if (ret)
-		goto release;
 
 	/*program new cursor bo to hardware*/
-	dm_set_cursor(amdgpu_crtc, amdgpu_crtc->cursor_addr, width, height);
-
-	/*un map old, not used anymore cursor bo ,
-	 * return memory and mapping back */
-	dm_crtc_unpin_cursor_bo_old(amdgpu_crtc);
-
-	/*assign new cursor bo to our internal cache*/
-	amdgpu_crtc->cursor_bo = &new_cursor_bo->gem_base;
+	dm_set_cursor(amdgpu_crtc, address, width, height);
 
 release:
 	return ret;
@@ -360,23 +246,6 @@ static int dm_crtc_cursor_move(struct drm_crtc *crtc,
 	return 0;
 }
 
-static void dm_crtc_cursor_reset(struct drm_crtc *crtc)
-{
-	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
-
-	DRM_DEBUG_KMS(
-		"%s: with cursor_bo %p\n",
-		__func__,
-		amdgpu_crtc->cursor_bo);
-
-	if (amdgpu_crtc->cursor_bo && amdgpu_crtc->stream) {
-		dm_set_cursor(
-		amdgpu_crtc,
-		amdgpu_crtc->cursor_addr,
-		amdgpu_crtc->cursor_width,
-		amdgpu_crtc->cursor_height);
-	}
-}
 static bool fill_rects_from_plane_state(
 	const struct drm_plane_state *state,
 	struct dc_surface *surface)
@@ -1172,8 +1041,6 @@ static int amdgpu_atomic_helper_page_flip(struct drm_crtc *crtc,
 /* Implemented only the options currently availible for the driver */
 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
 	.reset = drm_atomic_helper_crtc_reset,
-	.cursor_set = dm_crtc_cursor_set,
-	.cursor_move = dm_crtc_cursor_move,
 	.destroy = amdgpu_dm_crtc_destroy,
 	.gamma_set = drm_atomic_helper_legacy_gamma_set,
 	.set_config = drm_atomic_helper_set_config,
@@ -1742,6 +1609,18 @@ static int dm_plane_helper_prepare_fb(
 	}
 
 	amdgpu_bo_ref(rbo);
+
+	/* It's a hack for s3 since in 4.9 kernel filter out cursor buffer
+	 * prepare and cleanup in drm_atomic_helper_prepare_planes
+	 * and drm_atomic_helper_cleanup_planes because fb doens't in s3.
+	 * IN 4.10 kernel this code should be removed and amdgpu_device_suspend
+	 * code touching fram buffers should be avoided for DC.
+	 */
+	if (plane->type == DRM_PLANE_TYPE_CURSOR) {
+		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_state->crtc);
+
+		acrtc->cursor_bo = obj;
+	}
 	return 0;
 }
 
@@ -1839,6 +1718,10 @@ static uint32_t yuv_formats[] = {
 	DRM_FORMAT_NV21,
 };
 
+static const u32 cursor_formats[] = {
+	DRM_FORMAT_ARGB8888
+};
+
 int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
 			struct amdgpu_plane *aplane,
 			unsigned long possible_crtcs)
@@ -1869,7 +1752,14 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
 				aplane->plane_type, NULL);
 		break;
 	case DRM_PLANE_TYPE_CURSOR:
-		DRM_ERROR("KMS: Cursor plane not implemented.");
+		res = drm_universal_plane_init(
+				dm->adev->ddev,
+				&aplane->base,
+				possible_crtcs,
+				&dm_plane_funcs,
+				cursor_formats,
+				ARRAY_SIZE(cursor_formats),
+				aplane->plane_type, NULL);
 		break;
 	}
 
@@ -1882,9 +1772,18 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
 			struct drm_plane *plane,
 			uint32_t crtc_index)
 {
-	struct amdgpu_crtc *acrtc;
+	struct amdgpu_crtc *acrtc = NULL;
+	struct amdgpu_plane *cursor_plane;
+
 	int res = -ENOMEM;
 
+	cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
+	if (!cursor_plane)
+		goto fail;
+
+	cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR;
+	res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
+
 	acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
 	if (!acrtc)
 		goto fail;
@@ -1893,7 +1792,7 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
 			dm->ddev,
 			&acrtc->base,
 			plane,
-			NULL,
+			&cursor_plane->base,
 			&amdgpu_dm_crtc_funcs, NULL);
 
 	if (res)
@@ -1911,12 +1810,17 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
 	drm_mode_crtc_set_gamma_size(&acrtc->base, 256);
 
 	return 0;
+
 fail:
-	kfree(acrtc);
+	if (acrtc)
+		kfree(acrtc);
+	if (cursor_plane)
+		kfree(cursor_plane);
 	acrtc->crtc_id = -1;
 	return res;
 }
 
+
 static int to_drm_connector_type(enum signal_type st)
 {
 	switch (st) {
@@ -2431,6 +2335,34 @@ static void remove_stream(struct amdgpu_device *adev, struct amdgpu_crtc *acrtc)
 	acrtc->enabled = false;
 }
 
+static void handle_cursor_update(
+		struct drm_plane *plane,
+		struct drm_plane_state *old_plane_state)
+{
+	if (!plane->state->fb && !old_plane_state->fb)
+		return;
+
+	/* Check if it's a cursor on/off update or just cursor move*/
+	if (plane->state->fb == old_plane_state->fb)
+		dm_crtc_cursor_move(
+				plane->state->crtc,
+				plane->state->crtc_x,
+				plane->state->crtc_y);
+	else {
+		struct amdgpu_framebuffer *afb =
+				to_amdgpu_framebuffer(plane->state->fb);
+		dm_crtc_cursor_set(
+				(!!plane->state->fb) ?
+						plane->state->crtc :
+						old_plane_state->crtc,
+				(!!plane->state->fb) ?
+						afb->address :
+						0,
+				plane->state->crtc_w,
+				plane->state->crtc_h);
+	}
+}
+
 
 /*
  * Executes flip
@@ -2522,6 +2454,11 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state,
 		struct dm_connector_state *con_state = NULL;
 		bool pflip_needed;
 
+		if (plane->type == DRM_PLANE_TYPE_CURSOR) {
+			handle_cursor_update(plane, old_plane_state);
+			continue;
+		}
+
 		if (!fb || !crtc || !crtc->state->active)
 			continue;
 
@@ -2806,7 +2743,6 @@ void amdgpu_dm_atomic_commit_tail(
 				adev->dm.freesync_module, &acrtc->stream, 1);
 
 		manage_dm_interrupts(adev, acrtc, true);
-		dm_crtc_cursor_reset(&acrtc->base);
 	}
 
 
@@ -3186,18 +3122,19 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 			}
 		}
 
+
 		/*
-		 * TODO revisit when removing commit action
-		 * and looking at atomic flags directly
+		 * Hack: Commit needs planes right now, specifically for gamma
+		 * TODO rework commit to check CRTC for gamma change
 		 */
+		if (crtc_state->color_mgmt_changed) {
 
-		/* commit needs planes right now (for gamma, eg.) */
-		/* TODO rework commit to chack crtc for gamma change */
-		ret = drm_atomic_add_affected_planes(state, crtc);
-		if (ret)
-			return ret;
+			ret = drm_atomic_add_affected_planes(state, crtc);
+			if (ret)
+				return ret;
 
-		ret = -EINVAL;
+			ret = -EINVAL;
+		}
 	}
 
 	/* Check scaling and undersacn changes*/
@@ -3252,6 +3189,9 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 			struct drm_crtc_state *crtc_state;
 			bool pflip_needed;
 
+			/*TODO Implement atomic check for cursor plane */
+			if (plane->type == DRM_PLANE_TYPE_CURSOR)
+				continue;
 
 			if (!fb || !crtc || crtc_set[i] != crtc ||
 				!crtc->state->planes_changed || !crtc->state->active)
-- 
2.11.0

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[PATCH 05/27] drm/amd/display: Add function to get PSR state

[Harry Wentland]

From: Amy Zhang <Amy.Zhang@amd.com>

Change-Id: I7359d5d7b3e6a0569863f6bea10dbf4199be172d
Signed-off-by: Amy Zhang <Amy.Zhang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 13 +++++++++++++
 drivers/gpu/drm/amd/display/dc/dc.h           |  2 ++
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c |  2 ++
 drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h  |  1 +
 4 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 79f3947a3ee1..318aaa762f31 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1444,6 +1444,19 @@ bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable)
 	return true;
 }
 
+bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state)
+{
+	struct core_link *link = DC_LINK_TO_CORE(dc_link);
+	struct dc_context *ctx = link->ctx;
+	struct core_dc *core_dc = DC_TO_CORE(ctx->dc);
+	struct dmcu *dmcu = core_dc->res_pool->dmcu;
+
+	if (dmcu != NULL && link->psr_enabled)
+		dmcu->funcs->get_psr_state(dmcu, psr_state);
+
+	return true;
+}
+
 bool dc_link_setup_psr(const struct dc_link *dc_link,
 		const struct dc_stream *stream, struct psr_config *psr_config)
 {
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index ce052d12a104..328bfcb7dbb8 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -702,6 +702,8 @@ bool dc_link_set_abm_disable(const struct dc_link *dc_link);
 
 bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable);
 
+bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state);
+
 bool dc_link_setup_psr(const struct dc_link *dc_link,
 		const struct dc_stream *stream, struct psr_config *psr_config);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
index c58328cd787b..03b51e256e21 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
@@ -470,6 +470,7 @@ static const struct dmcu_funcs dce_funcs = {
 	.load_iram = dce_dmcu_load_iram,
 	.set_psr_enable = dce_dmcu_set_psr_enable,
 	.setup_psr = dce_dmcu_setup_psr,
+	.get_psr_state = dce_get_dmcu_psr_state
 };
 
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
@@ -477,6 +478,7 @@ static const struct dmcu_funcs dcn10_funcs = {
 	.load_iram = dcn10_dmcu_load_iram,
 	.set_psr_enable = dcn10_dmcu_set_psr_enable,
 	.setup_psr = dcn10_dmcu_setup_psr,
+	.get_psr_state = dcn10_get_dmcu_psr_state
 };
 #endif
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
index 656cfdc79891..dff0babb5cf7 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
@@ -41,6 +41,7 @@ struct dmcu_funcs {
 	void (*setup_psr)(struct dmcu *dmcu,
 			struct core_link *link,
 			struct psr_context *psr_context);
+	void (*get_psr_state)(struct dmcu *dmcu, uint32_t *psr_state);
 };
 
 #endif
-- 
2.11.0

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[PATCH 06/27] drm/amd/display: Remove redundant member from amdgpu_plane.

[Harry Wentland]

From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>

Change-Id: I074023eba6cec3ae1a1c06f2b4472abc7826df61
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c       | 2 +-
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 8 ++++----
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index c26bf362cc57..3fb6a6583309 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1209,7 +1209,7 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 			DRM_ERROR("KMS: Failed to allocate surface\n");
 			goto fail_free_planes;
 		}
-		mode_info->planes[i]->plane_type = mode_info->plane_type[i];
+		mode_info->planes[i]->base.type = mode_info->plane_type[i];
 		if (amdgpu_dm_plane_init(dm, mode_info->planes[i], 0xff)) {
 			DRM_ERROR("KMS: Failed to initialize plane\n");
 			goto fail_free_planes;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 75102fd1f1f7..37b2c61fb2fb 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -1728,7 +1728,7 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
 {
 	int res = -EPERM;
 
-	switch (aplane->plane_type) {
+	switch (aplane->base.type) {
 	case DRM_PLANE_TYPE_PRIMARY:
 		aplane->base.format_default = true;
 
@@ -1739,7 +1739,7 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
 				&dm_plane_funcs,
 				rgb_formats,
 				ARRAY_SIZE(rgb_formats),
-				aplane->plane_type, NULL);
+				aplane->base.type, NULL);
 		break;
 	case DRM_PLANE_TYPE_OVERLAY:
 		res = drm_universal_plane_init(
@@ -1749,7 +1749,7 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
 				&dm_plane_funcs,
 				yuv_formats,
 				ARRAY_SIZE(yuv_formats),
-				aplane->plane_type, NULL);
+				aplane->base.type, NULL);
 		break;
 	case DRM_PLANE_TYPE_CURSOR:
 		res = drm_universal_plane_init(
@@ -1759,7 +1759,7 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
 				&dm_plane_funcs,
 				cursor_formats,
 				ARRAY_SIZE(cursor_formats),
-				aplane->plane_type, NULL);
+				aplane->base.type, NULL);
 		break;
 	}
 
-- 
2.11.0

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[PATCH 07/27] drm/amd/display: Enable DCN clock gating

[Harry Wentland]

From: Hersen Wu <hersenxs.wu@amd.com>

Change-Id: I8979a9b8403115d6638dda415954596c9823f555
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 68 +++++++++++++++++-----
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |  4 --
 2 files changed, 53 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 62a77f48d437..24c1a0f5febe 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -516,12 +516,14 @@ static void power_on_plane(
 	/* disable clock power gating */
 
 	/* DCCG_GATE_DISABLE_CNTL only has one instance */
-	HWSEQ_REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL,
-			DISPCLK_DCCG_GATE_DISABLE, 1,
-			DPPCLK_GATE_DISABLE, 1);
-	/* DCFCLK_CNTL only has one instance */
-	HWSEQ_REG_UPDATE(DCFCLK_CNTL,
-			DCFCLK_GATE_DIS, 1);
+	if (ctx->dc->debug.disable_clock_gate) {
+		HWSEQ_REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL,
+				DISPCLK_DCCG_GATE_DISABLE, 1,
+				DPPCLK_GATE_DISABLE, 1);
+		/* DCFCLK_CNTL only has one instance */
+		HWSEQ_REG_UPDATE(DCFCLK_CNTL,
+				DCFCLK_GATE_DIS, 1);
+	}
 
 	HWSEQ_REG_SET(DC_IP_REQUEST_CNTL,
 			IP_REQUEST_EN, 1);
@@ -533,14 +535,6 @@ static void power_on_plane(
 	if (ctx->dc->debug.disable_clock_gate) {
 		HWSEQ_REG_UPDATE(DCCG_GATE_DISABLE_CNTL,
 				DISPCLK_DCCG_GATE_DISABLE, 0);
-	} else {
-		/* DCCG_GATE_DISABLE_CNTL only has one instance. inst_offset = 0 */
-		HWSEQ_REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL,
-				DISPCLK_DCCG_GATE_DISABLE, 0,
-				DPPCLK_GATE_DISABLE, 0);
-		/* DCFCLK_CNTL only has one instance. inst_offset = 0 */
-		HWSEQ_REG_UPDATE(DCFCLK_CNTL,
-				DCFCLK_GATE_DIS, 0);
 	}
 }
 
@@ -666,14 +660,58 @@ static void init_hw(struct core_dc *dc)
 			FD(DIO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE), 0,
 			FD(DIO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE), 0);
 
+	if (!dc->public.debug.disable_clock_gate) {
+		/* enable all DCN clock gating */
+		generic_reg_set_soc15(dc->ctx, 0, DCCG_GATE_DISABLE_CNTL, 19,
+				FD(DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE), 0);
+
+		generic_reg_set_soc15(dc->ctx, 0, DCCG_GATE_DISABLE_CNTL2, 14,
+				FD(DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE), 0);
+
+		generic_reg_update_soc15(dc->ctx, 0, DCFCLK_CNTL, 1,
+				FD(DCFCLK_CNTL__DCFCLK_GATE_DIS), 0);
+	}
+
 	/* This power gating should be one-time program for DAL.
 	 * It can only change by registry key
 	 * TODO: new task will for this.
 	 * if power gating is disable, power_on_plane and power_off_plane
 	 * should be skip. Otherwise, hand will be met in power_off_plane
 	 */
-
 	enable_power_gating_plane(dc->ctx, true);
+
+
 }
 
 static enum dc_status dcn10_prog_pixclk_crtc_otg(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 94cd7a9b0b19..660cb43fd3bc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -426,8 +426,6 @@ static const struct resource_caps res_cap = {
 
 static const struct dc_debug debug_defaults_drv = {
 		.disable_dcc = false,
-		.disable_dpp_power_gate = false,
-		.disable_hubp_power_gate = false,
 		.disable_dmcu = true,
 		.force_abm_enable = false,
 		.timing_trace = false,
@@ -440,8 +438,6 @@ static const struct dc_debug debug_defaults_drv = {
 };
 
 static const struct dc_debug debug_defaults_diags = {
-		.disable_dpp_power_gate = false,
-		.disable_hubp_power_gate = false,
 		.disable_clock_gate = true,
 		.disable_dmcu = true,
 		.force_abm_enable = false,
-- 
2.11.0

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[PATCH 08/27] drm/amd/display: Remove unsupported RGB formats

[Harry Wentland]

From: "Leo (Sunpeng) Li" <sunpeng.li@amd.com>

Do not broadcast (to DRM) unsupported RGB formats.

Change-Id: If6ab99f7056b518c5c2a77b1320ea9d2f0349776
Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 37b2c61fb2fb..5d44687c144c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -1698,11 +1698,6 @@ static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
  * check will succeed, and let DC to implement proper check
  */
 static uint32_t rgb_formats[] = {
-	DRM_FORMAT_XRGB4444,
-	DRM_FORMAT_ARGB4444,
-	DRM_FORMAT_RGBA4444,
-	DRM_FORMAT_ARGB1555,
-	DRM_FORMAT_RGB565,
 	DRM_FORMAT_RGB888,
 	DRM_FORMAT_XRGB8888,
 	DRM_FORMAT_ARGB8888,
-- 
2.11.0

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[PATCH 09/27] drm/amd/display: Don't update surface if dimensions are 0

[Harry Wentland]

From: Corbin McElhanney <corbin.mcelhanney@amd.com>

Change-Id: I787bcc4f2b4b3c5a13108c2451cd9f99d67d931f
Signed-off-by: Corbin McElhanney <corbin.mcelhanney@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 323a5e706908..976229eb2492 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1250,8 +1250,15 @@ void dc_update_surfaces_and_stream(struct dc *dc,
 		}
 	}
 
-	/* only proceed if we need to make a surface update */
-	if (!srf_updates)
+	/* do not perform surface update if surface has invalid dimensions
+	 * (all zero) and no scaling_info is provided
+	 */
+	if (surface_count > 0 &&
+			srf_updates->surface->src_rect.width == 0 &&
+			srf_updates->surface->src_rect.height == 0 &&
+			srf_updates->surface->dst_rect.width == 0 &&
+			srf_updates->surface->dst_rect.height == 0 &&
+			!srf_updates->scaling_info)
 		return;
 
 	update_type = dc_check_update_surfaces_for_stream(
-- 
2.11.0

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[PATCH 10/27] drm/amd/display: clean up mpc programing during fe reset

[Harry Wentland]

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

Change-Id: Ifd533c0316333c4179cf7b8bf725eeba5a4c09b2
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 14 ++++----------
 1 file changed, 4 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 24c1a0f5febe..877e2b6a7dd5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -868,16 +868,10 @@ static void reset_front_end_for_pipe(
 	 */
 	tree_cfg = &dc->current_context->res_ctx.mpc_tree[pipe_ctx->mpc_idx];
 
-	if (pipe_ctx->top_pipe == NULL)
-		dcn10_delete_mpc_tree(mpc, tree_cfg);
-	else {
-		if (dcn10_remove_dpp(mpc, tree_cfg, pipe_ctx->pipe_idx))
-			pipe_ctx->top_pipe->bottom_pipe = NULL;
-		else {
-			dm_logger_write(dc->ctx->logger, LOG_RESOURCE,
-				"%s: failed to find dpp to be removed!\n",
-				__func__);
-		}
+	if (!dcn10_remove_dpp(mpc, tree_cfg, pipe_ctx->pipe_idx)) {
+		dm_logger_write(dc->ctx->logger, LOG_RESOURCE,
+			"%s: failed to find dpp to be removed!\n",
+			__func__);
 	}
 
 	pipe_ctx->top_pipe = NULL;
-- 
2.11.0

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[PATCH 11/27] drm/amd/display: Add assertion for invalid surface dimensions

[Harry Wentland]

From: Corbin McElhanney <corbin.mcelhanney@amd.com>

Change-Id: Ie7e9e43fc522fcd35cc8eef11a021b1984b9c9c6
Signed-off-by: Corbin McElhanney <corbin.mcelhanney@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 976229eb2492..f5102b644942 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1258,8 +1258,10 @@ void dc_update_surfaces_and_stream(struct dc *dc,
 			srf_updates->surface->src_rect.height == 0 &&
 			srf_updates->surface->dst_rect.width == 0 &&
 			srf_updates->surface->dst_rect.height == 0 &&
-			!srf_updates->scaling_info)
+			!srf_updates->scaling_info) {
+		ASSERT(false);
 		return;
+	}
 
 	update_type = dc_check_update_surfaces_for_stream(
 			dc, srf_updates, surface_count, stream_update, stream_status);
-- 
2.11.0

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[PATCH 12/27] drm/amd/display: remove disable_clk_gate debug flag for DCN

[Harry Wentland]

From: Hersen Wu <hersenxs.wu@amd.com>

Change-Id: I6143202c8b6c3c730c098fc4cabcbc89d3cf8908
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 30 ----------------------
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |  1 -
 2 files changed, 31 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 877e2b6a7dd5..0e677f9db96a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -397,19 +397,6 @@ static void enable_power_gating_plane(
 	HWSEQ_REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
 	HWSEQ_REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
 	HWSEQ_REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
-
-	if (ctx->dc->debug.disable_clock_gate) {
-		/* probably better to just write entire register to 0xffff to
-		 * ensure all clock gating is disabled
-		 */
-		HWSEQ_REG_UPDATE_3(DCCG_GATE_DISABLE_CNTL,
-				DISPCLK_R_DCCG_GATE_DISABLE, 1,
-				DPREFCLK_R_DCCG_GATE_DISABLE, 1,
-				REFCLK_R_DIG_GATE_DISABLE, 1);
-		HWSEQ_REG_UPDATE(DCFCLK_CNTL,
-				DCFCLK_GATE_DIS, 1);
-	}
-
 }
 
 static void dpp_pg_control(
@@ -513,29 +500,12 @@ static void power_on_plane(
 {
 	uint32_t inst_offset = 0;
 
-	/* disable clock power gating */
-
-	/* DCCG_GATE_DISABLE_CNTL only has one instance */
-	if (ctx->dc->debug.disable_clock_gate) {
-		HWSEQ_REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL,
-				DISPCLK_DCCG_GATE_DISABLE, 1,
-				DPPCLK_GATE_DISABLE, 1);
-		/* DCFCLK_CNTL only has one instance */
-		HWSEQ_REG_UPDATE(DCFCLK_CNTL,
-				DCFCLK_GATE_DIS, 1);
-	}
-
 	HWSEQ_REG_SET(DC_IP_REQUEST_CNTL,
 			IP_REQUEST_EN, 1);
 	dpp_pg_control(ctx, plane_id, true);
 	hubp_pg_control(ctx, plane_id, true);
 	HWSEQ_REG_SET(DC_IP_REQUEST_CNTL,
 			IP_REQUEST_EN, 0);
-
-	if (ctx->dc->debug.disable_clock_gate) {
-		HWSEQ_REG_UPDATE(DCCG_GATE_DISABLE_CNTL,
-				DISPCLK_DCCG_GATE_DISABLE, 0);
-	}
 }
 
 /* fully check bios enabledisplaypowergating table. dal only need dce init
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 660cb43fd3bc..e527d10b3e1f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -438,7 +438,6 @@ static const struct dc_debug debug_defaults_drv = {
 };
 
 static const struct dc_debug debug_defaults_diags = {
-		.disable_clock_gate = true,
 		.disable_dmcu = true,
 		.force_abm_enable = false,
 		.timing_trace = true,
-- 
2.11.0

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[PATCH 13/27] drm/amd/display: disable forced stutter disable after programming watermark

[Harry Wentland]

From: Tony Cheng <tony.cheng@amd.com>

vbios will disable stutter pre-OS.  driver re-enable after programming watermark

Change-Id: Iefec5991ca9c776156b7c8c5f20fbd938102019b
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 5 +++++
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 6 ++++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
index da2f99dcd766..3e3fcf2395ae 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
@@ -582,6 +582,7 @@ static void program_watermarks(
 		unsigned int refclk_mhz)
 {
 	struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
+	uint32_t force_en = mem_input->ctx->dc->debug.disable_stutter ? 1 : 0;
 	/*
 	 * Need to clamp to max of the register values (i.e. no wrap)
 	 * for dcn1, all wm registers are 21-bit wide
@@ -793,6 +794,10 @@ static void program_watermarks(
 	REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
 			DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 68);
 
+	REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
+			DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, 0,
+			DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, force_en);
+
 #if 0
 	REG_UPDATE_2(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
 			DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, 1,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
index 48b313b213c0..37683d072b42 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
@@ -127,6 +127,7 @@
 	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D),\
 	SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\
 	SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\
+	SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\
 	SR(DCHUBBUB_ARB_SAT_LEVEL),\
 	SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\
 	/* todo:  get these from GVM instead of reading registers ourselves */\
@@ -239,6 +240,7 @@ struct dcn_mi_registers {
 	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D;
 	uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;
 	uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL;
+	uint32_t DCHUBBUB_ARB_DRAM_STATE_CNTL;
 	uint32_t DCHUBBUB_ARB_SAT_LEVEL;
 	uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND;
 
@@ -381,6 +383,8 @@ struct dcn_mi_registers {
 	MI_SF(DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh),\
 	MI_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh),\
 	MI_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh),\
+	MI_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh),\
+	MI_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh),\
 	MI_SF(DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh),\
 	MI_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh),\
 	/* todo:  get these from GVM instead of reading registers ourselves */\
@@ -515,6 +519,8 @@ struct dcn_mi_registers {
 	type SDPIF_AGP_TOP;\
 	type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\
 	type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\
+	type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE;\
+	type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE;\
 	type DCHUBBUB_ARB_SAT_LEVEL;\
 	type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\
 	/* todo:  get these from GVM instead of reading registers ourselves */\
-- 
2.11.0

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[PATCH 14/27] drm/amd/display: fix mpc alpha programming

[Harry Wentland]

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

Change-Id: Idee0068c6c94980de931803cb25dcf17bf774560
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  78 +++-----
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c   | 201 +++++++++------------
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h   |   6 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h        |  19 +-
 4 files changed, 115 insertions(+), 189 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 0e677f9db96a..447f6bf4644c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -125,14 +125,8 @@ static void lock_otg_master_update(
 	HWSEQ_REG_UPDATE(OTG0_OTG_GLOBAL_CONTROL0,
 			OTG_MASTER_UPDATE_LOCK_SEL, inst);
 
-	/* unlock master locker */
 	HWSEQ_REG_UPDATE(OTG0_OTG_MASTER_UPDATE_LOCK,
 			OTG_MASTER_UPDATE_LOCK, 1);
-
-	/* wait for unlock happens */
-	if (!wait_reg(ctx, inst_offset, OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, 1))
-			BREAK_TO_DEBUGGER();
-
 }
 
 static bool unlock_master_tg_and_wait(
@@ -1562,8 +1556,9 @@ static void update_dchubp_dpp(
 	enum dc_color_space color_space;
 	struct tg_color black_color = {0};
 	struct dcn10_mpc *mpc = TO_DCN10_MPC(dc->res_pool->mpc);
-
-	struct pipe_ctx *cur_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
+	struct pipe_ctx *temp_pipe;
+	int i;
+	int tree_pos = 0;
 
 	/* depends on DML calculation, DPP clock value may change dynamically */
 	enable_dppclk(
@@ -1609,41 +1604,30 @@ static void update_dchubp_dpp(
 	/* TODO: build stream pipes group id. For now, use stream otg
 	 * id as pipe group id
 	 */
-	pipe_ctx->mpc_idx = pipe_ctx->tg->inst;
-	tree_cfg = &context->res_ctx.mpc_tree[pipe_ctx->mpc_idx];
-
-	/* enable when bottom pipe is present and
-	 * it does not share a surface with current pipe
-	 */
-	if (pipe_ctx->bottom_pipe && surface != pipe_ctx->bottom_pipe->surface) {
+	/*pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->surface->public.per_pixel_alpha;*/
+	if (pipe_ctx->bottom_pipe && surface != pipe_ctx->bottom_pipe->surface)
 		pipe_ctx->scl_data.lb_params.alpha_en = 1;
-		tree_cfg->mode = TOP_BLND;
-	} else {
+	else
 		pipe_ctx->scl_data.lb_params.alpha_en = 0;
-		tree_cfg->mode = TOP_PASSTHRU;
-	}
-	if (!pipe_ctx->top_pipe && !cur_pipe_ctx->bottom_pipe) {
-		/* primary pipe, set mpc tree index 0 only */
-		tree_cfg->num_pipes = 1;
+	pipe_ctx->mpc_idx = pipe_ctx->tg->inst;
+	tree_cfg = &context->res_ctx.mpc_tree[pipe_ctx->mpc_idx];
+	if (tree_cfg->num_pipes == 0) {
 		tree_cfg->opp_id = pipe_ctx->tg->inst;
-		tree_cfg->dpp[0] = pipe_ctx->pipe_idx;
-		tree_cfg->mpcc[0] = pipe_ctx->pipe_idx;
+		for (i = 0; i < MAX_PIPES; i++) {
+			tree_cfg->dpp[i] = 0xf;
+			tree_cfg->mpcc[i] = 0xf;
+		}
 	}
 
-	if (!cur_pipe_ctx->top_pipe && !pipe_ctx->top_pipe) {
-
-		if (!cur_pipe_ctx->bottom_pipe)
-			dcn10_set_mpc_tree(mpc, tree_cfg);
-
-	} else if (!cur_pipe_ctx->top_pipe && pipe_ctx->top_pipe) {
-
-		dcn10_add_dpp(mpc, tree_cfg,
-			pipe_ctx->pipe_idx, pipe_ctx->pipe_idx, 1);
-	} else {
-		/* nothing to be done here */
-		ASSERT(cur_pipe_ctx->top_pipe && pipe_ctx->top_pipe);
-	}
+	for (temp_pipe = pipe_ctx->top_pipe;
+			temp_pipe != NULL; temp_pipe = temp_pipe->top_pipe)
+		tree_pos++;
 
+	tree_cfg->dpp[tree_pos] = pipe_ctx->pipe_idx;
+	tree_cfg->mpcc[tree_pos] = pipe_ctx->pipe_idx;
+	tree_cfg->per_pixel_alpha[tree_pos] = pipe_ctx->scl_data.lb_params.alpha_en;
+	tree_cfg->num_pipes = tree_pos + 1;
+	dcn10_set_mpc_tree(mpc, tree_cfg);
 
 	color_space = pipe_ctx->stream->public.output_color_space;
 	color_space_to_black_color(dc, color_space, &black_color);
@@ -1680,18 +1664,15 @@ static void program_all_pipe_in_tree(
 {
 	unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;
 
-	if (pipe_ctx->surface->public.visible || pipe_ctx->top_pipe == NULL) {
-		dcn10_power_on_fe(dc, pipe_ctx, context);
+	if (pipe_ctx->top_pipe == NULL) {
 
 		/* lock otg_master_update to process all pipes associated with
 		 * this OTG. this is done only one time.
 		 */
-		if (pipe_ctx->top_pipe == NULL) {
-			/* watermark is for all pipes */
-			pipe_ctx->mi->funcs->program_watermarks(
-					pipe_ctx->mi, &context->bw.dcn.watermarks, ref_clk_mhz);
-			lock_otg_master_update(dc->ctx, pipe_ctx->tg->inst);
-		}
+		/* watermark is for all pipes */
+		pipe_ctx->mi->funcs->program_watermarks(
+				pipe_ctx->mi, &context->bw.dcn.watermarks, ref_clk_mhz);
+		lock_otg_master_update(dc->ctx, pipe_ctx->tg->inst);
 
 		pipe_ctx->tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
 		pipe_ctx->tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
@@ -1702,12 +1683,11 @@ static void program_all_pipe_in_tree(
 		pipe_ctx->tg->funcs->program_global_sync(
 				pipe_ctx->tg);
 		pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, !is_pipe_tree_visible(pipe_ctx));
+	}
 
-
-
+	if (pipe_ctx->surface->public.visible) {
+		dcn10_power_on_fe(dc, pipe_ctx, context);
 		update_dchubp_dpp(dc, pipe_ctx, context);
-
-		/* Only support one plane for now. */
 	}
 
 	if (pipe_ctx->bottom_pipe != NULL)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
index cb22cd130e1a..58f80114e36b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
@@ -36,6 +36,9 @@
 #define FN(reg_name, field_name) \
 	mpc->mpc_shift->field_name, mpc->mpc_mask->field_name
 
+#define MODE_TOP_ONLY 1
+#define MODE_BLEND 3
+
 /* Internal function to set mpc output mux */
 static void set_output_mux(struct dcn10_mpc *mpc,
 	uint8_t opp_id,
@@ -45,32 +48,7 @@ static void set_output_mux(struct dcn10_mpc *mpc,
 		REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
 				OPP_PIPE_CLOCK_EN, 1);
 
-	REG_SET(MUX[opp_id], 0,
-			MPC_OUT_MUX, mpcc_id);
-
-/*	TODO: Move to post when ready.
-   if (mpcc_id == 0xf) {
-		MPCC_REG_UPDATE(OPP_PIPE0_OPP_PIPE_CONTROL,
-				OPP_PIPE_CLOCK_EN, 0);
-	}
-*/
-}
-
-static void set_blend_mode(struct dcn10_mpc *mpc,
-	enum blend_mode mode,
-	uint8_t mpcc_id)
-{
-	/* Enable per-pixel alpha on this pipe */
-	if (mode == TOP_BLND)
-		REG_UPDATE_3(MPCC_CONTROL[mpcc_id],
-				MPCC_ALPHA_BLND_MODE, 0,
-				MPCC_ALPHA_MULTIPLIED_MODE, 0,
-				MPCC_BLND_ACTIVE_OVERLAP_ONLY, 0);
-	else
-		REG_UPDATE_3(MPCC_CONTROL[mpcc_id],
-				MPCC_ALPHA_BLND_MODE, 0,
-				MPCC_ALPHA_MULTIPLIED_MODE, 1,
-				MPCC_BLND_ACTIVE_OVERLAP_ONLY, 1);
+	REG_SET(MUX[opp_id], 0, MPC_OUT_MUX, mpcc_id);
 }
 
 void dcn10_set_mpc_background_color(struct dcn10_mpc *mpc,
@@ -121,44 +99,27 @@ void dcn10_set_mpc_tree(struct dcn10_mpc *mpc,
 			REG_SET(MPCC_BOT_SEL[mpcc_inst], 0,
 				MPCC_BOT_SEL, 0xF);
 
-			/* MPCC_CONTROL->MPCC_MODE */
 			REG_UPDATE(MPCC_CONTROL[mpcc_inst],
-					MPCC_MODE, tree_cfg->mode);
+					MPCC_MODE, MODE_TOP_ONLY);
 		} else {
 			REG_SET(MPCC_BOT_SEL[mpcc_inst], 0,
 				MPCC_BOT_SEL, tree_cfg->dpp[i+1]);
 
-			/* MPCC_CONTROL->MPCC_MODE */
 			REG_UPDATE(MPCC_CONTROL[mpcc_inst],
-					MPCC_MODE, 3);
+					MPCC_MODE, MODE_BLEND);
 		}
 
 		if (i == 0)
 			set_output_mux(
 				mpc, tree_cfg->opp_id, mpcc_inst);
 
-		set_blend_mode(mpc, tree_cfg->mode, mpcc_inst);
+		REG_UPDATE_2(MPCC_CONTROL[mpcc_inst],
+				MPCC_ALPHA_BLND_MODE,
+				tree_cfg->per_pixel_alpha[i] ? 0 : 2,
+				MPCC_ALPHA_MULTIPLIED_MODE, 0);
 	}
 }
 
-void dcn10_set_mpc_passthrough(struct dcn10_mpc *mpc,
-	uint8_t dpp_idx,
-	uint8_t mpcc_idx,
-	uint8_t opp_idx)
-{
-	struct mpc_tree_cfg tree_cfg = { 0 };
-
-	tree_cfg.num_pipes = 1;
-	tree_cfg.opp_id = opp_idx;
-	tree_cfg.mode = TOP_PASSTHRU;
-	/* TODO: FPGA bring up one MPC has only 1 DPP and 1 MPCC
-	 * For blend case, need fill mode DPP and cascade MPCC
-	 */
-	tree_cfg.dpp[0] = dpp_idx;
-	tree_cfg.mpcc[0] = mpcc_idx;
-	dcn10_set_mpc_tree(mpc, &tree_cfg);
-}
-
 /*
  * This is the function to remove current MPC tree specified by tree_cfg
  * Before invoke this function, ensure that master lock of OPTC specified
@@ -188,6 +149,7 @@ void dcn10_delete_mpc_tree(struct dcn10_mpc *mpc,
 		 */
 		tree_cfg->dpp[i] = 0xf;
 		tree_cfg->mpcc[i] = 0xf;
+		tree_cfg->per_pixel_alpha[i] = false;
 	}
 	set_output_mux(mpc, tree_cfg->opp_id, 0xf);
 	tree_cfg->opp_id = 0xf;
@@ -208,6 +170,7 @@ bool dcn10_remove_dpp(struct dcn10_mpc *mpc,
 	uint8_t idx)
 {
 	int i;
+	uint8_t mpcc_inst;
 	bool found = false;
 
 	/* find dpp_idx from dpp array of tree_cfg */
@@ -218,54 +181,53 @@ bool dcn10_remove_dpp(struct dcn10_mpc *mpc,
 		}
 	}
 
-	if (found) {
-		/* add remove dpp/mpcc pair into pending list */
+	if (!found) {
+		BREAK_TO_DEBUGGER();
+		return false;
+	}
+	mpcc_inst = tree_cfg->mpcc[i];
 
-		/* TODO FPGA AddToPendingList if empty from pseudo code
-		 * AddToPendingList(tree_cfg->dpp[i],tree_cfg->mpcc[i]);
-		 */
-		uint8_t mpcc_inst = tree_cfg->mpcc[i];
+	REG_SET(MPCC_OPP_ID[mpcc_inst], 0,
+			MPCC_OPP_ID, 0xf);
 
-		REG_SET(MPCC_OPP_ID[mpcc_inst], 0,
-				MPCC_OPP_ID, 0xf);
+	REG_SET(MPCC_TOP_SEL[mpcc_inst], 0,
+			MPCC_TOP_SEL, 0xf);
 
-		REG_SET(MPCC_TOP_SEL[mpcc_inst], 0,
-				MPCC_TOP_SEL, 0xf);
+	REG_SET(MPCC_BOT_SEL[mpcc_inst], 0,
+			MPCC_BOT_SEL, 0xf);
+
+	if (i == 0) {
+		if (tree_cfg->num_pipes > 1)
+			set_output_mux(mpc,
+				tree_cfg->opp_id, tree_cfg->mpcc[i+1]);
+		else
+			set_output_mux(mpc, tree_cfg->opp_id, 0xf);
+	} else if (i == tree_cfg->num_pipes-1) {
+		mpcc_inst = tree_cfg->mpcc[i - 1];
 
 		REG_SET(MPCC_BOT_SEL[mpcc_inst], 0,
 				MPCC_BOT_SEL, 0xF);
 
-		if (i == 0) {
-			if (tree_cfg->num_pipes > 1)
-				set_output_mux(mpc,
-					tree_cfg->opp_id, tree_cfg->mpcc[i+1]);
-			else
-				set_output_mux(mpc, tree_cfg->opp_id, 0xf);
-		} else if (i == tree_cfg->num_pipes-1) {
-			mpcc_inst = tree_cfg->mpcc[i - 1];
-
-			REG_SET(MPCC_BOT_SEL[mpcc_inst], 0,
-					MPCC_BOT_SEL, 0xF);
-
-			REG_UPDATE(MPCC_CONTROL[mpcc_inst],
-					MPCC_MODE, tree_cfg->mode);
-		} else {
-			mpcc_inst = tree_cfg->mpcc[i - 1];
+		/* prev mpc is now last, set to top only*/
+		REG_UPDATE(MPCC_CONTROL[mpcc_inst],
+				MPCC_MODE, MODE_TOP_ONLY);
+	} else {
+		mpcc_inst = tree_cfg->mpcc[i - 1];
 
-			REG_SET(MPCC_BOT_SEL[mpcc_inst], 0,
-				MPCC_BOT_SEL, tree_cfg->mpcc[i+1]);
-		}
-		set_blend_mode(mpc, tree_cfg->mode, mpcc_inst);
+		REG_SET(MPCC_BOT_SEL[mpcc_inst], 0,
+			MPCC_BOT_SEL, tree_cfg->mpcc[i+1]);
+	}
 
-		/* update tree_cfg structure */
-		while (i < tree_cfg->num_pipes - 1) {
-			tree_cfg->dpp[i] = tree_cfg->dpp[i+1];
-			tree_cfg->mpcc[i] = tree_cfg->mpcc[i+1];
-			i++;
-		}
-		tree_cfg->num_pipes--;
+	/* update tree_cfg structure */
+	while (i < tree_cfg->num_pipes - 1) {
+		tree_cfg->dpp[i] = tree_cfg->dpp[i+1];
+		tree_cfg->mpcc[i] = tree_cfg->mpcc[i+1];
+		tree_cfg->per_pixel_alpha[i] = tree_cfg->per_pixel_alpha[i+1];
+		i++;
 	}
-	return found;
+	tree_cfg->num_pipes--;
+
+	return true;
 }
 
 /* TODO FPGA: how to handle DPP?
@@ -284,14 +246,14 @@ void dcn10_add_dpp(struct dcn10_mpc *mpc,
 	struct mpc_tree_cfg *tree_cfg,
 	uint8_t dpp_idx,
 	uint8_t mpcc_idx,
+	uint8_t per_pixel_alpha,
 	uint8_t position)
 {
-	uint8_t temp;
-	uint8_t temp1;
+	uint8_t prev;
+	uint8_t next;
 
 	REG_SET(MPCC_OPP_ID[mpcc_idx], 0,
 			MPCC_OPP_ID, tree_cfg->opp_id);
-
 	REG_SET(MPCC_TOP_SEL[mpcc_idx], 0,
 			MPCC_TOP_SEL, dpp_idx);
 
@@ -299,70 +261,71 @@ void dcn10_add_dpp(struct dcn10_mpc *mpc,
 		/* idle dpp/mpcc is added to the top layer of tree */
 		REG_SET(MPCC_BOT_SEL[mpcc_idx], 0,
 				MPCC_BOT_SEL, tree_cfg->mpcc[0]);
-		REG_UPDATE(MPCC_CONTROL[mpcc_idx],
-				MPCC_MODE, 3);
 
+		/* bottom mpc is always top only */
+		REG_UPDATE(MPCC_CONTROL[mpcc_idx],
+				MPCC_MODE, MODE_TOP_ONLY);
 		/* opp will get new output. from new added mpcc */
 		set_output_mux(mpc, tree_cfg->opp_id, mpcc_idx);
 
-		set_blend_mode(mpc, tree_cfg->mode, mpcc_idx);
-
 	} else if (position == tree_cfg->num_pipes) {
 		/* idle dpp/mpcc is added to the bottom layer of tree */
 
 		/* get instance of previous bottom mpcc, set to middle layer */
-		temp = tree_cfg->mpcc[tree_cfg->num_pipes - 1];
+		prev = tree_cfg->mpcc[position - 1];
 
-		REG_SET(MPCC_BOT_SEL[temp], 0,
+		REG_SET(MPCC_BOT_SEL[prev], 0,
 				MPCC_BOT_SEL, mpcc_idx);
 
-		REG_UPDATE(MPCC_CONTROL[temp],
-				MPCC_MODE, 3);
+		/* all mpcs other than bottom need to blend */
+		REG_UPDATE(MPCC_CONTROL[prev],
+				MPCC_MODE, MODE_BLEND);
 
 		/* mpcc_idx become new bottom mpcc*/
 		REG_SET(MPCC_BOT_SEL[mpcc_idx], 0,
 				MPCC_BOT_SEL, 0xf);
 
+		/* bottom mpc is always top only */
 		REG_UPDATE(MPCC_CONTROL[mpcc_idx],
-				MPCC_MODE, tree_cfg->mode);
-
-		set_blend_mode(mpc, tree_cfg->mode, mpcc_idx);
+				MPCC_MODE, MODE_TOP_ONLY);
 	} else {
 		/* idle dpp/mpcc is added to middle of tree */
-		temp = tree_cfg->mpcc[position - 1];
-		temp1 = tree_cfg->mpcc[position];
+		prev = tree_cfg->mpcc[position - 1]; /* mpc a */
+		next = tree_cfg->mpcc[position]; /* mpc b */
 
-		/* new mpcc instance temp1 is added right after temp*/
-		REG_SET(MPCC_BOT_SEL[temp], 0,
+		/* connect mpc inserted below mpc a*/
+		REG_SET(MPCC_BOT_SEL[prev], 0,
 				MPCC_BOT_SEL, mpcc_idx);
 
-		/* mpcc_idx connect previous temp+1 to new mpcc */
-		REG_SET(MPCC_BOT_SEL[mpcc_idx], 0,
-				MPCC_BOT_SEL, temp1);
+		/* blend on mpc being inserted */
+		REG_UPDATE(MPCC_CONTROL[mpcc_idx],
+				MPCC_MODE, MODE_BLEND);
 
-		/* temp TODO: may not need*/
-		REG_UPDATE(MPCC_CONTROL[temp],
-				MPCC_MODE, 3);
+		/* Connect mpc b below one inserted */
+		REG_SET(MPCC_BOT_SEL[mpcc_idx], 0,
+				MPCC_BOT_SEL, next);
 
-		set_blend_mode(mpc, tree_cfg->mode, temp);
 	}
-
-	/* update tree_cfg structure */
-	temp = tree_cfg->num_pipes - 1;
+	/* premultiplied mode only if alpha is on for the layer*/
+	REG_UPDATE_2(MPCC_CONTROL[mpcc_idx],
+			MPCC_ALPHA_BLND_MODE,
+			tree_cfg->per_pixel_alpha[position] ? 0 : 2,
+			MPCC_ALPHA_MULTIPLIED_MODE, 0);
 
 	/*
 	 * iterating from the last mpc/dpp pair to the one being added, shift
 	 * them down one position
 	 */
-	while (temp > position) {
-		tree_cfg->dpp[temp + 1] = tree_cfg->dpp[temp];
-		tree_cfg->mpcc[temp + 1] = tree_cfg->mpcc[temp];
-		temp--;
+	for (next = tree_cfg->num_pipes; next > position; next--) {
+		tree_cfg->dpp[next] = tree_cfg->dpp[next - 1];
+		tree_cfg->mpcc[next] = tree_cfg->mpcc[next - 1];
+		tree_cfg->per_pixel_alpha[next] = tree_cfg->per_pixel_alpha[next - 1];
 	}
 
 	/* insert the new mpc/dpp pair into the tree_cfg*/
 	tree_cfg->dpp[position] = dpp_idx;
 	tree_cfg->mpcc[position] = mpcc_idx;
+	tree_cfg->per_pixel_alpha[position] = per_pixel_alpha;
 	tree_cfg->num_pipes++;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
index 6550b93c9254..3e4eb655e913 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
@@ -105,11 +105,6 @@ struct dcn10_mpc {
 	const struct dcn_mpc_mask *mpc_mask;
 };
 
-void dcn10_set_mpc_passthrough(struct dcn10_mpc *mpc,
-	uint8_t dpp_idx,
-	uint8_t mpcc_idx,
-	uint8_t opp_idx);
-
 void dcn10_delete_mpc_tree(struct dcn10_mpc *mpc,
 	struct mpc_tree_cfg *tree_cfg);
 
@@ -121,6 +116,7 @@ void dcn10_add_dpp(struct dcn10_mpc *mpc,
 	struct mpc_tree_cfg *tree_cfg,
 	uint8_t dpp_idx,
 	uint8_t mpcc_idx,
+	uint8_t per_pixel_alpha,
 	uint8_t position);
 
 void wait_mpcc_idle(struct dcn10_mpc *mpc,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
index 2e86ebe5eeda..ec1a201747f2 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
@@ -25,19 +25,6 @@
 #ifndef __DC_MPC_H__
 #define __DC_MPC_H__
 
-/* define the maximum number of pipes
- * MAX_NUM_PIPPES = MAX_PIPES defined in core_type.h
- */
-enum {
-	MAX_NUM_PIPPES = 6
-};
-
-enum blend_mode {
-	DIGI_BYPASS = 0,	/* digital bypass */
-	TOP_PASSTHRU,		/* top layer pass through */
-	TOP_BLND		/* top layer blend */
-};
-
 /* This structure define the mpc tree configuration
  * num_pipes - number of pipes of the tree
  * opp_id - instance id of OPP to drive MPC
@@ -60,10 +47,10 @@ struct mpc_tree_cfg {
 	uint8_t num_pipes;
 	uint8_t opp_id;
 	/* dpp pipes for blend */
-	uint8_t dpp[MAX_NUM_PIPPES];
+	uint8_t dpp[6];
 	/* mpcc insatnces for blend */
-	uint8_t mpcc[MAX_NUM_PIPPES];
-	enum blend_mode mode;
+	uint8_t mpcc[6];
+	bool per_pixel_alpha[6];
 };
 
 struct mpcc_blnd_cfg {
-- 
2.11.0

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[PATCH 15/27] drm/amd/display: Refactor to call set PSR wait loop in dce_dmcu instead of dce_clocks

[Harry Wentland]

From: Amy Zhang <Amy.Zhang@amd.com>

Change-Id: I61437d58382fd3bdb2b02d44f4b731148543ddc9
Signed-off-by: Amy Zhang <Amy.Zhang@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c      |  52 +++++------
 drivers/gpu/drm/amd/display/dc/dc.h                |   3 +-
 drivers/gpu/drm/amd/display/dc/dc_types.h          | 101 +++++++++++++++++++++
 drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c    |  41 ++-------
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c      |  66 +++++++++++++-
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h      |   8 ++
 drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h       |   3 +
 .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h   | 101 ---------------------
 8 files changed, 213 insertions(+), 162 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 318aaa762f31..b2c8b572d57f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1458,17 +1458,17 @@ bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state)
 }
 
 bool dc_link_setup_psr(const struct dc_link *dc_link,
-		const struct dc_stream *stream, struct psr_config *psr_config)
+		const struct dc_stream *stream, struct psr_config *psr_config,
+		struct psr_context *psr_context)
 {
 	struct core_link *link = DC_LINK_TO_CORE(dc_link);
 	struct dc_context *ctx = link->ctx;
 	struct core_dc *core_dc = DC_TO_CORE(ctx->dc);
 	struct dmcu *dmcu = core_dc->res_pool->dmcu;
 	struct core_stream *core_stream = DC_STREAM_TO_CORE(stream);
-	struct psr_context psr_context = {0};
 	int i;
 
-	psr_context.controllerId = CONTROLLER_ID_UNDEFINED;
+	psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
 
 	if (dc_link != NULL &&
 		dmcu != NULL) {
@@ -1503,9 +1503,9 @@ bool dc_link_setup_psr(const struct dc_link *dc_link,
 			&psr_configuration.raw,
 			sizeof(psr_configuration.raw));
 
-		psr_context.channel = link->public.ddc->ddc_pin->hw_info.ddc_channel;
-		psr_context.transmitterId = link->link_enc->transmitter;
-		psr_context.engineId = link->link_enc->preferred_engine;
+		psr_context->channel = link->public.ddc->ddc_pin->hw_info.ddc_channel;
+		psr_context->transmitterId = link->link_enc->transmitter;
+		psr_context->engineId = link->link_enc->preferred_engine;
 
 		for (i = 0; i < MAX_PIPES; i++) {
 			if (core_dc->current_context->res_ctx.pipe_ctx[i].stream
@@ -1513,7 +1513,7 @@ bool dc_link_setup_psr(const struct dc_link *dc_link,
 				/* dmcu -1 for all controller id values,
 				 * therefore +1 here
 				 */
-				psr_context.controllerId =
+				psr_context->controllerId =
 					core_dc->current_context->res_ctx.
 					pipe_ctx[i].tg->inst + 1;
 				break;
@@ -1521,60 +1521,60 @@ bool dc_link_setup_psr(const struct dc_link *dc_link,
 		}
 
 		/* Hardcoded for now.  Can be Pcie or Uniphy (or Unknown)*/
-		psr_context.phyType = PHY_TYPE_UNIPHY;
+		psr_context->phyType = PHY_TYPE_UNIPHY;
 		/*PhyId is associated with the transmitter id*/
-		psr_context.smuPhyId = link->link_enc->transmitter;
+		psr_context->smuPhyId = link->link_enc->transmitter;
 
-		psr_context.crtcTimingVerticalTotal = stream->timing.v_total;
-		psr_context.vsyncRateHz = div64_u64(div64_u64((stream->
+		psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
+		psr_context->vsyncRateHz = div64_u64(div64_u64((stream->
 						timing.pix_clk_khz * 1000),
 						stream->timing.v_total),
 						stream->timing.h_total);
 
-		psr_context.psrSupportedDisplayConfig = true;
-		psr_context.psrExitLinkTrainingRequired =
+		psr_context->psrSupportedDisplayConfig = true;
+		psr_context->psrExitLinkTrainingRequired =
 			psr_config->psr_exit_link_training_required;
-		psr_context.sdpTransmitLineNumDeadline =
+		psr_context->sdpTransmitLineNumDeadline =
 			psr_config->psr_sdp_transmit_line_num_deadline;
-		psr_context.psrFrameCaptureIndicationReq =
+		psr_context->psrFrameCaptureIndicationReq =
 			psr_config->psr_frame_capture_indication_req;
 
-		psr_context.skipPsrWaitForPllLock = 0; /* only = 1 in KV */
+		psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */
 
-		psr_context.numberOfControllers =
+		psr_context->numberOfControllers =
 				link->dc->res_pool->res_cap->num_timing_generator;
 
-		psr_context.rfb_update_auto_en = true;
+		psr_context->rfb_update_auto_en = true;
 
 		/* 2 frames before enter PSR. */
-		psr_context.timehyst_frames = 2;
+		psr_context->timehyst_frames = 2;
 		/* half a frame
 		 * (units in 100 lines, i.e. a value of 1 represents 100 lines)
 		 */
-		psr_context.hyst_lines = stream->timing.v_total / 2 / 100;
-		psr_context.aux_repeats = 10;
+		psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
+		psr_context->aux_repeats = 10;
 
-		psr_context.psr_level.u32all = 0;
+		psr_context->psr_level.u32all = 0;
 
 		/* SMU will perform additional powerdown sequence.
 		 * For unsupported ASICs, set psr_level flag to skip PSR
 		 *  static screen notification to SMU.
 		 *  (Always set for DAL2, did not check ASIC)
 		 */
-		psr_context.psr_level.bits.SKIP_SMU_NOTIFICATION = 1;
+		psr_context->psr_level.bits.SKIP_SMU_NOTIFICATION = 1;
 
 		/* Complete PSR entry before aborting to prevent intermittent
 		 * freezes on certain eDPs
 		 */
-		psr_context.psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
+		psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
 
 		/* Controls additional delay after remote frame capture before
 		 * continuing power down, default = 0
 		 */
-		psr_context.frame_delay = 0;
+		psr_context->frame_delay = 0;
 
 		link->psr_enabled = true;
-		dmcu->funcs->setup_psr(dmcu, link, &psr_context);
+		dmcu->funcs->setup_psr(dmcu, link, psr_context);
 		return true;
 	} else
 		return false;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 328bfcb7dbb8..a20ba01d9e7b 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -705,7 +705,8 @@ bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable);
 bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state);
 
 bool dc_link_setup_psr(const struct dc_link *dc_link,
-		const struct dc_stream *stream, struct psr_config *psr_config);
+		const struct dc_stream *stream, struct psr_config *psr_config,
+		struct psr_context *psr_context);
 
 /* Request DC to detect if there is a Panel connected.
  * boot - If this call is during initial boot.
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index d2f3b9fd7a30..06354c36c499 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -31,6 +31,7 @@
 #include "dc_dp_types.h"
 #include "dc_hw_types.h"
 #include "dal_types.h"
+#include "grph_object_defs.h"
 
 /* forward declarations */
 struct dc_surface;
@@ -493,6 +494,106 @@ struct psr_config {
 	unsigned int psr_sdp_transmit_line_num_deadline;
 };
 
+union dmcu_psr_level {
+	struct {
+		unsigned int SKIP_CRC:1;
+		unsigned int SKIP_DP_VID_STREAM_DISABLE:1;
+		unsigned int SKIP_PHY_POWER_DOWN:1;
+		unsigned int SKIP_AUX_ACK_CHECK:1;
+		unsigned int SKIP_CRTC_DISABLE:1;
+		unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1;
+		unsigned int SKIP_SMU_NOTIFICATION:1;
+		unsigned int SKIP_AUTO_STATE_ADVANCE:1;
+		unsigned int DISABLE_PSR_ENTRY_ABORT:1;
+		unsigned int RESERVED:23;
+	} bits;
+	unsigned int u32all;
+};
+
+enum physical_phy_id {
+	PHYLD_0,
+	PHYLD_1,
+	PHYLD_2,
+	PHYLD_3,
+	PHYLD_4,
+	PHYLD_5,
+	PHYLD_6,
+	PHYLD_7,
+	PHYLD_8,
+	PHYLD_9,
+	PHYLD_COUNT,
+	PHYLD_UNKNOWN = (-1L)
+};
+
+enum phy_type {
+	PHY_TYPE_UNKNOWN  = 1,
+	PHY_TYPE_PCIE_PHY = 2,
+	PHY_TYPE_UNIPHY = 3,
+};
+
+struct psr_context {
+	/* ddc line */
+	enum channel_id channel;
+	/* Transmitter id */
+	enum transmitter transmitterId;
+	/* Engine Id is used for Dig Be source select */
+	enum engine_id engineId;
+	/* Controller Id used for Dig Fe source select */
+	enum controller_id controllerId;
+	/* Pcie or Uniphy */
+	enum phy_type phyType;
+	/* Physical PHY Id used by SMU interpretation */
+	enum physical_phy_id smuPhyId;
+	/* Vertical total pixels from crtc timing.
+	 * This is used for static screen detection.
+	 * ie. If we want to detect half a frame,
+	 * we use this to determine the hyst lines.
+	 */
+	unsigned int crtcTimingVerticalTotal;
+	/* PSR supported from panel capabilities and
+	 * current display configuration
+	 */
+	bool psrSupportedDisplayConfig;
+	/* Whether fast link training is supported by the panel */
+	bool psrExitLinkTrainingRequired;
+	/* If RFB setup time is greater than the total VBLANK time,
+	 * it is not possible for the sink to capture the video frame
+	 * in the same frame the SDP is sent. In this case,
+	 * the frame capture indication bit should be set and an extra
+	 * static frame should be transmitted to the sink.
+	 */
+	bool psrFrameCaptureIndicationReq;
+	/* Set the last possible line SDP may be transmitted without violating
+	 * the RFB setup time or entering the active video frame.
+	 */
+	unsigned int sdpTransmitLineNumDeadline;
+	/* The VSync rate in Hz used to calculate the
+	 * step size for smooth brightness feature
+	 */
+	unsigned int vsyncRateHz;
+	unsigned int skipPsrWaitForPllLock;
+	unsigned int numberOfControllers;
+	/* Unused, for future use. To indicate that first changed frame from
+	 * state3 shouldn't result in psr_inactive, but rather to perform
+	 * an automatic single frame rfb_update.
+	 */
+	bool rfb_update_auto_en;
+	/* Number of frame before entering static screen */
+	unsigned int timehyst_frames;
+	/* Partial frames before entering static screen */
+	unsigned int hyst_lines;
+	/* # of repeated AUX transaction attempts to make before
+	 * indicating failure to the driver
+	 */
+	unsigned int aux_repeats;
+	/* Controls hw blocks to power down during PSR active state */
+	union dmcu_psr_level psr_level;
+	/* Controls additional delay after remote frame capture before
+	 * continuing powerd own
+	 */
+	unsigned int frame_delay;
+};
+
 struct colorspace_transform {
 	struct fixed31_32 matrix[12];
 	bool enable_remap;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
index 8bc0d0ff3a2e..04cd70172cc7 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
@@ -31,6 +31,7 @@
 #include "dc.h"
 #include "core_dc.h"
 #include "dce_abm.h"
+#include "dmcu.h"
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 #include "dcn_calcs.h"
 #include "core_dc.h"
@@ -331,44 +332,18 @@ static void dce_set_clock(
 		clk->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
 }
 
-#define PSR_SET_WAITLOOP 0x31
-
-union dce110_dmcu_psr_config_data_wait_loop_reg1 {
-	struct {
-		unsigned int wait_loop:16; /* [15:0] */
-		unsigned int reserved:16; /* [31:16] */
-	} bits;
-	unsigned int u32;
-};
-
-static void dce_psr_wait_loop(
-		struct dce_disp_clk *clk_dce, unsigned int display_clk_khz)
-{
-	struct dc_context *ctx = clk_dce->base.ctx;
-	union dce110_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;
-
-	/* waitDMCUReadyForCmd */
-	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 100);
-
-	masterCmdData1.u32 = 0;
-	masterCmdData1.bits.wait_loop = display_clk_khz / 1000 / 7;
-	dm_write_reg(ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);
-
-	/* setDMCUParam_Cmd */
-	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP);
-
-	/* notifyDMCUMsg */
-	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
-}
-
 static void dce_psr_set_clock(
 	struct display_clock *clk,
 	int requested_clk_khz)
 {
 	struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
+	struct dc_context *ctx = clk_dce->base.ctx;
+	struct core_dc *core_dc = DC_TO_CORE(ctx->dc);
+	struct dmcu *dmcu = core_dc->res_pool->dmcu;
 
 	dce_set_clock(clk, requested_clk_khz);
-	dce_psr_wait_loop(clk_dce, requested_clk_khz);
+
+	dmcu->funcs->set_psr_wait_loop(dmcu, requested_clk_khz / 1000 / 7);
 }
 
 static void dce112_set_clock(
@@ -380,6 +355,7 @@ static void dce112_set_clock(
 	struct dc_bios *bp = clk->ctx->dc_bios;
 	struct core_dc *core_dc = DC_TO_CORE(clk->ctx->dc);
 	struct abm *abm =  core_dc->res_pool->abm;
+	struct dmcu *dmcu = core_dc->res_pool->dmcu;
 
 	/* Prepare to program display clock*/
 	memset(&dce_clk_params, 0, sizeof(dce_clk_params));
@@ -411,7 +387,8 @@ static void dce112_set_clock(
 	bp->funcs->set_dce_clock(bp, &dce_clk_params);
 
 	if (abm->funcs->is_dmcu_initialized(abm))
-		dce_psr_wait_loop(clk_dce, requested_clk_khz);
+		dmcu->funcs->set_psr_wait_loop(dmcu,
+				requested_clk_khz / 1000 / 7);
 
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
index 03b51e256e21..0fe3ee8e29d3 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
@@ -48,7 +48,9 @@
 #define PSR_ENABLE 0x20
 #define PSR_EXIT 0x21
 #define PSR_SET 0x23
+#define PSR_SET_WAITLOOP 0x31
 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK   0x00000001L
+unsigned int cached_wait_loop_number = 0;
 
 bool dce_dmcu_load_iram(struct dmcu *dmcu,
 		unsigned int start_offset,
@@ -252,6 +254,34 @@ static void dce_dmcu_setup_psr(struct dmcu *dmcu,
 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
 }
 
+static void dce_psr_wait_loop(
+	struct dmcu *dmcu,
+	unsigned int wait_loop_number)
+{
+	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
+	union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;
+
+	/* waitDMCUReadyForCmd */
+	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 100);
+
+	masterCmdData1.u32 = 0;
+	masterCmdData1.bits.wait_loop = wait_loop_number;
+	cached_wait_loop_number = wait_loop_number;
+	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);
+
+	/* setDMCUParam_Cmd */
+	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP);
+
+	/* notifyDMCUMsg */
+	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
+}
+
+static void dce_get_psr_wait_loop(unsigned int *psr_wait_loop_number)
+{
+	*psr_wait_loop_number = cached_wait_loop_number;
+	return;
+}
+
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 bool dcn10_dmcu_load_iram(struct dmcu *dmcu,
 		unsigned int start_offset,
@@ -464,13 +494,43 @@ static void dcn10_dmcu_setup_psr(struct dmcu *dmcu,
 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
 }
 
+static void dcn10_psr_wait_loop(
+	struct dmcu *dmcu,
+	unsigned int wait_loop_number)
+{
+	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
+	union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;
+
+	/* waitDMCUReadyForCmd */
+	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 100);
+
+	masterCmdData1.u32 = 0;
+	masterCmdData1.bits.wait_loop = wait_loop_number;
+	cached_wait_loop_number = wait_loop_number;
+	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);
+
+	/* setDMCUParam_Cmd */
+	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP);
+
+	/* notifyDMCUMsg */
+	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
+}
+
+static void dcn10_get_psr_wait_loop(unsigned int *psr_wait_loop_number)
+{
+	*psr_wait_loop_number = cached_wait_loop_number;
+	return;
+}
+
 #endif
 
 static const struct dmcu_funcs dce_funcs = {
 	.load_iram = dce_dmcu_load_iram,
 	.set_psr_enable = dce_dmcu_set_psr_enable,
 	.setup_psr = dce_dmcu_setup_psr,
-	.get_psr_state = dce_get_dmcu_psr_state
+	.get_psr_state = dce_get_dmcu_psr_state,
+	.set_psr_wait_loop = dce_psr_wait_loop,
+	.get_psr_wait_loop = dce_get_psr_wait_loop
 };
 
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
@@ -478,7 +538,9 @@ static const struct dmcu_funcs dcn10_funcs = {
 	.load_iram = dcn10_dmcu_load_iram,
 	.set_psr_enable = dcn10_dmcu_set_psr_enable,
 	.setup_psr = dcn10_dmcu_setup_psr,
-	.get_psr_state = dcn10_get_dmcu_psr_state
+	.get_psr_state = dcn10_get_dmcu_psr_state,
+	.set_psr_wait_loop = dcn10_psr_wait_loop,
+	.get_psr_wait_loop = dcn10_get_psr_wait_loop
 };
 #endif
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
index 584682ba1f77..c421a0250016 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
@@ -197,6 +197,14 @@ union dce_dmcu_psr_config_data_reg3 {
 	unsigned int u32All;
 };
 
+union dce_dmcu_psr_config_data_wait_loop_reg1 {
+	struct {
+		unsigned int wait_loop:16; /* [15:0] */
+		unsigned int reserved:16; /* [31:16] */
+	} bits;
+	unsigned int u32;
+};
+
 struct dmcu *dce_dmcu_create(
 	struct dc_context *ctx,
 	const struct dce_dmcu_registers *regs,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
index dff0babb5cf7..6067f464d805 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
@@ -42,6 +42,9 @@ struct dmcu_funcs {
 			struct core_link *link,
 			struct psr_context *psr_context);
 	void (*get_psr_state)(struct dmcu *dmcu, uint32_t *psr_state);
+	void (*set_psr_wait_loop)(struct dmcu *dmcu,
+			unsigned int wait_loop_number);
+	void (*get_psr_wait_loop)(unsigned int *psr_wait_loop_number);
 };
 
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
index 7307f96c7679..d330d38aff16 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
@@ -47,43 +47,6 @@ struct encoder_feature_support {
 	bool ycbcr420_supported;
 };
 
-enum physical_phy_id {
-	PHYLD_0,
-	PHYLD_1,
-	PHYLD_2,
-	PHYLD_3,
-	PHYLD_4,
-	PHYLD_5,
-	PHYLD_6,
-	PHYLD_7,
-	PHYLD_8,
-	PHYLD_9,
-	PHYLD_COUNT,
-	PHYLD_UNKNOWN = (-1L)
-};
-
-enum phy_type {
-	PHY_TYPE_UNKNOWN  = 1,
-	PHY_TYPE_PCIE_PHY = 2,
-	PHY_TYPE_UNIPHY = 3,
-};
-
-union dmcu_psr_level {
-	struct {
-		unsigned int SKIP_CRC:1;
-		unsigned int SKIP_DP_VID_STREAM_DISABLE:1;
-		unsigned int SKIP_PHY_POWER_DOWN:1;
-		unsigned int SKIP_AUX_ACK_CHECK:1;
-		unsigned int SKIP_CRTC_DISABLE:1;
-		unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1;
-		unsigned int SKIP_SMU_NOTIFICATION:1;
-		unsigned int SKIP_AUTO_STATE_ADVANCE:1;
-		unsigned int DISABLE_PSR_ENTRY_ABORT:1;
-		unsigned int RESERVED:23;
-	} bits;
-	unsigned int u32all;
-};
-
 union dpcd_psr_configuration {
 	struct {
 		unsigned char ENABLE                    : 1;
@@ -116,70 +79,6 @@ union psr_sink_psr_status {
 	unsigned char raw;
 };
 
-struct psr_context {
-	/* ddc line */
-	enum channel_id channel;
-	/* Transmitter id */
-	enum transmitter transmitterId;
-	/* Engine Id is used for Dig Be source select */
-	enum engine_id engineId;
-	/* Controller Id used for Dig Fe source select */
-	enum controller_id controllerId;
-	/* Pcie or Uniphy */
-	enum phy_type phyType;
-	/* Physical PHY Id used by SMU interpretation */
-	enum physical_phy_id smuPhyId;
-	/* Vertical total pixels from crtc timing.
-	 * This is used for static screen detection.
-	 * ie. If we want to detect half a frame,
-	 * we use this to determine the hyst lines.
-	 */
-	unsigned int crtcTimingVerticalTotal;
-	/* PSR supported from panel capabilities and
-	 * current display configuration
-	 */
-	bool psrSupportedDisplayConfig;
-	/* Whether fast link training is supported by the panel */
-	bool psrExitLinkTrainingRequired;
-	/* If RFB setup time is greater than the total VBLANK time,
-	 * it is not possible for the sink to capture the video frame
-	 * in the same frame the SDP is sent. In this case,
-	 * the frame capture indication bit should be set and an extra
-	 * static frame should be transmitted to the sink.
-	 */
-	bool psrFrameCaptureIndicationReq;
-	/* Set the last possible line SDP may be transmitted without violating
-	 * the RFB setup time or entering the active video frame.
-	 */
-	unsigned int sdpTransmitLineNumDeadline;
-	/* The VSync rate in Hz used to calculate the
-	 * step size for smooth brightness feature
-	 */
-	unsigned int vsyncRateHz;
-	unsigned int skipPsrWaitForPllLock;
-	unsigned int numberOfControllers;
-	/* Unused, for future use. To indicate that first changed frame from
-	 * state3 shouldn't result in psr_inactive, but rather to perform
-	 * an automatic single frame rfb_update.
-	 */
-	bool rfb_update_auto_en;
-	/* Number of frame before entering static screen */
-	unsigned int timehyst_frames;
-	/* Partial frames before entering static screen */
-	unsigned int hyst_lines;
-	/* # of repeated AUX transaction attempts to make before
-	 * indicating failure to the driver
-	 */
-	unsigned int aux_repeats;
-	/* Controls hw blocks to power down during PSR active state */
-	union dmcu_psr_level psr_level;
-	/* Controls additional delay after remote frame capture before
-	 * continuing powerd own
-	 */
-	unsigned int frame_delay;
-};
-
-
 struct link_encoder {
 	const struct link_encoder_funcs *funcs;
 	int32_t aux_channel_offset;
-- 
2.11.0

_______________________________________________
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amd-gfx@lists.freedesktop.org
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[PATCH 16/27] drm/amd/display: Fix DRR Enable on Desktop

[Harry Wentland]

From: Amy Zhang <Amy.Zhang@amd.com>

- Block PSR in Full screen apps to prevent incorrect static screen curser events
- Reprogram static screen events when update freesync state
- Program static ramp variable active after other values are programmed
- Correct wrong assigning of the nominal and current vcount

Change-Id: Ic8f79963981c113deaf0b435aa159229bcbedf67
Signed-off-by: Amy Zhang <Amy.Zhang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 .../drm/amd/display/modules/freesync/freesync.c    | 89 ++++++++++++++--------
 .../gpu/drm/amd/display/modules/inc/mod_freesync.h |  3 +-
 2 files changed, 61 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 9a073bc55144..f79c47951f90 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -257,8 +257,10 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync,
 		nom_refresh_rate_micro_hz = (unsigned int) temp;
 
 		if (core_freesync->opts.min_refresh_from_edid != 0 &&
-				dc_is_embedded_signal(
-					stream->sink->sink_signal)) {
+				dc_is_embedded_signal(stream->sink->sink_signal)
+				&& (nom_refresh_rate_micro_hz -
+				core_freesync->opts.min_refresh_from_edid *
+				1000000) >= 10000000) {
 			caps->supported = true;
 			caps->min_refresh_in_micro_hz =
 				core_freesync->opts.min_refresh_from_edid *
@@ -683,44 +685,47 @@ static void set_static_ramp_variables(struct core_freesync *core_freesync,
 		unsigned int index, bool enable_static_screen)
 {
 	unsigned int frame_duration = 0;
-
+	unsigned int nominal_refresh_rate = core_freesync->map[index].state.
+			nominal_refresh_rate_in_micro_hz;
+	unsigned int min_refresh_rate= core_freesync->map[index].caps->
+			min_refresh_in_micro_hz;
 	struct gradual_static_ramp *static_ramp_variables =
 			&core_freesync->map[index].state.static_ramp;
 
+	/* If we are ENABLING static screen, refresh rate should go DOWN.
+	 * If we are DISABLING static screen, refresh rate should go UP.
+	 */
+	if (enable_static_screen)
+		static_ramp_variables->ramp_direction_is_up = false;
+	else
+		static_ramp_variables->ramp_direction_is_up = true;
+
 	/* If ramp is not active, set initial frame duration depending on
 	 * whether we are enabling/disabling static screen mode. If the ramp is
 	 * already active, ramp should continue in the opposite direction
 	 * starting with the current frame duration
 	 */
 	if (!static_ramp_variables->ramp_is_active) {
-
-		static_ramp_variables->ramp_is_active = true;
-
 		if (enable_static_screen == true) {
 			/* Going to lower refresh rate, so start from max
 			 * refresh rate (min frame duration)
 			 */
 			frame_duration = ((unsigned int) (div64_u64(
 				(1000000000ULL * 1000000),
-				core_freesync->map[index].state.
-				nominal_refresh_rate_in_micro_hz)));
+				nominal_refresh_rate)));
 		} else {
 			/* Going to higher refresh rate, so start from min
 			 * refresh rate (max frame duration)
 			 */
 			frame_duration = ((unsigned int) (div64_u64(
 				(1000000000ULL * 1000000),
-				core_freesync->map[index].caps->min_refresh_in_micro_hz)));
+				min_refresh_rate)));
 		}
-
 		static_ramp_variables->
 			ramp_current_frame_duration_in_ns = frame_duration;
-	}
 
-	/* If we are ENABLING static screen, refresh rate should go DOWN.
-	 * If we are DISABLING static screen, refresh rate should go UP.
-	 */
-	static_ramp_variables->ramp_direction_is_up = !enable_static_screen;
+		static_ramp_variables->ramp_is_active = true;
+	}
 }
 
 void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
@@ -841,6 +846,7 @@ void mod_freesync_update_state(struct mod_freesync *mod_freesync,
 	unsigned int stream_index;
 	struct freesync_state *state;
 	struct core_freesync *core_freesync = NULL;
+	struct dc_static_screen_events triggers = {0};
 
 	if (mod_freesync == NULL)
 		return;
@@ -902,6 +908,14 @@ void mod_freesync_update_state(struct mod_freesync *mod_freesync,
 		}
 	}
 
+	/* Update mask */
+	triggers.overlay_update = true;
+	triggers.surface_update = true;
+
+	core_freesync->dc->stream_funcs.set_static_screen_events(
+		core_freesync->dc, streams, num_streams,
+		&triggers);
+
 	if (freesync_program_required)
 		/* Program freesync according to current state*/
 		set_freesync_on_streams(core_freesync, streams, num_streams);
@@ -1017,7 +1031,8 @@ bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync,
 bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync,
 		const struct dc_stream *streams,
 		unsigned int min_refresh,
-		unsigned int max_refresh)
+		unsigned int max_refresh,
+		struct mod_freesync_caps *caps)
 {
 	unsigned int index = 0;
 	struct core_freesync *core_freesync;
@@ -1030,7 +1045,10 @@ bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync,
 	index = map_index_from_stream(core_freesync, streams);
 	state = &core_freesync->map[index].state;
 
-	if (min_refresh == 0 || max_refresh == 0) {
+	if (max_refresh == 0)
+		max_refresh = state->nominal_refresh_rate_in_micro_hz;
+
+	if (min_refresh == 0) {
 		/* Restore defaults */
 		calc_freesync_range(core_freesync, streams, state,
 			core_freesync->map[index].caps->
@@ -1049,6 +1067,17 @@ bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync,
 			state->freesync_range.vmax);
 	}
 
+	if (min_refresh != 0 &&
+			dc_is_embedded_signal(streams->sink->sink_signal) &&
+			(max_refresh - min_refresh >= 10000000)) {
+		caps->supported = true;
+		caps->min_refresh_in_micro_hz = min_refresh;
+		caps->max_refresh_in_micro_hz = max_refresh;
+	}
+
+	/* Update the stream */
+	update_stream(core_freesync, streams);
+
 	return true;
 }
 
@@ -1115,8 +1144,8 @@ bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync,
 			core_freesync->dc, &stream, 1,
 			&position.vertical_count, &position.nominal_vcount)) {
 
-		*nom_v_pos = position.vertical_count;
-		*v_pos = position.nominal_vcount;
+		*nom_v_pos = position.nominal_vcount;
+		*v_pos = position.vertical_count;
 
 		return true;
 	}
@@ -1131,6 +1160,7 @@ void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync,
 	struct freesync_state *state;
 	struct core_freesync *core_freesync = NULL;
 	struct dc_static_screen_events triggers = {0};
+	unsigned long long temp = 0;
 
 	if (mod_freesync == NULL)
 		return;
@@ -1143,22 +1173,21 @@ void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync,
 
 		state = &core_freesync->map[map_index].state;
 
+		/* Update the field rate for new timing */
+		temp = streams[stream_index]->timing.pix_clk_khz;
+		temp *= 1000ULL * 1000ULL * 1000ULL;
+		temp = div_u64(temp,
+				streams[stream_index]->timing.h_total);
+		temp = div_u64(temp,
+				streams[stream_index]->timing.v_total);
+		state->nominal_refresh_rate_in_micro_hz =
+				(unsigned int) temp;
+
 		if (core_freesync->map[map_index].caps->supported) {
-			/* Update the field rate for new timing */
-			unsigned long long temp;
-			temp = streams[stream_index]->timing.pix_clk_khz;
-			temp *= 1000ULL * 1000ULL * 1000ULL;
-			temp = div_u64(temp,
-					streams[stream_index]->timing.h_total);
-			temp = div_u64(temp,
-					streams[stream_index]->timing.v_total);
-			state->nominal_refresh_rate_in_micro_hz =
-					(unsigned int) temp;
 
 			/* Update the stream */
 			update_stream(core_freesync, streams[stream_index]);
 
-
 			/* Calculate vmin/vmax and refresh rate for
 			 * current mode
 			 */
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
index 3947cc412ad7..f7f5a2cd7914 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
@@ -132,7 +132,8 @@ bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync,
 bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync,
 		const struct dc_stream *streams,
 		unsigned int min_refresh,
-		unsigned int max_refresh);
+		unsigned int max_refresh,
+		struct mod_freesync_caps *caps);
 
 bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync,
 		const struct dc_stream *stream,
-- 
2.11.0

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[PATCH 17/27] drm/amd/display: fix single link black screen

[Harry Wentland]

From: Charlene Liu <charlene.liu@amd.com>

Don't fall back to dual link DVI mode if the connector
is single Link only.

Change-Id: Ifef1bc5d4e38ab163e13de33fc8494baaf3b1d6b
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 236c8e9c0f6a..9f6a99f850ec 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1204,6 +1204,7 @@ bool resource_validate_attach_surfaces(
 
 /* Maximum TMDS single link pixel clock 165MHz */
 #define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000
+#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST 297000
 
 static void set_stream_engine_in_use(
 		struct resource_context *res_ctx,
@@ -1331,7 +1332,8 @@ static void update_stream_signal(struct core_stream *stream)
 	}
 
 	if (dc_is_dvi_signal(stream->signal)) {
-		if (stream->public.timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK_IN_KHZ)
+		if (stream->public.timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST &&
+			stream->public.sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
 			stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK;
 		else
 			stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
-- 
2.11.0

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[PATCH 18/27] drm/amd/display: Add function to log connectivity

[Harry Wentland]

From: Zeyu Fan <Zeyu.Fan@amd.com>

Change-Id: I2e8579035eea7dd2c4cefeb296efad4cdee8ddc4
Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 6 ++++++
 drivers/gpu/drm/amd/display/dc/basics/log_helpers.c       | 3 +++
 drivers/gpu/drm/amd/display/dc/dm_helpers.h               | 4 ++++
 3 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 3401780af2d3..dc2248c2058a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -321,6 +321,12 @@ bool dm_helpers_dp_mst_send_payload_allocation(
 	return true;
 }
 
+bool dm_helpers_dc_conn_log(struct dc_context*ctx, const char *msg)
+{
+	return true;
+}
+
+
 bool dm_helpers_dp_mst_start_top_mgr(
 		struct dc_context *ctx,
 		const struct dc_link *link,
diff --git a/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c b/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
index c4eddee8de1b..1268be9ebaf3 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
@@ -26,6 +26,7 @@
 #include "core_types.h"
 #include "logger.h"
 #include "include/logger_interface.h"
+#include "dm_helpers.h"
 
 #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
 
@@ -94,6 +95,8 @@ void dc_conn_log(struct dc_context *ctx,
 			dm_logger_append(&entry, "%2.2X ", hex_data[i]);
 
 	dm_logger_append(&entry, "^\n");
+	dm_helpers_dc_conn_log(ctx, entry.buf);
 	dm_logger_close(&entry);
+
 	va_end(args);
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
index c15a25ce8049..9fb606c49217 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
@@ -68,6 +68,10 @@ bool dm_helpers_dp_mst_start_top_mgr(
 		const struct dc_link *link,
 		bool boot);
 
+bool dm_helpers_dc_conn_log(
+		struct dc_context*ctx,
+		const char *msg);
+
 void dm_helpers_dp_mst_stop_top_mgr(
 		struct dc_context *ctx,
 		const struct dc_link *link);
-- 
2.11.0

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[PATCH 19/27] drm/amd/display: Call program_gamut explicitly instead of entire set_plane

[Harry Wentland]

From: Zeyu Fan <Zeyu.Fan@amd.com>

This fixes on boot crush on Vega, Polaris with Dal3.

Change-Id: Ia103a8b77879d573cdab0c98b3df563fa3677f80
Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c           |  3 +-
 .../amd/display/dc/dce110/dce110_hw_sequencer.c    | 42 ++++++++++++++++++++++
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  1 +
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |  3 ++
 4 files changed, 47 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index f5102b644942..657e10bae93f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -213,8 +213,7 @@ static bool set_gamut_remap(struct dc *dc, const struct dc_stream *stream)
 				== core_stream) {
 
 			pipes = &core_dc->current_context->res_ctx.pipe_ctx[i];
-			core_dc->hwss.set_plane_config(core_dc, pipes,
-					&core_dc->current_context->res_ctx);
+			core_dc->hwss.program_gamut_remap(pipes);
 			ret = true;
 		}
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 7dd4b02b5938..616533e25534 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1894,6 +1894,47 @@ static void program_surface_visibility(const struct core_dc *dc,
 
 }
 
+static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
+{
+	struct xfm_grph_csc_adjustment adjust;
+	memset(&adjust, 0, sizeof(adjust));
+	adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
+
+
+	if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) {
+		adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
+		adjust.temperature_matrix[0] =
+				pipe_ctx->stream->
+				public.gamut_remap_matrix.matrix[0];
+		adjust.temperature_matrix[1] =
+				pipe_ctx->stream->
+				public.gamut_remap_matrix.matrix[1];
+		adjust.temperature_matrix[2] =
+				pipe_ctx->stream->
+				public.gamut_remap_matrix.matrix[2];
+		adjust.temperature_matrix[3] =
+				pipe_ctx->stream->
+				public.gamut_remap_matrix.matrix[4];
+		adjust.temperature_matrix[4] =
+				pipe_ctx->stream->
+				public.gamut_remap_matrix.matrix[5];
+		adjust.temperature_matrix[5] =
+				pipe_ctx->stream->
+				public.gamut_remap_matrix.matrix[6];
+		adjust.temperature_matrix[6] =
+				pipe_ctx->stream->
+				public.gamut_remap_matrix.matrix[8];
+		adjust.temperature_matrix[7] =
+				pipe_ctx->stream->
+				public.gamut_remap_matrix.matrix[9];
+		adjust.temperature_matrix[8] =
+				pipe_ctx->stream->
+				public.gamut_remap_matrix.matrix[10];
+	}
+
+	pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust);
+}
+
 /**
  * TODO REMOVE, USE UPDATE INSTEAD
  */
@@ -2509,6 +2550,7 @@ static void dce110_power_down_fe(struct core_dc *dc, struct pipe_ctx *pipe)
 }
 
 static const struct hw_sequencer_funcs dce110_funcs = {
+	.program_gamut_remap = program_gamut_remap,
 	.init_hw = init_hw,
 	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
 	.apply_ctx_for_surface = dce110_apply_ctx_for_surface,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 447f6bf4644c..107f82df3053 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1899,6 +1899,7 @@ static void set_plane_config(
 }
 
 static const struct hw_sequencer_funcs dcn10_funcs = {
+	.program_gamut_remap = program_gamut_remap,
 	.init_hw = init_hw,
 	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
 	.apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index b53e1206dfb3..6f8733ec9b16 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -67,6 +67,9 @@ struct hw_sequencer_funcs {
 			struct pipe_ctx *pipe_ctx,
 			struct resource_context *res_ctx);
 
+	void (*program_gamut_remap)(
+			struct pipe_ctx *pipe_ctx);
+
 	void (*update_plane_addr)(
 		const struct core_dc *dc,
 		struct pipe_ctx *pipe_ctx);
-- 
2.11.0

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[PATCH 20/27] drm/amd/display: propagate surface alpha setting from OS to DC

[Harry Wentland]

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

Change-Id: I74a7f87d0c70a2ad1de9797ebae61976e49972ed
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c                  |  6 +++++-
 drivers/gpu/drm/amd/display/dc/core/dc_debug.c            |  6 ++++--
 drivers/gpu/drm/amd/display/dc/dc.h                       |  2 ++
 drivers/gpu/drm/amd/display/dc/dc_types.h                 |  2 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 10 ++++------
 5 files changed, 16 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 657e10bae93f..fb5bacb50ebc 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -998,6 +998,7 @@ bool dc_commit_surfaces_to_stream(
 		plane_info[i].stereo_format = new_surfaces[i]->stereo_format;
 		plane_info[i].tiling_info = new_surfaces[i]->tiling_info;
 		plane_info[i].visible = new_surfaces[i]->visible;
+		plane_info[i].per_pixel_alpha = new_surfaces[i]->per_pixel_alpha;
 		plane_info[i].dcc = new_surfaces[i]->dcc;
 		scaling_info[i].scaling_quality = new_surfaces[i]->scaling_quality;
 		scaling_info[i].src_rect = new_surfaces[i]->src_rect;
@@ -1068,7 +1069,7 @@ static enum surface_update_type get_plane_info_update_type(
 		const struct dc_surface_update *u,
 		int surface_index)
 {
-	struct dc_plane_info temp_plane_info = { { { { 0 } } } };
+	struct dc_plane_info temp_plane_info = { 0 };
 
 	if (!u->plane_info)
 		return UPDATE_TYPE_FAST;
@@ -1091,6 +1092,7 @@ static enum surface_update_type get_plane_info_update_type(
 
 	/* Special Validation parameters */
 	temp_plane_info.format = u->plane_info->format;
+	temp_plane_info.per_pixel_alpha = u->plane_info->per_pixel_alpha;
 
 	if (surface_index == 0)
 		temp_plane_info.visible = u->plane_info->visible;
@@ -1327,6 +1329,8 @@ void dc_update_surfaces_and_stream(struct dc *dc,
 					srf_updates[i].plane_info->tiling_info;
 			surface->public.visible =
 					srf_updates[i].plane_info->visible;
+			surface->public.per_pixel_alpha =
+					srf_updates[i].plane_info->per_pixel_alpha;
 			surface->public.dcc =
 					srf_updates[i].plane_info->dcc;
 		}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
index ee840e75ee1f..c60b59f41693 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
@@ -221,10 +221,12 @@ void update_surface_trace(
 			SURFACE_TRACE(
 					"plane_info->tiling_info.gfx8.pipe_config = %d;\n"
 					"plane_info->tiling_info.gfx8.array_mode = %d;\n"
-					"plane_info->visible = %d;\n",
+					"plane_info->visible = %d;\n"
+					"plane_info->per_pixel_alpha = %d;\n",
 					update->plane_info->tiling_info.gfx8.pipe_config,
 					update->plane_info->tiling_info.gfx8.array_mode,
-					update->plane_info->visible);
+					update->plane_info->visible,
+					update->plane_info->per_pixel_alpha);
 
 			SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n",
 					update->plane_info->tiling_info.gfx9.swizzle);
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index a20ba01d9e7b..7191b2519334 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -290,6 +290,7 @@ struct dc_transfer_func {
 };
 
 struct dc_surface {
+	bool per_pixel_alpha;
 	bool visible;
 	bool flip_immediate;
 	struct dc_plane_address address;
@@ -316,6 +317,7 @@ struct dc_surface {
 };
 
 struct dc_plane_info {
+	bool per_pixel_alpha;
 	union plane_size plane_size;
 	union dc_tiling_info tiling_info;
 	struct dc_plane_dcc_param dcc;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 06354c36c499..5269796b2a8e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -97,7 +97,7 @@ struct dc_context {
 
 #define MAX_EDID_BUFFER_SIZE 512
 #define EDID_BLOCK_SIZE 128
-#define MAX_SURFACE_NUM 2
+#define MAX_SURFACE_NUM 4
 #define NUM_PIXEL_FORMATS 10
 
 #include "dc_ddc_types.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 107f82df3053..0a346aafacce 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1559,7 +1559,9 @@ static void update_dchubp_dpp(
 	struct pipe_ctx *temp_pipe;
 	int i;
 	int tree_pos = 0;
+	bool per_pixel_alpha = surface->public.per_pixel_alpha && pipe_ctx->bottom_pipe;
 
+	/* TODO: proper fix once fpga works */
 	/* depends on DML calculation, DPP clock value may change dynamically */
 	enable_dppclk(
 		dc->ctx,
@@ -1604,11 +1606,7 @@ static void update_dchubp_dpp(
 	/* TODO: build stream pipes group id. For now, use stream otg
 	 * id as pipe group id
 	 */
-	/*pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->surface->public.per_pixel_alpha;*/
-	if (pipe_ctx->bottom_pipe && surface != pipe_ctx->bottom_pipe->surface)
-		pipe_ctx->scl_data.lb_params.alpha_en = 1;
-	else
-		pipe_ctx->scl_data.lb_params.alpha_en = 0;
+	pipe_ctx->scl_data.lb_params.alpha_en = per_pixel_alpha;
 	pipe_ctx->mpc_idx = pipe_ctx->tg->inst;
 	tree_cfg = &context->res_ctx.mpc_tree[pipe_ctx->mpc_idx];
 	if (tree_cfg->num_pipes == 0) {
@@ -1625,7 +1623,7 @@ static void update_dchubp_dpp(
 
 	tree_cfg->dpp[tree_pos] = pipe_ctx->pipe_idx;
 	tree_cfg->mpcc[tree_pos] = pipe_ctx->pipe_idx;
-	tree_cfg->per_pixel_alpha[tree_pos] = pipe_ctx->scl_data.lb_params.alpha_en;
+	tree_cfg->per_pixel_alpha[tree_pos] = per_pixel_alpha;
 	tree_cfg->num_pipes = tree_pos + 1;
 	dcn10_set_mpc_tree(mpc, tree_cfg);
 
-- 
2.11.0

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[PATCH 21/27] drm/amd/display: No need to get property before set

[Harry Wentland]

Get property requires a lock but if we add it we get a deadlock
on MST display detection. There's really no need to get the
property before setting it.

Change-Id: I67d523b856665f8b2b952c2747de56be74a136de
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 21 +++++----------------
 1 file changed, 5 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 5d44687c144c..7aa24057c2a5 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -1077,24 +1077,13 @@ static int amdgpu_freesync_update_property_atomic(
 				struct drm_connector *connector,
 				uint64_t val_capable)
 {
-	struct drm_device *dev;
-	struct amdgpu_device *adev;
-	int ret;
-	uint64_t val;
+	struct drm_device *dev = connector->dev;
+	struct amdgpu_device *adev = dev->dev_private;
 
-	dev  = connector->dev;
-	adev = dev->dev_private;
+	return drm_object_property_set_value(&connector->base,
+					     adev->mode_info.freesync_property,
+					     val_capable);
 
-	ret = drm_object_property_get_value(
-			&connector->base,
-			adev->mode_info.freesync_property,
-			&val);
-	if (ret == 0 && val != 0 && val_capable == 0)
-		ret = drm_object_property_set_value(
-				&connector->base,
-				adev->mode_info.freesync_property,
-				val_capable);
-	return ret;
 
 }
 
-- 
2.11.0

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[PATCH 22/27] drm/amd/display: Temporary disable BTR FreeSync support for now

[Harry Wentland]

From: Anthony Koo <Anthony.Koo@amd.com>

Reduce timer tick interval for the static screen

Change-Id: I4096ae0ee63a02f1923b1345f909f97c71ea961f
Signed-off-by: Anthony Koo <anthony.koo@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index f79c47951f90..7109742bd67c 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -436,11 +436,14 @@ static void calc_freesync_range(struct core_freesync *core_freesync,
 	}
 
 	/* Determine whether BTR can be supported */
-	if (max_frame_duration_in_ns >=
-			2 * min_frame_duration_in_ns)
-		core_freesync->map[index].caps->btr_supported = true;
-	else
-		core_freesync->map[index].caps->btr_supported = false;
+	//if (max_frame_duration_in_ns >=
+	//		2 * min_frame_duration_in_ns)
+	//	core_freesync->map[index].caps->btr_supported = true;
+	//else
+	//	core_freesync->map[index].caps->btr_supported = false;
+
+	/* Temp, keep btr disabled */
+	core_freesync->map[index].caps->btr_supported = false;
 
 	/* Cache the time variables */
 	state->time.max_render_time_in_us =
-- 
2.11.0

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[PATCH 23/27] drm/amd/display: Use surface update inuse for pending check.

[Harry Wentland]

From: Yongqiang Sun <yongqiang.sun@amd.com>

Change-Id: Ib7bb454bd0dd48a71bfe78601b07384c08386cc2
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 10 +++++++
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 32 ++++++++++++++++++++++
 2 files changed, 42 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
index 3e3fcf2395ae..8ad70625a746 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
@@ -821,13 +821,23 @@ bool mem_input_is_flip_pending(struct mem_input *mem_input)
 {
 	uint32_t update_pending = 0;
 	struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
+	struct dc_plane_address earliest_inuse_address;
 
 	REG_GET(DCSURF_FLIP_CONTROL,
 			SURFACE_UPDATE_PENDING, &update_pending);
 
+	REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
+			SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part);
+
+	REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
+			SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part);
+
 	if (update_pending)
 		return true;
 
+	if (earliest_inuse_address.grph.addr.quad_part != mem_input->request_address.grph.addr.quad_part)
+		return true;
+
 	mem_input->current_address = mem_input->request_address;
 	return false;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
index 37683d072b42..9e2f1bb69958 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
@@ -52,6 +52,14 @@
 	SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id),\
 	SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
 	SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\
+	SRI(DCSURF_SURFACE_INUSE, HUBPREQ, id),\
+	SRI(DCSURF_SURFACE_INUSE_HIGH, HUBPREQ, id),\
+	SRI(DCSURF_SURFACE_INUSE_C, HUBPREQ, id),\
+	SRI(DCSURF_SURFACE_INUSE_HIGH_C, HUBPREQ, id),\
+	SRI(DCSURF_SURFACE_EARLIEST_INUSE, HUBPREQ, id),\
+	SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, HUBPREQ, id),\
+	SRI(DCSURF_SURFACE_EARLIEST_INUSE_C, HUBPREQ, id),\
+	SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, HUBPREQ, id),\
 	SRI(DCSURF_SURFACE_CONTROL, HUBPREQ, id),\
 	SRI(HUBPRET_CONTROL, HUBPRET, id),\
 	SRI(DCN_EXPANSION_MODE, HUBPREQ, id),\
@@ -165,6 +173,14 @@ struct dcn_mi_registers {
 	uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C;
 	uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C;
 	uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_C;
+	uint32_t DCSURF_SURFACE_INUSE;
+	uint32_t DCSURF_SURFACE_INUSE_HIGH;
+	uint32_t DCSURF_SURFACE_INUSE_C;
+	uint32_t DCSURF_SURFACE_INUSE_HIGH_C;
+	uint32_t DCSURF_SURFACE_EARLIEST_INUSE;
+	uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH;
+	uint32_t DCSURF_SURFACE_EARLIEST_INUSE_C;
+	uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C;
 	uint32_t DCSURF_SURFACE_CONTROL;
 	uint32_t HUBPRET_CONTROL;
 	uint32_t DCN_EXPANSION_MODE;
@@ -297,6 +313,14 @@ struct dcn_mi_registers {
 	MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\
 	MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
 	MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\
+	MI_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\
+	MI_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\
+	MI_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\
+	MI_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C, SURFACE_INUSE_ADDRESS_HIGH_C, mask_sh),\
+	MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE, SURFACE_EARLIEST_INUSE_ADDRESS, mask_sh),\
+	MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\
+	MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\
+	MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\
 	MI_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\
 	MI_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\
 	MI_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\
@@ -433,6 +457,14 @@ struct dcn_mi_registers {
 	type PRIMARY_SURFACE_ADDRESS_C;\
 	type PRIMARY_META_SURFACE_ADDRESS_HIGH_C;\
 	type PRIMARY_META_SURFACE_ADDRESS_C;\
+	type SURFACE_INUSE_ADDRESS;\
+	type SURFACE_INUSE_ADDRESS_HIGH;\
+	type SURFACE_INUSE_ADDRESS_C;\
+	type SURFACE_INUSE_ADDRESS_HIGH_C;\
+	type SURFACE_EARLIEST_INUSE_ADDRESS;\
+	type SURFACE_EARLIEST_INUSE_ADDRESS_HIGH;\
+	type SURFACE_EARLIEST_INUSE_ADDRESS_C;\
+	type SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C;\
 	type PRIMARY_SURFACE_DCC_EN;\
 	type PRIMARY_SURFACE_DCC_IND_64B_BLK;\
 	type DET_BUF_PLANE1_BASE_ADDRESS;\
-- 
2.11.0

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[PATCH 24/27] drm/amd/display: fix enable_optc_clock reg_wait timeouts

[Harry Wentland]

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

Change-Id: Ie33d1204597c75114f14403a671755632a163ab9
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc_helper.c                    | 8 +++++++-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c | 8 ++++----
 2 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c
index a950dd53bca4..87fd5b9c8a16 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c
@@ -135,6 +135,9 @@ uint32_t generic_reg_wait(const struct dc_context *ctx,
 	uint32_t reg_val;
 	int i;
 
+	if (ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS)
+		time_out_num_tries *= 20;
+
 	for (i = 0; i <= time_out_num_tries; i++) {
 		if (i) {
 			if (0 < delay_between_poll_us && delay_between_poll_us < 1000)
@@ -152,7 +155,10 @@ uint32_t generic_reg_wait(const struct dc_context *ctx,
 			return reg_val;
 	}
 
-	DC_ERR("REG_WAIT timeout %dus * %d tries - %s\n",
+	dm_error("REG_WAIT timeout %dus * %d tries - %s\n",
 			delay_between_poll_us, time_out_num_tries, func_name);
+	if (ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
+		BREAK_TO_DEBUGGER();
+
 	return reg_val;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
index d7072132d456..c5a636c750fa 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
@@ -449,7 +449,7 @@ static void enable_optc_clock(struct timing_generator *tg, bool enable)
 
 		REG_WAIT(OPTC_INPUT_CLOCK_CONTROL,
 				OPTC_INPUT_CLK_ON, 1,
-				20000, 200000);
+				2000, 500);
 
 		/* Enable clock */
 		REG_UPDATE(OTG_CLOCK_CONTROL,
@@ -457,7 +457,7 @@ static void enable_optc_clock(struct timing_generator *tg, bool enable)
 
 		REG_WAIT(OTG_CLOCK_CONTROL,
 				OTG_CLOCK_ON, 1,
-				20000, 200000);
+				2000, 500);
 	} else  {
 		REG_UPDATE_2(OTG_CLOCK_CONTROL,
 				OTG_CLOCK_GATE_DIS, 0,
@@ -465,7 +465,7 @@ static void enable_optc_clock(struct timing_generator *tg, bool enable)
 
 		REG_WAIT(OTG_CLOCK_CONTROL,
 				OTG_CLOCK_ON, 0,
-				20000, 200000);
+				2000, 500);
 
 		REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
 				OPTC_INPUT_CLK_GATE_DIS, 0,
@@ -473,7 +473,7 @@ static void enable_optc_clock(struct timing_generator *tg, bool enable)
 
 		REG_WAIT(OPTC_INPUT_CLOCK_CONTROL,
 				OPTC_INPUT_CLK_ON, 0,
-				20000, 200000);
+				2000, 500);
 	}
 }
 
-- 
2.11.0

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[PATCH 25/27] drm/amd/display: add bw logging for dcn

[Harry Wentland]

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

Change-Id: I6242cae575f292728fea23069514379b87f421f5
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c   | 138 +++++++++++
 drivers/gpu/drm/amd/display/dc/core/dc.c           |   4 +-
 drivers/gpu/drm/amd/display/dc/core/dc_debug.c     |  36 +++
 drivers/gpu/drm/amd/display/dc/dc.h                |   1 +
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 260 +++++++++++++++++----
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |   2 +
 .../gpu/drm/amd/display/include/logger_interface.h |   4 +
 7 files changed, 396 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 6d8bc6c74a73..f0f688b99d37 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -1312,6 +1312,144 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct core_dc *dc)
 void dcn_bw_sync_calcs_and_dml(struct core_dc *dc)
 {
 	kernel_fpu_begin();
+	dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
+			"sr_exit_time: %d ns\n"
+			"sr_enter_plus_exit_time: %d ns\n"
+			"urgent_latency: %d ns\n"
+			"write_back_latency: %d ns\n"
+			"percent_of_ideal_drambw_received_after_urg_latency: %d %\n"
+			"max_request_size: %d bytes\n"
+			"dcfclkv_max0p9: %d kHz\n"
+			"dcfclkv_nom0p8: %d kHz\n"
+			"dcfclkv_mid0p72: %d kHz\n"
+			"dcfclkv_min0p65: %d kHz\n"
+			"max_dispclk_vmax0p9: %d kHz\n"
+			"max_dispclk_vnom0p8: %d kHz\n"
+			"max_dispclk_vmid0p72: %d kHz\n"
+			"max_dispclk_vmin0p65: %d kHz\n"
+			"max_dppclk_vmax0p9: %d kHz\n"
+			"max_dppclk_vnom0p8: %d kHz\n"
+			"max_dppclk_vmid0p72: %d kHz\n"
+			"max_dppclk_vmin0p65: %d kHz\n"
+			"socclk: %d kHz\n"
+			"fabric_and_dram_bandwidth_vmax0p9: %d MB/s\n"
+			"fabric_and_dram_bandwidth_vnom0p8: %d MB/s\n"
+			"fabric_and_dram_bandwidth_vmid0p72: %d MB/s\n"
+			"fabric_and_dram_bandwidth_vmin0p65: %d MB/s\n"
+			"phyclkv_max0p9: %d kHz\n"
+			"phyclkv_nom0p8: %d kHz\n"
+			"phyclkv_mid0p72: %d kHz\n"
+			"phyclkv_min0p65: %d kHz\n"
+			"downspreading: %d %\n"
+			"round_trip_ping_latency_cycles: %d DCFCLK Cycles\n"
+			"urgent_out_of_order_return_per_channel: %d Bytes\n"
+			"number_of_channels: %d\n"
+			"vmm_page_size: %d Bytes\n"
+			"dram_clock_change_latency: %d ns\n"
+			"return_bus_width: %d Bytes\n",
+			dc->dcn_soc.sr_exit_time * 1000,
+			dc->dcn_soc.sr_enter_plus_exit_time * 1000,
+			dc->dcn_soc.urgent_latency * 1000,
+			dc->dcn_soc.write_back_latency * 1000,
+			dc->dcn_soc.percent_of_ideal_drambw_received_after_urg_latency,
+			dc->dcn_soc.max_request_size,
+			dc->dcn_soc.dcfclkv_max0p9 * 1000,
+			dc->dcn_soc.dcfclkv_nom0p8 * 1000,
+			dc->dcn_soc.dcfclkv_mid0p72 * 1000,
+			dc->dcn_soc.dcfclkv_min0p65 * 1000,
+			dc->dcn_soc.max_dispclk_vmax0p9 * 1000,
+			dc->dcn_soc.max_dispclk_vnom0p8 * 1000,
+			dc->dcn_soc.max_dispclk_vmid0p72 * 1000,
+			dc->dcn_soc.max_dispclk_vmin0p65 * 1000,
+			dc->dcn_soc.max_dppclk_vmax0p9 * 1000,
+			dc->dcn_soc.max_dppclk_vnom0p8 * 1000,
+			dc->dcn_soc.max_dppclk_vmid0p72 * 1000,
+			dc->dcn_soc.max_dppclk_vmin0p65 * 1000,
+			dc->dcn_soc.socclk * 1000,
+			dc->dcn_soc.fabric_and_dram_bandwidth_vmax0p9 * 1000,
+			dc->dcn_soc.fabric_and_dram_bandwidth_vnom0p8 * 1000,
+			dc->dcn_soc.fabric_and_dram_bandwidth_vmid0p72 * 1000,
+			dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65 * 1000,
+			dc->dcn_soc.phyclkv_max0p9 * 1000,
+			dc->dcn_soc.phyclkv_nom0p8 * 1000,
+			dc->dcn_soc.phyclkv_mid0p72 * 1000,
+			dc->dcn_soc.phyclkv_min0p65 * 1000,
+			dc->dcn_soc.downspreading * 100,
+			dc->dcn_soc.round_trip_ping_latency_cycles,
+			dc->dcn_soc.urgent_out_of_order_return_per_channel,
+			dc->dcn_soc.number_of_channels,
+			dc->dcn_soc.vmm_page_size,
+			dc->dcn_soc.dram_clock_change_latency * 1000,
+			dc->dcn_soc.return_bus_width);
+	dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
+			"rob_buffer_size_in_kbyte: %d\n"
+			"det_buffer_size_in_kbyte: %d\n"
+			"dpp_output_buffer_pixels: %d\n"
+			"opp_output_buffer_lines: %d\n"
+			"pixel_chunk_size_in_kbyte: %d\n"
+			"pte_enable: %d\n"
+			"pte_chunk_size: %d kbytes\n"
+			"meta_chunk_size: %d kbytes\n"
+			"writeback_chunk_size: %d kbytes\n"
+			"odm_capability: %d\n"
+			"dsc_capability: %d\n"
+			"line_buffer_size: %d bits\n"
+			"max_line_buffer_lines: %d\n"
+			"is_line_buffer_bpp_fixed: %d\n"
+			"line_buffer_fixed_bpp: %d\n"
+			"writeback_luma_buffer_size: %d kbytes\n"
+			"writeback_chroma_buffer_size: %d kbytes\n"
+			"max_num_dpp: %d\n"
+			"max_num_writeback: %d\n"
+			"max_dchub_topscl_throughput: %d pixels/dppclk\n"
+			"max_pscl_tolb_throughput: %d pixels/dppclk\n"
+			"max_lb_tovscl_throughput: %d pixels/dppclk\n"
+			"max_vscl_tohscl_throughput: %d pixels/dppclk\n"
+			"max_hscl_ratio: %d\n"
+			"max_vscl_ratio: %d\n"
+			"max_hscl_taps: %d\n"
+			"max_vscl_taps: %d\n"
+			"pte_buffer_size_in_requests: %d\n"
+			"dispclk_ramping_margin: %d %\n"
+			"under_scan_factor: %d %\n"
+			"max_inter_dcn_tile_repeaters: %d\n"
+			"can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one: %d\n"
+			"bug_forcing_luma_and_chroma_request_to_same_size_fixed: %d\n"
+			"dcfclk_cstate_latency: %d\n",
+			dc->dcn_ip.rob_buffer_size_in_kbyte,
+			dc->dcn_ip.det_buffer_size_in_kbyte,
+			dc->dcn_ip.dpp_output_buffer_pixels,
+			dc->dcn_ip.opp_output_buffer_lines,
+			dc->dcn_ip.pixel_chunk_size_in_kbyte,
+			dc->dcn_ip.pte_enable,
+			dc->dcn_ip.pte_chunk_size,
+			dc->dcn_ip.meta_chunk_size,
+			dc->dcn_ip.writeback_chunk_size,
+			dc->dcn_ip.odm_capability,
+			dc->dcn_ip.dsc_capability,
+			dc->dcn_ip.line_buffer_size,
+			dc->dcn_ip.max_line_buffer_lines,
+			dc->dcn_ip.is_line_buffer_bpp_fixed,
+			dc->dcn_ip.line_buffer_fixed_bpp,
+			dc->dcn_ip.writeback_luma_buffer_size,
+			dc->dcn_ip.writeback_chroma_buffer_size,
+			dc->dcn_ip.max_num_dpp,
+			dc->dcn_ip.max_num_writeback,
+			dc->dcn_ip.max_dchub_topscl_throughput,
+			dc->dcn_ip.max_pscl_tolb_throughput,
+			dc->dcn_ip.max_lb_tovscl_throughput,
+			dc->dcn_ip.max_vscl_tohscl_throughput,
+			dc->dcn_ip.max_hscl_ratio,
+			dc->dcn_ip.max_vscl_ratio,
+			dc->dcn_ip.max_hscl_taps,
+			dc->dcn_ip.max_vscl_taps,
+			dc->dcn_ip.pte_buffer_size_in_requests,
+			dc->dcn_ip.dispclk_ramping_margin,
+			dc->dcn_ip.under_scan_factor * 100,
+			dc->dcn_ip.max_inter_dcn_tile_repeaters,
+			dc->dcn_ip.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one,
+			dc->dcn_ip.bug_forcing_luma_and_chroma_request_to_same_size_fixed,
+			dc->dcn_ip.dcfclk_cstate_latency);
 	dc->dml.soc.vmin.socclk_mhz = dc->dcn_soc.socclk;
 	dc->dml.soc.vmid.socclk_mhz = dc->dcn_soc.socclk;
 	dc->dml.soc.vnom.socclk_mhz = dc->dcn_soc.socclk;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index fb5bacb50ebc..47870a640f37 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1379,8 +1379,10 @@ void dc_update_surfaces_and_stream(struct dc *dc,
 		if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) {
 			BREAK_TO_DEBUGGER();
 			goto fail;
-		} else
+		} else {
 			core_dc->hwss.set_bandwidth(core_dc, context, false);
+			context_clock_trace(dc, context);
+		}
 	}
 
 	if (!surface_count)  /* reset */
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
index c60b59f41693..263dab6337a6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
@@ -29,6 +29,13 @@
 				##__VA_ARGS__); \
 } while (0)
 
+#define CLOCK_TRACE(...) do {\
+	if (dc->debug.clock_trace) \
+		dm_logger_write(logger, \
+				LOG_BANDWIDTH_CALCS, \
+				##__VA_ARGS__); \
+} while (0)
+
 void pre_surface_trace(
 		const struct dc *dc,
 		const struct dc_surface *const *surfaces,
@@ -314,3 +321,32 @@ void context_timing_trace(
 				h_pos[i], v_pos[i]);
 	}
 }
+
+void context_clock_trace(
+		const struct dc *dc,
+		struct validate_context *context)
+{
+	struct core_dc *core_dc = DC_TO_CORE(dc);
+	struct dal_logger *logger =  core_dc->ctx->logger;
+
+	CLOCK_TRACE("Current: dispclk_khz:%d  dppclk_div:%d  dcfclk_khz:%d\n"
+			"dcfclk_deep_sleep_khz:%d  fclk_khz:%d\n"
+			"dram_ccm_us:%d  min_active_dram_ccm_us:%d\n",
+			context->bw.dcn.calc_clk.dispclk_khz,
+			context->bw.dcn.calc_clk.dppclk_div,
+			context->bw.dcn.calc_clk.dcfclk_khz,
+			context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz,
+			context->bw.dcn.calc_clk.fclk_khz,
+			context->bw.dcn.calc_clk.dram_ccm_us,
+			context->bw.dcn.calc_clk.min_active_dram_ccm_us);
+	CLOCK_TRACE("Calculated: dispclk_khz:%d  dppclk_div:%d  dcfclk_khz:%d\n"
+			"dcfclk_deep_sleep_khz:%d  fclk_khz:%d\n"
+			"dram_ccm_us:%d  min_active_dram_ccm_us:%d\n",
+			context->bw.dcn.calc_clk.dispclk_khz,
+			context->bw.dcn.calc_clk.dppclk_div,
+			context->bw.dcn.calc_clk.dcfclk_khz,
+			context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz,
+			context->bw.dcn.calc_clk.fclk_khz,
+			context->bw.dcn.calc_clk.dram_ccm_us,
+			context->bw.dcn.calc_clk.min_active_dram_ccm_us);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 7191b2519334..e08e532cafb8 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -160,6 +160,7 @@ struct dc_debug {
 	bool max_disp_clk;
 	bool surface_trace;
 	bool timing_trace;
+	bool clock_trace;
 	bool validation_trace;
 	bool disable_stutter;
 	bool disable_dcc;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 0a346aafacce..93a34e2ef175 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1412,6 +1412,128 @@ static void dcn10_enable_timing_synchronization(
 	DC_SYNC_INFO("Sync complete\n");
 }
 
+static void print_rq_dlg_ttu(
+		struct core_dc *core_dc,
+		struct pipe_ctx *pipe_ctx)
+{
+	dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
+			"\n============== DML TTU Output parameters [%d] ==============\n"
+			"qos_level_low_wm: %d, \n"
+			"qos_level_high_wm: %d, \n"
+			"min_ttu_vblank: %d, \n"
+			"qos_level_flip: %d, \n"
+			"refcyc_per_req_delivery_l: %d, \n"
+			"qos_level_fixed_l: %d, \n"
+			"qos_ramp_disable_l: %d, \n"
+			"refcyc_per_req_delivery_pre_l: %d, \n"
+			"refcyc_per_req_delivery_c: %d, \n"
+			"qos_level_fixed_c: %d, \n"
+			"qos_ramp_disable_c: %d, \n"
+			"refcyc_per_req_delivery_pre_c: %d\n"
+			"=============================================================\n",
+			pipe_ctx->pipe_idx,
+			pipe_ctx->ttu_regs.qos_level_low_wm,
+			pipe_ctx->ttu_regs.qos_level_high_wm,
+			pipe_ctx->ttu_regs.min_ttu_vblank,
+			pipe_ctx->ttu_regs.qos_level_flip,
+			pipe_ctx->ttu_regs.refcyc_per_req_delivery_l,
+			pipe_ctx->ttu_regs.qos_level_fixed_l,
+			pipe_ctx->ttu_regs.qos_ramp_disable_l,
+			pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_l,
+			pipe_ctx->ttu_regs.refcyc_per_req_delivery_c,
+			pipe_ctx->ttu_regs.qos_level_fixed_c,
+			pipe_ctx->ttu_regs.qos_ramp_disable_c,
+			pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
+			);
+
+	dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
+			"\n============== DML DLG Output parameters [%d] ==============\n"
+			"refcyc_h_blank_end: %d, \n"
+			"dlg_vblank_end: %d, \n"
+			"min_dst_y_next_start: %d, \n"
+			"refcyc_per_htotal: %d, \n"
+			"refcyc_x_after_scaler: %d, \n"
+			"dst_y_after_scaler: %d, \n"
+			"dst_y_prefetch: %d, \n"
+			"dst_y_per_vm_vblank: %d, \n"
+			"dst_y_per_row_vblank: %d, \n"
+			"ref_freq_to_pix_freq: %d, \n"
+			"vratio_prefetch: %d, \n"
+			"refcyc_per_pte_group_vblank_l: %d, \n"
+			"refcyc_per_meta_chunk_vblank_l: %d, \n"
+			"dst_y_per_pte_row_nom_l: %d, \n"
+			"refcyc_per_pte_group_nom_l: %d, \n",
+			pipe_ctx->pipe_idx,
+			pipe_ctx->dlg_regs.refcyc_h_blank_end,
+			pipe_ctx->dlg_regs.dlg_vblank_end,
+			pipe_ctx->dlg_regs.min_dst_y_next_start,
+			pipe_ctx->dlg_regs.refcyc_per_htotal,
+			pipe_ctx->dlg_regs.refcyc_x_after_scaler,
+			pipe_ctx->dlg_regs.dst_y_after_scaler,
+			pipe_ctx->dlg_regs.dst_y_prefetch,
+			pipe_ctx->dlg_regs.dst_y_per_vm_vblank,
+			pipe_ctx->dlg_regs.dst_y_per_row_vblank,
+			pipe_ctx->dlg_regs.ref_freq_to_pix_freq,
+			pipe_ctx->dlg_regs.vratio_prefetch,
+			pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_l,
+			pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_l,
+			pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_l,
+			pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
+			);
+
+	dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
+			"\ndst_y_per_meta_row_nom_l: %d, \n"
+			"refcyc_per_meta_chunk_nom_l: %d, \n"
+			"refcyc_per_line_delivery_pre_l: %d, \n"
+			"refcyc_per_line_delivery_l: %d, \n"
+			"vratio_prefetch_c: %d, \n"
+			"refcyc_per_pte_group_vblank_c: %d, \n"
+			"refcyc_per_meta_chunk_vblank_c: %d, \n"
+			"dst_y_per_pte_row_nom_c: %d, \n"
+			"refcyc_per_pte_group_nom_c: %d, \n"
+			"dst_y_per_meta_row_nom_c: %d, \n"
+			"refcyc_per_meta_chunk_nom_c: %d, \n"
+			"refcyc_per_line_delivery_pre_c: %d, \n"
+			"refcyc_per_line_delivery_c: %d \n"
+			"========================================================\n",
+			pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_l,
+			pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_l,
+			pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l,
+			pipe_ctx->dlg_regs.refcyc_per_line_delivery_l,
+			pipe_ctx->dlg_regs.vratio_prefetch_c,
+			pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_c,
+			pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_c,
+			pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_c,
+			pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_c,
+			pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_c,
+			pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_c,
+			pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_c,
+			pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
+			);
+
+	dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
+			"\n============== DML RQ Output parameters [%d] ==============\n"
+			"chunk_size: %d \n"
+			"min_chunk_size: %d \n"
+			"meta_chunk_size: %d \n"
+			"min_meta_chunk_size: %d \n"
+			"dpte_group_size: %d \n"
+			"mpte_group_size: %d \n"
+			"swath_height: %d \n"
+			"pte_row_height_linear: %d \n"
+			"========================================================\n",
+			pipe_ctx->pipe_idx,
+			pipe_ctx->rq_regs.rq_regs_l.chunk_size,
+			pipe_ctx->rq_regs.rq_regs_l.min_chunk_size,
+			pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size,
+			pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size,
+			pipe_ctx->rq_regs.rq_regs_l.dpte_group_size,
+			pipe_ctx->rq_regs.rq_regs_l.mpte_group_size,
+			pipe_ctx->rq_regs.rq_regs_l.swath_height,
+			pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear
+			);
+}
+
 static void dcn10_power_on_fe(
 	struct core_dc *dc,
 	struct pipe_ctx *pipe_ctx,
@@ -1419,57 +1541,52 @@ static void dcn10_power_on_fe(
 {
 	struct dc_surface *dc_surface = &pipe_ctx->surface->public;
 
-	/* power up DCHUP and DPP from pseudo code pipe_move.c */
-	 /*TODO: function: power_on_plane. If already power up, skip
-	 */
-	{
-		power_on_plane(dc->ctx,
-			pipe_ctx->pipe_idx, pipe_ctx->tg->inst);
+	power_on_plane(dc->ctx,
+		pipe_ctx->pipe_idx, pipe_ctx->tg->inst);
 
-		/* enable DCFCLK current DCHUB */
-		enable_dcfclk(dc->ctx,
+	/* enable DCFCLK current DCHUB */
+	enable_dcfclk(dc->ctx,
+			pipe_ctx->pipe_idx,
+			pipe_ctx->pix_clk_params.requested_pix_clk,
+			context->bw.dcn.calc_clk.dppclk_div);
+	dc->current_context->bw.dcn.cur_clk.dppclk_div =
+			context->bw.dcn.calc_clk.dppclk_div;
+	context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div;
+
+	if (dc_surface) {
+		dm_logger_write(dc->ctx->logger, LOG_DC,
+				"Pipe:%d 0x%x: addr hi:0x%x, "
+				"addr low:0x%x, "
+				"src: %d, %d, %d,"
+				" %d; dst: %d, %d, %d, %d;\n",
 				pipe_ctx->pipe_idx,
-				pipe_ctx->pix_clk_params.requested_pix_clk,
-				context->bw.dcn.calc_clk.dppclk_div);
-		dc->current_context->bw.dcn.cur_clk.dppclk_div =
-				context->bw.dcn.calc_clk.dppclk_div;
-		context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div;
-
-		if (dc_surface) {
-			dm_logger_write(dc->ctx->logger, LOG_DC,
-					"Pipe:%d 0x%x: addr hi:0x%x, "
-					"addr low:0x%x, "
-					"src: %d, %d, %d,"
-					" %d; dst: %d, %d, %d, %d;\n",
-					pipe_ctx->pipe_idx,
-					dc_surface,
-					dc_surface->address.grph.addr.high_part,
-					dc_surface->address.grph.addr.low_part,
-					dc_surface->src_rect.x,
-					dc_surface->src_rect.y,
-					dc_surface->src_rect.width,
-					dc_surface->src_rect.height,
-					dc_surface->dst_rect.x,
-					dc_surface->dst_rect.y,
-					dc_surface->dst_rect.width,
-					dc_surface->dst_rect.height);
-
-			dm_logger_write(dc->ctx->logger, LOG_HW_SET_MODE,
-					"Pipe %d: width, height, x, y\n"
-					"viewport:%d, %d, %d, %d\n"
-					"recout:  %d, %d, %d, %d\n",
-					pipe_ctx->pipe_idx,
-					pipe_ctx->scl_data.viewport.width,
-					pipe_ctx->scl_data.viewport.height,
-					pipe_ctx->scl_data.viewport.x,
-					pipe_ctx->scl_data.viewport.y,
-					pipe_ctx->scl_data.recout.width,
-					pipe_ctx->scl_data.recout.height,
-					pipe_ctx->scl_data.recout.x,
-					pipe_ctx->scl_data.recout.y);
-		}
+				dc_surface,
+				dc_surface->address.grph.addr.high_part,
+				dc_surface->address.grph.addr.low_part,
+				dc_surface->src_rect.x,
+				dc_surface->src_rect.y,
+				dc_surface->src_rect.width,
+				dc_surface->src_rect.height,
+				dc_surface->dst_rect.x,
+				dc_surface->dst_rect.y,
+				dc_surface->dst_rect.width,
+				dc_surface->dst_rect.height);
+
+		dm_logger_write(dc->ctx->logger, LOG_HW_SET_MODE,
+				"Pipe %d: width, height, x, y\n"
+				"viewport:%d, %d, %d, %d\n"
+				"recout:  %d, %d, %d, %d\n",
+				pipe_ctx->pipe_idx,
+				pipe_ctx->scl_data.viewport.width,
+				pipe_ctx->scl_data.viewport.height,
+				pipe_ctx->scl_data.viewport.x,
+				pipe_ctx->scl_data.viewport.y,
+				pipe_ctx->scl_data.recout.width,
+				pipe_ctx->scl_data.recout.height,
+				pipe_ctx->scl_data.recout.x,
+				pipe_ctx->scl_data.recout.y);
+		print_rq_dlg_ttu(dc, pipe_ctx);
 	}
-
 }
 
 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
@@ -1743,6 +1860,53 @@ static void dcn10_apply_ctx_for_surface(
 		}
 	}
 
+	dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
+			"\n============== Watermark parameters ==============\n"
+			"a.urgent_ns: %d \n"
+			"a.cstate_enter_plus_exit: %d \n"
+			"a.cstate_exit: %d \n"
+			"a.pstate_change: %d \n"
+			"a.pte_meta_urgent: %d \n"
+			"b.urgent_ns: %d \n"
+			"b.cstate_enter_plus_exit: %d \n"
+			"b.cstate_exit: %d \n"
+			"b.pstate_change: %d \n"
+			"b.pte_meta_urgent: %d \n",
+			context->bw.dcn.watermarks.a.urgent_ns,
+			context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns,
+			context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns,
+			context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns,
+			context->bw.dcn.watermarks.a.pte_meta_urgent_ns,
+			context->bw.dcn.watermarks.b.urgent_ns,
+			context->bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns,
+			context->bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns,
+			context->bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns,
+			context->bw.dcn.watermarks.b.pte_meta_urgent_ns
+			);
+	dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
+			"\nc.urgent_ns: %d \n"
+			"c.cstate_enter_plus_exit: %d \n"
+			"c.cstate_exit: %d \n"
+			"c.pstate_change: %d \n"
+			"c.pte_meta_urgent: %d \n"
+			"d.urgent_ns: %d \n"
+			"d.cstate_enter_plus_exit: %d \n"
+			"d.cstate_exit: %d \n"
+			"d.pstate_change: %d \n"
+			"d.pte_meta_urgent: %d \n"
+			"========================================================\n",
+			context->bw.dcn.watermarks.c.urgent_ns,
+			context->bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns,
+			context->bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns,
+			context->bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns,
+			context->bw.dcn.watermarks.c.pte_meta_urgent_ns,
+			context->bw.dcn.watermarks.d.urgent_ns,
+			context->bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns,
+			context->bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns,
+			context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns,
+			context->bw.dcn.watermarks.d.pte_meta_urgent_ns
+			);
+
 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index e527d10b3e1f..6ada9a262721 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -429,6 +429,7 @@ static const struct dc_debug debug_defaults_drv = {
 		.disable_dmcu = true,
 		.force_abm_enable = false,
 		.timing_trace = false,
+		.clock_trace = true,
 		.disable_pplib_clock_request = true,
 		.disable_pplib_wm_range = false,
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
@@ -441,6 +442,7 @@ static const struct dc_debug debug_defaults_diags = {
 		.disable_dmcu = true,
 		.force_abm_enable = false,
 		.timing_trace = true,
+		.clock_trace = true,
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 		.disable_pplib_clock_request = true,
 		.disable_pplib_wm_range = true,
diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h
index 08a6911d3a3a..b75c343f8680 100644
--- a/drivers/gpu/drm/amd/display/include/logger_interface.h
+++ b/drivers/gpu/drm/amd/display/include/logger_interface.h
@@ -32,6 +32,7 @@ struct dc_context;
 struct dc_link;
 struct dc_surface_update;
 struct resource_context;
+struct validate_context;
 
 /*
  *
@@ -90,6 +91,9 @@ void context_timing_trace(
 		const struct dc *dc,
 		struct resource_context *res_ctx);
 
+void context_clock_trace(
+		const struct dc *dc,
+		struct validate_context *context);
 
 /* Any function which is empty or have incomplete implementation should be
  * marked by this macro.
-- 
2.11.0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 26/27] drm/amd/display: RV stereo support

[Harry Wentland]

From: Vitaly Prosyak <vitaly.prosyak@amd.com>

HDMI frame pack and DP frame alternate in band

Change-Id: I643614508abc3b93bf841ccf5f070b9566919f23
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h                |  21 ++-
 .../amd/display/dc/dcn10/dcn10_timing_generator.c  | 184 ++++++++++-----------
 .../amd/display/dc/dcn10/dcn10_timing_generator.h  |   5 +
 .../drm/amd/display/dc/inc/hw/timing_generator.h   |  12 ++
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |   4 +
 5 files changed, 124 insertions(+), 102 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index e08e532cafb8..fb86808dd309 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -361,6 +361,7 @@ struct dc_surface_status {
 	struct dc_plane_address requested_address;
 	struct dc_plane_address current_address;
 	bool is_flip_pending;
+	bool is_right_eye;
 };
 
 /*
@@ -476,7 +477,7 @@ struct dc_stream {
 	const struct dc_transfer_func *out_transfer_func;
 	struct colorspace_transform gamut_remap_matrix;
 	struct csc_transform csc_color_matrix;
-
+	enum view_3d_format view_format;
 	/* TODO: custom INFO packets */
 	/* TODO: ABM info (DMCU) */
 	/* TODO: PSR info */
@@ -591,6 +592,15 @@ bool dc_commit_streams(
 		struct dc *dc,
 		const struct dc_stream *streams[],
 		uint8_t stream_count);
+/*
+ * Enable stereo when commit_streams is not required,
+ * for example, frame alternate.
+ */
+bool dc_enable_stereo(
+	struct dc *dc,
+	struct validate_context *context,
+	const struct dc_stream *streams[],
+	uint8_t stream_count);
 
 /**
  * Create a new default stream for the requested sink
@@ -777,6 +787,14 @@ struct dc_container_id {
 	unsigned short productCode;
 };
 
+struct stereo_3d_features {
+	bool supported			;
+	bool allTimings			;
+	bool cloneMode			;
+	bool scaling			;
+	bool singleFrameSWPacked;
+};
+
 /*
  * The sink structure contains EDID and other display device properties
  */
@@ -788,6 +806,7 @@ struct dc_sink {
 	uint32_t dongle_max_pix_clk;
 	bool converter_disable_audio;
 	void *priv;
+	struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
 };
 
 void dc_sink_retain(const struct dc_sink *sink);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
index c5a636c750fa..bc3934d75b46 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
@@ -78,112 +78,22 @@ static void dcn10_program_global_sync(
 			VREADY_OFFSET, tg->dlg_otg_param.vready_offset);
 }
 
-struct crtc_stereo_flags {
-	uint8_t PROGRAM_STEREO         :1;
-	uint8_t PROGRAM_POLARITY       :1;
-	uint8_t RIGHT_EYE_POLARITY     :1;
-	uint8_t FRAME_PACKED           :1;
-	uint8_t DISABLE_STEREO_DP_SYNC :1;
-};
-
-static void dcn10_enable_stereo(struct timing_generator *tg,
-		const struct crtc_stereo_flags *flags,
-		const struct dc_crtc_timing *timing)
-{
-	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-
-	uint32_t active_width = timing->h_addressable;
-	uint32_t space1_size = timing->v_total - timing->v_addressable;
-
-	if (flags) {
-		uint32_t stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0;
-
-		if (flags->PROGRAM_STEREO)
-			REG_UPDATE_3(OTG_STEREO_CONTROL,
-					OTG_STEREO_EN, stereo_en,
-					OTG_STEREO_SYNC_OUTPUT_LINE_NUM, 0,
-					OTG_STEREO_SYNC_OUTPUT_POLARITY, 0);
-
-		if (flags->PROGRAM_POLARITY)
-			REG_UPDATE(OTG_STEREO_CONTROL,
-					OTG_STEREO_EYE_FLAG_POLARITY,
-					flags->RIGHT_EYE_POLARITY == 0 ? 0:1);
-
-		if (flags->DISABLE_STEREO_DP_SYNC)
-			REG_UPDATE(OTG_STEREO_CONTROL,
-					OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1);
-
-		if (flags->PROGRAM_STEREO && flags->FRAME_PACKED)
-			REG_UPDATE_3(OTG_3D_STRUCTURE_CONTROL,
-					OTG_3D_STRUCTURE_EN, 1,
-					OTG_3D_STRUCTURE_V_UPDATE_MODE, 1,
-					OTG_3D_STRUCTURE_STEREO_SEL_OVR, 1);
-
-	}
-
-	REG_UPDATE(OPPBUF_CONTROL,
-			OPPBUF_ACTIVE_WIDTH, active_width);
-
-	REG_UPDATE(OPPBUF_3D_PARAMETERS_0,
-			OPPBUF_3D_VACT_SPACE1_SIZE, space1_size);
-
-	return;
-}
-
 static void dcn10_disable_stereo(struct timing_generator *tg)
 {
 	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
 
 	REG_SET(OTG_STEREO_CONTROL, 0,
-			OTG_STEREO_EN, 0);
+		OTG_STEREO_EN, 0);
 
 	REG_SET_3(OTG_3D_STRUCTURE_CONTROL, 0,
-			OTG_3D_STRUCTURE_EN, 0,
-			OTG_3D_STRUCTURE_V_UPDATE_MODE, 0,
-			OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0);
+		OTG_3D_STRUCTURE_EN, 0,
+		OTG_3D_STRUCTURE_V_UPDATE_MODE, 0,
+		OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0);
 
 	REG_UPDATE(OPPBUF_CONTROL,
-			OPPBUF_ACTIVE_WIDTH, 0);
+		OPPBUF_ACTIVE_WIDTH, 0);
 	REG_UPDATE(OPPBUF_3D_PARAMETERS_0,
-			OPPBUF_3D_VACT_SPACE1_SIZE, 0);
-	return;
-}
-
-static bool is_frame_alternate_stereo(enum dc_timing_3d_format fmt)
-{
-	bool ret = false;
-	if (fmt == TIMING_3D_FORMAT_FRAME_ALTERNATE ||
-		fmt == TIMING_3D_FORMAT_INBAND_FA ||
-		fmt == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA ||
-		fmt == TIMING_3D_FORMAT_SIDEBAND_FA)
-		ret = true;
-	return ret;
-}
-
-static void dcn10_do_stereo(struct timing_generator *tg,
-		const struct dc_crtc_timing *dc_crtc_timing)
-{
-	struct crtc_stereo_flags stereo_flags = {0};
-	if (dc_crtc_timing->timing_3d_format == TIMING_3D_FORMAT_NONE ||
-		dc_crtc_timing->timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE ||
-		dc_crtc_timing->timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)
-		dcn10_disable_stereo(tg);
-	else {
-		stereo_flags.PROGRAM_STEREO = 1;
-		stereo_flags.PROGRAM_POLARITY = 1;
-		stereo_flags.DISABLE_STEREO_DP_SYNC = 0;
-		stereo_flags.RIGHT_EYE_POLARITY =
-				dc_crtc_timing->flags.RIGHT_EYE_3D_POLARITY;
-		if (dc_crtc_timing->timing_3d_format ==
-				TIMING_3D_FORMAT_HW_FRAME_PACKING)
-			stereo_flags.FRAME_PACKED = 1;
-
-		if (is_frame_alternate_stereo(
-				dc_crtc_timing->timing_3d_format) ||
-				dc_crtc_timing->timing_3d_format ==
-					TIMING_3D_FORMAT_HW_FRAME_PACKING)
-			dcn10_enable_stereo(tg, &stereo_flags, dc_crtc_timing);
-	}
+		OPPBUF_3D_VACT_SPACE1_SIZE, 0);
 }
 
 /**
@@ -361,9 +271,8 @@ static void tg_program_timing_generator(
 	REG_UPDATE(OTG_H_TIMING_CNTL,
 			OTG_H_TIMING_DIV_BY2, h_div_2);
 
-	/* Enable crtc stereo frame pack tested... todo more
-	 */
-	dcn10_do_stereo(tg, &patched_crtc_timing);
+	dcn10_disable_stereo( tg);
+
 }
 
 /** tg_program_blanking
@@ -605,7 +514,8 @@ static bool tg_validate_timing(
 		timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING &&
 		timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM &&
 		timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE &&
-		timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE)
+		timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE &&
+		timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA)
 		return false;
 
 	/* Temporarily blocking interlacing mode until it's supported */
@@ -1145,6 +1055,76 @@ void dcn10_timing_generator_get_crtc_scanoutpos(
 	*v_position = position.vertical_count;
 }
 
+
+
+static void dcn10_enable_stereo(struct timing_generator *tg,
+	const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
+{
+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+
+	uint32_t active_width = timing->h_addressable;
+	uint32_t space1_size = timing->v_total - timing->v_addressable;
+
+	if (flags) {
+		uint32_t stereo_en;
+		stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0;
+
+		if (flags->PROGRAM_STEREO)
+			REG_UPDATE_3(OTG_STEREO_CONTROL,
+				OTG_STEREO_EN, stereo_en,
+				OTG_STEREO_SYNC_OUTPUT_LINE_NUM, 0,
+				OTG_STEREO_SYNC_OUTPUT_POLARITY, 0);
+
+		if (flags->PROGRAM_POLARITY)
+			REG_UPDATE(OTG_STEREO_CONTROL,
+				OTG_STEREO_EYE_FLAG_POLARITY,
+				flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1);
+
+		if (flags->DISABLE_STEREO_DP_SYNC)
+			REG_UPDATE(OTG_STEREO_CONTROL,
+				OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1);
+
+		if (flags->PROGRAM_STEREO && flags->FRAME_PACKED)
+			REG_UPDATE_3(OTG_3D_STRUCTURE_CONTROL,
+				OTG_3D_STRUCTURE_EN, 1,
+				OTG_3D_STRUCTURE_V_UPDATE_MODE, 1,
+				OTG_3D_STRUCTURE_STEREO_SEL_OVR, 1);
+
+	}
+
+	REG_UPDATE(OPPBUF_CONTROL,
+		OPPBUF_ACTIVE_WIDTH, active_width);
+
+	REG_UPDATE(OPPBUF_3D_PARAMETERS_0,
+		OPPBUF_3D_VACT_SPACE1_SIZE, space1_size);
+}
+
+static void dcn10_program_stereo(struct timing_generator *tg,
+	const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
+{
+	if (flags->PROGRAM_STEREO)
+		dcn10_enable_stereo(tg, timing, flags);
+	else
+		dcn10_disable_stereo(tg);
+}
+
+
+static bool dcn10_is_stereo_left_eye(struct timing_generator *tg)
+{
+	bool ret = false;
+	uint32_t left_eye = 0;
+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+
+	REG_GET(OTG_STEREO_STATUS,
+		OTG_STEREO_CURRENT_EYE, &left_eye);
+	if (left_eye == 1)
+		ret = true;
+	else
+		ret = false;
+
+	return ret;
+}
+
 static struct timing_generator_funcs dcn10_tg_funcs = {
 		.validate_timing = tg_validate_timing,
 		.program_timing = tg_program_timing,
@@ -1183,7 +1163,9 @@ static struct timing_generator_funcs dcn10_tg_funcs = {
 		.enable_optc_clock = enable_optc_clock,
 		.set_drr = dcn10_timing_generator_set_drr,
 		.set_static_screen_control = set_static_screen_control,
-		.set_test_pattern = dcn10_timing_generator_set_test_pattern
+		.set_test_pattern = dcn10_timing_generator_set_test_pattern,
+		.program_stereo = dcn10_program_stereo,
+		.is_stereo_left_eye = dcn10_is_stereo_left_eye
 };
 
 void dcn10_timing_generator_init(struct dcn10_timing_generator *tgn10)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
index 85a763af1956..c880fa587790 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
@@ -51,6 +51,7 @@
 	SRI(OTG_CONTROL, OTG, inst),\
 	SRI(OTG_STEREO_CONTROL, OTG, inst),\
 	SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
+	SRI(OTG_STEREO_STATUS, OTG, inst),\
 	SRI(OTG_V_TOTAL_MAX, OTG, inst),\
 	SRI(OTG_V_TOTAL_MIN, OTG, inst),\
 	SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
@@ -96,6 +97,7 @@ struct dcn_tg_registers {
 	uint32_t OTG_CONTROL;
 	uint32_t OTG_STEREO_CONTROL;
 	uint32_t OTG_3D_STRUCTURE_CONTROL;
+	uint32_t OTG_STEREO_STATUS;
 	uint32_t OTG_V_TOTAL_MAX;
 	uint32_t OTG_V_TOTAL_MIN;
 	uint32_t OTG_V_TOTAL_CONTROL;
@@ -157,6 +159,8 @@ struct dcn_tg_registers {
 	SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\
 	SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\
 	SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
+	SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
+	SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\
 	SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\
 	SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
 	SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
@@ -243,6 +247,7 @@ struct dcn_tg_registers {
 	type OTG_STEREO_SYNC_OUTPUT_LINE_NUM;\
 	type OTG_STEREO_SYNC_OUTPUT_POLARITY;\
 	type OTG_STEREO_EYE_FLAG_POLARITY;\
+	type OTG_STEREO_CURRENT_EYE;\
 	type OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP;\
 	type OTG_3D_STRUCTURE_EN;\
 	type OTG_3D_STRUCTURE_V_UPDATE_MODE;\
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index 9f130affb31c..2b72d1d8012f 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -100,6 +100,15 @@ struct _dlg_otg_param {
 	enum signal_type signal;
 };
 #endif
+
+struct crtc_stereo_flags {
+	uint8_t PROGRAM_STEREO         : 1;
+	uint8_t PROGRAM_POLARITY       : 1;
+	uint8_t RIGHT_EYE_POLARITY     : 1;
+	uint8_t FRAME_PACKED           : 1;
+	uint8_t DISABLE_STEREO_DP_SYNC : 1;
+};
+
 struct timing_generator {
 	const struct timing_generator_funcs *funcs;
 	struct dc_bios *bp;
@@ -171,6 +180,9 @@ struct timing_generator_funcs {
 	void (*program_global_sync)(struct timing_generator *tg);
 	void (*enable_optc_clock)(struct timing_generator *tg, bool enable);
 #endif
+	void (*program_stereo)(struct timing_generator *tg,
+		const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags);
+	bool (*is_stereo_left_eye)(struct timing_generator *tg);
 };
 
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 6f8733ec9b16..52884815c67b 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -143,6 +143,10 @@ struct hw_sequencer_funcs {
 			struct pipe_ctx *pipe_ctx,
 			struct validate_context *context,
 			struct core_dc *dc);
+
+	void (*setup_stereo)(
+			struct pipe_ctx *pipe_ctx,
+			struct core_dc *dc);
 };
 
 void color_space_to_black_color(
-- 
2.11.0

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[PATCH 27/27] drm/amd/display: disable dcc when reset front end.

[Harry Wentland]

From: Yongqiang Sun <yongqiang.sun@amd.com>

Change-Id: Ief8354f612161481cd303512fa41001376504f81
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c |  2 ++
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c    | 15 +++++++++++----
 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h         |  3 +++
 3 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 93a34e2ef175..f2b581faa9b7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -825,6 +825,8 @@ static void reset_front_end_for_pipe(
 	if (!pipe_ctx->surface)
 		return;
 
+	pipe_ctx->mi->funcs->dcc_control(pipe_ctx->mi, false, false);
+
 	lock_otg_master_update(dc->ctx, pipe_ctx->tg->inst);
 
 	/* TODO: build stream pipes group id. For now, use stream otg
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
index 8ad70625a746..a58993aa400f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
@@ -369,16 +369,22 @@ static bool mem_input_program_surface_flip_and_addr(
 	return true;
 }
 
-static void program_control(struct dcn10_mem_input *mi,
-		struct dc_plane_dcc_param *dcc)
+static void dcc_control(struct mem_input *mem_input, bool enable,
+		bool independent_64b_blks)
 {
-	uint32_t dcc_en = dcc->enable ? 1 : 0;
-	uint32_t dcc_ind_64b_blk = dcc->grph.independent_64b_blks ? 1 : 0;
+	uint32_t dcc_en = enable ? 1 : 0;
+	uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0;
+	struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
 
 	REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
 			PRIMARY_SURFACE_DCC_EN, dcc_en,
 			PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk);
+}
 
+static void program_control(struct dcn10_mem_input *mi,
+		struct dc_plane_dcc_param *dcc)
+{
+	dcc_control(&mi->base, dcc->enable, dcc->grph.independent_64b_blks);
 }
 
 static void mem_input_program_surface_config(
@@ -1072,6 +1078,7 @@ static struct mem_input_funcs dcn10_mem_input_funcs = {
 	.mem_input_update_dchub = mem_input_update_dchub,
 	.mem_input_program_pte_vm = dcn_mem_input_program_pte_vm,
 	.set_blank = dcn_mi_set_blank,
+	.dcc_control = dcc_control,
 };
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
index bd0dfeb2afa2..64b810d48d07 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
@@ -86,6 +86,9 @@ struct mem_input_funcs {
 			struct _vcs_dpi_display_ttu_regs_st *ttu_regs,
 			struct _vcs_dpi_display_rq_regs_st *rq_regs,
 			struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);
+
+	void (*dcc_control)(struct mem_input *mem_input, bool enable,
+			bool independent_64b_blks);
 #endif
 
 	void (*mem_input_program_display_marks)(
-- 
2.11.0

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Re: [PATCH 00/27] DC Linux Patches Jun 9, 2017

[Tom St Denis]

These don't apply on top of 4.11 it fails on patch 4 "drm/amd/display: 
Universal cursor plane hook-up."

Maybe a rebase mistake when 4.11 was created?

Tom

On 09/06/17 04:11 PM, Harry Wentland wrote:
>   * Universal cursor plane
>   * Bunch of Raven fixes
>   * Couple of fixes for IGT
> 
> Amy Zhang (3):
>    drm/amd/display: Add function to get PSR state
>    drm/amd/display: Refactor to call set PSR wait loop in dce_dmcu
>      instead of dce_clocks
>    drm/amd/display: Fix DRR Enable on Desktop
> 
> Andrey Grodzovsky (2):
>    drm/amd/display: Universal cursor plane hook-up.
>    drm/amd/display: Remove redundant member from amdgpu_plane.
> 
> Anthony Koo (1):
>    drm/amd/display: Temporary disable BTR FreeSync support for now
> 
> Charlene Liu (1):
>    drm/amd/display: fix single link black screen
> 
> Corbin McElhanney (2):
>    drm/amd/display: Don't update surface if dimensions are 0
>    drm/amd/display: Add assertion for invalid surface dimensions
> 
> Dmytro Laktyushkin (8):
>    drm/amd/display: allow taking split pipes during resource mapping
>    drm/amd/display: fix surface attachment handling of pipe split
>    drm/amd/display: fix mpo + split pipe aquisition failure
>    drm/amd/display: clean up mpc programing during fe reset
>    drm/amd/display: fix mpc alpha programming
>    drm/amd/display: propagate surface alpha setting from OS to DC
>    drm/amd/display: fix enable_optc_clock reg_wait timeouts
>    drm/amd/display: add bw logging for dcn
> 
> Harry Wentland (1):
>    drm/amd/display: No need to get property before set
> 
> Hersen Wu (2):
>    drm/amd/display: Enable DCN clock gating
>    drm/amd/display: remove disable_clk_gate debug flag for DCN
> 
> Leo (Sunpeng) Li (1):
>    drm/amd/display: Remove unsupported RGB formats
> 
> Tony Cheng (1):
>    drm/amd/display: disable forced stutter disable after programming
>      watermark
> 
> Vitaly Prosyak (1):
>    drm/amd/display: RV stereo support
> 
> Yongqiang Sun (2):
>    drm/amd/display: Use surface update inuse for pending check.
>    drm/amd/display: disable dcc when reset front end.
> 
> Zeyu Fan (2):
>    drm/amd/display: Add function to log connectivity
>    drm/amd/display: Call program_gamut explicitly instead of entire
>      set_plane
> 
>   drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  |   2 +-
>   .../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c  |   6 +
>   .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c    | 274 +++++--------
>   .../gpu/drm/amd/display/dc/basics/log_helpers.c    |   3 +
>   drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c   | 138 +++++++
>   drivers/gpu/drm/amd/display/dc/core/dc.c           |  26 +-
>   drivers/gpu/drm/amd/display/dc/core/dc_debug.c     |  42 +-
>   drivers/gpu/drm/amd/display/dc/core/dc_link.c      |  65 +--
>   drivers/gpu/drm/amd/display/dc/core/dc_resource.c  |  90 +++--
>   drivers/gpu/drm/amd/display/dc/dc.h                |  29 +-
>   drivers/gpu/drm/amd/display/dc/dc_helper.c         |   8 +-
>   drivers/gpu/drm/amd/display/dc/dc_types.h          | 103 ++++-
>   drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c    |  41 +-
>   drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c      |  64 +++
>   drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h      |   8 +
>   .../amd/display/dc/dce110/dce110_hw_sequencer.c    |  42 ++
>   .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 435 ++++++++++++++-------
>   .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c |  30 +-
>   .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h |  38 ++
>   drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c   | 201 ++++------
>   drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h   |   6 +-
>   .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |   7 +-
>   .../amd/display/dc/dcn10/dcn10_timing_generator.c  | 192 +++++----
>   .../amd/display/dc/dcn10/dcn10_timing_generator.h  |   5 +
>   drivers/gpu/drm/amd/display/dc/dm_helpers.h        |   4 +
>   drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h       |   4 +
>   .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h   | 101 -----
>   drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h  |   3 +
>   drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h        |  19 +-
>   .../drm/amd/display/dc/inc/hw/timing_generator.h   |  12 +
>   drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |   7 +
>   .../gpu/drm/amd/display/include/logger_interface.h |   4 +
>   .../drm/amd/display/modules/freesync/freesync.c    | 102 +++--
>   .../gpu/drm/amd/display/modules/inc/mod_freesync.h |   3 +-
>   34 files changed, 1305 insertions(+), 809 deletions(-)
> 

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Re: [PATCH 00/27] DC Linux Patches Jun 9, 2017

[Harry Wentland]

On 2017-06-12 07:12 AM, Tom St Denis wrote:
> These don't apply on top of 4.11 it fails on patch 4 "drm/amd/display:
> Universal cursor plane hook-up."
> 
> Maybe a rebase mistake when 4.11 was created?
> 

I think the previous set is still missing. I'll merge the lot today.

Harry

> Tom
> 
> On 09/06/17 04:11 PM, Harry Wentland wrote:
>>   * Universal cursor plane
>>   * Bunch of Raven fixes
>>   * Couple of fixes for IGT
>>
>> Amy Zhang (3):
>>    drm/amd/display: Add function to get PSR state
>>    drm/amd/display: Refactor to call set PSR wait loop in dce_dmcu
>>      instead of dce_clocks
>>    drm/amd/display: Fix DRR Enable on Desktop
>>
>> Andrey Grodzovsky (2):
>>    drm/amd/display: Universal cursor plane hook-up.
>>    drm/amd/display: Remove redundant member from amdgpu_plane.
>>
>> Anthony Koo (1):
>>    drm/amd/display: Temporary disable BTR FreeSync support for now
>>
>> Charlene Liu (1):
>>    drm/amd/display: fix single link black screen
>>
>> Corbin McElhanney (2):
>>    drm/amd/display: Don't update surface if dimensions are 0
>>    drm/amd/display: Add assertion for invalid surface dimensions
>>
>> Dmytro Laktyushkin (8):
>>    drm/amd/display: allow taking split pipes during resource mapping
>>    drm/amd/display: fix surface attachment handling of pipe split
>>    drm/amd/display: fix mpo + split pipe aquisition failure
>>    drm/amd/display: clean up mpc programing during fe reset
>>    drm/amd/display: fix mpc alpha programming
>>    drm/amd/display: propagate surface alpha setting from OS to DC
>>    drm/amd/display: fix enable_optc_clock reg_wait timeouts
>>    drm/amd/display: add bw logging for dcn
>>
>> Harry Wentland (1):
>>    drm/amd/display: No need to get property before set
>>
>> Hersen Wu (2):
>>    drm/amd/display: Enable DCN clock gating
>>    drm/amd/display: remove disable_clk_gate debug flag for DCN
>>
>> Leo (Sunpeng) Li (1):
>>    drm/amd/display: Remove unsupported RGB formats
>>
>> Tony Cheng (1):
>>    drm/amd/display: disable forced stutter disable after programming
>>      watermark
>>
>> Vitaly Prosyak (1):
>>    drm/amd/display: RV stereo support
>>
>> Yongqiang Sun (2):
>>    drm/amd/display: Use surface update inuse for pending check.
>>    drm/amd/display: disable dcc when reset front end.
>>
>> Zeyu Fan (2):
>>    drm/amd/display: Add function to log connectivity
>>    drm/amd/display: Call program_gamut explicitly instead of entire
>>      set_plane
>>
>>   drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  |   2 +-
>>   .../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c  |   6 +
>>   .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c    | 274 +++++--------
>>   .../gpu/drm/amd/display/dc/basics/log_helpers.c    |   3 +
>>   drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c   | 138 +++++++
>>   drivers/gpu/drm/amd/display/dc/core/dc.c           |  26 +-
>>   drivers/gpu/drm/amd/display/dc/core/dc_debug.c     |  42 +-
>>   drivers/gpu/drm/amd/display/dc/core/dc_link.c      |  65 +--
>>   drivers/gpu/drm/amd/display/dc/core/dc_resource.c  |  90 +++--
>>   drivers/gpu/drm/amd/display/dc/dc.h                |  29 +-
>>   drivers/gpu/drm/amd/display/dc/dc_helper.c         |   8 +-
>>   drivers/gpu/drm/amd/display/dc/dc_types.h          | 103 ++++-
>>   drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c    |  41 +-
>>   drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c      |  64 +++
>>   drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h      |   8 +
>>   .../amd/display/dc/dce110/dce110_hw_sequencer.c    |  42 ++
>>   .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 435
>> ++++++++++++++-------
>>   .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c |  30 +-
>>   .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h |  38 ++
>>   drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c   | 201 ++++------
>>   drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h   |   6 +-
>>   .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |   7 +-
>>   .../amd/display/dc/dcn10/dcn10_timing_generator.c  | 192 +++++----
>>   .../amd/display/dc/dcn10/dcn10_timing_generator.h  |   5 +
>>   drivers/gpu/drm/amd/display/dc/dm_helpers.h        |   4 +
>>   drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h       |   4 +
>>   .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h   | 101 -----
>>   drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h  |   3 +
>>   drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h        |  19 +-
>>   .../drm/amd/display/dc/inc/hw/timing_generator.h   |  12 +
>>   drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |   7 +
>>   .../gpu/drm/amd/display/include/logger_interface.h |   4 +
>>   .../drm/amd/display/modules/freesync/freesync.c    | 102 +++--
>>   .../gpu/drm/amd/display/modules/inc/mod_freesync.h |   3 +-
>>   34 files changed, 1305 insertions(+), 809 deletions(-)
>>
> 
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