* [PATCH 0/5] drm/i915: PCH detection cleanup
@ 2017-06-20 13:03 ville.syrjala
2017-06-20 13:03 ` [PATCH 1/5] drm/i915: Use HAS_PCH_CPT() everywhere ville.syrjala
` (7 more replies)
0 siblings, 8 replies; 15+ messages in thread
From: ville.syrjala @ 2017-06-20 13:03 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan, Rodrigo Vivi
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
During the recent discusison on the PCH detection details it was
suggested that we should just always use the top 9 bits of the
ISA/LPC bridge device ID to detect the PCH type. Currently we use
either 8 or 9 bits depending on the PCH type.
Series available here:
git://github.com/vsyrjala/linux.git pch_id_9bits
Ville Syrjälä (5):
drm/i915: Use HAS_PCH_CPT() everywhere
drm/i915: s/Couar/Cougar/
drm/i915: Document that PPT==CPT and WPT==LPT
drm/i915: Clean up some expressions
drm/i915: Always use 9 bits of the LPC bridge device ID for PCH
detection
drivers/gpu/drm/i915/i915_drv.c | 51 ++++++++++++++++++--------------
drivers/gpu/drm/i915/i915_drv.h | 19 +++++++-----
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
drivers/gpu/drm/i915/intel_sdvo.c | 2 +-
4 files changed, 41 insertions(+), 33 deletions(-)
--
2.13.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 1/5] drm/i915: Use HAS_PCH_CPT() everywhere
2017-06-20 13:03 [PATCH 0/5] drm/i915: PCH detection cleanup ville.syrjala
@ 2017-06-20 13:03 ` ville.syrjala
2017-06-20 13:03 ` [PATCH 2/5] drm/i915: s/Couar/Cougar/ ville.syrjala
` (6 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: ville.syrjala @ 2017-06-20 13:03 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan, Rodrigo Vivi
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We have a few cases comparing pch_type directly. Let's just replace
them with HAS_PCH_CPT() since CPT/PPT is what they're looking for.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
drivers/gpu/drm/i915/intel_sdvo.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 77d3214e1a77..5f91ddc78c7a 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -363,7 +363,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
*/
if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
- (dev_priv->pch_type == PCH_CPT &&
+ (HAS_PCH_CPT(dev_priv) &&
!(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
DRM_INFO("Display fused off, disabling\n");
info->num_pipes = 0;
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 3f8f30b412cd..f902922d4ae6 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1343,7 +1343,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
}
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_CPT)
+ if (HAS_PCH_CPT(dev_priv))
sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);
else
sdvox |= SDVO_PIPE_SEL(crtc->pipe);
--
2.13.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/5] drm/i915: s/Couar/Cougar/
2017-06-20 13:03 [PATCH 0/5] drm/i915: PCH detection cleanup ville.syrjala
2017-06-20 13:03 ` [PATCH 1/5] drm/i915: Use HAS_PCH_CPT() everywhere ville.syrjala
@ 2017-06-20 13:03 ` ville.syrjala
2017-06-20 13:03 ` [PATCH 3/5] drm/i915: Document that PPT==CPT and WPT==LPT ville.syrjala
` (5 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: ville.syrjala @ 2017-06-20 13:03 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan, Rodrigo Vivi
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Fix a typo in the PCH type debug message.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index ee2325b180e7..aa99619bfc1b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -132,7 +132,7 @@ static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
} else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
ret = PCH_CPT;
- DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
+ DRM_DEBUG_KMS("Assuming CougarPoint PCH\n");
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
ret = PCH_LPT;
DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
--
2.13.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 3/5] drm/i915: Document that PPT==CPT and WPT==LPT
2017-06-20 13:03 [PATCH 0/5] drm/i915: PCH detection cleanup ville.syrjala
2017-06-20 13:03 ` [PATCH 1/5] drm/i915: Use HAS_PCH_CPT() everywhere ville.syrjala
2017-06-20 13:03 ` [PATCH 2/5] drm/i915: s/Couar/Cougar/ ville.syrjala
@ 2017-06-20 13:03 ` ville.syrjala
2017-06-20 13:03 ` [PATCH 4/5] drm/i915: Clean up some expressions ville.syrjala
` (4 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: ville.syrjala @ 2017-06-20 13:03 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan, Rodrigo Vivi
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
For our purposes PPT is equivalent to CPT, and WPT is equivalent to
LPT. Document that fact.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e1f7c97a338a..1b97eb098ffe 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1149,8 +1149,8 @@ struct i915_psr {
enum intel_pch {
PCH_NONE = 0, /* No PCH present */
PCH_IBX, /* Ibexpeak PCH */
- PCH_CPT, /* Cougarpoint PCH */
- PCH_LPT, /* Lynxpoint PCH */
+ PCH_CPT, /* Cougarpoint/Pantherpoint PCH */
+ PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */
PCH_SPT, /* Sunrisepoint PCH */
PCH_KBP, /* Kabypoint PCH */
PCH_CNP, /* Cannonpoint PCH */
--
2.13.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 4/5] drm/i915: Clean up some expressions
2017-06-20 13:03 [PATCH 0/5] drm/i915: PCH detection cleanup ville.syrjala
` (2 preceding siblings ...)
2017-06-20 13:03 ` [PATCH 3/5] drm/i915: Document that PPT==CPT and WPT==LPT ville.syrjala
@ 2017-06-20 13:03 ` ville.syrjala
2017-06-20 13:46 ` Jani Nikula
2017-06-20 13:03 ` [PATCH 5/5] drm/i915: Always use 9 bits of the LPC bridge device ID for PCH detection ville.syrjala
` (3 subsequent siblings)
7 siblings, 1 reply; 15+ messages in thread
From: ville.syrjala @ 2017-06-20 13:03 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan, Rodrigo Vivi
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Write the '!(SNB||IVB)' checks in the CPT/PPT detections
as '!SNB && !IVB' to make it less messy looking, and clear out
some useless parens the from the virtualization PCH detection case.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index aa99619bfc1b..1681be8d21f6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -185,15 +185,15 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
dev_priv->pch_id = id;
dev_priv->pch_type = PCH_CPT;
DRM_DEBUG_KMS("Found CougarPoint PCH\n");
- WARN_ON(!(IS_GEN6(dev_priv) ||
- IS_IVYBRIDGE(dev_priv)));
+ WARN_ON(!IS_GEN6(dev_priv) &&
+ !IS_IVYBRIDGE(dev_priv));
} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
/* PantherPoint is CPT compatible */
dev_priv->pch_id = id;
dev_priv->pch_type = PCH_CPT;
DRM_DEBUG_KMS("Found PantherPoint PCH\n");
- WARN_ON(!(IS_GEN6(dev_priv) ||
- IS_IVYBRIDGE(dev_priv)));
+ WARN_ON(!IS_GEN6(dev_priv) &&
+ !IS_IVYBRIDGE(dev_priv));
} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
dev_priv->pch_id = id;
dev_priv->pch_type = PCH_LPT;
@@ -240,9 +240,9 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
DRM_DEBUG_KMS("Found CannonPoint LP PCH\n");
WARN_ON(!IS_CANNONLAKE(dev_priv) &&
!IS_COFFEELAKE(dev_priv));
- } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
- (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
- ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
+ } else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
+ id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
+ (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
pch->subsystem_vendor ==
PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
pch->subsystem_device ==
--
2.13.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 5/5] drm/i915: Always use 9 bits of the LPC bridge device ID for PCH detection
2017-06-20 13:03 [PATCH 0/5] drm/i915: PCH detection cleanup ville.syrjala
` (3 preceding siblings ...)
2017-06-20 13:03 ` [PATCH 4/5] drm/i915: Clean up some expressions ville.syrjala
@ 2017-06-20 13:03 ` ville.syrjala
2017-06-20 14:34 ` Jani Nikula
` (2 more replies)
2017-06-20 13:49 ` ✗ Fi.CI.BAT: warning for drm/i915: PCH detection cleanup Patchwork
` (2 subsequent siblings)
7 siblings, 3 replies; 15+ messages in thread
From: ville.syrjala @ 2017-06-20 13:03 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan, Rodrigo Vivi
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Make the code less confusiong by always using the top 9 bits of the
LPC bridge device ID to detect the PCH type. We need to add a bit of
new code for WPT, and we need to adjust the KBP ID as well. All the
other pre-CNP IDs are fine as is.
The CNP ID I guessed based on the KBP + CNP LP IDs. But someone else
should really verify this.
The virtualization cases I think are fine. These P2X and P3X IDs
actually just look like the old PIIX4 and PIIX3 IDs to me. Not sure
why they're not called PIIX3/4 though. The qemu one has a comment
saying the full ID is 0x2918 which is fine with 9 bits.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 35 ++++++++++++++++++++---------------
drivers/gpu/drm/i915/i915_drv.h | 15 +++++++++------
2 files changed, 29 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1681be8d21f6..bfb39047f5e1 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -173,29 +173,25 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
if (pch->vendor == PCI_VENDOR_ID_INTEL) {
unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
- unsigned short id_ext = pch->device &
- INTEL_PCH_DEVICE_ID_MASK_EXT;
+
+ dev_priv->pch_id = id;
if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
- dev_priv->pch_id = id;
dev_priv->pch_type = PCH_IBX;
DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
WARN_ON(!IS_GEN5(dev_priv));
} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
- dev_priv->pch_id = id;
dev_priv->pch_type = PCH_CPT;
DRM_DEBUG_KMS("Found CougarPoint PCH\n");
WARN_ON(!IS_GEN6(dev_priv) &&
!IS_IVYBRIDGE(dev_priv));
} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
/* PantherPoint is CPT compatible */
- dev_priv->pch_id = id;
dev_priv->pch_type = PCH_CPT;
DRM_DEBUG_KMS("Found PantherPoint PCH\n");
WARN_ON(!IS_GEN6(dev_priv) &&
!IS_IVYBRIDGE(dev_priv));
} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
- dev_priv->pch_id = id;
dev_priv->pch_type = PCH_LPT;
DRM_DEBUG_KMS("Found LynxPoint PCH\n");
WARN_ON(!IS_HASWELL(dev_priv) &&
@@ -203,39 +199,49 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
WARN_ON(IS_HSW_ULT(dev_priv) ||
IS_BDW_ULT(dev_priv));
} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
- dev_priv->pch_id = id;
dev_priv->pch_type = PCH_LPT;
DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
WARN_ON(!IS_HASWELL(dev_priv) &&
!IS_BROADWELL(dev_priv));
WARN_ON(!IS_HSW_ULT(dev_priv) &&
!IS_BDW_ULT(dev_priv));
+ } else if (id == INTEL_PCH_WPT_DEVICE_ID_TYPE) {
+ /* WildcatPoint is LPT compatible */
+ dev_priv->pch_type = PCH_LPT;
+ DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
+ WARN_ON(!IS_HASWELL(dev_priv) &&
+ !IS_BROADWELL(dev_priv));
+ WARN_ON(IS_HSW_ULT(dev_priv) ||
+ IS_BDW_ULT(dev_priv));
+ } else if (id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE) {
+ /* WildcatPoint is LPT compatible */
+ dev_priv->pch_type = PCH_LPT;
+ DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
+ WARN_ON(!IS_HASWELL(dev_priv) &&
+ !IS_BROADWELL(dev_priv));
+ WARN_ON(!IS_HSW_ULT(dev_priv) &&
+ !IS_BDW_ULT(dev_priv));
} else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
- dev_priv->pch_id = id;
dev_priv->pch_type = PCH_SPT;
DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
WARN_ON(!IS_SKYLAKE(dev_priv) &&
!IS_KABYLAKE(dev_priv));
- } else if (id_ext == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
- dev_priv->pch_id = id_ext;
+ } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_SPT;
DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
WARN_ON(!IS_SKYLAKE(dev_priv) &&
!IS_KABYLAKE(dev_priv));
} else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
- dev_priv->pch_id = id;
dev_priv->pch_type = PCH_KBP;
DRM_DEBUG_KMS("Found KabyPoint PCH\n");
WARN_ON(!IS_SKYLAKE(dev_priv) &&
!IS_KABYLAKE(dev_priv));
} else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
- dev_priv->pch_id = id;
dev_priv->pch_type = PCH_CNP;
DRM_DEBUG_KMS("Found CannonPoint PCH\n");
WARN_ON(!IS_CANNONLAKE(dev_priv) &&
!IS_COFFEELAKE(dev_priv));
- } else if (id_ext == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
- dev_priv->pch_id = id_ext;
+ } else if (id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_CNP;
DRM_DEBUG_KMS("Found CannonPoint LP PCH\n");
WARN_ON(!IS_CANNONLAKE(dev_priv) &&
@@ -247,7 +253,6 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
pch->subsystem_device ==
PCI_SUBDEVICE_ID_QEMU)) {
- dev_priv->pch_id = id;
dev_priv->pch_type =
intel_virt_detect_pch(dev_priv);
} else
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1b97eb098ffe..4a884cf9b47d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2996,17 +2996,18 @@ intel_info(const struct drm_i915_private *dev_priv)
#define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
-#define INTEL_PCH_DEVICE_ID_MASK 0xff00
-#define INTEL_PCH_DEVICE_ID_MASK_EXT 0xff80
+#define INTEL_PCH_DEVICE_ID_MASK 0xff80
#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
+#define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
+#define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
-#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
-#define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
+#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
+#define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA380
#define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
@@ -3020,9 +3021,11 @@ intel_info(const struct drm_i915_private *dev_priv)
#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
#define HAS_PCH_LPT_LP(dev_priv) \
- ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
+ ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
+ (dev_priv)->pch_id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
#define HAS_PCH_LPT_H(dev_priv) \
- ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
+ ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
+ (dev_priv)->pch_id == INTEL_PCH_WPT_DEVICE_ID_TYPE)
#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
--
2.13.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 4/5] drm/i915: Clean up some expressions
2017-06-20 13:03 ` [PATCH 4/5] drm/i915: Clean up some expressions ville.syrjala
@ 2017-06-20 13:46 ` Jani Nikula
0 siblings, 0 replies; 15+ messages in thread
From: Jani Nikula @ 2017-06-20 13:46 UTC (permalink / raw)
To: ville.syrjala, intel-gfx; +Cc: Dhinakaran Pandiyan, Rodrigo Vivi
On Tue, 20 Jun 2017, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Write the '!(SNB||IVB)' checks in the CPT/PPT detections
> as '!SNB && !IVB' to make it less messy looking, and clear out
> some useless parens the from the virtualization PCH detection case.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Patches 1-4
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index aa99619bfc1b..1681be8d21f6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -185,15 +185,15 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
> dev_priv->pch_id = id;
> dev_priv->pch_type = PCH_CPT;
> DRM_DEBUG_KMS("Found CougarPoint PCH\n");
> - WARN_ON(!(IS_GEN6(dev_priv) ||
> - IS_IVYBRIDGE(dev_priv)));
> + WARN_ON(!IS_GEN6(dev_priv) &&
> + !IS_IVYBRIDGE(dev_priv));
> } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
> /* PantherPoint is CPT compatible */
> dev_priv->pch_id = id;
> dev_priv->pch_type = PCH_CPT;
> DRM_DEBUG_KMS("Found PantherPoint PCH\n");
> - WARN_ON(!(IS_GEN6(dev_priv) ||
> - IS_IVYBRIDGE(dev_priv)));
> + WARN_ON(!IS_GEN6(dev_priv) &&
> + !IS_IVYBRIDGE(dev_priv));
> } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
> dev_priv->pch_id = id;
> dev_priv->pch_type = PCH_LPT;
> @@ -240,9 +240,9 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
> DRM_DEBUG_KMS("Found CannonPoint LP PCH\n");
> WARN_ON(!IS_CANNONLAKE(dev_priv) &&
> !IS_COFFEELAKE(dev_priv));
> - } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
> - (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
> - ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
> + } else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
> + id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
> + (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
> pch->subsystem_vendor ==
> PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
> pch->subsystem_device ==
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* ✗ Fi.CI.BAT: warning for drm/i915: PCH detection cleanup
2017-06-20 13:03 [PATCH 0/5] drm/i915: PCH detection cleanup ville.syrjala
` (4 preceding siblings ...)
2017-06-20 13:03 ` [PATCH 5/5] drm/i915: Always use 9 bits of the LPC bridge device ID for PCH detection ville.syrjala
@ 2017-06-20 13:49 ` Patchwork
2017-06-21 18:05 ` ✓ Fi.CI.BAT: success for drm/i915: PCH detection cleanup (rev2) Patchwork
2017-06-22 16:55 ` [PATCH 0/5] drm/i915: PCH detection cleanup Ville Syrjälä
7 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2017-06-20 13:49 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: PCH detection cleanup
URL : https://patchwork.freedesktop.org/series/26046/
State : warning
== Summary ==
Series 26046v1 drm/i915: PCH detection cleanup
https://patchwork.freedesktop.org/api/1.0/series/26046/revisions/1/mbox/
Test gem_exec_suspend:
Subgroup basic-s4-devices:
dmesg-warn -> PASS (fi-kbl-r) fdo#100125
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass -> DMESG-WARN (fi-byt-j1900) fdo#101516
Test drv_module_reload:
Subgroup basic-reload:
pass -> DMESG-WARN (fi-skl-6700hq)
fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125
fdo#101516 https://bugs.freedesktop.org/show_bug.cgi?id=101516
fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time:448s
fi-bdw-gvtdvm total:278 pass:256 dwarn:8 dfail:0 fail:0 skip:14 time:427s
fi-bsw-n3050 total:278 pass:241 dwarn:1 dfail:0 fail:0 skip:36 time:530s
fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time:506s
fi-byt-j1900 total:278 pass:252 dwarn:2 dfail:0 fail:0 skip:24 time:495s
fi-byt-n2820 total:278 pass:248 dwarn:2 dfail:0 fail:0 skip:28 time:484s
fi-glk-2a total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time:589s
fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:434s
fi-hsw-4770r total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:415s
fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time:423s
fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:494s
fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:469s
fi-kbl-7500u total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:469s
fi-kbl-7560u total:278 pass:267 dwarn:1 dfail:0 fail:0 skip:10 time:569s
fi-kbl-r total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:575s
fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:456s
fi-skl-6700hq total:278 pass:220 dwarn:3 dfail:0 fail:30 skip:24 time:338s
fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 time:473s
fi-skl-6770hq total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:472s
fi-skl-gvtdvm total:278 pass:265 dwarn:0 dfail:0 fail:0 skip:13 time:431s
fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:538s
fi-snb-2600 total:278 pass:249 dwarn:0 dfail:0 fail:0 skip:29 time:407s
3e0add868ae0aa06f3203e3862ea74ab94cab013 drm-tip: 2017y-06m-20d-11h-42m-47s UTC integration manifest
0ccd16a drm/i915: Always use 9 bits of the LPC bridge device ID for PCH detection
78ec2a2 drm/i915: Clean up some expressions
34ed642 drm/i915: Document that PPT==CPT and WPT==LPT
8cdafaf drm/i915: s/Couar/Cougar/
046ff25 drm/i915: Use HAS_PCH_CPT() everywhere
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4997/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 5/5] drm/i915: Always use 9 bits of the LPC bridge device ID for PCH detection
2017-06-20 13:03 ` [PATCH 5/5] drm/i915: Always use 9 bits of the LPC bridge device ID for PCH detection ville.syrjala
@ 2017-06-20 14:34 ` Jani Nikula
2017-06-20 14:52 ` Ville Syrjälä
2017-06-20 18:36 ` Pandiyan, Dhinakaran
2017-06-21 17:49 ` [PATCH v2 " ville.syrjala
2 siblings, 1 reply; 15+ messages in thread
From: Jani Nikula @ 2017-06-20 14:34 UTC (permalink / raw)
To: ville.syrjala, intel-gfx; +Cc: Dhinakaran Pandiyan, Rodrigo Vivi
On Tue, 20 Jun 2017, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Make the code less confusiong by always using the top 9 bits of the
> LPC bridge device ID to detect the PCH type. We need to add a bit of
> new code for WPT, and we need to adjust the KBP ID as well. All the
> other pre-CNP IDs are fine as is.
Seems to me this fixes a (theoretical?) bug with KBP matching some
Lewisburg parts (a2xx).
> The CNP ID I guessed based on the KBP + CNP LP IDs. But someone else
> should really verify this.
Sorry, couldn't find definite info on this.
> The virtualization cases I think are fine. These P2X and P3X IDs
> actually just look like the old PIIX4 and PIIX3 IDs to me. Not sure
> why they're not called PIIX3/4 though. The qemu one has a comment
> saying the full ID is 0x2918 which is fine with 9 bits.
Nor this. This starts ignoring some 71xx device ids, but I'm guessing
they're not relevant.
Not as strong confidence as I'd like, but
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
PS. I thought about switching this to array based matching. It could
define the mask for each id to be matched, so you could e.g. add qemu as
0x2918. And you could have the debug strings there too. But I couldn't
think of a neat way to do the platform/pch cross checks (callbacks don't
count as neat). So I guess this is good enough for now.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 35 ++++++++++++++++++++---------------
> drivers/gpu/drm/i915/i915_drv.h | 15 +++++++++------
> 2 files changed, 29 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 1681be8d21f6..bfb39047f5e1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -173,29 +173,25 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
> while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
> if (pch->vendor == PCI_VENDOR_ID_INTEL) {
Someone should switch this to "if (vendor != intel) continue" when the
dust has settled, and free up some horizontal screen real estate.
> unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
> - unsigned short id_ext = pch->device &
> - INTEL_PCH_DEVICE_ID_MASK_EXT;
> +
> + dev_priv->pch_id = id;
>
> if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
> - dev_priv->pch_id = id;
> dev_priv->pch_type = PCH_IBX;
> DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
> WARN_ON(!IS_GEN5(dev_priv));
> } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
> - dev_priv->pch_id = id;
> dev_priv->pch_type = PCH_CPT;
> DRM_DEBUG_KMS("Found CougarPoint PCH\n");
> WARN_ON(!IS_GEN6(dev_priv) &&
> !IS_IVYBRIDGE(dev_priv));
> } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
> /* PantherPoint is CPT compatible */
> - dev_priv->pch_id = id;
> dev_priv->pch_type = PCH_CPT;
> DRM_DEBUG_KMS("Found PantherPoint PCH\n");
> WARN_ON(!IS_GEN6(dev_priv) &&
> !IS_IVYBRIDGE(dev_priv));
> } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
> - dev_priv->pch_id = id;
> dev_priv->pch_type = PCH_LPT;
> DRM_DEBUG_KMS("Found LynxPoint PCH\n");
> WARN_ON(!IS_HASWELL(dev_priv) &&
> @@ -203,39 +199,49 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
> WARN_ON(IS_HSW_ULT(dev_priv) ||
> IS_BDW_ULT(dev_priv));
> } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
> - dev_priv->pch_id = id;
> dev_priv->pch_type = PCH_LPT;
> DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
> WARN_ON(!IS_HASWELL(dev_priv) &&
> !IS_BROADWELL(dev_priv));
> WARN_ON(!IS_HSW_ULT(dev_priv) &&
> !IS_BDW_ULT(dev_priv));
> + } else if (id == INTEL_PCH_WPT_DEVICE_ID_TYPE) {
> + /* WildcatPoint is LPT compatible */
> + dev_priv->pch_type = PCH_LPT;
> + DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
> + WARN_ON(!IS_HASWELL(dev_priv) &&
> + !IS_BROADWELL(dev_priv));
> + WARN_ON(IS_HSW_ULT(dev_priv) ||
> + IS_BDW_ULT(dev_priv));
> + } else if (id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE) {
> + /* WildcatPoint is LPT compatible */
> + dev_priv->pch_type = PCH_LPT;
> + DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
> + WARN_ON(!IS_HASWELL(dev_priv) &&
> + !IS_BROADWELL(dev_priv));
> + WARN_ON(!IS_HSW_ULT(dev_priv) &&
> + !IS_BDW_ULT(dev_priv));
> } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
> - dev_priv->pch_id = id;
> dev_priv->pch_type = PCH_SPT;
> DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
> WARN_ON(!IS_SKYLAKE(dev_priv) &&
> !IS_KABYLAKE(dev_priv));
> - } else if (id_ext == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
> - dev_priv->pch_id = id_ext;
> + } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
> dev_priv->pch_type = PCH_SPT;
> DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
> WARN_ON(!IS_SKYLAKE(dev_priv) &&
> !IS_KABYLAKE(dev_priv));
> } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
> - dev_priv->pch_id = id;
> dev_priv->pch_type = PCH_KBP;
> DRM_DEBUG_KMS("Found KabyPoint PCH\n");
> WARN_ON(!IS_SKYLAKE(dev_priv) &&
> !IS_KABYLAKE(dev_priv));
> } else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
> - dev_priv->pch_id = id;
> dev_priv->pch_type = PCH_CNP;
> DRM_DEBUG_KMS("Found CannonPoint PCH\n");
> WARN_ON(!IS_CANNONLAKE(dev_priv) &&
> !IS_COFFEELAKE(dev_priv));
> - } else if (id_ext == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
> - dev_priv->pch_id = id_ext;
> + } else if (id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
> dev_priv->pch_type = PCH_CNP;
> DRM_DEBUG_KMS("Found CannonPoint LP PCH\n");
> WARN_ON(!IS_CANNONLAKE(dev_priv) &&
> @@ -247,7 +253,6 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
> PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
> pch->subsystem_device ==
> PCI_SUBDEVICE_ID_QEMU)) {
> - dev_priv->pch_id = id;
> dev_priv->pch_type =
> intel_virt_detect_pch(dev_priv);
> } else
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1b97eb098ffe..4a884cf9b47d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2996,17 +2996,18 @@ intel_info(const struct drm_i915_private *dev_priv)
>
> #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
>
> -#define INTEL_PCH_DEVICE_ID_MASK 0xff00
> -#define INTEL_PCH_DEVICE_ID_MASK_EXT 0xff80
> +#define INTEL_PCH_DEVICE_ID_MASK 0xff80
> #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
> #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
> #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
> #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
> #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
> +#define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
> +#define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
> #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
> #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
> -#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
> -#define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
> +#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
> +#define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA380
> #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
> #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
> #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
> @@ -3020,9 +3021,11 @@ intel_info(const struct drm_i915_private *dev_priv)
> #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
> #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
> #define HAS_PCH_LPT_LP(dev_priv) \
> - ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
> + ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
> + (dev_priv)->pch_id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
> #define HAS_PCH_LPT_H(dev_priv) \
> - ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
> + ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
> + (dev_priv)->pch_id == INTEL_PCH_WPT_DEVICE_ID_TYPE)
> #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
> #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
> #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 5/5] drm/i915: Always use 9 bits of the LPC bridge device ID for PCH detection
2017-06-20 14:34 ` Jani Nikula
@ 2017-06-20 14:52 ` Ville Syrjälä
0 siblings, 0 replies; 15+ messages in thread
From: Ville Syrjälä @ 2017-06-20 14:52 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, Dhinakaran Pandiyan, Rodrigo Vivi
On Tue, Jun 20, 2017 at 05:34:42PM +0300, Jani Nikula wrote:
> On Tue, 20 Jun 2017, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Make the code less confusiong by always using the top 9 bits of the
> > LPC bridge device ID to detect the PCH type. We need to add a bit of
> > new code for WPT, and we need to adjust the KBP ID as well. All the
> > other pre-CNP IDs are fine as is.
>
> Seems to me this fixes a (theoretical?) bug with KBP matching some
> Lewisburg parts (a2xx).
I presume those things wouldn't have a GPU anyway, so can't happen I
suppose.
>
> > The CNP ID I guessed based on the KBP + CNP LP IDs. But someone else
> > should really verify this.
>
> Sorry, couldn't find definite info on this.
>
> > The virtualization cases I think are fine. These P2X and P3X IDs
> > actually just look like the old PIIX4 and PIIX3 IDs to me. Not sure
> > why they're not called PIIX3/4 though. The qemu one has a comment
> > saying the full ID is 0x2918 which is fine with 9 bits.
>
> Nor this. This starts ignoring some 71xx device ids, but I'm guessing
> they're not relevant.
The 440MX I guess. Not sure why any virtual machine would present
the mobile variant rather than the desktop 440BX. So I wouldn't
worry about it, and if it turns out that I'm wrong we can always
add the extra ID.
>
> Not as strong confidence as I'd like, but
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
>
> PS. I thought about switching this to array based matching. It could
> define the mask for each id to be matched, so you could e.g. add qemu as
> 0x2918. And you could have the debug strings there too. But I couldn't
> think of a neat way to do the platform/pch cross checks (callbacks don't
> count as neat). So I guess this is good enough for now.
My brain went through the same exercise, and came up with the same
result unfortunately.
>
>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.c | 35 ++++++++++++++++++++---------------
> > drivers/gpu/drm/i915/i915_drv.h | 15 +++++++++------
> > 2 files changed, 29 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > index 1681be8d21f6..bfb39047f5e1 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -173,29 +173,25 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
> > while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
> > if (pch->vendor == PCI_VENDOR_ID_INTEL) {
>
> Someone should switch this to "if (vendor != intel) continue" when the
> dust has settled, and free up some horizontal screen real estate.
>
> > unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
> > - unsigned short id_ext = pch->device &
> > - INTEL_PCH_DEVICE_ID_MASK_EXT;
> > +
> > + dev_priv->pch_id = id;
> >
> > if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
> > - dev_priv->pch_id = id;
> > dev_priv->pch_type = PCH_IBX;
> > DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
> > WARN_ON(!IS_GEN5(dev_priv));
> > } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
> > - dev_priv->pch_id = id;
> > dev_priv->pch_type = PCH_CPT;
> > DRM_DEBUG_KMS("Found CougarPoint PCH\n");
> > WARN_ON(!IS_GEN6(dev_priv) &&
> > !IS_IVYBRIDGE(dev_priv));
> > } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
> > /* PantherPoint is CPT compatible */
> > - dev_priv->pch_id = id;
> > dev_priv->pch_type = PCH_CPT;
> > DRM_DEBUG_KMS("Found PantherPoint PCH\n");
> > WARN_ON(!IS_GEN6(dev_priv) &&
> > !IS_IVYBRIDGE(dev_priv));
> > } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
> > - dev_priv->pch_id = id;
> > dev_priv->pch_type = PCH_LPT;
> > DRM_DEBUG_KMS("Found LynxPoint PCH\n");
> > WARN_ON(!IS_HASWELL(dev_priv) &&
> > @@ -203,39 +199,49 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
> > WARN_ON(IS_HSW_ULT(dev_priv) ||
> > IS_BDW_ULT(dev_priv));
> > } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
> > - dev_priv->pch_id = id;
> > dev_priv->pch_type = PCH_LPT;
> > DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
> > WARN_ON(!IS_HASWELL(dev_priv) &&
> > !IS_BROADWELL(dev_priv));
> > WARN_ON(!IS_HSW_ULT(dev_priv) &&
> > !IS_BDW_ULT(dev_priv));
> > + } else if (id == INTEL_PCH_WPT_DEVICE_ID_TYPE) {
> > + /* WildcatPoint is LPT compatible */
> > + dev_priv->pch_type = PCH_LPT;
> > + DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
> > + WARN_ON(!IS_HASWELL(dev_priv) &&
> > + !IS_BROADWELL(dev_priv));
> > + WARN_ON(IS_HSW_ULT(dev_priv) ||
> > + IS_BDW_ULT(dev_priv));
> > + } else if (id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE) {
> > + /* WildcatPoint is LPT compatible */
> > + dev_priv->pch_type = PCH_LPT;
> > + DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
> > + WARN_ON(!IS_HASWELL(dev_priv) &&
> > + !IS_BROADWELL(dev_priv));
> > + WARN_ON(!IS_HSW_ULT(dev_priv) &&
> > + !IS_BDW_ULT(dev_priv));
> > } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
> > - dev_priv->pch_id = id;
> > dev_priv->pch_type = PCH_SPT;
> > DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
> > WARN_ON(!IS_SKYLAKE(dev_priv) &&
> > !IS_KABYLAKE(dev_priv));
> > - } else if (id_ext == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
> > - dev_priv->pch_id = id_ext;
> > + } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
> > dev_priv->pch_type = PCH_SPT;
> > DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
> > WARN_ON(!IS_SKYLAKE(dev_priv) &&
> > !IS_KABYLAKE(dev_priv));
> > } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
> > - dev_priv->pch_id = id;
> > dev_priv->pch_type = PCH_KBP;
> > DRM_DEBUG_KMS("Found KabyPoint PCH\n");
> > WARN_ON(!IS_SKYLAKE(dev_priv) &&
> > !IS_KABYLAKE(dev_priv));
> > } else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
> > - dev_priv->pch_id = id;
> > dev_priv->pch_type = PCH_CNP;
> > DRM_DEBUG_KMS("Found CannonPoint PCH\n");
> > WARN_ON(!IS_CANNONLAKE(dev_priv) &&
> > !IS_COFFEELAKE(dev_priv));
> > - } else if (id_ext == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
> > - dev_priv->pch_id = id_ext;
> > + } else if (id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
> > dev_priv->pch_type = PCH_CNP;
> > DRM_DEBUG_KMS("Found CannonPoint LP PCH\n");
> > WARN_ON(!IS_CANNONLAKE(dev_priv) &&
> > @@ -247,7 +253,6 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
> > PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
> > pch->subsystem_device ==
> > PCI_SUBDEVICE_ID_QEMU)) {
> > - dev_priv->pch_id = id;
> > dev_priv->pch_type =
> > intel_virt_detect_pch(dev_priv);
> > } else
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 1b97eb098ffe..4a884cf9b47d 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -2996,17 +2996,18 @@ intel_info(const struct drm_i915_private *dev_priv)
> >
> > #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
> >
> > -#define INTEL_PCH_DEVICE_ID_MASK 0xff00
> > -#define INTEL_PCH_DEVICE_ID_MASK_EXT 0xff80
> > +#define INTEL_PCH_DEVICE_ID_MASK 0xff80
> > #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
> > #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
> > #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
> > #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
> > #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
> > +#define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
> > +#define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
> > #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
> > #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
> > -#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
> > -#define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
> > +#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
> > +#define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA380
> > #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
> > #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
> > #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
> > @@ -3020,9 +3021,11 @@ intel_info(const struct drm_i915_private *dev_priv)
> > #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
> > #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
> > #define HAS_PCH_LPT_LP(dev_priv) \
> > - ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
> > + ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
> > + (dev_priv)->pch_id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
> > #define HAS_PCH_LPT_H(dev_priv) \
> > - ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
> > + ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
> > + (dev_priv)->pch_id == INTEL_PCH_WPT_DEVICE_ID_TYPE)
> > #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
> > #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
> > #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
>
> --
> Jani Nikula, Intel Open Source Technology Center
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 5/5] drm/i915: Always use 9 bits of the LPC bridge device ID for PCH detection
2017-06-20 13:03 ` [PATCH 5/5] drm/i915: Always use 9 bits of the LPC bridge device ID for PCH detection ville.syrjala
2017-06-20 14:34 ` Jani Nikula
@ 2017-06-20 18:36 ` Pandiyan, Dhinakaran
2017-06-20 18:50 ` Ville Syrjälä
2017-06-21 17:49 ` [PATCH v2 " ville.syrjala
2 siblings, 1 reply; 15+ messages in thread
From: Pandiyan, Dhinakaran @ 2017-06-20 18:36 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx, Vivi, Rodrigo
On Tue, 2017-06-20 at 16:03 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Make the code less confusiong by always using the top 9 bits of the
> LPC bridge device ID to detect the PCH type. We need to add a bit of
> new code for WPT, and we need to adjust the KBP ID as well. All the
> other pre-CNP IDs are fine as is.
I had a similar patch written but dropped it because I could not
ascertain the nature of support for WPT and the full Dev ID's for P2X
and P3X. Still cannot verify if the changes for P2X and P3X are correct,
but thanks for doing this.
Curious if LPC is the same as ISA, which iirc the code refers to.
>
> The CNP ID I guessed based on the KBP + CNP LP IDs. But someone else
> should really verify this.
>
The previous version was correct.
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> with
the CNP change reverted.
> The virtualization cases I think are fine. These P2X and P3X IDs
> actually just look like the old PIIX4 and PIIX3 IDs to me. Not sure
> why they're not called PIIX3/4 though. The qemu one has a comment
> saying the full ID is 0x2918 which is fine with 9 bits.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 35 ++++++++++++++++++++---------------
> drivers/gpu/drm/i915/i915_drv.h | 15 +++++++++------
> 2 files changed, 29 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 1681be8d21f6..bfb39047f5e1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -173,29 +173,25 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
> while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
> if (pch->vendor == PCI_VENDOR_ID_INTEL) {
> unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
> - unsigned short id_ext = pch->device &
> - INTEL_PCH_DEVICE_ID_MASK_EXT;
> +
> + dev_priv->pch_id = id;
>
> if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
> - dev_priv->pch_id = id;
> dev_priv->pch_type = PCH_IBX;
> DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
> WARN_ON(!IS_GEN5(dev_priv));
> } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
> - dev_priv->pch_id = id;
> dev_priv->pch_type = PCH_CPT;
> DRM_DEBUG_KMS("Found CougarPoint PCH\n");
> WARN_ON(!IS_GEN6(dev_priv) &&
> !IS_IVYBRIDGE(dev_priv));
> } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
> /* PantherPoint is CPT compatible */
> - dev_priv->pch_id = id;
> dev_priv->pch_type = PCH_CPT;
> DRM_DEBUG_KMS("Found PantherPoint PCH\n");
> WARN_ON(!IS_GEN6(dev_priv) &&
> !IS_IVYBRIDGE(dev_priv));
> } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
> - dev_priv->pch_id = id;
> dev_priv->pch_type = PCH_LPT;
> DRM_DEBUG_KMS("Found LynxPoint PCH\n");
> WARN_ON(!IS_HASWELL(dev_priv) &&
> @@ -203,39 +199,49 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
> WARN_ON(IS_HSW_ULT(dev_priv) ||
> IS_BDW_ULT(dev_priv));
> } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
> - dev_priv->pch_id = id;
> dev_priv->pch_type = PCH_LPT;
> DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
> WARN_ON(!IS_HASWELL(dev_priv) &&
> !IS_BROADWELL(dev_priv));
> WARN_ON(!IS_HSW_ULT(dev_priv) &&
> !IS_BDW_ULT(dev_priv));
> + } else if (id == INTEL_PCH_WPT_DEVICE_ID_TYPE) {
> + /* WildcatPoint is LPT compatible */
> + dev_priv->pch_type = PCH_LPT;
> + DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
> + WARN_ON(!IS_HASWELL(dev_priv) &&
> + !IS_BROADWELL(dev_priv));
> + WARN_ON(IS_HSW_ULT(dev_priv) ||
> + IS_BDW_ULT(dev_priv));
> + } else if (id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE) {
> + /* WildcatPoint is LPT compatible */
> + dev_priv->pch_type = PCH_LPT;
> + DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
> + WARN_ON(!IS_HASWELL(dev_priv) &&
> + !IS_BROADWELL(dev_priv));
> + WARN_ON(!IS_HSW_ULT(dev_priv) &&
> + !IS_BDW_ULT(dev_priv));
> } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
> - dev_priv->pch_id = id;
> dev_priv->pch_type = PCH_SPT;
> DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
> WARN_ON(!IS_SKYLAKE(dev_priv) &&
> !IS_KABYLAKE(dev_priv));
> - } else if (id_ext == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
> - dev_priv->pch_id = id_ext;
> + } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
> dev_priv->pch_type = PCH_SPT;
> DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
> WARN_ON(!IS_SKYLAKE(dev_priv) &&
> !IS_KABYLAKE(dev_priv));
> } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
> - dev_priv->pch_id = id;
> dev_priv->pch_type = PCH_KBP;
> DRM_DEBUG_KMS("Found KabyPoint PCH\n");
> WARN_ON(!IS_SKYLAKE(dev_priv) &&
> !IS_KABYLAKE(dev_priv));
> } else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
> - dev_priv->pch_id = id;
> dev_priv->pch_type = PCH_CNP;
> DRM_DEBUG_KMS("Found CannonPoint PCH\n");
> WARN_ON(!IS_CANNONLAKE(dev_priv) &&
> !IS_COFFEELAKE(dev_priv));
> - } else if (id_ext == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
> - dev_priv->pch_id = id_ext;
> + } else if (id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
> dev_priv->pch_type = PCH_CNP;
> DRM_DEBUG_KMS("Found CannonPoint LP PCH\n");
> WARN_ON(!IS_CANNONLAKE(dev_priv) &&
> @@ -247,7 +253,6 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
> PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
> pch->subsystem_device ==
> PCI_SUBDEVICE_ID_QEMU)) {
> - dev_priv->pch_id = id;
> dev_priv->pch_type =
> intel_virt_detect_pch(dev_priv);
> } else
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1b97eb098ffe..4a884cf9b47d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2996,17 +2996,18 @@ intel_info(const struct drm_i915_private *dev_priv)
>
> #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
>
> -#define INTEL_PCH_DEVICE_ID_MASK 0xff00
> -#define INTEL_PCH_DEVICE_ID_MASK_EXT 0xff80
> +#define INTEL_PCH_DEVICE_ID_MASK 0xff80
> #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
> #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
> #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
> #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
> #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
> +#define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
> +#define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
> #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
> #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
> -#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
> -#define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
> +#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
> +#define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA380
0xA300
> #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
> #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
> #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
> @@ -3020,9 +3021,11 @@ intel_info(const struct drm_i915_private *dev_priv)
> #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
> #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
> #define HAS_PCH_LPT_LP(dev_priv) \
> - ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
> + ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
> + (dev_priv)->pch_id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
> #define HAS_PCH_LPT_H(dev_priv) \
> - ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
> + ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
> + (dev_priv)->pch_id == INTEL_PCH_WPT_DEVICE_ID_TYPE)
> #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
> #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
> #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 5/5] drm/i915: Always use 9 bits of the LPC bridge device ID for PCH detection
2017-06-20 18:36 ` Pandiyan, Dhinakaran
@ 2017-06-20 18:50 ` Ville Syrjälä
0 siblings, 0 replies; 15+ messages in thread
From: Ville Syrjälä @ 2017-06-20 18:50 UTC (permalink / raw)
To: Pandiyan, Dhinakaran; +Cc: intel-gfx, Vivi, Rodrigo
On Tue, Jun 20, 2017 at 06:36:11PM +0000, Pandiyan, Dhinakaran wrote:
>
>
>
> On Tue, 2017-06-20 at 16:03 +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Make the code less confusiong by always using the top 9 bits of the
> > LPC bridge device ID to detect the PCH type. We need to add a bit of
> > new code for WPT, and we need to adjust the KBP ID as well. All the
> > other pre-CNP IDs are fine as is.
>
> I had a similar patch written but dropped it because I could not
> ascertain the nature of support for WPT and the full Dev ID's for P2X
> and P3X. Still cannot verify if the changes for P2X and P3X are correct,
> but thanks for doing this.
>
> Curious if LPC is the same as ISA, which iirc the code refers to.
LPC is the stripped down to the bone remnants of ISA.
>
>
> >
> > The CNP ID I guessed based on the KBP + CNP LP IDs. But someone else
> > should really verify this.
> >
>
> The previous version was correct.
Dang. Apparently my crystal ball wasn't quite good enough.
>
> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> with
> the CNP change reverted.
>
> > The virtualization cases I think are fine. These P2X and P3X IDs
> > actually just look like the old PIIX4 and PIIX3 IDs to me. Not sure
> > why they're not called PIIX3/4 though. The qemu one has a comment
> > saying the full ID is 0x2918 which is fine with 9 bits.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.c | 35 ++++++++++++++++++++---------------
> > drivers/gpu/drm/i915/i915_drv.h | 15 +++++++++------
> > 2 files changed, 29 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > index 1681be8d21f6..bfb39047f5e1 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -173,29 +173,25 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
> > while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
> > if (pch->vendor == PCI_VENDOR_ID_INTEL) {
> > unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
> > - unsigned short id_ext = pch->device &
> > - INTEL_PCH_DEVICE_ID_MASK_EXT;
> > +
> > + dev_priv->pch_id = id;
> >
> > if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
> > - dev_priv->pch_id = id;
> > dev_priv->pch_type = PCH_IBX;
> > DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
> > WARN_ON(!IS_GEN5(dev_priv));
> > } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
> > - dev_priv->pch_id = id;
> > dev_priv->pch_type = PCH_CPT;
> > DRM_DEBUG_KMS("Found CougarPoint PCH\n");
> > WARN_ON(!IS_GEN6(dev_priv) &&
> > !IS_IVYBRIDGE(dev_priv));
> > } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
> > /* PantherPoint is CPT compatible */
> > - dev_priv->pch_id = id;
> > dev_priv->pch_type = PCH_CPT;
> > DRM_DEBUG_KMS("Found PantherPoint PCH\n");
> > WARN_ON(!IS_GEN6(dev_priv) &&
> > !IS_IVYBRIDGE(dev_priv));
> > } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
> > - dev_priv->pch_id = id;
> > dev_priv->pch_type = PCH_LPT;
> > DRM_DEBUG_KMS("Found LynxPoint PCH\n");
> > WARN_ON(!IS_HASWELL(dev_priv) &&
> > @@ -203,39 +199,49 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
> > WARN_ON(IS_HSW_ULT(dev_priv) ||
> > IS_BDW_ULT(dev_priv));
> > } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
> > - dev_priv->pch_id = id;
> > dev_priv->pch_type = PCH_LPT;
> > DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
> > WARN_ON(!IS_HASWELL(dev_priv) &&
> > !IS_BROADWELL(dev_priv));
> > WARN_ON(!IS_HSW_ULT(dev_priv) &&
> > !IS_BDW_ULT(dev_priv));
> > + } else if (id == INTEL_PCH_WPT_DEVICE_ID_TYPE) {
> > + /* WildcatPoint is LPT compatible */
> > + dev_priv->pch_type = PCH_LPT;
> > + DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
> > + WARN_ON(!IS_HASWELL(dev_priv) &&
> > + !IS_BROADWELL(dev_priv));
> > + WARN_ON(IS_HSW_ULT(dev_priv) ||
> > + IS_BDW_ULT(dev_priv));
> > + } else if (id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE) {
> > + /* WildcatPoint is LPT compatible */
> > + dev_priv->pch_type = PCH_LPT;
> > + DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
> > + WARN_ON(!IS_HASWELL(dev_priv) &&
> > + !IS_BROADWELL(dev_priv));
> > + WARN_ON(!IS_HSW_ULT(dev_priv) &&
> > + !IS_BDW_ULT(dev_priv));
> > } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
> > - dev_priv->pch_id = id;
> > dev_priv->pch_type = PCH_SPT;
> > DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
> > WARN_ON(!IS_SKYLAKE(dev_priv) &&
> > !IS_KABYLAKE(dev_priv));
> > - } else if (id_ext == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
> > - dev_priv->pch_id = id_ext;
> > + } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
> > dev_priv->pch_type = PCH_SPT;
> > DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
> > WARN_ON(!IS_SKYLAKE(dev_priv) &&
> > !IS_KABYLAKE(dev_priv));
> > } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
> > - dev_priv->pch_id = id;
> > dev_priv->pch_type = PCH_KBP;
> > DRM_DEBUG_KMS("Found KabyPoint PCH\n");
> > WARN_ON(!IS_SKYLAKE(dev_priv) &&
> > !IS_KABYLAKE(dev_priv));
> > } else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
> > - dev_priv->pch_id = id;
> > dev_priv->pch_type = PCH_CNP;
> > DRM_DEBUG_KMS("Found CannonPoint PCH\n");
> > WARN_ON(!IS_CANNONLAKE(dev_priv) &&
> > !IS_COFFEELAKE(dev_priv));
> > - } else if (id_ext == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
> > - dev_priv->pch_id = id_ext;
> > + } else if (id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
> > dev_priv->pch_type = PCH_CNP;
> > DRM_DEBUG_KMS("Found CannonPoint LP PCH\n");
> > WARN_ON(!IS_CANNONLAKE(dev_priv) &&
> > @@ -247,7 +253,6 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
> > PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
> > pch->subsystem_device ==
> > PCI_SUBDEVICE_ID_QEMU)) {
> > - dev_priv->pch_id = id;
> > dev_priv->pch_type =
> > intel_virt_detect_pch(dev_priv);
> > } else
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 1b97eb098ffe..4a884cf9b47d 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -2996,17 +2996,18 @@ intel_info(const struct drm_i915_private *dev_priv)
> >
> > #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
> >
> > -#define INTEL_PCH_DEVICE_ID_MASK 0xff00
> > -#define INTEL_PCH_DEVICE_ID_MASK_EXT 0xff80
> > +#define INTEL_PCH_DEVICE_ID_MASK 0xff80
> > #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
> > #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
> > #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
> > #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
> > #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
> > +#define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
> > +#define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
> > #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
> > #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
> > -#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
> > -#define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
> > +#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
> > +#define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA380
>
> 0xA300
>
>
> > #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
> > #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
> > #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
> > @@ -3020,9 +3021,11 @@ intel_info(const struct drm_i915_private *dev_priv)
> > #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
> > #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
> > #define HAS_PCH_LPT_LP(dev_priv) \
> > - ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
> > + ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
> > + (dev_priv)->pch_id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
> > #define HAS_PCH_LPT_H(dev_priv) \
> > - ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
> > + ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
> > + (dev_priv)->pch_id == INTEL_PCH_WPT_DEVICE_ID_TYPE)
> > #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
> > #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
> > #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 5/5] drm/i915: Always use 9 bits of the LPC bridge device ID for PCH detection
2017-06-20 13:03 ` [PATCH 5/5] drm/i915: Always use 9 bits of the LPC bridge device ID for PCH detection ville.syrjala
2017-06-20 14:34 ` Jani Nikula
2017-06-20 18:36 ` Pandiyan, Dhinakaran
@ 2017-06-21 17:49 ` ville.syrjala
2 siblings, 0 replies; 15+ messages in thread
From: ville.syrjala @ 2017-06-21 17:49 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan, Rodrigo Vivi
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Make the code less confusiong by always using the top 9 bits of the
LPC bridge device ID to detect the PCH type. We need to add a bit of
new code for WPT, and we need to adjust the KBP ID as well. All the
other pre-CNP IDs are fine as is.
The virtualization cases I think are fine. These P2X and P3X IDs
actually just look like the old PIIX4 and PIIX3 IDs to me. Not sure
why they're not called PIIX3/4 though. The qemu one has a comment
saying the full ID is 0x2918 which is fine with 9 bits.
v2: Keep the CNP ID as 0xa300 (DK)
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 35 ++++++++++++++++++++---------------
drivers/gpu/drm/i915/i915_drv.h | 13 ++++++++-----
2 files changed, 28 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1681be8d21f6..bfb39047f5e1 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -173,29 +173,25 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
if (pch->vendor == PCI_VENDOR_ID_INTEL) {
unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
- unsigned short id_ext = pch->device &
- INTEL_PCH_DEVICE_ID_MASK_EXT;
+
+ dev_priv->pch_id = id;
if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
- dev_priv->pch_id = id;
dev_priv->pch_type = PCH_IBX;
DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
WARN_ON(!IS_GEN5(dev_priv));
} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
- dev_priv->pch_id = id;
dev_priv->pch_type = PCH_CPT;
DRM_DEBUG_KMS("Found CougarPoint PCH\n");
WARN_ON(!IS_GEN6(dev_priv) &&
!IS_IVYBRIDGE(dev_priv));
} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
/* PantherPoint is CPT compatible */
- dev_priv->pch_id = id;
dev_priv->pch_type = PCH_CPT;
DRM_DEBUG_KMS("Found PantherPoint PCH\n");
WARN_ON(!IS_GEN6(dev_priv) &&
!IS_IVYBRIDGE(dev_priv));
} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
- dev_priv->pch_id = id;
dev_priv->pch_type = PCH_LPT;
DRM_DEBUG_KMS("Found LynxPoint PCH\n");
WARN_ON(!IS_HASWELL(dev_priv) &&
@@ -203,39 +199,49 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
WARN_ON(IS_HSW_ULT(dev_priv) ||
IS_BDW_ULT(dev_priv));
} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
- dev_priv->pch_id = id;
dev_priv->pch_type = PCH_LPT;
DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
WARN_ON(!IS_HASWELL(dev_priv) &&
!IS_BROADWELL(dev_priv));
WARN_ON(!IS_HSW_ULT(dev_priv) &&
!IS_BDW_ULT(dev_priv));
+ } else if (id == INTEL_PCH_WPT_DEVICE_ID_TYPE) {
+ /* WildcatPoint is LPT compatible */
+ dev_priv->pch_type = PCH_LPT;
+ DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
+ WARN_ON(!IS_HASWELL(dev_priv) &&
+ !IS_BROADWELL(dev_priv));
+ WARN_ON(IS_HSW_ULT(dev_priv) ||
+ IS_BDW_ULT(dev_priv));
+ } else if (id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE) {
+ /* WildcatPoint is LPT compatible */
+ dev_priv->pch_type = PCH_LPT;
+ DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
+ WARN_ON(!IS_HASWELL(dev_priv) &&
+ !IS_BROADWELL(dev_priv));
+ WARN_ON(!IS_HSW_ULT(dev_priv) &&
+ !IS_BDW_ULT(dev_priv));
} else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
- dev_priv->pch_id = id;
dev_priv->pch_type = PCH_SPT;
DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
WARN_ON(!IS_SKYLAKE(dev_priv) &&
!IS_KABYLAKE(dev_priv));
- } else if (id_ext == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
- dev_priv->pch_id = id_ext;
+ } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_SPT;
DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
WARN_ON(!IS_SKYLAKE(dev_priv) &&
!IS_KABYLAKE(dev_priv));
} else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
- dev_priv->pch_id = id;
dev_priv->pch_type = PCH_KBP;
DRM_DEBUG_KMS("Found KabyPoint PCH\n");
WARN_ON(!IS_SKYLAKE(dev_priv) &&
!IS_KABYLAKE(dev_priv));
} else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
- dev_priv->pch_id = id;
dev_priv->pch_type = PCH_CNP;
DRM_DEBUG_KMS("Found CannonPoint PCH\n");
WARN_ON(!IS_CANNONLAKE(dev_priv) &&
!IS_COFFEELAKE(dev_priv));
- } else if (id_ext == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
- dev_priv->pch_id = id_ext;
+ } else if (id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_CNP;
DRM_DEBUG_KMS("Found CannonPoint LP PCH\n");
WARN_ON(!IS_CANNONLAKE(dev_priv) &&
@@ -247,7 +253,6 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
pch->subsystem_device ==
PCI_SUBDEVICE_ID_QEMU)) {
- dev_priv->pch_id = id;
dev_priv->pch_type =
intel_virt_detect_pch(dev_priv);
} else
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1b97eb098ffe..212b29e38470 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2996,16 +2996,17 @@ intel_info(const struct drm_i915_private *dev_priv)
#define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
-#define INTEL_PCH_DEVICE_ID_MASK 0xff00
-#define INTEL_PCH_DEVICE_ID_MASK_EXT 0xff80
+#define INTEL_PCH_DEVICE_ID_MASK 0xff80
#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
+#define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
+#define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
-#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
+#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
#define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
#define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
@@ -3020,9 +3021,11 @@ intel_info(const struct drm_i915_private *dev_priv)
#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
#define HAS_PCH_LPT_LP(dev_priv) \
- ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
+ ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
+ (dev_priv)->pch_id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
#define HAS_PCH_LPT_H(dev_priv) \
- ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
+ ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
+ (dev_priv)->pch_id == INTEL_PCH_WPT_DEVICE_ID_TYPE)
#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
--
2.13.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: PCH detection cleanup (rev2)
2017-06-20 13:03 [PATCH 0/5] drm/i915: PCH detection cleanup ville.syrjala
` (5 preceding siblings ...)
2017-06-20 13:49 ` ✗ Fi.CI.BAT: warning for drm/i915: PCH detection cleanup Patchwork
@ 2017-06-21 18:05 ` Patchwork
2017-06-22 16:55 ` [PATCH 0/5] drm/i915: PCH detection cleanup Ville Syrjälä
7 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2017-06-21 18:05 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: PCH detection cleanup (rev2)
URL : https://patchwork.freedesktop.org/series/26046/
State : success
== Summary ==
Series 26046v2 drm/i915: PCH detection cleanup
https://patchwork.freedesktop.org/api/1.0/series/26046/revisions/2/mbox/
Test prime_busy:
Subgroup basic-wait-after-default:
pass -> DMESG-WARN (fi-skl-6700hq) fdo#101515 +1
fdo#101515 https://bugs.freedesktop.org/show_bug.cgi?id=101515
fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time:437s
fi-bdw-gvtdvm total:278 pass:256 dwarn:8 dfail:0 fail:0 skip:14 time:437s
fi-bsw-n3050 total:278 pass:241 dwarn:1 dfail:0 fail:0 skip:36 time:527s
fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time:513s
fi-byt-j1900 total:278 pass:252 dwarn:2 dfail:0 fail:0 skip:24 time:491s
fi-byt-n2820 total:278 pass:248 dwarn:2 dfail:0 fail:0 skip:28 time:481s
fi-glk-2a total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time:587s
fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:434s
fi-hsw-4770r total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:409s
fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time:416s
fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:493s
fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:475s
fi-kbl-7500u total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:466s
fi-kbl-7560u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:570s
fi-kbl-r total:278 pass:259 dwarn:1 dfail:0 fail:0 skip:18 time:578s
fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:465s
fi-skl-6700hq total:278 pass:220 dwarn:3 dfail:0 fail:30 skip:24 time:341s
fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 time:464s
fi-skl-6770hq total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:477s
fi-skl-gvtdvm total:278 pass:265 dwarn:0 dfail:0 fail:0 skip:13 time:437s
fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:547s
fi-snb-2600 total:278 pass:249 dwarn:0 dfail:0 fail:0 skip:29 time:403s
0a9fd1712c87aac1b6065a58cb46582a6a117cee drm-tip: 2017y-06m-21d-15h-44m-13s UTC integration manifest
d6a02ef drm/i915: Always use 9 bits of the LPC bridge device ID for PCH detection
3079363 drm/i915: Clean up some expressions
e0580ac drm/i915: Document that PPT==CPT and WPT==LPT
a468727 drm/i915: s/Couar/Cougar/
bda1c29 drm/i915: Use HAS_PCH_CPT() everywhere
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_5017/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 0/5] drm/i915: PCH detection cleanup
2017-06-20 13:03 [PATCH 0/5] drm/i915: PCH detection cleanup ville.syrjala
` (6 preceding siblings ...)
2017-06-21 18:05 ` ✓ Fi.CI.BAT: success for drm/i915: PCH detection cleanup (rev2) Patchwork
@ 2017-06-22 16:55 ` Ville Syrjälä
7 siblings, 0 replies; 15+ messages in thread
From: Ville Syrjälä @ 2017-06-22 16:55 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan, Rodrigo Vivi
On Tue, Jun 20, 2017 at 04:03:05PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> During the recent discusison on the PCH detection details it was
> suggested that we should just always use the top 9 bits of the
> ISA/LPC bridge device ID to detect the PCH type. Currently we use
> either 8 or 9 bits depending on the PCH type.
>
> Series available here:
> git://github.com/vsyrjala/linux.git pch_id_9bits
>
> Ville Syrjälä (5):
> drm/i915: Use HAS_PCH_CPT() everywhere
> drm/i915: s/Couar/Cougar/
> drm/i915: Document that PPT==CPT and WPT==LPT
> drm/i915: Clean up some expressions
> drm/i915: Always use 9 bits of the LPC bridge device ID for PCH
> detection
Series pushed to dinq. Thanks for the review.
>
> drivers/gpu/drm/i915/i915_drv.c | 51 ++++++++++++++++++--------------
> drivers/gpu/drm/i915/i915_drv.h | 19 +++++++-----
> drivers/gpu/drm/i915/intel_device_info.c | 2 +-
> drivers/gpu/drm/i915/intel_sdvo.c | 2 +-
> 4 files changed, 41 insertions(+), 33 deletions(-)
>
> --
> 2.13.0
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2017-06-22 16:55 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-06-20 13:03 [PATCH 0/5] drm/i915: PCH detection cleanup ville.syrjala
2017-06-20 13:03 ` [PATCH 1/5] drm/i915: Use HAS_PCH_CPT() everywhere ville.syrjala
2017-06-20 13:03 ` [PATCH 2/5] drm/i915: s/Couar/Cougar/ ville.syrjala
2017-06-20 13:03 ` [PATCH 3/5] drm/i915: Document that PPT==CPT and WPT==LPT ville.syrjala
2017-06-20 13:03 ` [PATCH 4/5] drm/i915: Clean up some expressions ville.syrjala
2017-06-20 13:46 ` Jani Nikula
2017-06-20 13:03 ` [PATCH 5/5] drm/i915: Always use 9 bits of the LPC bridge device ID for PCH detection ville.syrjala
2017-06-20 14:34 ` Jani Nikula
2017-06-20 14:52 ` Ville Syrjälä
2017-06-20 18:36 ` Pandiyan, Dhinakaran
2017-06-20 18:50 ` Ville Syrjälä
2017-06-21 17:49 ` [PATCH v2 " ville.syrjala
2017-06-20 13:49 ` ✗ Fi.CI.BAT: warning for drm/i915: PCH detection cleanup Patchwork
2017-06-21 18:05 ` ✓ Fi.CI.BAT: success for drm/i915: PCH detection cleanup (rev2) Patchwork
2017-06-22 16:55 ` [PATCH 0/5] drm/i915: PCH detection cleanup Ville Syrjälä
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