From: Jan Glauber <jglauber@cavium.com> To: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com>, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Borislav Petkov <bp@alien8.de>, Jan Glauber <jglauber@cavium.com> Subject: [PATCH v6 3/3] perf: cavium: Add Documentation Date: Fri, 23 Jun 2017 15:01:28 +0200 [thread overview] Message-ID: <20170623130128.11006-4-jglauber@cavium.com> (raw) In-Reply-To: <20170623130128.11006-1-jglauber@cavium.com> Document Cavium SoC PMUs. Signed-off-by: Jan Glauber <jglauber@cavium.com> --- Documentation/perf/cavium-pmu.txt | 74 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/perf/cavium-pmu.txt diff --git a/Documentation/perf/cavium-pmu.txt b/Documentation/perf/cavium-pmu.txt new file mode 100644 index 0000000..37669b9 --- /dev/null +++ b/Documentation/perf/cavium-pmu.txt @@ -0,0 +1,74 @@ +Cavium ThunderX and OcteonTx Performance Monitoring Unit (PMU) +============================================================== + +Cavium SoCs contain various system devices such as L2 caches, processor +interconnect and memory controllers. Unfortunately the PMU counters +are not following a common design so each device has a slightly different +approach how to control and use the PMU counters. + +Common properties of all devices carrying PMU counters: +- The devices are PCI devices and the counters are embedded somewhere + in the PCI register space. +- All counters are 64 bit wide. +- There are no overflow interrupts (unnecessary because of the 64 bit wide counters). + +Properties depending on the device type: +- How to start/stop the counters +- Programmable vs. fixed purpose counters +- Stoppable vs. always running counters +- Independent vs. grouped counters +- Read-only vs. writable counters +- PCI device to PMU group relationship + + +Devices with PMU counters +------------------------- + +Memory controller (LMC): +- one PCI device per LMC +- fixed-purpose counters +- always running counters without start/stop/reset control +- read-only counters + +CCPI interface controller (OCX) Transmit link (TLK) counters: +- writable counters +- only one PCI device exposes multiple TLK units (3 units on T88) +- start/stop control per unit +- only present on multi-socket systems + +PMU (perf) driver +----------------- + +The cavium-pmu driver registers several perf PMU drivers. Each of the perf +driver provides description of its available events and configuration options +in sysfs, see /sys/devices/<lmcX/ocx_tlkX>/. + +The "format" directory describes format of the config (event ID), +The "events" directory shows the names of the events and provides configuration +templates for all supported event types that can be used with perf tool. For +example, "lmc0/dclk_cnt/" is an equivalent of "lmc0/config=2/". + +Each perf driver also provides a "cpumask" sysfs attribute, which contains a +single CPU ID of the processor which will be used to handle all the PMU events. + +Example for perf tool use: + + / # perf list | grep -e lmc + lmc0/bank_conflict1/ [Kernel PMU event] + lmc0/bank_conflict2/ [Kernel PMU event] + lmc0/dclk_cnt/ [Kernel PMU event] + lmc0/ifb_cnt/ [Kernel PMU event] + lmc0/ops_cnt/ [Kernel PMU event] + + / # perf stat -a -e lmc0/ops_cnt/,lmc0/dclk_cnt/ -- sleep 1 + + Performance counter stats for 'system wide': + + 176,133 lmc0/ops_cnt/ + 670,243,653 lmc0/dclk_cnt/ + + 1.005479295 seconds time elapsed + +The driver does not support sampling, therefore "perf record" will +not work. System wide mode ("-a") must be used as per-task (without "-a") +perf sessions are not supported. -- 2.9.0.rc0.21.g7777322
WARNING: multiple messages have this Message-ID (diff)
From: jglauber@cavium.com (Jan Glauber) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v6 3/3] perf: cavium: Add Documentation Date: Fri, 23 Jun 2017 15:01:28 +0200 [thread overview] Message-ID: <20170623130128.11006-4-jglauber@cavium.com> (raw) In-Reply-To: <20170623130128.11006-1-jglauber@cavium.com> Document Cavium SoC PMUs. Signed-off-by: Jan Glauber <jglauber@cavium.com> --- Documentation/perf/cavium-pmu.txt | 74 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/perf/cavium-pmu.txt diff --git a/Documentation/perf/cavium-pmu.txt b/Documentation/perf/cavium-pmu.txt new file mode 100644 index 0000000..37669b9 --- /dev/null +++ b/Documentation/perf/cavium-pmu.txt @@ -0,0 +1,74 @@ +Cavium ThunderX and OcteonTx Performance Monitoring Unit (PMU) +============================================================== + +Cavium SoCs contain various system devices such as L2 caches, processor +interconnect and memory controllers. Unfortunately the PMU counters +are not following a common design so each device has a slightly different +approach how to control and use the PMU counters. + +Common properties of all devices carrying PMU counters: +- The devices are PCI devices and the counters are embedded somewhere + in the PCI register space. +- All counters are 64 bit wide. +- There are no overflow interrupts (unnecessary because of the 64 bit wide counters). + +Properties depending on the device type: +- How to start/stop the counters +- Programmable vs. fixed purpose counters +- Stoppable vs. always running counters +- Independent vs. grouped counters +- Read-only vs. writable counters +- PCI device to PMU group relationship + + +Devices with PMU counters +------------------------- + +Memory controller (LMC): +- one PCI device per LMC +- fixed-purpose counters +- always running counters without start/stop/reset control +- read-only counters + +CCPI interface controller (OCX) Transmit link (TLK) counters: +- writable counters +- only one PCI device exposes multiple TLK units (3 units on T88) +- start/stop control per unit +- only present on multi-socket systems + +PMU (perf) driver +----------------- + +The cavium-pmu driver registers several perf PMU drivers. Each of the perf +driver provides description of its available events and configuration options +in sysfs, see /sys/devices/<lmcX/ocx_tlkX>/. + +The "format" directory describes format of the config (event ID), +The "events" directory shows the names of the events and provides configuration +templates for all supported event types that can be used with perf tool. For +example, "lmc0/dclk_cnt/" is an equivalent of "lmc0/config=2/". + +Each perf driver also provides a "cpumask" sysfs attribute, which contains a +single CPU ID of the processor which will be used to handle all the PMU events. + +Example for perf tool use: + + / # perf list | grep -e lmc + lmc0/bank_conflict1/ [Kernel PMU event] + lmc0/bank_conflict2/ [Kernel PMU event] + lmc0/dclk_cnt/ [Kernel PMU event] + lmc0/ifb_cnt/ [Kernel PMU event] + lmc0/ops_cnt/ [Kernel PMU event] + + / # perf stat -a -e lmc0/ops_cnt/,lmc0/dclk_cnt/ -- sleep 1 + + Performance counter stats for 'system wide': + + 176,133 lmc0/ops_cnt/ + 670,243,653 lmc0/dclk_cnt/ + + 1.005479295 seconds time elapsed + +The driver does not support sampling, therefore "perf record" will +not work. System wide mode ("-a") must be used as per-task (without "-a") +perf sessions are not supported. -- 2.9.0.rc0.21.g7777322
next prev parent reply other threads:[~2017-06-23 13:02 UTC|newest] Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-06-23 13:01 [PATCH v6 0/3] Cavium ARM64 uncore PMU support Jan Glauber 2017-06-23 13:01 ` Jan Glauber 2017-06-23 13:01 ` [PATCH v6 1/3] perf: cavium: Support memory controller PMU counters Jan Glauber 2017-06-23 13:01 ` Jan Glauber 2017-06-23 13:01 ` [PATCH v6 2/3] perf: cavium: Support transmit-link " Jan Glauber 2017-06-23 13:01 ` Jan Glauber 2017-06-23 13:01 ` Jan Glauber [this message] 2017-06-23 13:01 ` [PATCH v6 3/3] perf: cavium: Add Documentation Jan Glauber 2017-06-23 13:56 ` [PATCH v6 0/3] Cavium ARM64 uncore PMU support Borislav Petkov 2017-06-23 13:56 ` Borislav Petkov
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20170623130128.11006-4-jglauber@cavium.com \ --to=jglauber@cavium.com \ --cc=bp@alien8.de \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=mark.rutland@arm.com \ --cc=will.deacon@arm.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.