* [U-Boot] [PATCH 4/4] powerpc, 8xx: Add support for MCR3000 board from CSSI
2017-06-23 12:57 [U-Boot] [PATCH 0/4] powerpc, 8xx: Add support for MCR3000 board from CSSI Christophe Leroy
` (2 preceding siblings ...)
2017-06-23 12:57 ` [U-Boot] [PATCH 3/4] powerpc, 8xx: Properly set CPM frequency in the device tree Christophe Leroy
@ 2017-06-23 12:57 ` Christophe Leroy
2017-06-23 13:52 ` Wolfgang Denk
2017-07-03 21:46 ` [U-Boot] [U-Boot, " Tom Rini
3 siblings, 2 replies; 15+ messages in thread
From: Christophe Leroy @ 2017-06-23 12:57 UTC (permalink / raw)
To: u-boot
CS Systemes d'Information (CSSI) manufactures two boards, named MCR3000
and CMPC885 which are respectively based on MPC866 and MPC885 processors.
This patch adds support for the first board.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/cpu/mpc8xx/Kconfig | 5 +
arch/powerpc/cpu/mpc8xx/cpu_init.c | 2 +
arch/powerpc/cpu/mpc8xx/fec.c | 20 ++
board/cssi/MAINTAINERS | 6 +
board/cssi/MCR3000/Kconfig | 15 ++
board/cssi/MCR3000/MCR3000.c | 436 +++++++++++++++++++++++++++++++++++++
board/cssi/MCR3000/Makefile | 9 +
board/cssi/MCR3000/nand.c | 77 +++++++
board/cssi/MCR3000/u-boot.lds | 91 ++++++++
configs/MCR3000_defconfig | 37 ++++
include/configs/MCR3000.h | 293 +++++++++++++++++++++++++
11 files changed, 991 insertions(+)
create mode 100644 board/cssi/MAINTAINERS
create mode 100644 board/cssi/MCR3000/Kconfig
create mode 100644 board/cssi/MCR3000/MCR3000.c
create mode 100644 board/cssi/MCR3000/Makefile
create mode 100644 board/cssi/MCR3000/nand.c
create mode 100644 board/cssi/MCR3000/u-boot.lds
create mode 100644 configs/MCR3000_defconfig
create mode 100644 include/configs/MCR3000.h
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index a425cba8aa..817c240a8a 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -8,6 +8,11 @@ choice
prompt "Target select"
optional
+config TARGET_MCR3000
+ bool "Support MCR3000 board from CSSI"
+
endchoice
+source "board/cssi/MCR3000/Kconfig"
+
endmenu
diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c
index 5da12faf21..2f7437f6f5 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c
@@ -37,7 +37,9 @@ void cpu_init_f (volatile immap_t * immr)
/* SYPCR - contains watchdog control (11-9) */
+#ifndef CONFIG_TARGET_MCR3000
immr->im_siu_conf.sc_sypcr = CONFIG_SYS_SYPCR;
+#endif
#if defined(CONFIG_WATCHDOG)
reset_8xx_watchdog (immr);
diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c
index 680d286964..bdad8791be 100644
--- a/arch/powerpc/cpu/mpc8xx/fec.c
+++ b/arch/powerpc/cpu/mpc8xx/fec.c
@@ -443,6 +443,26 @@ static void fec_pin_init(int fecidx)
immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
else
immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
+
+#if defined (CONFIG_TARGET_MCR3000)
+ immr->im_ioport.iop_papar = 0xBBFF;
+ immr->im_ioport.iop_padir = 0x04F0;
+ immr->im_ioport.iop_paodr = 0x0000;
+
+ immr->im_cpm.cp_pbpar = 0x000133FF;
+ immr->im_cpm.cp_pbdir = 0x0003BF0F;
+ immr->im_cpm.cp_pbodr = 0x00000000;
+
+ immr->im_ioport.iop_pcpar = 0x0400;
+ immr->im_ioport.iop_pcdir = 0x0080;
+ immr->im_ioport.iop_pcso = 0x0D53;
+ immr->im_ioport.iop_pcint = 0x0000;
+
+ immr->im_ioport.iop_pdpar = 0x03FE;
+ immr->im_ioport.iop_pddir = 0x1C09;
+
+ immr->im_ioport.utmode |= 0x80;
+#endif
#endif
#endif /* CONFIG_ETHER_ON_FEC1 */
diff --git a/board/cssi/MAINTAINERS b/board/cssi/MAINTAINERS
new file mode 100644
index 0000000000..cbf1406a54
--- /dev/null
+++ b/board/cssi/MAINTAINERS
@@ -0,0 +1,6 @@
+BOARDS from CS Systemes d'Information
+M: Christophe Leroy <christophe.leroy@c-s.fr>
+S: Maintained
+F: board/cssi/
+F: include/configs/MCR3000.h
+F: configs/MCR3000_defconfig
diff --git a/board/cssi/MCR3000/Kconfig b/board/cssi/MCR3000/Kconfig
new file mode 100644
index 0000000000..ecfd90fd4c
--- /dev/null
+++ b/board/cssi/MCR3000/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MCR3000
+
+config SYS_BOARD
+ default "MCR3000"
+
+config SYS_VENDOR
+ default "cssi"
+
+config SYS_CONFIG_NAME
+ default "MCR3000"
+
+config SYS_TEXT_BASE
+ default 0x04000000
+
+endif
diff --git a/board/cssi/MCR3000/MCR3000.c b/board/cssi/MCR3000/MCR3000.c
new file mode 100644
index 0000000000..b99c5f6fc3
--- /dev/null
+++ b/board/cssi/MCR3000/MCR3000.c
@@ -0,0 +1,436 @@
+/*
+ * Copyright (C) 2010-2017 CS Systemes d'Information
+ * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
+ * Christophe Leroy <christophe.leroy@c-s.fr>
+ *
+ * Board specific routines for the MCR3000 board
+ *
+ * - initialisation
+ * - memory controller
+ * - serial io initialisation
+ * - ethernet io initialisation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <mpc8xx.h>
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+
+/* -------------------------------------------------------------------------
+ * constant
+ */
+static const uint cs1_dram_table_66[] = {
+ /* DRAM - single read. (offset 0 in upm RAM)
+ */
+ 0x0F3DFC04, 0x0FEFBC04, 0x00BE7804, 0x0FFDF400,
+ 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+ /* DRAM - burst read. (offset 8 in upm RAM)
+ */
+ 0x0F3DFC04, 0x0FEFBC04, 0x00BF7C04, 0x00FFFC00,
+ 0x00FFFC00, 0x00FEF800, 0x0FFDF400, 0x1FFFFC05,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+ /* DRAM - single write. (offset 18 in upm RAM)
+ */
+ 0x0F3DFC04, 0x0FEFB800, 0x00BF7404, 0x0FFEF804,
+ 0x0FFDF404, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
+
+ /* DRAM - burst write. (offset 20 in upm RAM)
+ */
+ 0x0F3DFC04, 0x0FEFB800, 0x00BF7400, 0x00FFFC00,
+ 0x00FFFC00, 0x00FFFC04, 0x0FFEF804, 0x0FFDF404,
+ 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+ /* refresh (offset 30 in upm RAM)
+ */
+ 0x0FFDF404, 0x0FFEBC04, 0x0FFD7C84, 0x0FFFFC04,
+ 0x0FFFFC04, 0x0FFFFC04, 0x1FFFFC85, 0xFFFFFFFF,
+
+ /* init
+ */
+ 0x0FEEB874, 0x0FBD7474, 0x1FFFFC45, 0xFFFFFFFF,
+
+ /* exception. (offset 3c in upm RAM)
+ */
+ 0xFFFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+};
+
+/* -------------------------------------------------------------------------
+ * Device Tree Support
+ */
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+int fdt_set_node_and_value (void *blob, char *nodename, char *regname, void *var, int size)
+{
+ int ret = 0;
+ int nodeoffset = 0;
+
+ nodeoffset = fdt_path_offset (blob, nodename);
+ if (nodeoffset >= 0) {
+ ret = fdt_setprop (blob, nodeoffset, regname, var,
+ size);
+ if (ret < 0) {
+ printf("ft_blob_update(): cannot set %s/%s property; err: %s\n", nodename, regname, fdt_strerror (ret));
+ }
+ } else {
+ printf("ft_blob_update(): cannot find %s node err:%s\n", nodename, fdt_strerror (nodeoffset));
+ }
+ return ret;
+}
+
+int fdt_del_node_name (void *blob, char *nodename)
+{
+ int ret = 0;
+ int nodeoffset = 0;
+
+ nodeoffset = fdt_path_offset (blob, nodename);
+ if (nodeoffset >= 0) {
+ ret = fdt_del_node (blob, nodeoffset);
+ if (ret < 0) {
+ printf("%s: cannot delete %s; err: %s\n", __func__, nodename, fdt_strerror (ret));
+ }
+ } else {
+ printf("%s: cannot find %s node err:%s\n", __func__, nodename, fdt_strerror (nodeoffset));
+ }
+ return ret;
+}
+
+int fdt_del_prop_name (void *blob, char *nodename, char *propname)
+{
+ int ret = 0;
+ int nodeoffset = 0;
+
+ nodeoffset = fdt_path_offset (blob, nodename);
+ if (nodeoffset >= 0) {
+ ret = fdt_delprop (blob, nodeoffset, propname);
+ if (ret < 0) {
+ printf("%s: cannot delete %s %s; err: %s\n", __func__, nodename, propname, fdt_strerror (ret));
+ }
+ } else {
+ printf("%s: cannot find %s node err:%s\n", __func__, nodename, fdt_strerror (nodeoffset));
+ }
+ return ret;
+}
+
+/*
+ * update "brg" property in the blob
+ */
+void ft_blob_update (void *blob, bd_t *bd)
+{
+ uchar enetaddr[6];
+ ulong brg_data = 0;
+
+ /* BRG */
+ brg_data = cpu_to_be32(bd->bi_busfreq);
+ fdt_set_node_and_value(blob, "/soc/cpm", "brg-frequency", &brg_data, sizeof(brg_data));
+
+ /* MAC addr */
+ if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
+ fdt_set_node_and_value(blob, "ethernet0", "local-mac-address", enetaddr, sizeof(u8) * 6);
+ }
+
+ /* Bus Frequency for CPM */
+ fdt_set_node_and_value(blob, "/soc", "bus-frequency", &bd->bi_busfreq, sizeof(u32));
+}
+
+void ft_e1_setup (void *blob)
+{
+ ulong data_rate = 2;
+ ulong channel_phase = 0;
+ char *sync = "receive";
+
+ /* Set data rate */
+ fdt_set_node_and_value(blob, "/localbus/e1-wan", "data-rate", &data_rate,
+ sizeof(u32));
+
+ /* Set channel phase to 0 */
+ fdt_set_node_and_value(blob, "/localbus/e1-wan", "channel-phase",
+ &channel_phase, sizeof(u32));
+
+ /* rising edge sync pulse transmit */
+ fdt_set_node_and_value(blob, "/localbus/e1-wan", "rising-edge-sync-pulse",
+ sync, sizeof(u8) * strlen(sync));
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+ ft_blob_update(blob, bd);
+ ft_e1_setup(blob);
+}
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
+
+
+
+/* -------------------------------------------------------------------------
+ * return CPU frequency
+ */
+/*static unsigned int board_get_cpufreq (void)
+{
+ return (CONFIG_SYS_CLK_FREQ);
+}*/
+
+
+/* -------------------------------------------------------------------------
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+ serial_putc ('B');
+ serial_putc ('O');
+ serial_putc ('A');
+ serial_putc ('R');
+ serial_putc ('D');
+ serial_putc (':');
+ serial_putc (' ');
+ serial_putc ('M');
+ serial_putc ('C');
+ serial_putc ('R');
+ serial_putc ('3');
+ serial_putc ('0');
+ serial_putc ('0');
+ serial_putc ('0');
+ serial_putc (' ');
+ serial_putc ('C');
+ serial_putc ('S');
+ serial_putc ('S');
+ serial_putc ('I');
+ serial_putc ('\n');
+
+ return 0;
+}
+
+
+/* -------------------------------------------------------------------------
+ * Initialize SDRAM
+ */
+int dram_init(void)
+{
+ volatile immap_t *immap = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ long int ram_sz = 0;
+
+ /*
+ * Only initialize memory controller when running from FLASH.
+ * When running from RAM, don't touch it.
+ */
+ if ( ((ulong) dram_init & CONFIG_SYS_FLASH_BASE) == CONFIG_SYS_FLASH_BASE) {
+ printf("UPMA init for SDRAM (CAS latency 2), ");
+ printf("init address 0x%08x, size ",(int)dram_init);
+ /* Configure UPMA for cs1 */
+ upmconfig (UPMA, (uint *) cs1_dram_table_66, sizeof (cs1_dram_table_66) / sizeof (uint));
+ udelay(10);
+ memctl->memc_mptpr = 0x0200;
+ memctl->memc_mamr = 0x14904000;
+ udelay(10);
+ memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+ memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
+ udelay(10);
+ memctl->memc_mcr = 0x80002830;
+ memctl->memc_mar = 0x00000088;
+ memctl->memc_mcr = 0x80002038;
+ udelay(200);
+ /* now map other option and base registers */
+ memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
+ memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
+ memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+ memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
+ memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
+ memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
+ memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM;
+ memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM;
+ memctl->memc_or6 = CONFIG_SYS_OR6_PRELIM;
+ memctl->memc_br6 = CONFIG_SYS_BR6_PRELIM;
+ memctl->memc_or7 = CONFIG_SYS_OR7_PRELIM;
+ memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM;
+
+ ram_sz = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_MAX_SIZE);
+ }
+
+ gd->ram_size = ram_sz;
+
+ return 0;
+}
+
+/* -------------------------------------------------------------------------
+ * Specific board pre-initialization
+ */
+int board_early_init_r (void)
+{
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ char *s;
+
+#if defined(CONFIG_WATCHDOG)
+ s = getenv("watchdog");
+ /* watchdog disabled */
+ if (strcmp(s, "off") == 0) {
+ printf(" Watchdog disabled\n");
+ immr->im_siu_conf.sc_sypcr = CONFIG_SYS_SYPCR & ~(SYPCR_SWE | SYPCR_SWRI);
+
+ /* watchdog is enabled */
+ } else {
+
+ /* NMI mode */
+ if (strcmp(s, "nmi") == 0) {
+ printf(" Watchdog enabled nmi\n");
+ immr->im_siu_conf.sc_sypcr = (CONFIG_SYS_SYPCR & ~(SYPCR_SWRI)) | SYPCR_SWE;
+
+ /* normal mode by default */
+ } else {
+ printf(" Watchdog enabled\n");
+ immr->im_siu_conf.sc_sypcr = CONFIG_SYS_SYPCR | SYPCR_SWE | SYPCR_SWRI;
+ }
+ }
+#else
+ immr->im_siu_conf.sc_sypcr = CONFIG_SYS_SYPCR & ~(SYPCR_SWE | SYPCR_SWRI);
+#endif
+ return 0;
+}
+
+/* -------------------------------------------------------------------------
+ * Miscelaneous init
+ */
+
+#define ADDR_CPLD_R_ETAT ((unsigned short *)0x10000806)
+#define R_ID_CPLD_MASK 0xFF00
+
+#define ADDR_FLASH_ENV_AREA ((unsigned short *)0x04040000)
+
+struct environment {
+ uint32_t crc;
+ uint8_t data[];
+};
+
+
+#define LEN_STR 80
+
+int misc_init_r (void)
+{
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile iop8xx_t *iop = (iop8xx_t *) &immr->im_ioport;
+ char str[LEN_STR];
+ char s_ethaddr[LEN_STR];
+ char s_id_cpld[LEN_STR];
+ char s_num_serie[LEN_STR];
+ char s_password[LEN_STR];
+ unsigned short version_cpld;
+ struct environment *env;
+ uint32_t crc;
+ char *s;
+ int i, j;
+
+ /* --------------------------------------------
+ * GPIO or per. Function
+ * PCPAR[13] = 0 [0x0004] -> GPIO: (BTN_ACQ_AL)
+ * -------------------------------------------- */
+ iop->iop_pcpar |= 0x0000; /* set bits */
+ iop->iop_pcpar &= ~0x0004; /* reset bit */
+
+ /* ----------------------------------------------
+ * In/Out or per. Function 0/1
+ * PCDIR[13] = 1 [0x0004] -> GPIO: IN (CS_POT1_5V)
+ * ---------------------------------------------- */
+ iop->iop_pcdir |= 0x0000;
+ iop->iop_pcdir &= ~0x0004;
+
+ /* if BTN_ACQ_IN is pressed then bootdelay is changed to 60 second */
+ if ((iop->iop_pcdat & 0x0004) == 0) {
+ setenv("bootdelay", "60");
+ }
+
+ /* verifying environment variable area */
+ env = (struct environment *)CONFIG_ENV_ADDR;
+ crc = crc32(0, env->data, (CONFIG_ENV_SIZE - sizeof(uint32_t)));
+ if (crc != env->crc) {
+ /* It can be an update request */
+ for (i=0 ; i<8 ; i++) {str[i] = *(((uint8_t *)CONFIG_ENV_ADDR) + i); str[(i+1)] = 0;}
+ if (strcmp(str, "ETHADDR=") == 0) {
+ /* getting saved value */
+ i = 0;
+ for (j=0 ; j<4 ; j++) {
+ while (*(((uint8_t *)CONFIG_ENV_ADDR) + i) != '=') {
+ i++;
+ }
+ switch (j) {
+ case 0: s = s_ethaddr; break;
+ case 1: s = s_num_serie; break;
+ case 2: s = s_id_cpld; break;
+ case 3: s = s_password; break;
+ }
+ do {
+ i++;
+ *s = *(((uint8_t *)CONFIG_ENV_ADDR) + i);
+ s++;
+ } while (*(((uint8_t *)CONFIG_ENV_ADDR) + i) != 0x00);
+ }
+
+ /* creating or updating environment variable */
+ if (s_ethaddr[0] != 0x00) {
+ setenv("ethaddr", s_ethaddr);
+ }
+ if (s_num_serie[0] != 0x00) {
+ setenv("num_serie", s_num_serie);
+ }
+ if (s_id_cpld[0] != 0x00) {
+ setenv("id_cpld", s_id_cpld);
+ }
+ if (s_password[0] != 0x00) {
+ setenv("password", s_password);
+ }
+ saveenv();
+ }
+ }
+
+ /* we do not modify environment variable area if CRC is false */
+ crc = crc32(0, env->data, (CONFIG_ENV_SIZE - sizeof(uint32_t)));
+ if (crc == env->crc) {
+ /* getting version value in CPLD register */
+ for (i=0 ; i<LEN_STR ; i++) str[i] = 0;
+ version_cpld = *ADDR_CPLD_R_ETAT & R_ID_CPLD_MASK;
+ if (((version_cpld >> 12) & 0x000f) < 0x000a) {
+ str[0] = ((version_cpld >> 12) & 0x000f) + 0x30;
+ } else {
+ str[0] = (((version_cpld >> 12) & 0x000f) - 0x000a) + 0x41;
+ }
+ if (((version_cpld >> 8) & 0x000f) < 0x000a) {
+ str[1] = ((version_cpld >> 8) & 0x000f) + 0x30;
+ } else {
+ str[1] = (((version_cpld >> 8) & 0x000f) - 0x000a) + 0x41;
+ }
+ str[2] = 0x30;
+ str[3] = 0x30;
+
+ /* updating "id_cpld" variable if not corresponding with the value in register */
+ s = getenv("id_cpld");
+ if ((s == NULL) || (strcmp(s, str) != 0)) {
+ setenv("id_cpld", str);
+ saveenv();
+ }
+ }
+
+ return 0;
+}
+
+int board_early_init_f (void)
+{
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+
+ /*
+ * Erase FPGA(s) for reboot
+ */
+ immr->im_cpm.cp_pbdat &= ~0x00020000; /* PROGFPGA down */
+ immr->im_cpm.cp_pbdir |= 0x00020000; /* PROGFPGA output */
+ udelay(1); /* Wait more than 300ns */
+ immr->im_cpm.cp_pbdat |= 0x00020000; /* PROGFPGA up */
+ return 0;
+}
+
diff --git a/board/cssi/MCR3000/Makefile b/board/cssi/MCR3000/Makefile
new file mode 100644
index 0000000000..4ae57b8bdc
--- /dev/null
+++ b/board/cssi/MCR3000/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2010-2017 CS Systemes d'Information
+# Christophe Leroy <christophe.leroy@c-s.fr>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+#
+
+obj-y = MCR3000.o nand.o
diff --git a/board/cssi/MCR3000/nand.c b/board/cssi/MCR3000/nand.c
new file mode 100644
index 0000000000..5c43205907
--- /dev/null
+++ b/board/cssi/MCR3000/nand.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2010-2017 CS Systemes d'Information
+ * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
+ * Christophe Leroy <christophe.leroy@c-s.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+
+#if defined(CONFIG_CMD_NAND)
+#include <nand.h>
+
+#define BIT_CLE ((unsigned short)0x0800)
+#define BIT_ALE ((unsigned short)0x0400)
+#define BIT_NCE ((unsigned short)0x1000)
+
+static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
+{
+ struct nand_chip *this = mtdinfo->priv;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ unsigned short pddat = 0;
+
+
+ /* The hardware control change */
+ if (ctrl & NAND_CTRL_CHANGE) {
+
+ /* saving current value */
+ pddat = immr->im_ioport.iop_pddat;
+
+ /* Clearing ALE and CLE */
+ pddat &= ~(BIT_CLE | BIT_ALE);
+
+ /* Driving NCE pin */
+ if (ctrl & NAND_NCE) {
+ pddat &= ~BIT_NCE;
+ } else {
+ pddat |= BIT_NCE;
+ }
+
+ /* Driving CLE and ALE pin */
+ if (ctrl & NAND_CLE) {
+ pddat |= BIT_CLE;
+ }
+ if (ctrl & NAND_ALE) {
+ pddat |= BIT_ALE;
+ }
+
+ /* applying new value */
+ immr->im_ioport.iop_pddat = pddat;
+ }
+
+ /* Writing the command */
+ if (cmd != NAND_CMD_NONE) {
+ *((unsigned char *)this->IO_ADDR_W) = (unsigned char)cmd;
+ }
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+
+ /* Set GPIO Port */
+ immr->im_ioport.iop_pddir |= 0x1c00;
+ immr->im_ioport.iop_pdpar &= ~0x1c00;
+ immr->im_ioport.iop_pddat |= 0x1000; /* au repos CE doit etre à 1 */
+ immr->im_ioport.iop_pddat &= ~0x0c00; /* au repos ALE et CLE sont à 0 */
+
+ nand->chip_delay = 60;
+ nand->ecc.mode = NAND_ECC_SOFT;
+ nand->cmd_ctrl = nand_hwcontrol;
+
+ return 0;
+}
+
+#endif /* defined(CONFIG_CMD_NAND) */
diff --git a/board/cssi/MCR3000/u-boot.lds b/board/cssi/MCR3000/u-boot.lds
new file mode 100644
index 0000000000..2234bd8d1d
--- /dev/null
+++ b/board/cssi/MCR3000/u-boot.lds
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2010-2017 CS Systemes d'Information
+ * Christophe Leroy <christophe.leroy@c-s.fr>
+ *
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Modified by Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .text :
+ {
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
+ arch/powerpc/cpu/mpc8xx/built-in.o (.text*)
+ arch/powerpc/lib/built-in.o (.text*)
+ board/cssi/MCR3000/built-in.o (.text*)
+ disk/built-in.o (.text*)
+ drivers/net/built-in.o (.text*)
+
+ *(.text)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ KEEP(*(.got))
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.bss*)
+ *(.sbss*)
+ *(COMMON)
+ . = ALIGN(4);
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
+ENTRY(_start)
diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig
new file mode 100644
index 0000000000..61fea2ee09
--- /dev/null
+++ b/configs/MCR3000_defconfig
@@ -0,0 +1,37 @@
+CONFIG_PPC=y
+CONFIG_8xx=y
+CONFIG_TARGET_MCR3000=y
+CONFIG_BOOTDELAY=5
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_NET=y
+CONFIG_CMD_DHCP=y
+# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set
+# CONFIG_MMC is not set
+CONFIG_MTD_NOR_FLASH=y
+# CONFIG_PCI is not set
+CONFIG_OF_LIBFDT=y
+CONFIG_SYS_PROMPT="S3K> "
+
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_REGINFO=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_NAND=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_MD5SUM is not set
+# CONFIG_CMD_MISC is not set
+# CONFIG_CMD_SETGETDCR is not set
+# CONFIG_CMD_SHA1 is not set
+# CONFIG_CMD_SOURCE is not set
diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h
new file mode 100644
index 0000000000..8268ba438e
--- /dev/null
+++ b/include/configs/MCR3000.h
@@ -0,0 +1,293 @@
+/*
+ * Copyright (C) 2010-2017 CS Systemes d'Information
+ * Christophe Leroy <christophe.leroy@c-s.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC866 1
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+
+#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
+#undef CONFIG_8xx_CONS_SMC2
+#undef CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_EXTRA_ENV_SETTINGS "sdram_type=SDRAM\0" \
+ "flash_type=AM29LV160DB\0" \
+ "loadaddr=0x400000\0" \
+ "filename=uImage.lzma\0" \
+ "nfsroot=/opt/ofs\0" \
+ "dhcp_ip=ip=:::::eth0:dhcp\0" \
+ "console_args=console=ttyCPM0,115200N8\0" \
+ "flashboot=setenv bootargs " \
+ "${console_args} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:mcr3k:eth0:off " \
+ "${ofl_args}; " \
+ "bootm 0x04060000 - 0x04050000\0" \
+ "tftpboot=setenv bootargs " \
+ "${console_args} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:mcr3k:eth0:off " \
+ "${ofl_args}; " \
+ "tftp ${loadaddr} ${filename};" \
+ "tftp 0xf00000 mcr3000.dtb;" \
+ "bootm ${loadaddr} - 0xf00000\0" \
+ "netboot=dhcp ${loadaddr} ${filename};" \
+ "tftp 0xf00000 mcr3000.dtb;" \
+ "setenv bootargs " \
+ "root=/dev/nfs rw " \
+ "${console_args} " \
+ "${dhcp_ip};" \
+ "bootm ${loadaddr} - 0xf00000\0" \
+ "nfsboot=setenv bootargs " \
+ "root=/dev/nfs rw nfsroot=${serverip}:${nfsroot} " \
+ "${console_args} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:mcr3k:eth0:off;" \
+ "bootm 0x04060000 - 0x04050000\0" \
+ "dhcpboot=dhcp ${loadaddr} ${filename};" \
+ "tftp 0xf00000 mcr3000.dtb;" \
+ "setenv bootargs " \
+ "${console_args} " \
+ "${dhcp_ip} " \
+ "${ofl_args}; " \
+ "bootm ${loadaddr} - 0xf00000\0"
+
+#define CONFIG_BOOTDELAY 5 /* autoboot. Put -1 to disabled */
+
+#define CONFIG_IPADDR 192.168.0.3
+#define CONFIG_SERVERIP 192.168.0.1
+#define CONFIG_NETMASK 255.0.0.0
+
+#define CONFIG_BOOTCOMMAND "run flashboot"
+#define CONFIG_BOOTARGS "ubi.mtd=4 root=ubi0:rootfs rw rootfstype=ubifs rootflags=sync " \
+ "console=ttyCPM0,115200N8 " \
+ "ip=${ipaddr}:::${netmask}:mcr3k:eth0:off"
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#undef CONFIG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
+
+#define CONFIG_WATCHDOG 1 /* watchdog enabled */
+
+
+
+/*-----------------------------------------------------------------------
+ * Password configuration.
+ */
+#define CONFIG_AUTOBOOT_KEYED 1 /* Enable "password" protection */
+#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n"
+#define CONFIG_AUTOBOOT_DELAY_STR "root" /* 1st password */
+
+
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#ifdef CONFIG_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "S3K> "
+#endif
+
+#define CONFIG_SYS_MEMTEST_START 0x00002000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 8 KB ... 8 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
+
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+
+#define CONFIG_SYS_CLK_FREQ 132000000
+#define CONFIG_8xx_GCLK_FREQ 132000000
+
+
+
+/*-----------------------------------------------------------------------
+ * Physical memory map of the MCR3000 board
+ */
+#define CONFIG_SYS_IMMR 0xFF000000 /* Internal Memory Mapped Register*/
+
+#define CONFIG_SYS_OR0_PRELIM 0xFFC00926
+#define CONFIG_SYS_BR0_PRELIM 0x04000801
+#define CONFIG_SYS_OR1_PRELIM 0xFE000E00
+#define CONFIG_SYS_BR1_PRELIM 0x00000081
+#define CONFIG_SYS_OR2_PRELIM 0xFFFF8F2A
+#define CONFIG_SYS_BR2_PRELIM 0x08000801
+#define CONFIG_SYS_OR3_PRELIM 0xFFFF8142
+#define CONFIG_SYS_BR3_PRELIM 0x0C000401
+#define CONFIG_SYS_OR4_PRELIM 0xFFFF8D08
+#define CONFIG_SYS_BR4_PRELIM 0x10000801
+#define CONFIG_SYS_OR5_PRELIM 0xFFFF8916
+#define CONFIG_SYS_BR5_PRELIM 0x14000801
+#define CONFIG_SYS_OR6_PRELIM 0xFFFF0908
+#define CONFIG_SYS_BR6_PRELIM 0x18000801
+#define CONFIG_SYS_OR7_PRELIM 0xFFFF810A
+#define CONFIG_SYS_BR7_PRELIM 0x1C000001
+
+#define ADDR_FLASH ( CONFIG_SYS_BR0_PRELIM & 0xFFFF0000)
+#define ADDR_SDRAM ( CONFIG_SYS_BR1_PRELIM & 0xFFFF0000)
+#define ADDR_RAMDP ( CONFIG_SYS_BR2_PRELIM & 0xFFFF0000)
+#define ADDR_NAND ( CONFIG_SYS_BR3_PRELIM & 0xFFFF0000)
+#define ADDR_MTSL1 ((CONFIG_SYS_BR4_PRELIM & 0xFFFF0000) | 0x00000000)
+#define ADDR_MTSL2 ((CONFIG_SYS_BR4_PRELIM & 0xFFFF0000) | 0x00000200)
+#define ADDR_E1 ((CONFIG_SYS_BR4_PRELIM & 0xFFFF0000) | 0x00000400)
+#define ADDR_SEM ((CONFIG_SYS_BR4_PRELIM & 0xFFFF0000) | 0x00000600)
+#define ADDR_CPLD ((CONFIG_SYS_BR4_PRELIM & 0xFFFF0000) | 0x00000800)
+
+
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2f00 /* End of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size (bytes) reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+
+
+/*-----------------------------------------------------------------------
+ * RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero)
+ */
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_MAX_SIZE (32*1024*1024) /* 32 Mega Bytes */
+
+
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* FLASH address */
+#define CONFIG_SYS_FLASH_CFI 1 /* The flash is CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+
+
+/*-----------------------------------------------------------------------
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4096 KB for malloc() */
+
+
+
+/*-----------------------------------------------------------------------
+ * Environment Configuration
+ */
+/* environment is in FLASH */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_SECT_SIZE (64 * 1024) /* Total size of Environment Sector */
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
+#define CONFIG_ENV_OVERWRITE 1 /* Allow user to modify environment */
+
+
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+
+
+
+/*-----------------------------------------------------------------------
+ * Configuration registers
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
+
+#else
+#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_MLRC01)
+
+/* TBSCR - Time Base Status and Control Register */
+#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
+
+/* PISCR - Periodic Interrupt Status and Control */
+#define CONFIG_SYS_PISCR 0x0000
+
+/* PLPRCR */
+#define CONFIG_SYS_PLPRCR (0x00460004)
+
+/* SCCR - System Clock and reset Control Register */
+#define SCCR_MASK SCCR_COM00
+#define CONFIG_SYS_SCCR (SCCR_RTSEL | SCCR_CRQEN | SCCR_EBDF01)
+
+#define CONFIG_SYS_DER (0x2002000F)
+
+
+
+/*-----------------------------------------------------------------------
+ * Ethernet configuration part
+ */
+#define CONFIG_MII 1
+#define CONFIG_SYS_DISCOVER_PHY 1
+#define CONFIG_MII_INIT 1
+#define FEC_ENET 1
+
+
+
+/*-----------------------------------------------------------------------
+ * NAND configuration part
+ */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_MAX_CHIPS 1
+#define CONFIG_SYS_NAND_BASE 0x0C000000 /* Base address of the NAND FLASH */
+
+
+
+/*-----------------------------------------------------------------------
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+
+
+/*-----------------------------------------------------------------------
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+
+
+/*-----------------------------------------------------------------------
+ * Misc Settings
+ */
+#define CONFIG_LZMA
+#define CONFIG_SHA256
+
+
+
+#endif /* __CONFIG_H */
--
2.12.0
^ permalink raw reply related [flat|nested] 15+ messages in thread