* [RESEND 1/2] drm/i915/dp: Fix the t11_t12 panel power cycle delay from VBT read
@ 2017-06-26 19:21 Manasi Navare
2017-06-26 19:21 ` [RESEND 2/2] drm/i915/dp: Remove -1/+1 from t11_t12 for Gen9_LP/CNP case Manasi Navare
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Manasi Navare @ 2017-06-26 19:21 UTC (permalink / raw)
To: intel-gfx
When we read the VBT t11_t12 value for panel power cycle delay,
it is a zero based value so we need to 100ms to that. And then it
needs to be multiplied by 10 to store it in 100usecs unit same as
SW VBT.
v3:
* Add it as part of series
v2:
* Change the VBT value instead of HW readout and pp div (Ville Syrjala)
Reviewed-by: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Clint Taylor <clinton.a.taylor@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index bca4ac1..be9e17a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5234,6 +5234,11 @@ intel_dp_init_panel_power_sequencer(struct drm_device *dev,
intel_pps_dump_state("cur", &cur);
vbt = dev_priv->vbt.edp.pps;
+ /* T11_T12 delay is special and actually in units of 100ms, but zero
+ * based in the hw (so we need to add 100 ms). But the sw vbt
+ * table multiplies it with 1000 to make it in units of 100usec,
+ * too. */
+ vbt.t11_t12 += 100 * 10;
/* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
* our hw here, which are all in 100usec. */
--
2.1.4
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* [RESEND 2/2] drm/i915/dp: Remove -1/+1 from t11_t12 for Gen9_LP/CNP case
2017-06-26 19:21 [RESEND 1/2] drm/i915/dp: Fix the t11_t12 panel power cycle delay from VBT read Manasi Navare
@ 2017-06-26 19:21 ` Manasi Navare
2017-06-26 19:32 ` ✓ Fi.CI.BAT: success for series starting with [RESEND,1/2] drm/i915/dp: Fix the t11_t12 panel power cycle delay from VBT read Patchwork
2017-06-27 9:59 ` [RESEND 1/2] " Ville Syrjälä
2 siblings, 0 replies; 4+ messages in thread
From: Manasi Navare @ 2017-06-26 19:21 UTC (permalink / raw)
To: intel-gfx
Now the VBT.seq->t11_t12 value adds 100ms to both Gen9_LP
as well as non Gen9_LP cases so no need to special case
and do -1 during HW readout and +1 during pp_div write
for Gen9_LP/CNP case.
Reviewed-by: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Clint Taylor <clinton.a.taylor@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 10 +++-------
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index be9e17a..67bc8a7a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5178,12 +5178,8 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
PANEL_POWER_DOWN_DELAY_SHIFT;
if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
- u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
- BXT_POWER_CYCLE_DELAY_SHIFT;
- if (tmp > 0)
- seq->t11_t12 = (tmp - 1) * 1000;
- else
- seq->t11_t12 = 0;
+ seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
+ BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
} else {
seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
@@ -5342,7 +5338,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
pp_div = I915_READ(regs.pp_ctrl);
pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
- pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
+ pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
<< BXT_POWER_CYCLE_DELAY_SHIFT);
} else {
pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
--
2.1.4
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [RESEND,1/2] drm/i915/dp: Fix the t11_t12 panel power cycle delay from VBT read
2017-06-26 19:21 [RESEND 1/2] drm/i915/dp: Fix the t11_t12 panel power cycle delay from VBT read Manasi Navare
2017-06-26 19:21 ` [RESEND 2/2] drm/i915/dp: Remove -1/+1 from t11_t12 for Gen9_LP/CNP case Manasi Navare
@ 2017-06-26 19:32 ` Patchwork
2017-06-27 9:59 ` [RESEND 1/2] " Ville Syrjälä
2 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2017-06-26 19:32 UTC (permalink / raw)
To: Navare, Manasi D; +Cc: intel-gfx
== Series Details ==
Series: series starting with [RESEND,1/2] drm/i915/dp: Fix the t11_t12 panel power cycle delay from VBT read
URL : https://patchwork.freedesktop.org/series/26388/
State : success
== Summary ==
Series 26388v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/26388/revisions/1/mbox/
Test gem_exec_suspend:
Subgroup basic-s4-devices:
dmesg-warn -> PASS (fi-kbl-7560u) fdo#100125
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
fail -> PASS (fi-blb-e6850) fdo#101599
fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125
fdo#101599 https://bugs.freedesktop.org/show_bug.cgi?id=101599
fi-bdw-5557u total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:441s
fi-bdw-gvtdvm total:279 pass:257 dwarn:8 dfail:0 fail:0 skip:14 time:424s
fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:356s
fi-bsw-n3050 total:279 pass:242 dwarn:1 dfail:0 fail:0 skip:36 time:545s
fi-bxt-j4205 total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:511s
fi-byt-j1900 total:279 pass:253 dwarn:2 dfail:0 fail:0 skip:24 time:485s
fi-byt-n2820 total:279 pass:249 dwarn:2 dfail:0 fail:0 skip:28 time:486s
fi-glk-2a total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:600s
fi-hsw-4770 total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:435s
fi-hsw-4770r total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:418s
fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:427s
fi-ivb-3520m total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:488s
fi-ivb-3770 total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:479s
fi-kbl-7500u total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:466s
fi-kbl-7560u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:571s
fi-kbl-r total:279 pass:260 dwarn:1 dfail:0 fail:0 skip:18 time:583s
fi-pnv-d510 total:279 pass:221 dwarn:3 dfail:0 fail:0 skip:55 time:559s
fi-skl-6260u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:456s
fi-skl-6700k total:279 pass:257 dwarn:4 dfail:0 fail:0 skip:18 time:467s
fi-skl-6770hq total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:485s
fi-skl-gvtdvm total:279 pass:266 dwarn:0 dfail:0 fail:0 skip:13 time:436s
fi-snb-2520m total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:534s
fi-snb-2600 total:279 pass:250 dwarn:0 dfail:0 fail:0 skip:29 time:402s
21d74e215ad650f0e8e30de609bd65601f0aa11d drm-tip: 2017y-06m-26d-09h-12m-14s UTC integration manifest
62da23b drm/i915/dp: Remove -1/+1 from t11_t12 for Gen9_LP/CNP case
5a36c79 drm/i915/dp: Fix the t11_t12 panel power cycle delay from VBT read
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_5045/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [RESEND 1/2] drm/i915/dp: Fix the t11_t12 panel power cycle delay from VBT read
2017-06-26 19:21 [RESEND 1/2] drm/i915/dp: Fix the t11_t12 panel power cycle delay from VBT read Manasi Navare
2017-06-26 19:21 ` [RESEND 2/2] drm/i915/dp: Remove -1/+1 from t11_t12 for Gen9_LP/CNP case Manasi Navare
2017-06-26 19:32 ` ✓ Fi.CI.BAT: success for series starting with [RESEND,1/2] drm/i915/dp: Fix the t11_t12 panel power cycle delay from VBT read Patchwork
@ 2017-06-27 9:59 ` Ville Syrjälä
2 siblings, 0 replies; 4+ messages in thread
From: Ville Syrjälä @ 2017-06-27 9:59 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Mon, Jun 26, 2017 at 12:21:44PM -0700, Manasi Navare wrote:
> When we read the VBT t11_t12 value for panel power cycle delay,
> it is a zero based value so we need to 100ms to that. And then it
> needs to be multiplied by 10 to store it in 100usecs unit same as
> SW VBT.
>
> v3:
> * Add it as part of series
> v2:
> * Change the VBT value instead of HW readout and pp div (Ville Syrjala)
>
> Reviewed-by: Ville Syrjala <ville.syrjala@linux.intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Clint Taylor <clinton.a.taylor@intel.com>
Thanks. CI seems happy so both patches pushed to dinq.
> ---
> drivers/gpu/drm/i915/intel_dp.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index bca4ac1..be9e17a 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -5234,6 +5234,11 @@ intel_dp_init_panel_power_sequencer(struct drm_device *dev,
> intel_pps_dump_state("cur", &cur);
>
> vbt = dev_priv->vbt.edp.pps;
> + /* T11_T12 delay is special and actually in units of 100ms, but zero
> + * based in the hw (so we need to add 100 ms). But the sw vbt
> + * table multiplies it with 1000 to make it in units of 100usec,
> + * too. */
> + vbt.t11_t12 += 100 * 10;
>
> /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
> * our hw here, which are all in 100usec. */
> --
> 2.1.4
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
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2017-06-26 19:21 [RESEND 1/2] drm/i915/dp: Fix the t11_t12 panel power cycle delay from VBT read Manasi Navare
2017-06-26 19:21 ` [RESEND 2/2] drm/i915/dp: Remove -1/+1 from t11_t12 for Gen9_LP/CNP case Manasi Navare
2017-06-26 19:32 ` ✓ Fi.CI.BAT: success for series starting with [RESEND,1/2] drm/i915/dp: Fix the t11_t12 panel power cycle delay from VBT read Patchwork
2017-06-27 9:59 ` [RESEND 1/2] " Ville Syrjälä
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