* [PATCH V2] mmc: renesas_sdhi_core: on R-Car 2+, make use of CBSY bit
@ 2017-06-28 15:21 Wolfram Sang
2017-06-28 17:01 ` Geert Uytterhoeven
2017-07-11 14:43 ` Ulf Hansson
0 siblings, 2 replies; 3+ messages in thread
From: Wolfram Sang @ 2017-06-28 15:21 UTC (permalink / raw)
To: linux-mmc; +Cc: linux-renesas-soc, Dirk Behme, Yoshihiro Shimoda, Wolfram Sang
Most registers need to wait until the command is completed, not
necessarily until the bus is free. At least, R-Car 2+ SoCs can signal
that via the CBSY bit, so let's use it there instead of SCLKDIVEN to
save a little bit of delay.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
Tested on H2 and M3-W.
Change since V1:
Rebased on top of mmc/next with Simon's Gen3 DMA patches.
drivers/mmc/host/renesas_sdhi_core.c | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
index 569bcdd5e6537a..be806d3e9afeec 100644
--- a/drivers/mmc/host/renesas_sdhi_core.c
+++ b/drivers/mmc/host/renesas_sdhi_core.c
@@ -398,12 +398,14 @@ static void renesas_sdhi_hw_reset(struct tmio_mmc_host *host)
sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
}
-static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host)
+static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit)
{
int timeout = 1000;
+ /* CBSY is set when busy, SCLKDIVEN is cleared when busy */
+ u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0);
- while (--timeout && !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
- & TMIO_STAT_SCLKDIVEN))
+ while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
+ & bit) == wait_state)
udelay(1);
if (!timeout) {
@@ -416,17 +418,22 @@ static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host)
static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
{
+ u32 bit = TMIO_STAT_SCLKDIVEN;
+
switch (addr) {
case CTL_SD_CMD:
case CTL_STOP_INTERNAL_ACTION:
case CTL_XFER_BLK_COUNT:
- case CTL_SD_CARD_CLK_CTL:
case CTL_SD_XFER_LEN:
case CTL_SD_MEM_CARD_OPT:
case CTL_TRANSACTION_CTL:
case CTL_DMA_ENABLE:
case EXT_ACC:
- return renesas_sdhi_wait_idle(host);
+ if (host->pdata->flags & TMIO_MMC_MIN_RCAR2)
+ bit = TMIO_STAT_CMD_BUSY;
+ /* fallthrough */
+ case CTL_SD_CARD_CLK_CTL:
+ return renesas_sdhi_wait_idle(host, bit);
}
return 0;
--
2.11.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH V2] mmc: renesas_sdhi_core: on R-Car 2+, make use of CBSY bit
2017-06-28 15:21 [PATCH V2] mmc: renesas_sdhi_core: on R-Car 2+, make use of CBSY bit Wolfram Sang
@ 2017-06-28 17:01 ` Geert Uytterhoeven
2017-07-11 14:43 ` Ulf Hansson
1 sibling, 0 replies; 3+ messages in thread
From: Geert Uytterhoeven @ 2017-06-28 17:01 UTC (permalink / raw)
To: Wolfram Sang; +Cc: Linux MMC List, Linux-Renesas, Dirk Behme, Yoshihiro Shimoda
Hi Wolfram,
On Wed, Jun 28, 2017 at 5:21 PM, Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> Most registers need to wait until the command is completed, not
> necessarily until the bus is free. At least, R-Car 2+ SoCs can signal
> that via the CBSY bit, so let's use it there instead of SCLKDIVEN to
> save a little bit of delay.
>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> ---
>
> Tested on H2 and M3-W.
>
> Change since V1:
>
> Rebased on top of mmc/next with Simon's Gen3 DMA patches.
>
> drivers/mmc/host/renesas_sdhi_core.c | 17 ++++++++++++-----
> 1 file changed, 12 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
> index 569bcdd5e6537a..be806d3e9afeec 100644
> --- a/drivers/mmc/host/renesas_sdhi_core.c
> +++ b/drivers/mmc/host/renesas_sdhi_core.c
> @@ -398,12 +398,14 @@ static void renesas_sdhi_hw_reset(struct tmio_mmc_host *host)
> sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
> }
>
> -static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host)
> +static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit)
> {
> int timeout = 1000;
> + /* CBSY is set when busy, SCLKDIVEN is cleared when busy */
> + u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0);
>
> - while (--timeout && !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
> - & TMIO_STAT_SCLKDIVEN))
> + while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
> + & bit) == wait_state)
Do you have any figures on the number of loops saved?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH V2] mmc: renesas_sdhi_core: on R-Car 2+, make use of CBSY bit
2017-06-28 15:21 [PATCH V2] mmc: renesas_sdhi_core: on R-Car 2+, make use of CBSY bit Wolfram Sang
2017-06-28 17:01 ` Geert Uytterhoeven
@ 2017-07-11 14:43 ` Ulf Hansson
1 sibling, 0 replies; 3+ messages in thread
From: Ulf Hansson @ 2017-07-11 14:43 UTC (permalink / raw)
To: Wolfram Sang; +Cc: linux-mmc, Linux-Renesas, Dirk Behme, Yoshihiro Shimoda
On 28 June 2017 at 17:21, Wolfram Sang <wsa+renesas@sang-engineering.com> wrote:
> Most registers need to wait until the command is completed, not
> necessarily until the bus is free. At least, R-Car 2+ SoCs can signal
> that via the CBSY bit, so let's use it there instead of SCLKDIVEN to
> save a little bit of delay.
>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Thanks, applied for next!
Kind regards
Uffe
> ---
>
> Tested on H2 and M3-W.
>
> Change since V1:
>
> Rebased on top of mmc/next with Simon's Gen3 DMA patches.
>
> drivers/mmc/host/renesas_sdhi_core.c | 17 ++++++++++++-----
> 1 file changed, 12 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
> index 569bcdd5e6537a..be806d3e9afeec 100644
> --- a/drivers/mmc/host/renesas_sdhi_core.c
> +++ b/drivers/mmc/host/renesas_sdhi_core.c
> @@ -398,12 +398,14 @@ static void renesas_sdhi_hw_reset(struct tmio_mmc_host *host)
> sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
> }
>
> -static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host)
> +static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit)
> {
> int timeout = 1000;
> + /* CBSY is set when busy, SCLKDIVEN is cleared when busy */
> + u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0);
>
> - while (--timeout && !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
> - & TMIO_STAT_SCLKDIVEN))
> + while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
> + & bit) == wait_state)
> udelay(1);
>
> if (!timeout) {
> @@ -416,17 +418,22 @@ static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host)
>
> static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
> {
> + u32 bit = TMIO_STAT_SCLKDIVEN;
> +
> switch (addr) {
> case CTL_SD_CMD:
> case CTL_STOP_INTERNAL_ACTION:
> case CTL_XFER_BLK_COUNT:
> - case CTL_SD_CARD_CLK_CTL:
> case CTL_SD_XFER_LEN:
> case CTL_SD_MEM_CARD_OPT:
> case CTL_TRANSACTION_CTL:
> case CTL_DMA_ENABLE:
> case EXT_ACC:
> - return renesas_sdhi_wait_idle(host);
> + if (host->pdata->flags & TMIO_MMC_MIN_RCAR2)
> + bit = TMIO_STAT_CMD_BUSY;
> + /* fallthrough */
> + case CTL_SD_CARD_CLK_CTL:
> + return renesas_sdhi_wait_idle(host, bit);
> }
>
> return 0;
> --
> 2.11.0
>
> --
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^ permalink raw reply [flat|nested] 3+ messages in thread
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2017-06-28 15:21 [PATCH V2] mmc: renesas_sdhi_core: on R-Car 2+, make use of CBSY bit Wolfram Sang
2017-06-28 17:01 ` Geert Uytterhoeven
2017-07-11 14:43 ` Ulf Hansson
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