[PATCH] drm/i915: reintroduce VLV/CHV PFI programming power domain workaround

[PATCH] drm/i915: reintroduce VLV/CHV PFI programming power domain workaround

[Gabriel Krisman Bertazi]

There are still cases on these platforms where an attempt is made to
configure the CDCLK while the power domain is off, like when coming back
from a suspend.  So the workaround below is still needed.

This effectively reverts commit 63ff30442519 ("drm/i915: Nuke the
VLV/CHV PFI programming power domain workaround").

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101517

Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Gabriel Krisman Bertazi <krisman@collabora.co.uk>
---
 drivers/gpu/drm/i915/intel_cdclk.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index b8914db7d2e1..1241e5891b29 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -491,6 +491,14 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
 	int cdclk = cdclk_state->cdclk;
 	u32 val, cmd;
 
+	/* There are cases where we can end up here with power domains
+	 * off and a CDCLK frequency other than the minimum, like when
+	 * issuing a modeset without actually changing any display after
+	 * a system suspend.  So grab the PIPE-A domain, which covers
+	 * the HW blocks needed for the following programming.
+	 */
+	intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
+
 	if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
 		cmd = 2;
 	else if (cdclk == 266667)
@@ -549,6 +557,8 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
 	intel_update_cdclk(dev_priv);
 
 	vlv_program_pfi_credits(dev_priv);
+
+	intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
 }
 
 static void chv_set_cdclk(struct drm_i915_private *dev_priv,
@@ -568,6 +578,14 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
 		return;
 	}
 
+	/* There are cases where we can end up here with power domains
+	 * off and a CDCLK frequency other than the minimum, like when
+	 * issuing a modeset without actually changing any display after
+	 * a system suspend.  So grab the PIPE-A domain, which covers
+	 * the HW blocks needed for the following programming.
+	 */
+	intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
+
 	/*
 	 * Specs are full of misinformation, but testing on actual
 	 * hardware has shown that we just need to write the desired
@@ -590,6 +608,8 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
 	intel_update_cdclk(dev_priv);
 
 	vlv_program_pfi_credits(dev_priv);
+
+	intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
 }
 
 static int bdw_calc_cdclk(int max_pixclk)
-- 
2.11.0

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✓ Fi.CI.BAT: success for drm/i915: reintroduce VLV/CHV PFI programming power domain workaround

[Patchwork]

== Series Details ==

Series: drm/i915: reintroduce VLV/CHV PFI programming power domain workaround
URL   : https://patchwork.freedesktop.org/series/26509/
State : success

== Summary ==

Series 26509v1 drm/i915: reintroduce VLV/CHV PFI programming power domain workaround
https://patchwork.freedesktop.org/api/1.0/series/26509/revisions/1/mbox/

Test gem_exec_flush:
        Subgroup basic-batch-kernel-default-uc:
                fail       -> PASS       (fi-snb-2600) fdo#100007
Test gem_exec_suspend:
        Subgroup basic-s4-devices:
                pass       -> DMESG-WARN (fi-kbl-7560u) fdo#100125
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-a:
                dmesg-warn -> PASS       (fi-byt-j1900) fdo#101517 +3

fdo#100007 https://bugs.freedesktop.org/show_bug.cgi?id=100007
fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125
fdo#101517 https://bugs.freedesktop.org/show_bug.cgi?id=101517

fi-bdw-5557u     total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  time:446s
fi-bdw-gvtdvm    total:279  pass:257  dwarn:8   dfail:0   fail:0   skip:14  time:433s
fi-blb-e6850     total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  time:388s
fi-bsw-n3050     total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  time:541s
fi-bxt-j4205     total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:514s
fi-byt-j1900     total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  time:492s
fi-byt-n2820     total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  time:484s
fi-glk-2a        total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:600s
fi-hsw-4770      total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:437s
fi-hsw-4770r     total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:411s
fi-ilk-650       total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  time:425s
fi-ivb-3520m     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:496s
fi-ivb-3770      total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:477s
fi-kbl-7500u     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:467s
fi-kbl-7560u     total:279  pass:268  dwarn:1   dfail:0   fail:0   skip:10  time:569s
fi-kbl-r         total:279  pass:260  dwarn:1   dfail:0   fail:0   skip:18  time:583s
fi-pnv-d510      total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  time:564s
fi-skl-6260u     total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:465s
fi-skl-6700hq    total:279  pass:223  dwarn:1   dfail:0   fail:30  skip:24  time:337s
fi-skl-6700k     total:279  pass:257  dwarn:4   dfail:0   fail:0   skip:18  time:473s
fi-skl-6770hq    total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:475s
fi-skl-gvtdvm    total:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  time:437s
fi-snb-2520m     total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  time:554s
fi-snb-2600      total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  time:402s

85a692e2c6a7cf93082044d776e838cb9e9b2146 drm-tip: 2017y-06m-28d-14h-24m-59s UTC integration manifest
6eb533a drm/i915: reintroduce VLV/CHV PFI programming power domain workaround

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_5063/
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Re: [PATCH] drm/i915: reintroduce VLV/CHV PFI programming power domain workaround

[Ville Syrjälä]

On Wed, Jun 28, 2017 at 06:06:05PM -0300, Gabriel Krisman Bertazi wrote:
> There are still cases on these platforms where an attempt is made to
> configure the CDCLK while the power domain is off, like when coming back
> from a suspend.  So the workaround below is still needed.
> 
> This effectively reverts commit 63ff30442519 ("drm/i915: Nuke the
> VLV/CHV PFI programming power domain workaround").
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101517
> 
> Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Gabriel Krisman Bertazi <krisman@collabora.co.uk>

Cc: stable@vger.kernel.org
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

and pushed to dinq. Thanks for the patch.

> ---
>  drivers/gpu/drm/i915/intel_cdclk.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index b8914db7d2e1..1241e5891b29 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -491,6 +491,14 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
>  	int cdclk = cdclk_state->cdclk;
>  	u32 val, cmd;
>  
> +	/* There are cases where we can end up here with power domains
> +	 * off and a CDCLK frequency other than the minimum, like when
> +	 * issuing a modeset without actually changing any display after
> +	 * a system suspend.  So grab the PIPE-A domain, which covers
> +	 * the HW blocks needed for the following programming.
> +	 */
> +	intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
> +
>  	if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
>  		cmd = 2;
>  	else if (cdclk == 266667)
> @@ -549,6 +557,8 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
>  	intel_update_cdclk(dev_priv);
>  
>  	vlv_program_pfi_credits(dev_priv);
> +
> +	intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
>  }
>  
>  static void chv_set_cdclk(struct drm_i915_private *dev_priv,
> @@ -568,6 +578,14 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
>  		return;
>  	}
>  
> +	/* There are cases where we can end up here with power domains
> +	 * off and a CDCLK frequency other than the minimum, like when
> +	 * issuing a modeset without actually changing any display after
> +	 * a system suspend.  So grab the PIPE-A domain, which covers
> +	 * the HW blocks needed for the following programming.
> +	 */
> +	intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
> +
>  	/*
>  	 * Specs are full of misinformation, but testing on actual
>  	 * hardware has shown that we just need to write the desired
> @@ -590,6 +608,8 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
>  	intel_update_cdclk(dev_priv);
>  
>  	vlv_program_pfi_credits(dev_priv);
> +
> +	intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
>  }
>  
>  static int bdw_calc_cdclk(int max_pixclk)
> -- 
> 2.11.0

-- 
Ville Syrjälä
Intel OTC
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