* [PATCH 0/2] Add ZTE ZX PWM device driver support @ 2017-06-29 2:54 ` Shawn Guo 0 siblings, 0 replies; 12+ messages in thread From: Shawn Guo @ 2017-06-29 2:54 UTC (permalink / raw) To: Thierry Reding, Rob Herring Cc: Baoyou Xie, Xin Zhou, Jun Nie, linux-pwm-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Shawn Guo From: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> The series adds the dt-bindings document and device driver for PWM controller found on ZTE ZX family SoCs. Shawn Guo (2): dt-bindings: pwm: add bindings doc for ZTE ZX PWM controller pwm: add ZTE ZX PWM device driver Documentation/devicetree/bindings/pwm/pwm-zx.txt | 22 ++ drivers/pwm/Kconfig | 9 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-zx.c | 244 +++++++++++++++++++++++ 4 files changed, 276 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-zx.txt create mode 100644 drivers/pwm/pwm-zx.c -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 0/2] Add ZTE ZX PWM device driver support @ 2017-06-29 2:54 ` Shawn Guo 0 siblings, 0 replies; 12+ messages in thread From: Shawn Guo @ 2017-06-29 2:54 UTC (permalink / raw) To: linux-arm-kernel From: Shawn Guo <shawn.guo@linaro.org> The series adds the dt-bindings document and device driver for PWM controller found on ZTE ZX family SoCs. Shawn Guo (2): dt-bindings: pwm: add bindings doc for ZTE ZX PWM controller pwm: add ZTE ZX PWM device driver Documentation/devicetree/bindings/pwm/pwm-zx.txt | 22 ++ drivers/pwm/Kconfig | 9 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-zx.c | 244 +++++++++++++++++++++++ 4 files changed, 276 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-zx.txt create mode 100644 drivers/pwm/pwm-zx.c -- 1.9.1 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/2] dt-bindings: pwm: add bindings doc for ZTE ZX PWM controller 2017-06-29 2:54 ` Shawn Guo @ 2017-06-29 2:54 ` Shawn Guo -1 siblings, 0 replies; 12+ messages in thread From: Shawn Guo @ 2017-06-29 2:54 UTC (permalink / raw) To: Thierry Reding, Rob Herring Cc: Baoyou Xie, Xin Zhou, Jun Nie, linux-pwm, devicetree, linux-arm-kernel, Shawn Guo From: Shawn Guo <shawn.guo@linaro.org> It adds bindings document for ZTE ZX PWM controller. The device has two clocks: PCLK and WCLK. The PCLK is for register access, and WCLK is the reference clock for calculating period and duty cycles. Also, the device supports polarity configuration, so #pwm-cells should be 3. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> --- Documentation/devicetree/bindings/pwm/pwm-zx.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-zx.txt diff --git a/Documentation/devicetree/bindings/pwm/pwm-zx.txt b/Documentation/devicetree/bindings/pwm/pwm-zx.txt new file mode 100644 index 000000000000..a6bcc75c9164 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-zx.txt @@ -0,0 +1,22 @@ +ZTE ZX PWM controller + +Required properties: + - compatible: Should be "zte,zx296718-pwm". + - reg: Physical base address and length of the controller's registers. + - clocks : The phandle and specifier referencing the controller's clocks. + - clock-names: "pclk" for PCLK, "wclk" for WCLK to the PWM controller. The + PCLK is for register access, while WCLK is the reference clock for + calculating period and duty cycles. + - #pwm-cells: Should be 3. See pwm.txt in this directory for a description of + the cells format. + +Example: + + pwm: pwm@1439000 { + compatible = "zte,zx296718-pwm"; + reg = <0x1439000 0x1000>; + clocks = <&lsp1crm LSP1_PWM_PCLK>, + <&lsp1crm LSP1_PWM_WCLK>; + clock-names = "pclk", "wclk"; + #pwm-cells = <3>; + }; -- 1.9.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 1/2] dt-bindings: pwm: add bindings doc for ZTE ZX PWM controller @ 2017-06-29 2:54 ` Shawn Guo 0 siblings, 0 replies; 12+ messages in thread From: Shawn Guo @ 2017-06-29 2:54 UTC (permalink / raw) To: linux-arm-kernel From: Shawn Guo <shawn.guo@linaro.org> It adds bindings document for ZTE ZX PWM controller. The device has two clocks: PCLK and WCLK. The PCLK is for register access, and WCLK is the reference clock for calculating period and duty cycles. Also, the device supports polarity configuration, so #pwm-cells should be 3. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> --- Documentation/devicetree/bindings/pwm/pwm-zx.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-zx.txt diff --git a/Documentation/devicetree/bindings/pwm/pwm-zx.txt b/Documentation/devicetree/bindings/pwm/pwm-zx.txt new file mode 100644 index 000000000000..a6bcc75c9164 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-zx.txt @@ -0,0 +1,22 @@ +ZTE ZX PWM controller + +Required properties: + - compatible: Should be "zte,zx296718-pwm". + - reg: Physical base address and length of the controller's registers. + - clocks : The phandle and specifier referencing the controller's clocks. + - clock-names: "pclk" for PCLK, "wclk" for WCLK to the PWM controller. The + PCLK is for register access, while WCLK is the reference clock for + calculating period and duty cycles. + - #pwm-cells: Should be 3. See pwm.txt in this directory for a description of + the cells format. + +Example: + + pwm: pwm at 1439000 { + compatible = "zte,zx296718-pwm"; + reg = <0x1439000 0x1000>; + clocks = <&lsp1crm LSP1_PWM_PCLK>, + <&lsp1crm LSP1_PWM_WCLK>; + clock-names = "pclk", "wclk"; + #pwm-cells = <3>; + }; -- 1.9.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
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* Re: [PATCH 1/2] dt-bindings: pwm: add bindings doc for ZTE ZX PWM controller 2017-06-29 2:54 ` Shawn Guo @ 2017-07-06 14:57 ` Rob Herring -1 siblings, 0 replies; 12+ messages in thread From: Rob Herring @ 2017-07-06 14:57 UTC (permalink / raw) To: Shawn Guo Cc: Thierry Reding, Baoyou Xie, Xin Zhou, Jun Nie, linux-pwm-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Shawn Guo On Thu, Jun 29, 2017 at 10:54:33AM +0800, Shawn Guo wrote: > From: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> > > It adds bindings document for ZTE ZX PWM controller. The device > has two clocks: PCLK and WCLK. The PCLK is for register access, and > WCLK is the reference clock for calculating period and duty cycles. > Also, the device supports polarity configuration, so #pwm-cells should > be 3. > > Signed-off-by: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> > --- > Documentation/devicetree/bindings/pwm/pwm-zx.txt | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/pwm-zx.txt Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/2] dt-bindings: pwm: add bindings doc for ZTE ZX PWM controller @ 2017-07-06 14:57 ` Rob Herring 0 siblings, 0 replies; 12+ messages in thread From: Rob Herring @ 2017-07-06 14:57 UTC (permalink / raw) To: linux-arm-kernel On Thu, Jun 29, 2017 at 10:54:33AM +0800, Shawn Guo wrote: > From: Shawn Guo <shawn.guo@linaro.org> > > It adds bindings document for ZTE ZX PWM controller. The device > has two clocks: PCLK and WCLK. The PCLK is for register access, and > WCLK is the reference clock for calculating period and duty cycles. > Also, the device supports polarity configuration, so #pwm-cells should > be 3. > > Signed-off-by: Shawn Guo <shawn.guo@linaro.org> > --- > Documentation/devicetree/bindings/pwm/pwm-zx.txt | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/pwm-zx.txt Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 12+ messages in thread
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* [PATCH 2/2] pwm: add ZTE ZX PWM device driver 2017-06-29 2:54 ` Shawn Guo @ 2017-06-29 2:54 ` Shawn Guo -1 siblings, 0 replies; 12+ messages in thread From: Shawn Guo @ 2017-06-29 2:54 UTC (permalink / raw) To: Thierry Reding, Rob Herring Cc: Baoyou Xie, Xin Zhou, Jun Nie, linux-pwm-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Shawn Guo From: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> It adds PWM device driver for ZTE ZX family SoCs. The PWM controller supports 4 devices with polarity configuration. The driver has been tested with pwm-regulator support to scale core voltage via cpufreq. Signed-off-by: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> --- drivers/pwm/Kconfig | 9 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-zx.c | 244 +++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 254 insertions(+) create mode 100644 drivers/pwm/pwm-zx.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 313c10789ca2..e98175331a69 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -500,4 +500,13 @@ config PWM_VT8500 To compile this driver as a module, choose M here: the module will be called pwm-vt8500. +config PWM_ZX + tristate "ZTE ZX PWM support" + depends on ARCH_ZX + help + Generic PWM framework driver for ZTE ZX family SoCs. + + To compile this driver as a module, choose M here: the module + will be called pwm-zx. + endif diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 93da1f79a3b8..75ab74094d7b 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -49,3 +49,4 @@ obj-$(CONFIG_PWM_TIPWMSS) += pwm-tipwmss.o obj-$(CONFIG_PWM_TWL) += pwm-twl.o obj-$(CONFIG_PWM_TWL_LED) += pwm-twl-led.o obj-$(CONFIG_PWM_VT8500) += pwm-vt8500.o +obj-$(CONFIG_PWM_ZX) += pwm-zx.o diff --git a/drivers/pwm/pwm-zx.c b/drivers/pwm/pwm-zx.c new file mode 100644 index 000000000000..5c81c2ddc0a9 --- /dev/null +++ b/drivers/pwm/pwm-zx.c @@ -0,0 +1,244 @@ +/* + * Copyright (C) 2017 Sanechips Technology Co., Ltd. + * Copyright 2017 Linaro Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pwm.h> +#include <linux/slab.h> + +#define ZX_PWM_MODE 0x0 +#define ZX_PWM_CLKDIV_MASK GENMASK(11, 2) +#define ZX_PWM_CLKDIV(x) (((x) << 8) & ZX_PWM_CLKDIV_MASK) +#define ZX_PWM_POLAR BIT(1) +#define ZX_PWM_EN BIT(0) +#define ZX_PWM_PERIOD 0x4 +#define ZX_PWM_DUTY 0x8 + +#define ZX_PWM_CLKDIV_MAX 1023 +#define ZX_PWM_PERIOD_MAX 65535 + +struct zx_pwm_chip { + struct pwm_chip chip; + struct clk *pclk; + struct clk *wclk; + void __iomem *base; +}; + +#define to_zx_pwm_chip(_chip) container_of(_chip, struct zx_pwm_chip, chip) + +static inline u32 zx_pwm_readl(struct zx_pwm_chip *zpc, unsigned int hwpwm, + unsigned int offset) +{ + return readl(zpc->base + (hwpwm + 1) * 0x10 + offset); +} + +static inline void zx_pwm_writel(struct zx_pwm_chip *zpc, unsigned int hwpwm, + unsigned int offset, u32 val) +{ + writel(val, zpc->base + (hwpwm + 1) * 0x10 + offset); +} + +static int zx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct zx_pwm_chip *zpc = to_zx_pwm_chip(chip); + unsigned int period_cycles; + unsigned int duty_cycles; + unsigned long long c; + unsigned long rate; + int div = 1; + u32 val; + + /* Find out the best divider */ + rate = clk_get_rate(zpc->wclk); + while (1) { + c = rate / div; + c = c * period_ns; + do_div(c, NSEC_PER_SEC); + if (c < ZX_PWM_PERIOD_MAX) + break; + div++; + if (div > ZX_PWM_CLKDIV_MAX) + return -ERANGE; + } + + /* Calculate duty cycles */ + period_cycles = c; + c *= duty_ns; + do_div(c, period_ns); + duty_cycles = c; + + /* + * If the pwm is being enabled, we have to temporarily disable it + * before configuring the registers. + */ + if (pwm_is_enabled(pwm)) { + val = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_MODE); + val &= ~ZX_PWM_EN; + zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_MODE, val); + } + + /* Set up registers */ + val = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_MODE); + val &= ZX_PWM_CLKDIV_MASK; + val |= ZX_PWM_CLKDIV(div); + zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_MODE, val); + + zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_PERIOD, period_cycles); + zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_DUTY, duty_cycles); + + /* Re-enable the pwm if needed */ + if (pwm_is_enabled(pwm)) { + val = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_MODE); + val |= ZX_PWM_EN; + zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_MODE, val); + } + + return 0; +} + +static int zx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct zx_pwm_chip *zpc = to_zx_pwm_chip(chip); + u32 val; + int ret; + + ret = clk_prepare_enable(zpc->wclk); + if (ret) + return ret; + + /* Enable the pwm */ + val = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_MODE); + val |= ZX_PWM_EN; + zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_MODE, val); + + return 0; +} + +static void zx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct zx_pwm_chip *zpc = to_zx_pwm_chip(chip); + u32 val; + + /* Disable the pwm */ + val = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_MODE); + val &= ~ZX_PWM_EN; + zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_MODE, val); + + clk_disable_unprepare(zpc->wclk); +} + +static int zx_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm, + enum pwm_polarity polarity) +{ + struct zx_pwm_chip *zpc = to_zx_pwm_chip(chip); + u32 val; + + val = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_MODE); + + if (polarity == PWM_POLARITY_INVERSED) + val &= ~ZX_PWM_POLAR; + else + val |= ZX_PWM_POLAR; + + zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_MODE, val); + + return 0; +} + +static const struct pwm_ops zx_pwm_ops = { + .config = zx_pwm_config, + .enable = zx_pwm_enable, + .disable = zx_pwm_disable, + .set_polarity = zx_pwm_set_polarity, + .owner = THIS_MODULE, +}; + +static int zx_pwm_probe(struct platform_device *pdev) +{ + struct zx_pwm_chip *zpc; + struct resource *res; + int ret; + + zpc = devm_kzalloc(&pdev->dev, sizeof(*zpc), GFP_KERNEL); + if (!zpc) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + zpc->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(zpc->base)) + return PTR_ERR(zpc->base); + + zpc->pclk = devm_clk_get(&pdev->dev, "pclk"); + if (IS_ERR(zpc->pclk)) + return PTR_ERR(zpc->pclk); + + zpc->wclk = devm_clk_get(&pdev->dev, "wclk"); + if (IS_ERR(zpc->wclk)) + return PTR_ERR(zpc->wclk); + + zpc->chip.dev = &pdev->dev; + zpc->chip.ops = &zx_pwm_ops; + zpc->chip.base = -1; + zpc->chip.npwm = 4; + zpc->chip.of_xlate = of_pwm_xlate_with_flags; + zpc->chip.of_pwm_n_cells = 3; + + ret = pwmchip_add(&zpc->chip); + if (ret < 0) { + dev_err(&pdev->dev, "failed to add pwm chip %d\n", ret); + return ret; + } + + platform_set_drvdata(pdev, zpc); + + ret = clk_prepare_enable(zpc->pclk); + if (ret) + goto pwm_remove; + + return 0; + +pwm_remove: + pwmchip_remove(&zpc->chip); + return ret; +} + +static int zx_pwm_remove(struct platform_device *pdev) +{ + struct zx_pwm_chip *zpc = platform_get_drvdata(pdev); + + clk_disable_unprepare(zpc->pclk); + + return pwmchip_remove(&zpc->chip); +} + +static const struct of_device_id zx_pwm_dt_ids[] = { + { .compatible = "zte,zx296718-pwm", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, zx_pwm_dt_ids); + +static struct platform_driver zx_pwm_driver = { + .driver = { + .name = "zx-pwm", + .of_match_table = zx_pwm_dt_ids, + }, + .probe = zx_pwm_probe, + .remove = zx_pwm_remove, +}; +module_platform_driver(zx_pwm_driver); + +MODULE_ALIAS("platform:zx-pwm"); +MODULE_AUTHOR("Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>"); +MODULE_DESCRIPTION("ZTE ZX PWM Driver"); +MODULE_LICENSE("GPL v2"); -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/2] pwm: add ZTE ZX PWM device driver @ 2017-06-29 2:54 ` Shawn Guo 0 siblings, 0 replies; 12+ messages in thread From: Shawn Guo @ 2017-06-29 2:54 UTC (permalink / raw) To: linux-arm-kernel From: Shawn Guo <shawn.guo@linaro.org> It adds PWM device driver for ZTE ZX family SoCs. The PWM controller supports 4 devices with polarity configuration. The driver has been tested with pwm-regulator support to scale core voltage via cpufreq. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> --- drivers/pwm/Kconfig | 9 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-zx.c | 244 +++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 254 insertions(+) create mode 100644 drivers/pwm/pwm-zx.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 313c10789ca2..e98175331a69 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -500,4 +500,13 @@ config PWM_VT8500 To compile this driver as a module, choose M here: the module will be called pwm-vt8500. +config PWM_ZX + tristate "ZTE ZX PWM support" + depends on ARCH_ZX + help + Generic PWM framework driver for ZTE ZX family SoCs. + + To compile this driver as a module, choose M here: the module + will be called pwm-zx. + endif diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 93da1f79a3b8..75ab74094d7b 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -49,3 +49,4 @@ obj-$(CONFIG_PWM_TIPWMSS) += pwm-tipwmss.o obj-$(CONFIG_PWM_TWL) += pwm-twl.o obj-$(CONFIG_PWM_TWL_LED) += pwm-twl-led.o obj-$(CONFIG_PWM_VT8500) += pwm-vt8500.o +obj-$(CONFIG_PWM_ZX) += pwm-zx.o diff --git a/drivers/pwm/pwm-zx.c b/drivers/pwm/pwm-zx.c new file mode 100644 index 000000000000..5c81c2ddc0a9 --- /dev/null +++ b/drivers/pwm/pwm-zx.c @@ -0,0 +1,244 @@ +/* + * Copyright (C) 2017 Sanechips Technology Co., Ltd. + * Copyright 2017 Linaro Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pwm.h> +#include <linux/slab.h> + +#define ZX_PWM_MODE 0x0 +#define ZX_PWM_CLKDIV_MASK GENMASK(11, 2) +#define ZX_PWM_CLKDIV(x) (((x) << 8) & ZX_PWM_CLKDIV_MASK) +#define ZX_PWM_POLAR BIT(1) +#define ZX_PWM_EN BIT(0) +#define ZX_PWM_PERIOD 0x4 +#define ZX_PWM_DUTY 0x8 + +#define ZX_PWM_CLKDIV_MAX 1023 +#define ZX_PWM_PERIOD_MAX 65535 + +struct zx_pwm_chip { + struct pwm_chip chip; + struct clk *pclk; + struct clk *wclk; + void __iomem *base; +}; + +#define to_zx_pwm_chip(_chip) container_of(_chip, struct zx_pwm_chip, chip) + +static inline u32 zx_pwm_readl(struct zx_pwm_chip *zpc, unsigned int hwpwm, + unsigned int offset) +{ + return readl(zpc->base + (hwpwm + 1) * 0x10 + offset); +} + +static inline void zx_pwm_writel(struct zx_pwm_chip *zpc, unsigned int hwpwm, + unsigned int offset, u32 val) +{ + writel(val, zpc->base + (hwpwm + 1) * 0x10 + offset); +} + +static int zx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct zx_pwm_chip *zpc = to_zx_pwm_chip(chip); + unsigned int period_cycles; + unsigned int duty_cycles; + unsigned long long c; + unsigned long rate; + int div = 1; + u32 val; + + /* Find out the best divider */ + rate = clk_get_rate(zpc->wclk); + while (1) { + c = rate / div; + c = c * period_ns; + do_div(c, NSEC_PER_SEC); + if (c < ZX_PWM_PERIOD_MAX) + break; + div++; + if (div > ZX_PWM_CLKDIV_MAX) + return -ERANGE; + } + + /* Calculate duty cycles */ + period_cycles = c; + c *= duty_ns; + do_div(c, period_ns); + duty_cycles = c; + + /* + * If the pwm is being enabled, we have to temporarily disable it + * before configuring the registers. + */ + if (pwm_is_enabled(pwm)) { + val = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_MODE); + val &= ~ZX_PWM_EN; + zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_MODE, val); + } + + /* Set up registers */ + val = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_MODE); + val &= ZX_PWM_CLKDIV_MASK; + val |= ZX_PWM_CLKDIV(div); + zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_MODE, val); + + zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_PERIOD, period_cycles); + zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_DUTY, duty_cycles); + + /* Re-enable the pwm if needed */ + if (pwm_is_enabled(pwm)) { + val = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_MODE); + val |= ZX_PWM_EN; + zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_MODE, val); + } + + return 0; +} + +static int zx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct zx_pwm_chip *zpc = to_zx_pwm_chip(chip); + u32 val; + int ret; + + ret = clk_prepare_enable(zpc->wclk); + if (ret) + return ret; + + /* Enable the pwm */ + val = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_MODE); + val |= ZX_PWM_EN; + zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_MODE, val); + + return 0; +} + +static void zx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct zx_pwm_chip *zpc = to_zx_pwm_chip(chip); + u32 val; + + /* Disable the pwm */ + val = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_MODE); + val &= ~ZX_PWM_EN; + zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_MODE, val); + + clk_disable_unprepare(zpc->wclk); +} + +static int zx_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm, + enum pwm_polarity polarity) +{ + struct zx_pwm_chip *zpc = to_zx_pwm_chip(chip); + u32 val; + + val = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_MODE); + + if (polarity == PWM_POLARITY_INVERSED) + val &= ~ZX_PWM_POLAR; + else + val |= ZX_PWM_POLAR; + + zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_MODE, val); + + return 0; +} + +static const struct pwm_ops zx_pwm_ops = { + .config = zx_pwm_config, + .enable = zx_pwm_enable, + .disable = zx_pwm_disable, + .set_polarity = zx_pwm_set_polarity, + .owner = THIS_MODULE, +}; + +static int zx_pwm_probe(struct platform_device *pdev) +{ + struct zx_pwm_chip *zpc; + struct resource *res; + int ret; + + zpc = devm_kzalloc(&pdev->dev, sizeof(*zpc), GFP_KERNEL); + if (!zpc) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + zpc->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(zpc->base)) + return PTR_ERR(zpc->base); + + zpc->pclk = devm_clk_get(&pdev->dev, "pclk"); + if (IS_ERR(zpc->pclk)) + return PTR_ERR(zpc->pclk); + + zpc->wclk = devm_clk_get(&pdev->dev, "wclk"); + if (IS_ERR(zpc->wclk)) + return PTR_ERR(zpc->wclk); + + zpc->chip.dev = &pdev->dev; + zpc->chip.ops = &zx_pwm_ops; + zpc->chip.base = -1; + zpc->chip.npwm = 4; + zpc->chip.of_xlate = of_pwm_xlate_with_flags; + zpc->chip.of_pwm_n_cells = 3; + + ret = pwmchip_add(&zpc->chip); + if (ret < 0) { + dev_err(&pdev->dev, "failed to add pwm chip %d\n", ret); + return ret; + } + + platform_set_drvdata(pdev, zpc); + + ret = clk_prepare_enable(zpc->pclk); + if (ret) + goto pwm_remove; + + return 0; + +pwm_remove: + pwmchip_remove(&zpc->chip); + return ret; +} + +static int zx_pwm_remove(struct platform_device *pdev) +{ + struct zx_pwm_chip *zpc = platform_get_drvdata(pdev); + + clk_disable_unprepare(zpc->pclk); + + return pwmchip_remove(&zpc->chip); +} + +static const struct of_device_id zx_pwm_dt_ids[] = { + { .compatible = "zte,zx296718-pwm", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, zx_pwm_dt_ids); + +static struct platform_driver zx_pwm_driver = { + .driver = { + .name = "zx-pwm", + .of_match_table = zx_pwm_dt_ids, + }, + .probe = zx_pwm_probe, + .remove = zx_pwm_remove, +}; +module_platform_driver(zx_pwm_driver); + +MODULE_ALIAS("platform:zx-pwm"); +MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); +MODULE_DESCRIPTION("ZTE ZX PWM Driver"); +MODULE_LICENSE("GPL v2"); -- 1.9.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] pwm: add ZTE ZX PWM device driver 2017-06-29 2:54 ` Shawn Guo @ 2017-07-25 11:53 ` Thierry Reding -1 siblings, 0 replies; 12+ messages in thread From: Thierry Reding @ 2017-07-25 11:53 UTC (permalink / raw) To: Shawn Guo Cc: Rob Herring, Baoyou Xie, Xin Zhou, Jun Nie, linux-pwm, devicetree, linux-arm-kernel, Shawn Guo [-- Attachment #1: Type: text/plain, Size: 3421 bytes --] On Thu, Jun 29, 2017 at 10:54:34AM +0800, Shawn Guo wrote: > From: Shawn Guo <shawn.guo@linaro.org> > > It adds PWM device driver for ZTE ZX family SoCs. The PWM controller > supports 4 devices with polarity configuration. > > The driver has been tested with pwm-regulator support to scale core > voltage via cpufreq. > > Signed-off-by: Shawn Guo <shawn.guo@linaro.org> > --- > drivers/pwm/Kconfig | 9 ++ > drivers/pwm/Makefile | 1 + > drivers/pwm/pwm-zx.c | 244 +++++++++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 254 insertions(+) > create mode 100644 drivers/pwm/pwm-zx.c Hi Shawn, This is close to perfect. Two minor things, see below. > diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig > index 313c10789ca2..e98175331a69 100644 > --- a/drivers/pwm/Kconfig > +++ b/drivers/pwm/Kconfig > @@ -500,4 +500,13 @@ config PWM_VT8500 > To compile this driver as a module, choose M here: the module > will be called pwm-vt8500. > > +config PWM_ZX > + tristate "ZTE ZX PWM support" > + depends on ARCH_ZX > + help > + Generic PWM framework driver for ZTE ZX family SoCs. > + > + To compile this driver as a module, choose M here: the module > + will be called pwm-zx. > + > endif > diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile > index 93da1f79a3b8..75ab74094d7b 100644 > --- a/drivers/pwm/Makefile > +++ b/drivers/pwm/Makefile > @@ -49,3 +49,4 @@ obj-$(CONFIG_PWM_TIPWMSS) += pwm-tipwmss.o > obj-$(CONFIG_PWM_TWL) += pwm-twl.o > obj-$(CONFIG_PWM_TWL_LED) += pwm-twl-led.o > obj-$(CONFIG_PWM_VT8500) += pwm-vt8500.o > +obj-$(CONFIG_PWM_ZX) += pwm-zx.o > diff --git a/drivers/pwm/pwm-zx.c b/drivers/pwm/pwm-zx.c > new file mode 100644 > index 000000000000..5c81c2ddc0a9 > --- /dev/null > +++ b/drivers/pwm/pwm-zx.c > @@ -0,0 +1,244 @@ > +/* > + * Copyright (C) 2017 Sanechips Technology Co., Ltd. > + * Copyright 2017 Linaro Ltd. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > + > +#include <linux/clk.h> > +#include <linux/err.h> > +#include <linux/io.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/platform_device.h> > +#include <linux/pwm.h> > +#include <linux/slab.h> > + > +#define ZX_PWM_MODE 0x0 > +#define ZX_PWM_CLKDIV_MASK GENMASK(11, 2) > +#define ZX_PWM_CLKDIV(x) (((x) << 8) & ZX_PWM_CLKDIV_MASK) > +#define ZX_PWM_POLAR BIT(1) > +#define ZX_PWM_EN BIT(0) > +#define ZX_PWM_PERIOD 0x4 > +#define ZX_PWM_DUTY 0x8 > + > +#define ZX_PWM_CLKDIV_MAX 1023 > +#define ZX_PWM_PERIOD_MAX 65535 > + > +struct zx_pwm_chip { > + struct pwm_chip chip; > + struct clk *pclk; > + struct clk *wclk; > + void __iomem *base; > +}; > + > +#define to_zx_pwm_chip(_chip) container_of(_chip, struct zx_pwm_chip, chip) Please use a static inline function for this. That way diagnostic messages from the compiler make more sense. [...] > +static const struct pwm_ops zx_pwm_ops = { > + .config = zx_pwm_config, > + .enable = zx_pwm_enable, > + .disable = zx_pwm_disable, > + .set_polarity = zx_pwm_set_polarity, > + .owner = THIS_MODULE, > +}; Please convert this to implement the atomic PWM callbacks (->apply() and ->get_state()). Thanks, Thierry [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 2/2] pwm: add ZTE ZX PWM device driver @ 2017-07-25 11:53 ` Thierry Reding 0 siblings, 0 replies; 12+ messages in thread From: Thierry Reding @ 2017-07-25 11:53 UTC (permalink / raw) To: linux-arm-kernel On Thu, Jun 29, 2017 at 10:54:34AM +0800, Shawn Guo wrote: > From: Shawn Guo <shawn.guo@linaro.org> > > It adds PWM device driver for ZTE ZX family SoCs. The PWM controller > supports 4 devices with polarity configuration. > > The driver has been tested with pwm-regulator support to scale core > voltage via cpufreq. > > Signed-off-by: Shawn Guo <shawn.guo@linaro.org> > --- > drivers/pwm/Kconfig | 9 ++ > drivers/pwm/Makefile | 1 + > drivers/pwm/pwm-zx.c | 244 +++++++++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 254 insertions(+) > create mode 100644 drivers/pwm/pwm-zx.c Hi Shawn, This is close to perfect. Two minor things, see below. > diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig > index 313c10789ca2..e98175331a69 100644 > --- a/drivers/pwm/Kconfig > +++ b/drivers/pwm/Kconfig > @@ -500,4 +500,13 @@ config PWM_VT8500 > To compile this driver as a module, choose M here: the module > will be called pwm-vt8500. > > +config PWM_ZX > + tristate "ZTE ZX PWM support" > + depends on ARCH_ZX > + help > + Generic PWM framework driver for ZTE ZX family SoCs. > + > + To compile this driver as a module, choose M here: the module > + will be called pwm-zx. > + > endif > diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile > index 93da1f79a3b8..75ab74094d7b 100644 > --- a/drivers/pwm/Makefile > +++ b/drivers/pwm/Makefile > @@ -49,3 +49,4 @@ obj-$(CONFIG_PWM_TIPWMSS) += pwm-tipwmss.o > obj-$(CONFIG_PWM_TWL) += pwm-twl.o > obj-$(CONFIG_PWM_TWL_LED) += pwm-twl-led.o > obj-$(CONFIG_PWM_VT8500) += pwm-vt8500.o > +obj-$(CONFIG_PWM_ZX) += pwm-zx.o > diff --git a/drivers/pwm/pwm-zx.c b/drivers/pwm/pwm-zx.c > new file mode 100644 > index 000000000000..5c81c2ddc0a9 > --- /dev/null > +++ b/drivers/pwm/pwm-zx.c > @@ -0,0 +1,244 @@ > +/* > + * Copyright (C) 2017 Sanechips Technology Co., Ltd. > + * Copyright 2017 Linaro Ltd. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > + > +#include <linux/clk.h> > +#include <linux/err.h> > +#include <linux/io.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/platform_device.h> > +#include <linux/pwm.h> > +#include <linux/slab.h> > + > +#define ZX_PWM_MODE 0x0 > +#define ZX_PWM_CLKDIV_MASK GENMASK(11, 2) > +#define ZX_PWM_CLKDIV(x) (((x) << 8) & ZX_PWM_CLKDIV_MASK) > +#define ZX_PWM_POLAR BIT(1) > +#define ZX_PWM_EN BIT(0) > +#define ZX_PWM_PERIOD 0x4 > +#define ZX_PWM_DUTY 0x8 > + > +#define ZX_PWM_CLKDIV_MAX 1023 > +#define ZX_PWM_PERIOD_MAX 65535 > + > +struct zx_pwm_chip { > + struct pwm_chip chip; > + struct clk *pclk; > + struct clk *wclk; > + void __iomem *base; > +}; > + > +#define to_zx_pwm_chip(_chip) container_of(_chip, struct zx_pwm_chip, chip) Please use a static inline function for this. That way diagnostic messages from the compiler make more sense. [...] > +static const struct pwm_ops zx_pwm_ops = { > + .config = zx_pwm_config, > + .enable = zx_pwm_enable, > + .disable = zx_pwm_disable, > + .set_polarity = zx_pwm_set_polarity, > + .owner = THIS_MODULE, > +}; Please convert this to implement the atomic PWM callbacks (->apply() and ->get_state()). Thanks, Thierry -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 833 bytes Desc: not available URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20170725/8c21e80f/attachment.sig> ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] pwm: add ZTE ZX PWM device driver 2017-07-25 11:53 ` Thierry Reding @ 2017-07-27 8:26 ` Shawn Guo -1 siblings, 0 replies; 12+ messages in thread From: Shawn Guo @ 2017-07-27 8:26 UTC (permalink / raw) To: Thierry Reding Cc: Rob Herring, Baoyou Xie, Xin Zhou, Jun Nie, linux-pwm, devicetree, linux-arm-kernel, Shawn Guo On Tue, Jul 25, 2017 at 01:53:43PM +0200, Thierry Reding wrote: > On Thu, Jun 29, 2017 at 10:54:34AM +0800, Shawn Guo wrote: > > From: Shawn Guo <shawn.guo@linaro.org> > > > > It adds PWM device driver for ZTE ZX family SoCs. The PWM controller > > supports 4 devices with polarity configuration. > > > > The driver has been tested with pwm-regulator support to scale core > > voltage via cpufreq. > > > > Signed-off-by: Shawn Guo <shawn.guo@linaro.org> > > --- > > drivers/pwm/Kconfig | 9 ++ > > drivers/pwm/Makefile | 1 + > > drivers/pwm/pwm-zx.c | 244 +++++++++++++++++++++++++++++++++++++++++++++++++++ > > 3 files changed, 254 insertions(+) > > create mode 100644 drivers/pwm/pwm-zx.c > > Hi Shawn, > > This is close to perfect. Two minor things, see below. Hi Thierry, Thanks for helping review the patch. I just send out v2 to address your comments. Shawn ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 2/2] pwm: add ZTE ZX PWM device driver @ 2017-07-27 8:26 ` Shawn Guo 0 siblings, 0 replies; 12+ messages in thread From: Shawn Guo @ 2017-07-27 8:26 UTC (permalink / raw) To: linux-arm-kernel On Tue, Jul 25, 2017 at 01:53:43PM +0200, Thierry Reding wrote: > On Thu, Jun 29, 2017 at 10:54:34AM +0800, Shawn Guo wrote: > > From: Shawn Guo <shawn.guo@linaro.org> > > > > It adds PWM device driver for ZTE ZX family SoCs. The PWM controller > > supports 4 devices with polarity configuration. > > > > The driver has been tested with pwm-regulator support to scale core > > voltage via cpufreq. > > > > Signed-off-by: Shawn Guo <shawn.guo@linaro.org> > > --- > > drivers/pwm/Kconfig | 9 ++ > > drivers/pwm/Makefile | 1 + > > drivers/pwm/pwm-zx.c | 244 +++++++++++++++++++++++++++++++++++++++++++++++++++ > > 3 files changed, 254 insertions(+) > > create mode 100644 drivers/pwm/pwm-zx.c > > Hi Shawn, > > This is close to perfect. Two minor things, see below. Hi Thierry, Thanks for helping review the patch. I just send out v2 to address your comments. Shawn ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2017-07-27 8:26 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
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2017-06-29 2:54 [PATCH 0/2] Add ZTE ZX PWM device driver support Shawn Guo
2017-06-29 2:54 ` Shawn Guo
2017-06-29 2:54 ` [PATCH 1/2] dt-bindings: pwm: add bindings doc for ZTE ZX PWM controller Shawn Guo
2017-06-29 2:54 ` Shawn Guo
[not found] ` <1498704874-14599-2-git-send-email-shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
2017-07-06 14:57 ` Rob Herring
2017-07-06 14:57 ` Rob Herring
[not found] ` <1498704874-14599-1-git-send-email-shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
2017-06-29 2:54 ` [PATCH 2/2] pwm: add ZTE ZX PWM device driver Shawn Guo
2017-06-29 2:54 ` Shawn Guo
2017-07-25 11:53 ` Thierry Reding
2017-07-25 11:53 ` Thierry Reding
2017-07-27 8:26 ` Shawn Guo
2017-07-27 8:26 ` Shawn Guo
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