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From: ard.biesheuvel@linaro.org (Ard Biesheuvel)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC PATCH 03/10] arm64: crypto: avoid register x18 in scalar AES code
Date: Wed, 12 Jul 2017 15:44:16 +0100	[thread overview]
Message-ID: <20170712144424.19528-4-ard.biesheuvel@linaro.org> (raw)
In-Reply-To: <20170712144424.19528-1-ard.biesheuvel@linaro.org>

Register x18 is the platform register, and is not unconditionally
classified as a caller save register by the AAPCS64 ABI. So avoid
using it in our AES assembler code, to allow the kernel to use it
as a task_struct pointer.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 arch/arm64/crypto/aes-cipher-core.S | 55 ++++++++++----------
 1 file changed, 28 insertions(+), 27 deletions(-)

diff --git a/arch/arm64/crypto/aes-cipher-core.S b/arch/arm64/crypto/aes-cipher-core.S
index f2f9cc519309..62c91b9fcd56 100644
--- a/arch/arm64/crypto/aes-cipher-core.S
+++ b/arch/arm64/crypto/aes-cipher-core.S
@@ -17,8 +17,7 @@
 	out		.req	x1
 	in		.req	x2
 	rounds		.req	x3
-	tt		.req	x4
-	lt		.req	x2
+	tt		.req	x2
 
 	.macro		__pair, enc, reg0, reg1, in0, in1e, in1d, shift
 	ubfx		\reg0, \in0, #\shift, #8
@@ -34,17 +33,17 @@
 	.macro		__hround, out0, out1, in0, in1, in2, in3, t0, t1, enc
 	ldp		\out0, \out1, [rk], #8
 
-	__pair		\enc, w13, w14, \in0, \in1, \in3, 0
-	__pair		\enc, w15, w16, \in1, \in2, \in0, 8
-	__pair		\enc, w17, w18, \in2, \in3, \in1, 16
+	__pair		\enc, w12, w13, \in0, \in1, \in3, 0
+	__pair		\enc, w14, w15, \in1, \in2, \in0, 8
+	__pair		\enc, w16, w17, \in2, \in3, \in1, 16
 	__pair		\enc, \t0, \t1, \in3, \in0, \in2, 24
 
-	eor		\out0, \out0, w13
-	eor		\out1, \out1, w14
-	eor		\out0, \out0, w15, ror #24
-	eor		\out1, \out1, w16, ror #24
-	eor		\out0, \out0, w17, ror #16
-	eor		\out1, \out1, w18, ror #16
+	eor		\out0, \out0, w12
+	eor		\out1, \out1, w13
+	eor		\out0, \out0, w14, ror #24
+	eor		\out1, \out1, w15, ror #24
+	eor		\out0, \out0, w16, ror #16
+	eor		\out1, \out1, w17, ror #16
 	eor		\out0, \out0, \t0, ror #8
 	eor		\out1, \out1, \t1, ror #8
 	.endm
@@ -60,42 +59,44 @@
 	.endm
 
 	.macro		do_crypt, round, ttab, ltab
-	ldp		w5, w6, [in]
-	ldp		w7, w8, [in, #8]
-	ldp		w9, w10, [rk], #16
-	ldp		w11, w12, [rk, #-8]
+	ldp		w4, w5, [in]
+	ldp		w6, w7, [in, #8]
+	ldp		w8, w9, [rk], #16
+	ldp		w10, w11, [rk, #-8]
 
+CPU_BE(	rev		w4, w4		)
 CPU_BE(	rev		w5, w5		)
 CPU_BE(	rev		w6, w6		)
 CPU_BE(	rev		w7, w7		)
-CPU_BE(	rev		w8, w8		)
 
+	eor		w4, w4, w8
 	eor		w5, w5, w9
 	eor		w6, w6, w10
 	eor		w7, w7, w11
-	eor		w8, w8, w12
 
 	adr_l		tt, \ttab
-	adr_l		lt, \ltab
 
 	tbnz		rounds, #1, 1f
 
-0:	\round		w9, w10, w11, w12, w5, w6, w7, w8
-	\round		w5, w6, w7, w8, w9, w10, w11, w12
+0:	\round		w8, w9, w10, w11, w4, w5, w6, w7
+	\round		w4, w5, w6, w7, w8, w9, w10, w11
 
 1:	subs		rounds, rounds, #4
-	\round		w9, w10, w11, w12, w5, w6, w7, w8
-	csel		tt, tt, lt, hi
-	\round		w5, w6, w7, w8, w9, w10, w11, w12
-	b.hi		0b
+	\round		w8, w9, w10, w11, w4, w5, w6, w7
+	b.ls		2f
+	\round		w4, w5, w6, w7, w8, w9, w10, w11
+	b		0b
 
+2:	adr_l		tt, \ltab
+	\round		w4, w5, w6, w7, w8, w9, w10, w11
+
+CPU_BE(	rev		w4, w4		)
 CPU_BE(	rev		w5, w5		)
 CPU_BE(	rev		w6, w6		)
 CPU_BE(	rev		w7, w7		)
-CPU_BE(	rev		w8, w8		)
 
-	stp		w5, w6, [out]
-	stp		w7, w8, [out, #8]
+	stp		w4, w5, [out]
+	stp		w6, w7, [out, #8]
 	ret
 	.endm
 
-- 
2.9.3

WARNING: multiple messages have this Message-ID (diff)
From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
To: linux-arm-kernel@lists.infradead.org,
	kernel-hardening@lists.openwall.com
Cc: mark.rutland@arm.com, labbott@fedoraproject.org,
	will.deacon@arm.com, dave.martin@arm.com,
	catalin.marinas@arm.com,
	Ard Biesheuvel <ard.biesheuvel@linaro.org>
Subject: [kernel-hardening] [RFC PATCH 03/10] arm64: crypto: avoid register x18 in scalar AES code
Date: Wed, 12 Jul 2017 15:44:16 +0100	[thread overview]
Message-ID: <20170712144424.19528-4-ard.biesheuvel@linaro.org> (raw)
In-Reply-To: <20170712144424.19528-1-ard.biesheuvel@linaro.org>

Register x18 is the platform register, and is not unconditionally
classified as a caller save register by the AAPCS64 ABI. So avoid
using it in our AES assembler code, to allow the kernel to use it
as a task_struct pointer.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 arch/arm64/crypto/aes-cipher-core.S | 55 ++++++++++----------
 1 file changed, 28 insertions(+), 27 deletions(-)

diff --git a/arch/arm64/crypto/aes-cipher-core.S b/arch/arm64/crypto/aes-cipher-core.S
index f2f9cc519309..62c91b9fcd56 100644
--- a/arch/arm64/crypto/aes-cipher-core.S
+++ b/arch/arm64/crypto/aes-cipher-core.S
@@ -17,8 +17,7 @@
 	out		.req	x1
 	in		.req	x2
 	rounds		.req	x3
-	tt		.req	x4
-	lt		.req	x2
+	tt		.req	x2
 
 	.macro		__pair, enc, reg0, reg1, in0, in1e, in1d, shift
 	ubfx		\reg0, \in0, #\shift, #8
@@ -34,17 +33,17 @@
 	.macro		__hround, out0, out1, in0, in1, in2, in3, t0, t1, enc
 	ldp		\out0, \out1, [rk], #8
 
-	__pair		\enc, w13, w14, \in0, \in1, \in3, 0
-	__pair		\enc, w15, w16, \in1, \in2, \in0, 8
-	__pair		\enc, w17, w18, \in2, \in3, \in1, 16
+	__pair		\enc, w12, w13, \in0, \in1, \in3, 0
+	__pair		\enc, w14, w15, \in1, \in2, \in0, 8
+	__pair		\enc, w16, w17, \in2, \in3, \in1, 16
 	__pair		\enc, \t0, \t1, \in3, \in0, \in2, 24
 
-	eor		\out0, \out0, w13
-	eor		\out1, \out1, w14
-	eor		\out0, \out0, w15, ror #24
-	eor		\out1, \out1, w16, ror #24
-	eor		\out0, \out0, w17, ror #16
-	eor		\out1, \out1, w18, ror #16
+	eor		\out0, \out0, w12
+	eor		\out1, \out1, w13
+	eor		\out0, \out0, w14, ror #24
+	eor		\out1, \out1, w15, ror #24
+	eor		\out0, \out0, w16, ror #16
+	eor		\out1, \out1, w17, ror #16
 	eor		\out0, \out0, \t0, ror #8
 	eor		\out1, \out1, \t1, ror #8
 	.endm
@@ -60,42 +59,44 @@
 	.endm
 
 	.macro		do_crypt, round, ttab, ltab
-	ldp		w5, w6, [in]
-	ldp		w7, w8, [in, #8]
-	ldp		w9, w10, [rk], #16
-	ldp		w11, w12, [rk, #-8]
+	ldp		w4, w5, [in]
+	ldp		w6, w7, [in, #8]
+	ldp		w8, w9, [rk], #16
+	ldp		w10, w11, [rk, #-8]
 
+CPU_BE(	rev		w4, w4		)
 CPU_BE(	rev		w5, w5		)
 CPU_BE(	rev		w6, w6		)
 CPU_BE(	rev		w7, w7		)
-CPU_BE(	rev		w8, w8		)
 
+	eor		w4, w4, w8
 	eor		w5, w5, w9
 	eor		w6, w6, w10
 	eor		w7, w7, w11
-	eor		w8, w8, w12
 
 	adr_l		tt, \ttab
-	adr_l		lt, \ltab
 
 	tbnz		rounds, #1, 1f
 
-0:	\round		w9, w10, w11, w12, w5, w6, w7, w8
-	\round		w5, w6, w7, w8, w9, w10, w11, w12
+0:	\round		w8, w9, w10, w11, w4, w5, w6, w7
+	\round		w4, w5, w6, w7, w8, w9, w10, w11
 
 1:	subs		rounds, rounds, #4
-	\round		w9, w10, w11, w12, w5, w6, w7, w8
-	csel		tt, tt, lt, hi
-	\round		w5, w6, w7, w8, w9, w10, w11, w12
-	b.hi		0b
+	\round		w8, w9, w10, w11, w4, w5, w6, w7
+	b.ls		2f
+	\round		w4, w5, w6, w7, w8, w9, w10, w11
+	b		0b
 
+2:	adr_l		tt, \ltab
+	\round		w4, w5, w6, w7, w8, w9, w10, w11
+
+CPU_BE(	rev		w4, w4		)
 CPU_BE(	rev		w5, w5		)
 CPU_BE(	rev		w6, w6		)
 CPU_BE(	rev		w7, w7		)
-CPU_BE(	rev		w8, w8		)
 
-	stp		w5, w6, [out]
-	stp		w7, w8, [out, #8]
+	stp		w4, w5, [out]
+	stp		w6, w7, [out, #8]
 	ret
 	.endm
 
-- 
2.9.3

  parent reply	other threads:[~2017-07-12 14:44 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-07-12 14:44 [RFC PATCH 00/10] arm64: allow virtually mapped stacks to be enabled Ard Biesheuvel
2017-07-12 14:44 ` [kernel-hardening] " Ard Biesheuvel
2017-07-12 14:44 ` [RFC PATCH 01/10] arm64/lib: copy_page: use consistent prefetch stride Ard Biesheuvel
2017-07-12 14:44   ` [kernel-hardening] " Ard Biesheuvel
2017-07-12 14:44 ` [RFC PATCH 02/10] arm64/lib: copy_page: avoid x18 register in assembler code Ard Biesheuvel
2017-07-12 14:44   ` [kernel-hardening] " Ard Biesheuvel
2017-07-12 14:44 ` Ard Biesheuvel [this message]
2017-07-12 14:44   ` [kernel-hardening] [RFC PATCH 03/10] arm64: crypto: avoid register x18 in scalar AES code Ard Biesheuvel
2017-07-12 14:44 ` [RFC PATCH 04/10] arm64: kvm: stop treating register x18 as caller save Ard Biesheuvel
2017-07-12 14:44   ` [kernel-hardening] " Ard Biesheuvel
2017-07-12 14:44 ` [RFC PATCH 05/10] arm64: kernel: avoid x18 as an arbitrary temp register Ard Biesheuvel
2017-07-12 14:44   ` [kernel-hardening] " Ard Biesheuvel
2017-07-12 14:44 ` [RFC PATCH 06/10] arm64: kbuild: reserve reg x18 from general allocation by the compiler Ard Biesheuvel
2017-07-12 14:44   ` [kernel-hardening] " Ard Biesheuvel
2017-07-12 14:44 ` [RFC PATCH 07/10] arm64: kernel: switch to register x18 as a task struct pointer Ard Biesheuvel
2017-07-12 14:44   ` [kernel-hardening] " Ard Biesheuvel
2017-07-13 10:41   ` Dave Martin
2017-07-13 10:41     ` [kernel-hardening] " Dave Martin
2017-07-13 12:27     ` Ard Biesheuvel
2017-07-13 12:27       ` [kernel-hardening] " Ard Biesheuvel
2017-07-13 14:11       ` Dave Martin
2017-07-13 14:11         ` [kernel-hardening] " Dave Martin
2017-07-12 14:44 ` [RFC PATCH 08/10] arm64/kernel: dump entire stack if sp points elsewhere Ard Biesheuvel
2017-07-12 14:44   ` [kernel-hardening] " Ard Biesheuvel
2017-07-12 14:44 ` [RFC PATCH 09/10] arm64: mm: add C level handling for stack overflows Ard Biesheuvel
2017-07-12 14:44   ` [kernel-hardening] " Ard Biesheuvel
2017-07-12 14:44 ` [RFC PATCH 10/10] arm64: kernel: add support for virtually mapped stacks Ard Biesheuvel
2017-07-12 14:44   ` [kernel-hardening] " Ard Biesheuvel
2017-07-12 22:59   ` Mark Rutland
2017-07-12 22:59     ` [kernel-hardening] " Mark Rutland
2017-07-13  9:12     ` Mark Rutland
2017-07-13  9:12       ` Mark Rutland
2017-07-13 10:35   ` Dave Martin
2017-07-13 10:35     ` [kernel-hardening] " Dave Martin
2017-07-12 20:12 ` [RFC PATCH 00/10] arm64: allow virtually mapped stacks to be enabled Laura Abbott
2017-07-12 20:12   ` [kernel-hardening] " Laura Abbott
2017-07-12 20:49   ` Ard Biesheuvel
2017-07-12 20:49     ` [kernel-hardening] " Ard Biesheuvel
2017-07-12 21:32     ` Andy Lutomirski
2017-07-12 21:32       ` [kernel-hardening] " Andy Lutomirski
2017-07-12 22:47 ` Mark Rutland
2017-07-12 22:47   ` [kernel-hardening] " Mark Rutland
2017-07-13  6:51   ` Ard Biesheuvel
2017-07-13  6:51     ` [kernel-hardening] " Ard Biesheuvel

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