From: Joerg Roedel <joro@8bytes.org> To: "Tian, Kevin" <kevin.tian@intel.com> Cc: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>, Jacob Pan <jacob.jun.pan@linux.intel.com>, "Lan, Tianyu" <tianyu.lan@intel.com>, "Liu, Yi L" <yi.l.liu@linux.intel.com>, LKML <linux-kernel@vger.kernel.org>, "iommu@lists.linux-foundation.org" <iommu@lists.linux-foundation.org>, Jean Delvare <khali@linux-fr.org>, David Woodhouse <dwmw2@infradead.org> Subject: Re: [PATCH 3/9] iommu: Introduce iommu do invalidate API function Date: Wed, 26 Jul 2017 11:02:40 +0200 [thread overview] Message-ID: <20170726090240.GD30429@8bytes.org> (raw) In-Reply-To: <AADFC41AFE54684AB9EE6CBC0274A5D190D25CCB@SHSMSX101.ccr.corp.intel.com> On Wed, Jul 05, 2017 at 07:57:57AM +0000, Tian, Kevin wrote: > > > struct tlb_invalidate_info > > > { > > > __u32 model; /* Vendor number */ I don't like to have a model-specifier here, as I don't think its needed. > > > __u8 granularity > > > #define DEVICE_SELECTVIE_INV (1 << 0) > > > #define PAGE_SELECTIVE_INV (1 << 0) > > > #define PASID_SELECTIVE_INV (1 << 1) > > > __u32 pasid; > > > __u64 addr; > > > __u64 size; > > > > > > /* Since IOMMU format has already been validated for this table, > > > the IOMMU driver knows that the following structure is in a > > > format it knows */ > > > __u8 opaque[]; > > > }; > > > > > I just gave some information in another thread: > > https://lists.gnu.org/archive/html/qemu-devel/2017-07/msg00853.html > > Below summarizes all the invalidation capabilities supported by Intel VTd: > > Scope: All PASIDs, single PASID > for each PASID: > all mappings, or page-selective mappings (addr, size) > invalidation target: > IOTLB entries (leaf) > paging structure cache (non-leaf) > PASID cache (pasid->cr3) > invalidation hint: > whether global pages are included > drain reads/writes The AMD IOMMU for example supports similar flushing capabilities. They are all based on a IOMMU-independent PCI standards (PASID, PRI, ATS), and the interface can be designed around those standards instead of IOMMU hardware implementations. If a given hardware implementation does not support all of the above flushing modes, it is always free to flush more than requested as supported by its capabilities. Regards, Joerg
WARNING: multiple messages have this Message-ID (diff)
From: Joerg Roedel <joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org> To: "Tian, Kevin" <kevin.tian-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> Cc: "Lan, Tianyu" <tianyu.lan-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>, "Liu, Yi L" <yi.l.liu-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>, LKML <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>, "iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org" <iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org>, Jean Delvare <khali-PUYAD+kWke1g9hUCZPvPmw@public.gmane.org>, David Woodhouse <dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org> Subject: Re: [PATCH 3/9] iommu: Introduce iommu do invalidate API function Date: Wed, 26 Jul 2017 11:02:40 +0200 [thread overview] Message-ID: <20170726090240.GD30429@8bytes.org> (raw) In-Reply-To: <AADFC41AFE54684AB9EE6CBC0274A5D190D25CCB-0J0gbvR4kThpB2pF5aRoyrfspsVTdybXVpNB7YpNyf8@public.gmane.org> On Wed, Jul 05, 2017 at 07:57:57AM +0000, Tian, Kevin wrote: > > > struct tlb_invalidate_info > > > { > > > __u32 model; /* Vendor number */ I don't like to have a model-specifier here, as I don't think its needed. > > > __u8 granularity > > > #define DEVICE_SELECTVIE_INV (1 << 0) > > > #define PAGE_SELECTIVE_INV (1 << 0) > > > #define PASID_SELECTIVE_INV (1 << 1) > > > __u32 pasid; > > > __u64 addr; > > > __u64 size; > > > > > > /* Since IOMMU format has already been validated for this table, > > > the IOMMU driver knows that the following structure is in a > > > format it knows */ > > > __u8 opaque[]; > > > }; > > > > > I just gave some information in another thread: > > https://lists.gnu.org/archive/html/qemu-devel/2017-07/msg00853.html > > Below summarizes all the invalidation capabilities supported by Intel VTd: > > Scope: All PASIDs, single PASID > for each PASID: > all mappings, or page-selective mappings (addr, size) > invalidation target: > IOTLB entries (leaf) > paging structure cache (non-leaf) > PASID cache (pasid->cr3) > invalidation hint: > whether global pages are included > drain reads/writes The AMD IOMMU for example supports similar flushing capabilities. They are all based on a IOMMU-independent PCI standards (PASID, PRI, ATS), and the interface can be designed around those standards instead of IOMMU hardware implementations. If a given hardware implementation does not support all of the above flushing modes, it is always free to flush more than requested as supported by its capabilities. Regards, Joerg
next prev parent reply other threads:[~2017-07-26 9:03 UTC|newest] Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-06-27 19:47 [RFC 0/9] IOMMU driver support for shared virtual memory virtualization Jacob Pan 2017-06-27 19:47 ` Jacob Pan 2017-06-27 19:47 ` [PATCH 1/9] iommu: Introduce bind_pasid_table API function Jacob Pan 2017-06-28 9:57 ` Joerg Roedel 2017-06-28 9:57 ` Joerg Roedel 2017-06-27 19:47 ` [PATCH 2/9] iommu/vt-d: add bind_pasid_table function Jacob Pan 2017-06-27 19:47 ` Jacob Pan 2017-06-28 10:02 ` Joerg Roedel 2017-06-28 10:02 ` Joerg Roedel 2017-07-05 7:38 ` Tian, Kevin 2017-07-05 7:38 ` Tian, Kevin 2017-06-27 19:47 ` [PATCH 3/9] iommu: Introduce iommu do invalidate API function Jacob Pan 2017-06-28 10:08 ` Joerg Roedel 2017-06-28 16:09 ` Jacob Pan 2017-06-28 16:09 ` Jacob Pan 2017-06-28 17:07 ` Jean-Philippe Brucker 2017-06-28 17:07 ` Jean-Philippe Brucker 2017-07-05 7:57 ` Tian, Kevin 2017-07-05 7:57 ` Tian, Kevin 2017-07-05 12:42 ` Jean-Philippe Brucker 2017-07-05 12:42 ` Jean-Philippe Brucker 2017-07-26 9:02 ` Joerg Roedel [this message] 2017-07-26 9:02 ` Joerg Roedel 2017-06-27 19:47 ` [PATCH 4/9] iommu/vt-d: Add iommu do invalidate function Jacob Pan 2017-06-27 19:47 ` [PATCH 5/9] iommu: Introduce fault notifier API Jacob Pan 2017-06-28 10:16 ` Joerg Roedel 2017-06-28 10:16 ` Joerg Roedel 2017-06-28 16:16 ` Jacob Pan 2017-06-28 16:16 ` Jacob Pan 2017-06-27 19:48 ` [PATCH 6/9] iommu/vt-d: track device with pasid table bond to a guest Jacob Pan 2017-06-27 19:48 ` [PATCH 7/9] iommu/dmar: notify unrecoverable faults Jacob Pan 2017-06-27 19:48 ` [PATCH 8/9] iommu/intel-svm: notify page request to guest Jacob Pan 2017-06-27 19:48 ` [PATCH 9/9] iommu/intel-svm: replace dev ops with generic fault notifier Jacob Pan 2017-08-16 9:44 ` [RFC 0/9] IOMMU driver support for shared virtual memory virtualization Joerg Roedel 2017-08-16 9:44 ` Joerg Roedel 2017-08-16 15:14 ` Jacob Pan 2017-08-16 15:14 ` Jacob Pan 2017-08-16 16:23 ` Joerg Roedel
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