[PATCH] drm/amdgpu: Fix undue fallthroughs in golden registers initialization

[PATCH] drm/amdgpu: Fix undue fallthroughs in golden registers initialization

[Jean Delvare]

As I was staring at the si_init_golden_registers code, I noticed that
the Pitcairn initialization silently falls through the Cape Verde
initialization, and the Oland initialization falls through the Hainan
initialization. However there is no comment stating that this is
intentional, and the radeon driver doesn't have any such fallthrough,
so I suspect this is not supposed to happen.

Signed-off-by: Jean Delvare <jdelvare@suse.de>
Fixes: 62a37553414a ("drm/amdgpu: add si implementation v10")
Cc: Ken Wang <Qingqing.Wang@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Marek Olšák" <maraeo@gmail.com>
Cc: "Christian König" <christian.koenig@amd.com>
Cc: Flora Cui <Flora.Cui@amd.com>
---
If the fallthroughs are really supposed to happen, comments should be
added that say so. Surprisingly it doesn't seem to make any
difference on my Oland card.

 drivers/gpu/drm/amd/amdgpu/si.c |    2 ++
 1 file changed, 2 insertions(+)

--- linux-4.12.orig/drivers/gpu/drm/amd/amdgpu/si.c	2017-07-30 09:25:46.891083334 +0200
+++ linux-4.12/drivers/gpu/drm/amd/amdgpu/si.c	2017-07-30 09:45:24.350188642 +0200
@@ -1385,6 +1385,7 @@ static void si_init_golden_registers(str
 		amdgpu_program_register_sequence(adev,
 						 pitcairn_mgcg_cgcg_init,
 						 (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
+		break;
 	case CHIP_VERDE:
 		amdgpu_program_register_sequence(adev,
 						 verde_golden_registers,
@@ -1409,6 +1410,7 @@ static void si_init_golden_registers(str
 		amdgpu_program_register_sequence(adev,
 						 oland_mgcg_cgcg_init,
 						 (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
+		break;
 	case CHIP_HAINAN:
 		amdgpu_program_register_sequence(adev,
 						 hainan_golden_registers,


-- 
Jean Delvare
SUSE L3 Support
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Re: [PATCH] drm/amdgpu: Fix undue fallthroughs in golden registers initialization

[Marek Olšák]

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Reviewed-by: Marek Olšák <marek.olsak-5C7GfCeVMHo@public.gmane.org>

Marek

On Sun, Jul 30, 2017 at 10:18 AM, Jean Delvare <jdelvare-l3A5Bk7waGM@public.gmane.org> wrote:

> As I was staring at the si_init_golden_registers code, I noticed that
> the Pitcairn initialization silently falls through the Cape Verde
> initialization, and the Oland initialization falls through the Hainan
> initialization. However there is no comment stating that this is
> intentional, and the radeon driver doesn't have any such fallthrough,
> so I suspect this is not supposed to happen.
>
> Signed-off-by: Jean Delvare <jdelvare-l3A5Bk7waGM@public.gmane.org>
> Fixes: 62a37553414a ("drm/amdgpu: add si implementation v10")
> Cc: Ken Wang <Qingqing.Wang-5C7GfCeVMHo@public.gmane.org>
> Cc: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>
> Cc: "Marek Olšák" <maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: "Christian König" <christian.koenig-5C7GfCeVMHo@public.gmane.org>
> Cc: Flora Cui <Flora.Cui-5C7GfCeVMHo@public.gmane.org>
> ---
> If the fallthroughs are really supposed to happen, comments should be
> added that say so. Surprisingly it doesn't seem to make any
> difference on my Oland card.
>
>  drivers/gpu/drm/amd/amdgpu/si.c |    2 ++
>  1 file changed, 2 insertions(+)
>
> --- linux-4.12.orig/drivers/gpu/drm/amd/amdgpu/si.c     2017-07-30
> 09:25:46.891083334 +0200
> +++ linux-4.12/drivers/gpu/drm/amd/amdgpu/si.c  2017-07-30
> 09:45:24.350188642 +0200
> @@ -1385,6 +1385,7 @@ static void si_init_golden_registers(str
>                 amdgpu_program_register_sequence(adev,
>                                                  pitcairn_mgcg_cgcg_init,
>                                                  (const
> u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
> +               break;
>         case CHIP_VERDE:
>                 amdgpu_program_register_sequence(adev,
>                                                  verde_golden_registers,
> @@ -1409,6 +1410,7 @@ static void si_init_golden_registers(str
>                 amdgpu_program_register_sequence(adev,
>                                                  oland_mgcg_cgcg_init,
>                                                  (const
> u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
> +               break;
>         case CHIP_HAINAN:
>                 amdgpu_program_register_sequence(adev,
>                                                  hainan_golden_registers,
>
>
> --
> Jean Delvare
> SUSE L3 Support
>

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Re: [PATCH] drm/amdgpu: Fix undue fallthroughs in golden registers initialization

[Alex Deucher]

On Sun, Jul 30, 2017 at 9:07 PM, Marek Olšák <maraeo@gmail.com> wrote:
> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
>
> Marek
>
> On Sun, Jul 30, 2017 at 10:18 AM, Jean Delvare <jdelvare@suse.de> wrote:
>>
>> As I was staring at the si_init_golden_registers code, I noticed that
>> the Pitcairn initialization silently falls through the Cape Verde
>> initialization, and the Oland initialization falls through the Hainan
>> initialization. However there is no comment stating that this is
>> intentional, and the radeon driver doesn't have any such fallthrough,
>> so I suspect this is not supposed to happen.
>>
>> Signed-off-by: Jean Delvare <jdelvare@suse.de>
>> Fixes: 62a37553414a ("drm/amdgpu: add si implementation v10")
>> Cc: Ken Wang <Qingqing.Wang@amd.com>
>> Cc: Alex Deucher <alexander.deucher@amd.com>
>> Cc: "Marek Olšák" <maraeo@gmail.com>
>> Cc: "Christian König" <christian.koenig@amd.com>
>> Cc: Flora Cui <Flora.Cui@amd.com>

Applied.  thanks!

Alex


>> ---
>> If the fallthroughs are really supposed to happen, comments should be
>> added that say so. Surprisingly it doesn't seem to make any
>> difference on my Oland card.
>>
>>  drivers/gpu/drm/amd/amdgpu/si.c |    2 ++
>>  1 file changed, 2 insertions(+)
>>
>> --- linux-4.12.orig/drivers/gpu/drm/amd/amdgpu/si.c     2017-07-30
>> 09:25:46.891083334 +0200
>> +++ linux-4.12/drivers/gpu/drm/amd/amdgpu/si.c  2017-07-30
>> 09:45:24.350188642 +0200
>> @@ -1385,6 +1385,7 @@ static void si_init_golden_registers(str
>>                 amdgpu_program_register_sequence(adev,
>>                                                  pitcairn_mgcg_cgcg_init,
>>                                                  (const
>> u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
>> +               break;
>>         case CHIP_VERDE:
>>                 amdgpu_program_register_sequence(adev,
>>                                                  verde_golden_registers,
>> @@ -1409,6 +1410,7 @@ static void si_init_golden_registers(str
>>                 amdgpu_program_register_sequence(adev,
>>                                                  oland_mgcg_cgcg_init,
>>                                                  (const
>> u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
>> +               break;
>>         case CHIP_HAINAN:
>>                 amdgpu_program_register_sequence(adev,
>>                                                  hainan_golden_registers,
>>
>>
>> --
>> Jean Delvare
>> SUSE L3 Support
>
>
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
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