* [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers
@ 2017-07-06 6:33 Zhiqiang Hou
2017-07-06 6:33 ` [PATCH 2/3] PCI: designware: enable write permission before updating class code Zhiqiang Hou
` (2 more replies)
0 siblings, 3 replies; 13+ messages in thread
From: Zhiqiang Hou @ 2017-07-06 6:33 UTC (permalink / raw)
To: linux-pci, bhelgaas, jingoohan1, Joao.Pinto; +Cc: Hou Zhiqiang
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
The read-only DBI registers can be written over the DBI when set
the "Write to RO Registers Using DBI" (DBI_RO_WR_EN) field of the
MISC_CONTROL_1_OFF register.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
drivers/pci/dwc/pcie-designware.h | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index b4d2a89..bbdf35b 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -76,6 +76,9 @@
#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
#define PCIE_ATU_UPPER_TARGET 0x91C
+#define PCIE_MISC_CONTROL_1_OFF 0x8BC
+#define PCIE_DBI_RO_WR_EN (0x1 << 0)
+
/*
* iATU Unroll-specific register definitions
* From 4.80 core version the address translation will be made by unroll
@@ -279,6 +282,28 @@ static inline u32 dw_pcie_readl_dbi2(struct dw_pcie *pci, u32 reg)
return __dw_pcie_read_dbi(pci, pci->dbi_base2, reg, 0x4);
}
+static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci)
+{
+ u32 reg;
+ u32 val;
+
+ reg = PCIE_MISC_CONTROL_1_OFF;
+ val = dw_pcie_readl_dbi(pci, reg);
+ val |= PCIE_DBI_RO_WR_EN;
+ dw_pcie_writel_dbi(pci, reg, val);
+}
+
+static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci)
+{
+ u32 reg;
+ u32 val;
+
+ reg = PCIE_MISC_CONTROL_1_OFF;
+ val = dw_pcie_readl_dbi(pci, reg);
+ val &= ~PCIE_DBI_RO_WR_EN;
+ dw_pcie_writel_dbi(pci, reg, val);
+}
+
#ifdef CONFIG_PCIE_DW_HOST
irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
void dw_pcie_msi_init(struct pcie_port *pp);
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/3] PCI: designware: enable write permission before updating class code
2017-07-06 6:33 [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers Zhiqiang Hou
@ 2017-07-06 6:33 ` Zhiqiang Hou
2017-07-06 6:33 ` [PATCH 3/3] PCI: layerscape: refactor the host_init function Zhiqiang Hou
2017-07-06 9:44 ` [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers Joao Pinto
2 siblings, 0 replies; 13+ messages in thread
From: Zhiqiang Hou @ 2017-07-06 6:33 UTC (permalink / raw)
To: linux-pci, bhelgaas, jingoohan1, Joao.Pinto; +Cc: Hou Zhiqiang
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
drivers/pci/dwc/pcie-designware-host.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
index d29c020..6e10cda 100644
--- a/drivers/pci/dwc/pcie-designware-host.c
+++ b/drivers/pci/dwc/pcie-designware-host.c
@@ -634,8 +634,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
+ /* Enable write permission for the DBI read-only register */
+ dw_pcie_dbi_ro_wr_en(pci);
/* program correct class for RC */
dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
+ /* Better disable write permission right after the update */
+ dw_pcie_dbi_ro_wr_dis(pci);
dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
val |= PORT_LOGIC_SPEED_CHANGE;
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 3/3] PCI: layerscape: refactor the host_init function
2017-07-06 6:33 [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers Zhiqiang Hou
2017-07-06 6:33 ` [PATCH 2/3] PCI: designware: enable write permission before updating class code Zhiqiang Hou
@ 2017-07-06 6:33 ` Zhiqiang Hou
2017-08-02 21:11 ` Bjorn Helgaas
2017-07-06 9:44 ` [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers Joao Pinto
2 siblings, 1 reply; 13+ messages in thread
From: Zhiqiang Hou @ 2017-07-06 6:33 UTC (permalink / raw)
To: linux-pci, bhelgaas, jingoohan1, Joao.Pinto; +Cc: Hou Zhiqiang, Minghuan Lian
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Main changes:
- Make the ls1021a's host_init reuse layerscape platform's common
host_init function.
- Will not use the outbound windows configured by bootloader, but
introduce DWC common setup function dw_pcie_setup_rc and disable
the bootloader configured outbound windows. And remove the duplicate
class field fix code.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
---
drivers/pci/dwc/pci-layerscape.c | 85 ++++++++++++++++++++++------------------
1 file changed, 46 insertions(+), 39 deletions(-)
diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
index fd86128..9bed3cd 100644
--- a/drivers/pci/dwc/pci-layerscape.c
+++ b/drivers/pci/dwc/pci-layerscape.c
@@ -33,7 +33,8 @@
/* PEX Internal Configuration Registers */
#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
-#define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */
+
+#define PCIE_IATU_NUM 6
struct ls_pcie_drvdata {
u32 lut_offset;
@@ -69,15 +70,9 @@ static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
{
struct dw_pcie *pci = pcie->pci;
+ dw_pcie_dbi_ro_wr_en(pci);
iowrite8(PCI_HEADER_TYPE_BRIDGE, pci->dbi_base + PCI_HEADER_TYPE);
-}
-
-/* Fix class value */
-static void ls_pcie_fix_class(struct ls_pcie *pcie)
-{
- struct dw_pcie *pci = pcie->pci;
-
- iowrite16(PCI_CLASS_BRIDGE_PCI, pci->dbi_base + PCI_CLASS_DEVICE);
+ dw_pcie_dbi_ro_wr_dis(pci);
}
/* Drop MSG TLP except for Vendor MSG */
@@ -91,6 +86,14 @@ static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
iowrite32(val, pci->dbi_base + PCIE_STRFMR1);
}
+static void ls_pcie_disable_outbound_atus(struct ls_pcie *pcie)
+{
+ int i;
+
+ for (i = 0; i < PCIE_IATU_NUM; i++)
+ dw_pcie_disable_atu(pcie->pci, DW_PCIE_REGION_OUTBOUND, i);
+}
+
static int ls1021_pcie_link_up(struct dw_pcie *pci)
{
u32 state;
@@ -108,33 +111,6 @@ static int ls1021_pcie_link_up(struct dw_pcie *pci)
return 1;
}
-static void ls1021_pcie_host_init(struct pcie_port *pp)
-{
- struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
- struct ls_pcie *pcie = to_ls_pcie(pci);
- struct device *dev = pci->dev;
- u32 index[2];
-
- pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
- "fsl,pcie-scfg");
- if (IS_ERR(pcie->scfg)) {
- dev_err(dev, "No syscfg phandle specified\n");
- pcie->scfg = NULL;
- return;
- }
-
- if (of_property_read_u32_array(dev->of_node,
- "fsl,pcie-scfg", index, 2)) {
- pcie->scfg = NULL;
- return;
- }
- pcie->index = index[1];
-
- dw_pcie_setup_rc(pp);
-
- ls_pcie_drop_msg_tlp(pcie);
-}
-
static int ls_pcie_link_up(struct dw_pcie *pci)
{
struct ls_pcie *pcie = to_ls_pcie(pci);
@@ -155,11 +131,42 @@ static void ls_pcie_host_init(struct pcie_port *pp)
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct ls_pcie *pcie = to_ls_pcie(pci);
- iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN);
- ls_pcie_fix_class(pcie);
+ /*
+ * Disable the outbound windows configured by bootloader to avoid
+ * one transaction hitting multiple outbound windows and the function
+ * dw_pcie_setup_rc will re-configure the outbound windows.
+ */
+ ls_pcie_disable_outbound_atus(pcie);
+
ls_pcie_clear_multifunction(pcie);
ls_pcie_drop_msg_tlp(pcie);
- iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN);
+
+ dw_pcie_setup_rc(pp);
+}
+
+static void ls1021_pcie_host_init(struct pcie_port *pp)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct ls_pcie *pcie = to_ls_pcie(pci);
+ struct device *dev = pci->dev;
+ u32 index[2];
+
+ pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
+ "fsl,pcie-scfg");
+ if (IS_ERR(pcie->scfg)) {
+ dev_err(dev, "No syscfg phandle specified\n");
+ pcie->scfg = NULL;
+ return;
+ }
+
+ if (of_property_read_u32_array(dev->of_node,
+ "fsl,pcie-scfg", index, 2)) {
+ pcie->scfg = NULL;
+ return;
+ }
+ pcie->index = index[1];
+
+ ls_pcie_host_init(pp);
}
static int ls_pcie_msi_host_init(struct pcie_port *pp,
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers
2017-07-06 6:33 [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers Zhiqiang Hou
2017-07-06 6:33 ` [PATCH 2/3] PCI: designware: enable write permission before updating class code Zhiqiang Hou
2017-07-06 6:33 ` [PATCH 3/3] PCI: layerscape: refactor the host_init function Zhiqiang Hou
@ 2017-07-06 9:44 ` Joao Pinto
2017-07-07 3:48 ` Z.q. Hou
2017-08-02 21:25 ` Bjorn Helgaas
2 siblings, 2 replies; 13+ messages in thread
From: Joao Pinto @ 2017-07-06 9:44 UTC (permalink / raw)
To: Zhiqiang Hou, linux-pci, Joao.Pinto; +Cc: bhelgaas, jingoohan1
Hi Zhiqiang,
Às 7:33 AM de 7/6/2017, Zhiqiang Hou escreveu:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>
> The read-only DBI registers can be written over the DBI when set
> the "Write to RO Registers Using DBI" (DBI_RO_WR_EN) field of the
> MISC_CONTROL_1_OFF register.
I would suggest you to add a cover-letter next time to explain the global
picture of the patch-set.
I understand your need for this patch, but I don't agree on the approach.
Sometimes the people in charge of the hardware design / configuration, forget to
specify the device class and that can be problematic for some drivers, and so
the typical workaround is to set it in the driver using a quirk for example.
You can see some examples here:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/quirks.c
Thanks,
Joao
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
> drivers/pci/dwc/pcie-designware.h | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
> index b4d2a89..bbdf35b 100644
> --- a/drivers/pci/dwc/pcie-designware.h
> +++ b/drivers/pci/dwc/pcie-designware.h
> @@ -76,6 +76,9 @@
> #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
> #define PCIE_ATU_UPPER_TARGET 0x91C
>
> +#define PCIE_MISC_CONTROL_1_OFF 0x8BC
> +#define PCIE_DBI_RO_WR_EN (0x1 << 0)
> +
> /*
> * iATU Unroll-specific register definitions
> * From 4.80 core version the address translation will be made by unroll
> @@ -279,6 +282,28 @@ static inline u32 dw_pcie_readl_dbi2(struct dw_pcie *pci, u32 reg)
> return __dw_pcie_read_dbi(pci, pci->dbi_base2, reg, 0x4);
> }
>
> +static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci)
> +{
> + u32 reg;
> + u32 val;
> +
> + reg = PCIE_MISC_CONTROL_1_OFF;
> + val = dw_pcie_readl_dbi(pci, reg);
> + val |= PCIE_DBI_RO_WR_EN;
> + dw_pcie_writel_dbi(pci, reg, val);
> +}
> +
> +static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci)
> +{
> + u32 reg;
> + u32 val;
> +
> + reg = PCIE_MISC_CONTROL_1_OFF;
> + val = dw_pcie_readl_dbi(pci, reg);
> + val &= ~PCIE_DBI_RO_WR_EN;
> + dw_pcie_writel_dbi(pci, reg, val);
> +}
> +
> #ifdef CONFIG_PCIE_DW_HOST
> irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
> void dw_pcie_msi_init(struct pcie_port *pp);
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers
2017-07-06 9:44 ` [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers Joao Pinto
@ 2017-07-07 3:48 ` Z.q. Hou
2017-07-07 8:53 ` Joao Pinto
2017-08-02 21:25 ` Bjorn Helgaas
1 sibling, 1 reply; 13+ messages in thread
From: Z.q. Hou @ 2017-07-07 3:48 UTC (permalink / raw)
To: Joao Pinto, linux-pci; +Cc: bhelgaas, jingoohan1
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers
2017-07-07 3:48 ` Z.q. Hou
@ 2017-07-07 8:53 ` Joao Pinto
2017-07-11 4:11 ` Z.q. Hou
0 siblings, 1 reply; 13+ messages in thread
From: Joao Pinto @ 2017-07-07 8:53 UTC (permalink / raw)
To: Z.q. Hou, Joao Pinto, linux-pci, bhelgaas; +Cc: jingoohan1
Hi Zhiqiang,
Às 4:48 AM de 7/7/2017, Z.q. Hou escreveu:
> Hi Joao,
>
>
>
> Thanks a lot for your comments!
>
>
>
>> -----Original Message-----
>
>> From: Joao Pinto [mailto:Joao.Pinto@synopsys.com]
>
>> Sent: 2017年7月6日 17:44
>
>> To: Z.q. Hou <zhiqiang.hou@nxp.com>; linux-pci@vger.kernel.org;
>
>> Joao.Pinto@synopsys.com
>
>> Cc: bhelgaas@google.com; jingoohan1@gmail.com
>
>> Subject: Re: [PATCH 1/3] PCI: designware: add accessors for write permission
>
>> of DBI read-only registers
>
>>
>
>>
>
>> Hi Zhiqiang,
>
>>
>
>> Às 7:33 AM de 7/6/2017, Zhiqiang Hou escreveu:
>
>>> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>
>>>
>
>>> The read-only DBI registers can be written over the DBI when set the
>
>>> "Write to RO Registers Using DBI" (DBI_RO_WR_EN) field of the
>
>>> MISC_CONTROL_1_OFF register.
>
>>
>
>> I would suggest you to add a cover-letter next time to explain the global
>
>> picture of the patch-set.
>
>
>
> Thanks, I will.
>
>
>
>>
>
>> I understand your need for this patch, but I don't agree on the approach.
>
>
>
> In the DWC common code, there is a function write a DBI read-only register 'Device class code', and the first 2 patches is to fix it.
>
> The 3rd patch is to refactor the Layerscape PCIe driver's host_init function and reuse the new added accessors.
>
>
>
>> Sometimes the people in charge of the hardware design / configuration, forget
>
>> to specify the device class and that can be problematic for some drivers, and
>
>> so the typical workaround is to set it in the driver using a quirk for example.
>
>>
>
>> You can see some examples here:
>
>> https://urldefense.proofpoint.com/v2/url?u=https-3A__git.kernel.org_pub_scm_linux_kernel_git_torvalds_linux.git_tree_drivers_&d=DwIGaQ&c=DPL6_X_6JkXFx7AXWqB0tg&r=s2fO0hii0OGNOv9qQy_HRXy-xAJUD1NNoEcc3io_kx0&m=0DrBCvOc_J7LaMXBei1qCXxxfbLxWaVErKZ6Rkm6bUc&s=sOEmExQFqrCEmpAx9LjSeKRvkW1D-W82ckX5WGCgFWw&e=
>
>> pci/quirks.c
>
>
>
> I don't know the PCI quirks, do you mean remove the pci Device Class fix code from the DWC common code and add it to quirks?
>
In my opinion adding fixes to a common code is not a good approach. I would
suggest the fix to go into the quirks file.
@Bjorn: The quirks file is the best place for this type of fixes right?
Thanks,
Joao
>
>
> Thanks,
>
> Zhiqiang
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers
2017-07-07 8:53 ` Joao Pinto
@ 2017-07-11 4:11 ` Z.q. Hou
2017-07-17 19:41 ` Jingoo Han
0 siblings, 1 reply; 13+ messages in thread
From: Z.q. Hou @ 2017-07-11 4:11 UTC (permalink / raw)
To: Joao Pinto, linux-pci, bhelgaas; +Cc: jingoohan1
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers
2017-07-11 4:11 ` Z.q. Hou
@ 2017-07-17 19:41 ` Jingoo Han
2017-07-18 3:00 ` Z.q. Hou
0 siblings, 1 reply; 13+ messages in thread
From: Jingoo Han @ 2017-07-17 19:41 UTC (permalink / raw)
To: 'Z.q. Hou', 'Joao Pinto', linux-pci, bhelgaas
On Tuesday, July 11, 2017 12:11 AM, Z.q. Hou wrote:
>=20
> Hi Bjorn,
>=20
> Due to all Freescale Layerscpe PCIe controllers have to fix the Class =
code,
> and this fixup existed in both Layerscape pcie driver and DWC common =
code,
> so I want to reuse the fixup in DWC common code.
> Can you give me any suggestion?
Please don't add your comment on top of the email.
>=20
> > -----Original Message-----
> > From: Joao Pinto [mailto:Joao.Pinto@synopsys.com]
> > Sent: 2017=E5=B9=B47=E6=9C=887=E6=97=A5 16:53
> > To: Z.q. Hou <zhiqiang.hou@nxp.com>; Joao Pinto
> > <Joao.Pinto@synopsys.com>; linux-pci@vger.kernel.org;
> > bhelgaas@google.com
> > Cc: jingoohan1@gmail.com
> > Subject: Re: [PATCH 1/3] PCI: designware: add accessors for write
> permission
> > of DBI read-only registers
> >
> >
> > Hi Zhiqiang,
> >
> > =C3=80s 4:48 AM de 7/7/2017, Z.q. Hou escreveu:
> > > Hi Joao,
> > >
> > >
> > >
> > > Thanks a lot for your comments!
> > >
> > >
> > >
> > >> -----Original Message-----
> > >
> > >> From: Joao Pinto [mailto:Joao.Pinto@synopsys.com]
> > >
> > >> Sent: 2017=E5=B9=B47=E6=9C=886=E6=97=A5 17:44
> > >
> > >> To: Z.q. Hou <zhiqiang.hou@nxp.com>; linux-pci@vger.kernel.org;
> > >
> > >> Joao.Pinto@synopsys.com
> > >
> > >> Cc: bhelgaas@google.com; jingoohan1@gmail.com
> > >
> > >> Subject: Re: [PATCH 1/3] PCI: designware: add accessors for write
> > >> permission
> > >
> > >> of DBI read-only registers
> > >
> > >>
> > >
> > >>
> > >
> > >> Hi Zhiqiang,
> > >
> > >>
> > >
> > >> =C3=80s 7:33 AM de 7/6/2017, Zhiqiang Hou escreveu:
> > >
> > >>> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > >
> > >>>
> > >
> > >>> The read-only DBI registers can be written over the DBI when set =
the
> > >
> > >>> "Write to RO Registers Using DBI" (DBI_RO_WR_EN) field of the
> > >
> > >>> MISC_CONTROL_1_OFF register.
> > >
> > >>
> > >
> > >> I would suggest you to add a cover-letter next time to explain =
the
> > >> global
> > >
> > >> picture of the patch-set.
> > >
> > >
> > >
> > > Thanks, I will.
> > >
> > >
> > >
> > >>
> > >
> > >> I understand your need for this patch, but I don't agree on the
> approach.
> > >
> > >
> > >
> > > In the DWC common code, there is a function write a DBI read-only
> register
> > 'Device class code', and the first 2 patches is to fix it.
> > >
> > > The 3rd patch is to refactor the Layerscape PCIe driver's =
host_init
> function
> > and reuse the new added accessors.
> > >
> > >
> > >
> > >> Sometimes the people in charge of the hardware design /
> > >> configuration, forget
> > >
> > >> to specify the device class and that can be problematic for some
> > >> drivers, and
> > >
> > >> so the typical workaround is to set it in the driver using a =
quirk
> for example.
> > >
> > >>
> > >
> > >> You can see some examples here:
> > >
> > >> =
https://urldefense.proofpoint.com/v2/url?u=3Dhttps-3A__git.kernel.org_p
> > >> =
ub_scm_linux_kernel_git_torvalds_linux.git_tree_drivers_&d=3DDwIGaQ&c=3DD=
> > >>
> > PL6_X_6JkXFx7AXWqB0tg&r=3Ds2fO0hii0OGNOv9qQy_HRXy-xAJUD1NNoEcc3io
> > _kx0&m
> > >>
> > =3D0DrBCvOc_J7LaMXBei1qCXxxfbLxWaVErKZ6Rkm6bUc&s=3DsOEmExQFqrCEmpA
> > x9LjSeK
> > >> RvkW1D-W82ckX5WGCgFWw&e=3D
> > >
> > >> pci/quirks.c
> > >
> > >
> > >
> > > I don't know the PCI quirks, do you mean remove the pci Device =
Class
> fix
> > code from the DWC common code and add it to quirks?
> > >
> >
> > In my opinion adding fixes to a common code is not a good approach. =
I
> would
> > suggest the fix to go into the quirks file.
Your answer should be added to here.
Then, it will help other people follow this email thread.
Best regards,
Jingoo Han
> >
> > @Bjorn: The quirks file is the best place for this type of fixes =
right?
>=20
> Thanks,
> Zhiqiang
>=20
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers
2017-07-17 19:41 ` Jingoo Han
@ 2017-07-18 3:00 ` Z.q. Hou
0 siblings, 0 replies; 13+ messages in thread
From: Z.q. Hou @ 2017-07-18 3:00 UTC (permalink / raw)
To: Jingoo Han, 'Joao Pinto', linux-pci, bhelgaas
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 3/3] PCI: layerscape: refactor the host_init function
2017-07-06 6:33 ` [PATCH 3/3] PCI: layerscape: refactor the host_init function Zhiqiang Hou
@ 2017-08-02 21:11 ` Bjorn Helgaas
2017-08-03 3:17 ` Z.q. Hou
0 siblings, 1 reply; 13+ messages in thread
From: Bjorn Helgaas @ 2017-08-02 21:11 UTC (permalink / raw)
To: Zhiqiang Hou; +Cc: linux-pci, bhelgaas, jingoohan1, Joao.Pinto, Minghuan Lian
On Thu, Jul 06, 2017 at 02:33:49PM +0800, Zhiqiang Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>
> Main changes:
> - Make the ls1021a's host_init reuse layerscape platform's common
> host_init function.
> - Will not use the outbound windows configured by bootloader, but
> introduce DWC common setup function dw_pcie_setup_rc and disable
> the bootloader configured outbound windows. And remove the duplicate
> class field fix code.
This seems to have two or even three distinct changes mixed together.
Please split them into separate patches. In particular, you mention a
class code fix -- that should be its own separate patch.
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> ---
> drivers/pci/dwc/pci-layerscape.c | 85 ++++++++++++++++++++++------------------
> 1 file changed, 46 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
> index fd86128..9bed3cd 100644
> --- a/drivers/pci/dwc/pci-layerscape.c
> +++ b/drivers/pci/dwc/pci-layerscape.c
> @@ -33,7 +33,8 @@
>
> /* PEX Internal Configuration Registers */
> #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
> -#define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */
> +
> +#define PCIE_IATU_NUM 6
>
> struct ls_pcie_drvdata {
> u32 lut_offset;
> @@ -69,15 +70,9 @@ static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
> {
> struct dw_pcie *pci = pcie->pci;
>
> + dw_pcie_dbi_ro_wr_en(pci);
> iowrite8(PCI_HEADER_TYPE_BRIDGE, pci->dbi_base + PCI_HEADER_TYPE);
> -}
> -
> -/* Fix class value */
> -static void ls_pcie_fix_class(struct ls_pcie *pcie)
> -{
> - struct dw_pcie *pci = pcie->pci;
> -
> - iowrite16(PCI_CLASS_BRIDGE_PCI, pci->dbi_base + PCI_CLASS_DEVICE);
> + dw_pcie_dbi_ro_wr_dis(pci);
> }
>
> /* Drop MSG TLP except for Vendor MSG */
> @@ -91,6 +86,14 @@ static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
> iowrite32(val, pci->dbi_base + PCIE_STRFMR1);
> }
>
> +static void ls_pcie_disable_outbound_atus(struct ls_pcie *pcie)
> +{
> + int i;
> +
> + for (i = 0; i < PCIE_IATU_NUM; i++)
> + dw_pcie_disable_atu(pcie->pci, DW_PCIE_REGION_OUTBOUND, i);
> +}
> +
> static int ls1021_pcie_link_up(struct dw_pcie *pci)
> {
> u32 state;
> @@ -108,33 +111,6 @@ static int ls1021_pcie_link_up(struct dw_pcie *pci)
> return 1;
> }
>
> -static void ls1021_pcie_host_init(struct pcie_port *pp)
> -{
> - struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> - struct ls_pcie *pcie = to_ls_pcie(pci);
> - struct device *dev = pci->dev;
> - u32 index[2];
> -
> - pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
> - "fsl,pcie-scfg");
> - if (IS_ERR(pcie->scfg)) {
> - dev_err(dev, "No syscfg phandle specified\n");
> - pcie->scfg = NULL;
> - return;
> - }
> -
> - if (of_property_read_u32_array(dev->of_node,
> - "fsl,pcie-scfg", index, 2)) {
> - pcie->scfg = NULL;
> - return;
> - }
> - pcie->index = index[1];
> -
> - dw_pcie_setup_rc(pp);
> -
> - ls_pcie_drop_msg_tlp(pcie);
> -}
> -
> static int ls_pcie_link_up(struct dw_pcie *pci)
> {
> struct ls_pcie *pcie = to_ls_pcie(pci);
> @@ -155,11 +131,42 @@ static void ls_pcie_host_init(struct pcie_port *pp)
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> struct ls_pcie *pcie = to_ls_pcie(pci);
>
> - iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN);
> - ls_pcie_fix_class(pcie);
> + /*
> + * Disable the outbound windows configured by bootloader to avoid
> + * one transaction hitting multiple outbound windows and the function
> + * dw_pcie_setup_rc will re-configure the outbound windows.
> + */
> + ls_pcie_disable_outbound_atus(pcie);
> +
> ls_pcie_clear_multifunction(pcie);
> ls_pcie_drop_msg_tlp(pcie);
> - iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN);
> +
> + dw_pcie_setup_rc(pp);
> +}
> +
> +static void ls1021_pcie_host_init(struct pcie_port *pp)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct ls_pcie *pcie = to_ls_pcie(pci);
> + struct device *dev = pci->dev;
> + u32 index[2];
> +
> + pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
> + "fsl,pcie-scfg");
> + if (IS_ERR(pcie->scfg)) {
> + dev_err(dev, "No syscfg phandle specified\n");
> + pcie->scfg = NULL;
> + return;
> + }
> +
> + if (of_property_read_u32_array(dev->of_node,
> + "fsl,pcie-scfg", index, 2)) {
> + pcie->scfg = NULL;
> + return;
> + }
> + pcie->index = index[1];
> +
> + ls_pcie_host_init(pp);
> }
>
> static int ls_pcie_msi_host_init(struct pcie_port *pp,
> --
> 2.1.0.27.g96db324
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers
2017-07-06 9:44 ` [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers Joao Pinto
2017-07-07 3:48 ` Z.q. Hou
@ 2017-08-02 21:25 ` Bjorn Helgaas
2017-08-03 3:25 ` Z.q. Hou
1 sibling, 1 reply; 13+ messages in thread
From: Bjorn Helgaas @ 2017-08-02 21:25 UTC (permalink / raw)
To: Joao Pinto; +Cc: Zhiqiang Hou, linux-pci, bhelgaas, jingoohan1
On Thu, Jul 06, 2017 at 10:44:04AM +0100, Joao Pinto wrote:
>
> Hi Zhiqiang,
>
> Às 7:33 AM de 7/6/2017, Zhiqiang Hou escreveu:
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > The read-only DBI registers can be written over the DBI when set
> > the "Write to RO Registers Using DBI" (DBI_RO_WR_EN) field of the
> > MISC_CONTROL_1_OFF register.
>
> I would suggest you to add a cover-letter next time to explain the global
> picture of the patch-set.
>
> I understand your need for this patch, but I don't agree on the approach.
> Sometimes the people in charge of the hardware design / configuration, forget to
> specify the device class and that can be problematic for some drivers, and so
> the typical workaround is to set it in the driver using a quirk for example.
>
> You can see some examples here:
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/quirks.c
I assume you're suggesting something similar to quirk_tw686x_class() and
fixup_ti816x_class(), quirk_amd_nl_class(), quirk_eisa_bridge(),
fixup_rev1_53c810(), etc.
The current dw_pcie_setup_rc() contains this:
/* program correct class for RC */
dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
That suggests that DesignWare-based devices have the wrong class code,
and we're trying to fix it.
Patch 2/3 of this series suggests that the existing fix doesn't
actually work because the register is read-only.
If it's necessary and possible to update the class code register in
dw_pcie_setup_rc(), I think that's a reasonable spot to do it.
The quirks in drivers/pci/quirks.c are necessary because per spec, the
PCI Class Code is read-only, so in general we can't update it.
In the DesignWare case, the driver has additional device-specific
knowledge that allows it to update Class Code value, and I think it
makes sense to do it there.
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > ---
> > drivers/pci/dwc/pcie-designware.h | 25 +++++++++++++++++++++++++
> > 1 file changed, 25 insertions(+)
> >
> > diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
> > index b4d2a89..bbdf35b 100644
> > --- a/drivers/pci/dwc/pcie-designware.h
> > +++ b/drivers/pci/dwc/pcie-designware.h
> > @@ -76,6 +76,9 @@
> > #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
> > #define PCIE_ATU_UPPER_TARGET 0x91C
> >
> > +#define PCIE_MISC_CONTROL_1_OFF 0x8BC
> > +#define PCIE_DBI_RO_WR_EN (0x1 << 0)
> > +
> > /*
> > * iATU Unroll-specific register definitions
> > * From 4.80 core version the address translation will be made by unroll
> > @@ -279,6 +282,28 @@ static inline u32 dw_pcie_readl_dbi2(struct dw_pcie *pci, u32 reg)
> > return __dw_pcie_read_dbi(pci, pci->dbi_base2, reg, 0x4);
> > }
> >
> > +static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci)
> > +{
> > + u32 reg;
> > + u32 val;
> > +
> > + reg = PCIE_MISC_CONTROL_1_OFF;
> > + val = dw_pcie_readl_dbi(pci, reg);
> > + val |= PCIE_DBI_RO_WR_EN;
> > + dw_pcie_writel_dbi(pci, reg, val);
> > +}
> > +
> > +static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci)
> > +{
> > + u32 reg;
> > + u32 val;
> > +
> > + reg = PCIE_MISC_CONTROL_1_OFF;
> > + val = dw_pcie_readl_dbi(pci, reg);
> > + val &= ~PCIE_DBI_RO_WR_EN;
> > + dw_pcie_writel_dbi(pci, reg, val);
> > +}
> > +
> > #ifdef CONFIG_PCIE_DW_HOST
> > irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
> > void dw_pcie_msi_init(struct pcie_port *pp);
> >
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 3/3] PCI: layerscape: refactor the host_init function
2017-08-02 21:11 ` Bjorn Helgaas
@ 2017-08-03 3:17 ` Z.q. Hou
0 siblings, 0 replies; 13+ messages in thread
From: Z.q. Hou @ 2017-08-03 3:17 UTC (permalink / raw)
To: Bjorn Helgaas; +Cc: linux-pci, bhelgaas, jingoohan1, Joao.Pinto, M.h. Lian
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^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers
2017-08-02 21:25 ` Bjorn Helgaas
@ 2017-08-03 3:25 ` Z.q. Hou
0 siblings, 0 replies; 13+ messages in thread
From: Z.q. Hou @ 2017-08-03 3:25 UTC (permalink / raw)
To: Bjorn Helgaas, Joao Pinto; +Cc: linux-pci, bhelgaas, jingoohan1
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^ permalink raw reply [flat|nested] 13+ messages in thread
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Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
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2017-07-06 6:33 [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers Zhiqiang Hou
2017-07-06 6:33 ` [PATCH 2/3] PCI: designware: enable write permission before updating class code Zhiqiang Hou
2017-07-06 6:33 ` [PATCH 3/3] PCI: layerscape: refactor the host_init function Zhiqiang Hou
2017-08-02 21:11 ` Bjorn Helgaas
2017-08-03 3:17 ` Z.q. Hou
2017-07-06 9:44 ` [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers Joao Pinto
2017-07-07 3:48 ` Z.q. Hou
2017-07-07 8:53 ` Joao Pinto
2017-07-11 4:11 ` Z.q. Hou
2017-07-17 19:41 ` Jingoo Han
2017-07-18 3:00 ` Z.q. Hou
2017-08-02 21:25 ` Bjorn Helgaas
2017-08-03 3:25 ` Z.q. Hou
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