* [PATCH 00/10] PCI: pci resource allocation test module
@ 2017-08-05 6:37 Yinghai Lu
2017-08-05 6:37 ` [PATCH 01/10] PCI: avoid arch_remove_reservations() for PCI_TEST Yinghai Lu
` (7 more replies)
0 siblings, 8 replies; 9+ messages in thread
From: Yinghai Lu @ 2017-08-05 6:37 UTC (permalink / raw)
To: Bjorn Helgaas; +Cc: Linus Torvalds, linux-pci, linux-kernel, Yinghai Lu
Read from data file and mask file, to build simulated data structure, and
have pci_ops to use them.
Extract calling for pci_create_root_bus, scan_child_bus, resource survey
and resource assign ... to see if those functions work as expected with
simulated data.
mask is with rw bits on pci registers, so we can make pci BAR sizing working.
It also support bus number assign-all.
Only tested on x86 64bit arch.
# insmod pci_test.ko data_file=pci_test_data.txt mask_file=pci_test_mask.txt
# lspci -tv
# cat /proc/ioports_test
# cat /proc/iomem_test
# rmmod pci_test
also in git://git.kernel.org/pub/scm/linux/kernel/git/yinghai/linux-yinghai.git for_pci_v4.14_pci_next
Thanks
Yinghai
Yinghai Lu (10):
PCI: avoid arch_remove_reservations() for PCI_TEST
PCI: introduce ioport_res/iomem_res for PCI_TEST
PCI: export symbol for PCI_TEST module
PCI: extend pci device match_driver state
PCI: Add PCI_TEST module for resource allocation
PCI: PCI_TEST simple data
PCI: PCI_TEST data from x5-8
PCI: PCI_TEST data from x5-8 with zeroed bus number
PCI: PCI_TEST data from x2-8
PCI: PCI_TEST data from x2-8 with zeroed bus number
arch/x86/kernel/resource.c | 15 +-
arch/x86/pci/i386.c | 1 +
drivers/iommu/amd_iommu_init.c | 2 +-
drivers/pci/Kconfig | 6 +
drivers/pci/Makefile | 2 +
drivers/pci/bus.c | 3 +-
drivers/pci/pci-driver.c | 2 +-
drivers/pci/pci_test.c | 1281 ++
drivers/pci/pci_test_data.txt | 24 +
drivers/pci/pci_test_data_x2-8.txt | 22818 +++++++++++++++++++++++++++++++
drivers/pci/pci_test_data_x2-8_bus.txt | 22818 +++++++++++++++++++++++++++++++
drivers/pci/pci_test_data_x5-8.txt | 5656 ++++++++
drivers/pci/pci_test_data_x5-8_bus.txt | 5656 ++++++++
drivers/pci/pci_test_mask.txt | 5 +
drivers/pci/pci_test_mask_x2-8.txt | 319 +
drivers/pci/pci_test_mask_x5-8.txt | 176 +
drivers/pci/probe.c | 4 +-
drivers/pci/quirks.c | 2 +-
drivers/pci/setup-bus.c | 3 +-
drivers/pci/setup-res.c | 4 +-
include/linux/ioport.h | 3 +-
include/linux/pci.h | 15 +-
kernel/resource.c | 7 +-
23 files changed, 58808 insertions(+), 14 deletions(-)
create mode 100644 drivers/pci/pci_test.c
create mode 100644 drivers/pci/pci_test_data.txt
create mode 100644 drivers/pci/pci_test_data_x2-8.txt
create mode 100644 drivers/pci/pci_test_data_x2-8_bus.txt
create mode 100644 drivers/pci/pci_test_data_x5-8.txt
create mode 100644 drivers/pci/pci_test_data_x5-8_bus.txt
create mode 100644 drivers/pci/pci_test_mask.txt
create mode 100644 drivers/pci/pci_test_mask_x2-8.txt
create mode 100644 drivers/pci/pci_test_mask_x5-8.txt
--
2.9.4
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 01/10] PCI: avoid arch_remove_reservations() for PCI_TEST
2017-08-05 6:37 [PATCH 00/10] PCI: pci resource allocation test module Yinghai Lu
@ 2017-08-05 6:37 ` Yinghai Lu
2017-08-05 6:37 ` [PATCH 02/10] PCI: introduce ioport_res/iomem_res " Yinghai Lu
` (6 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Yinghai Lu @ 2017-08-05 6:37 UTC (permalink / raw)
To: Bjorn Helgaas; +Cc: Linus Torvalds, linux-pci, linux-kernel, Yinghai Lu
arch_remove_reservations will clip out with e820 from host that kernel
running, that will cause failure from PCI_TEST from simulated data.
PCI_TEST has different iomem resource instead iomem_resource,
so check if iomem_resource is related to avoid calling
arch_remove_reservations()
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
---
arch/x86/kernel/resource.c | 15 +++++++++++++--
include/linux/ioport.h | 3 ++-
kernel/resource.c | 5 +++--
3 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/arch/x86/kernel/resource.c b/arch/x86/kernel/resource.c
index 5ab3895..f19b0f6 100644
--- a/arch/x86/kernel/resource.c
+++ b/arch/x86/kernel/resource.c
@@ -35,14 +35,25 @@ static void remove_e820_regions(struct resource *avail)
}
}
-void arch_remove_reservations(struct resource *avail)
+static int is_from_iomem_resource(struct resource *root)
+{
+ while (root->parent)
+ root = root->parent;
+
+ if (root == &iomem_resource)
+ return 1;
+
+ return 0;
+}
+
+void arch_remove_reservations(struct resource *root, struct resource *avail)
{
/*
* Trim out BIOS area (high 2MB) and E820 regions. We do not remove
* the low 1MB unconditionally, as this area is needed for some ISA
* cards requiring a memory range, e.g. the i82365 PCMCIA controller.
*/
- if (avail->flags & IORESOURCE_MEM) {
+ if ((avail->flags & IORESOURCE_MEM) && is_from_iomem_resource(root)) {
resource_clip(avail, BIOS_ROM_BASE, BIOS_ROM_END);
remove_e820_regions(avail);
diff --git a/include/linux/ioport.h b/include/linux/ioport.h
index 6230064..4e9272d 100644
--- a/include/linux/ioport.h
+++ b/include/linux/ioport.h
@@ -177,7 +177,8 @@ extern struct resource *insert_resource_conflict(struct resource *parent, struct
extern int insert_resource(struct resource *parent, struct resource *new);
extern void insert_resource_expand_to_fit(struct resource *root, struct resource *new);
extern int remove_resource(struct resource *old);
-extern void arch_remove_reservations(struct resource *avail);
+extern void arch_remove_reservations(struct resource *root,
+ struct resource *avail);
extern int allocate_resource(struct resource *root, struct resource *new,
resource_size_t size, resource_size_t min,
resource_size_t max, resource_size_t align,
diff --git a/kernel/resource.c b/kernel/resource.c
index 9b5f044..4174020 100644
--- a/kernel/resource.c
+++ b/kernel/resource.c
@@ -570,7 +570,8 @@ int region_intersects(resource_size_t start, size_t size, unsigned long flags,
}
EXPORT_SYMBOL_GPL(region_intersects);
-void __weak arch_remove_reservations(struct resource *avail)
+void __weak arch_remove_reservations(struct resource *root,
+ struct resource *avail)
{
}
@@ -622,7 +623,7 @@ static int __find_resource(struct resource *root, struct resource *old,
goto next;
resource_clip(&tmp, constraint->min, constraint->max);
- arch_remove_reservations(&tmp);
+ arch_remove_reservations(root, &tmp);
/* Check for overflow after ALIGN() */
avail.start = ALIGN(tmp.start, constraint->align);
--
2.9.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 02/10] PCI: introduce ioport_res/iomem_res for PCI_TEST
2017-08-05 6:37 [PATCH 00/10] PCI: pci resource allocation test module Yinghai Lu
2017-08-05 6:37 ` [PATCH 01/10] PCI: avoid arch_remove_reservations() for PCI_TEST Yinghai Lu
@ 2017-08-05 6:37 ` Yinghai Lu
2017-08-05 6:37 ` [PATCH 03/10] PCI: export symbol for PCI_TEST module Yinghai Lu
` (5 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Yinghai Lu @ 2017-08-05 6:37 UTC (permalink / raw)
To: Bjorn Helgaas; +Cc: Linus Torvalds, linux-pci, linux-kernel, Yinghai Lu
Make every bus to take the pointer to correct iomem_res instead of
using iomem_resource directly.
So PCI_TEST could use different iomem_res later.
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
---
drivers/pci/probe.c | 2 ++
drivers/pci/quirks.c | 2 +-
drivers/pci/setup-bus.c | 2 +-
drivers/pci/setup-res.c | 4 ++--
include/linux/pci.h | 13 +++++++++++++
5 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index c31310d..1811016 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -881,6 +881,8 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
child->msi = parent->msi;
child->sysdata = parent->sysdata;
child->bus_flags = parent->bus_flags;
+ child->iomem_res = parent->iomem_res;
+ child->ioport_res = parent->ioport_res;
/* initialize some portions of the bus device, but don't register it
* now as the parent is not properly set up yet.
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 6967c6b..dc31098 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -1617,7 +1617,7 @@ static void quirk_alder_ioapic(struct pci_dev *pdev)
* not touch this (and it's already covered by the fixmap), so
* forcibly insert it into the resource tree */
if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
- insert_resource(&iomem_resource, &pdev->resource[0]);
+ insert_resource(iomem_res(pdev->bus), &pdev->resource[0]);
/* The next five BARs all seem to be rubbish, so just clean
* them out */
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index 958da7d..1c30102 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -805,7 +805,7 @@ static struct resource *find_free_bus_resource(struct pci_bus *bus,
struct resource *r;
pci_bus_for_each_resource(bus, r, i) {
- if (r == &ioport_resource || r == &iomem_resource)
+ if (r == ioport_res(bus) || r == iomem_res(bus))
continue;
if (r && (r->flags & type_mask) == type && !r->parent)
return r;
diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c
index 85774b7..43921a4 100644
--- a/drivers/pci/setup-res.c
+++ b/drivers/pci/setup-res.c
@@ -215,9 +215,9 @@ static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
root = pci_find_parent_resource(dev, res);
if (!root) {
if (res->flags & IORESOURCE_IO)
- root = &ioport_resource;
+ root = ioport_res(dev->bus);
else
- root = &iomem_resource;
+ root = iomem_res(dev->bus);
}
dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 4869e66..c58a635 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -524,6 +524,9 @@ struct pci_bus {
void *sysdata; /* hook for sys-specific extension */
struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
+ struct resource *iomem_res; /* pointer to root iomem_resource */
+ struct resource *ioport_res; /* pointer to root ioport_resource */
+
unsigned char number; /* bus number */
unsigned char primary; /* number of primary bridge */
unsigned char max_bus_speed; /* enum pci_bus_speed */
@@ -545,6 +548,16 @@ struct pci_bus {
#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
+static inline struct resource *iomem_res(struct pci_bus *bus)
+{
+ return bus->iomem_res ? : &iomem_resource;
+}
+
+static inline struct resource *ioport_res(struct pci_bus *bus)
+{
+ return bus->ioport_res ? : &ioport_resource;
+}
+
/*
* Returns true if the PCI bus is root (behind host-PCI bridge),
* false otherwise
--
2.9.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 03/10] PCI: export symbol for PCI_TEST module
2017-08-05 6:37 [PATCH 00/10] PCI: pci resource allocation test module Yinghai Lu
2017-08-05 6:37 ` [PATCH 01/10] PCI: avoid arch_remove_reservations() for PCI_TEST Yinghai Lu
2017-08-05 6:37 ` [PATCH 02/10] PCI: introduce ioport_res/iomem_res " Yinghai Lu
@ 2017-08-05 6:37 ` Yinghai Lu
2017-08-05 6:37 ` [PATCH 04/10] PCI: extend pci device match_driver state Yinghai Lu
` (4 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Yinghai Lu @ 2017-08-05 6:37 UTC (permalink / raw)
To: Bjorn Helgaas; +Cc: Linus Torvalds, linux-pci, linux-kernel, Yinghai Lu
We need to use them from pci_test module, so expose them.
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
---
arch/x86/pci/i386.c | 1 +
drivers/pci/setup-bus.c | 1 +
kernel/resource.c | 2 ++
3 files changed, 4 insertions(+)
diff --git a/arch/x86/pci/i386.c b/arch/x86/pci/i386.c
index 7b43071..9065c58 100644
--- a/arch/x86/pci/i386.c
+++ b/arch/x86/pci/i386.c
@@ -383,6 +383,7 @@ void pcibios_resource_survey_bus(struct pci_bus *bus)
if (!(pci_probe & PCI_ASSIGN_ROMS))
pcibios_allocate_rom_resources(bus);
}
+EXPORT_SYMBOL_GPL(pcibios_resource_survey_bus);
void __init pcibios_resource_survey(void)
{
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index 1c30102..24292e9 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -1839,6 +1839,7 @@ void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
/* dump the resource on buses */
pci_bus_dump_resources(bus);
}
+EXPORT_SYMBOL_GPL(pci_assign_unassigned_root_bus_resources);
void __init pci_assign_unassigned_resources(void)
{
diff --git a/kernel/resource.c b/kernel/resource.c
index 4174020..0d40d9a 100644
--- a/kernel/resource.c
+++ b/kernel/resource.c
@@ -301,6 +301,8 @@ void release_child_resources(struct resource *r)
write_unlock(&resource_lock);
}
+EXPORT_SYMBOL_GPL(release_child_resources);
+
/**
* request_resource_conflict - request and reserve an I/O or memory resource
* @root: root resource descriptor
--
2.9.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 04/10] PCI: extend pci device match_driver state
2017-08-05 6:37 [PATCH 00/10] PCI: pci resource allocation test module Yinghai Lu
` (2 preceding siblings ...)
2017-08-05 6:37 ` [PATCH 03/10] PCI: export symbol for PCI_TEST module Yinghai Lu
@ 2017-08-05 6:37 ` Yinghai Lu
2017-08-05 6:37 ` [PATCH 05/10] PCI: Add PCI_TEST module for resource allocation Yinghai Lu
` (3 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Yinghai Lu @ 2017-08-05 6:37 UTC (permalink / raw)
To: Bjorn Helgaas; +Cc: Linus Torvalds, linux-pci, linux-kernel, Yinghai Lu
Change it from false/true to -1/0/1.
If it is set from -1, then it will never get change to 1 later.
For PCI_TEST, the simulated device does not have realy function
support except bus number and BAR setting.
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
---
drivers/iommu/amd_iommu_init.c | 2 +-
drivers/pci/bus.c | 3 ++-
drivers/pci/pci-driver.c | 2 +-
drivers/pci/probe.c | 2 +-
include/linux/pci.h | 2 +-
5 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c
index 3723037..6d706ca 100644
--- a/drivers/iommu/amd_iommu_init.c
+++ b/drivers/iommu/amd_iommu_init.c
@@ -1558,7 +1558,7 @@ static int iommu_init_pci(struct amd_iommu *iommu)
return -ENODEV;
/* Prevent binding other PCI device drivers to IOMMU devices */
- iommu->dev->match_driver = false;
+ iommu->dev->match_driver = 0;
pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
&iommu->cap);
diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c
index bc56cf1..e2c0bda 100644
--- a/drivers/pci/bus.c
+++ b/drivers/pci/bus.c
@@ -322,7 +322,8 @@ void pci_bus_add_device(struct pci_dev *dev)
pci_proc_attach_device(dev);
pci_bridge_d3_update(dev);
- dev->match_driver = true;
+ if (dev->match_driver == 0)
+ dev->match_driver = 1;
retval = device_attach(&dev->dev);
if (retval < 0 && retval != -EPROBE_DEFER) {
dev_warn(&dev->dev, "device attach failed (%d)\n", retval);
diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c
index d51e873..c67b872 100644
--- a/drivers/pci/pci-driver.c
+++ b/drivers/pci/pci-driver.c
@@ -1373,7 +1373,7 @@ static int pci_bus_match(struct device *dev, struct device_driver *drv)
struct pci_driver *pci_drv;
const struct pci_device_id *found_id;
- if (!pci_dev->match_driver)
+ if (pci_dev->match_driver != 1)
return 0;
pci_drv = to_pci_driver(drv);
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 1811016..34ffbdf 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -2021,7 +2021,7 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
pci_set_msi_domain(dev);
/* Notifier could use PCI capabilities */
- dev->match_driver = false;
+ dev->match_driver = 0;
ret = device_add(&dev->dev);
WARN_ON(ret < 0);
}
diff --git a/include/linux/pci.h b/include/linux/pci.h
index c58a635..6e81d64 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -344,7 +344,7 @@ struct pci_dev {
unsigned int irq;
struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
- bool match_driver; /* Skip attaching driver */
+ int match_driver; /* Skip attaching driver */
/* These fields are used by common fixups */
unsigned int transparent:1; /* Subtractive decode PCI bridge */
unsigned int multifunction:1;/* Part of multi-function device */
--
2.9.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 05/10] PCI: Add PCI_TEST module for resource allocation
2017-08-05 6:37 [PATCH 00/10] PCI: pci resource allocation test module Yinghai Lu
` (3 preceding siblings ...)
2017-08-05 6:37 ` [PATCH 04/10] PCI: extend pci device match_driver state Yinghai Lu
@ 2017-08-05 6:37 ` Yinghai Lu
2017-08-05 6:37 ` [PATCH 06/10] PCI: PCI_TEST simple data Yinghai Lu
` (2 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Yinghai Lu @ 2017-08-05 6:37 UTC (permalink / raw)
To: Bjorn Helgaas; +Cc: Linus Torvalds, linux-pci, linux-kernel, Yinghai Lu
Read from data file and mask file, to build simulated data structure, and
have pci_ops to use them.
Extract calling for pci_create_root_bus, scan_child_bus, resource survey
and resource assign ... to see if those functions work as expected with
simulated data.
mask is with rw bits on pci registers, so we can make pci BAR sizing working.
It also support bus number assign-all.
Only tested on x86 64bit arch.
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
---
drivers/pci/Kconfig | 6 +
drivers/pci/Makefile | 2 +
drivers/pci/pci_test.c | 1281 ++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 1289 insertions(+)
create mode 100644 drivers/pci/pci_test.c
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index c32a77f..3183331 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -134,6 +134,12 @@ config PCI_HYPERV
The PCI device frontend driver allows the kernel to import arbitrary
PCI devices from a PCI backend to support PCI driver domains.
+config PCI_TEST
+ tristate "PCI test"
+ depends on PCI && X86_64
+ help
+ PCI test module to verify PCI resource allocation with simulated data
+
source "drivers/pci/hotplug/Kconfig"
source "drivers/pci/dwc/Kconfig"
source "drivers/pci/host/Kconfig"
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 66a21ac..043b979 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -51,6 +51,8 @@ obj-$(CONFIG_XEN_PCIDEV_FRONTEND) += xen-pcifront.o
obj-$(CONFIG_OF) += of.o
+obj-$(CONFIG_PCI_TEST) += pci_test.o
+
ccflags-$(CONFIG_PCI_DEBUG) := -DDEBUG
# PCI host controller drivers
diff --git a/drivers/pci/pci_test.c b/drivers/pci/pci_test.c
new file mode 100644
index 0000000..02ab2d2
--- /dev/null
+++ b/drivers/pci/pci_test.c
@@ -0,0 +1,1281 @@
+/*
+ * drivers/pci/pci_test.c
+ * by Yinghai Lu <yinghai@kernel.org>
+ *
+ * # insmod pci_test.ko data_file=pci_test_data.txt mask_file=pci_test_mask.txt
+ * # lspci -tv
+ * # cat /proc/ioports_test
+ * # cat /proc/iomem_test
+ * # rmmod pci_test
+ *
+ * data_file: is root bus resource from boot log + "lspci -vvxxxx"
+ * mask_file: modified from "lspci -vvxxxx" with mask head.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/cache.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/fs.h>
+#include <linux/proc_fs.h>
+#include <linux/seq_file.h>
+
+struct test_pci_root {
+ struct list_head node;
+ u16 segment;
+ u8 busnumber;
+ struct resource secondary;
+ struct resource c_pri; /* holder for child primary */
+ struct list_head root_res_list;
+ struct resource secondary_os;
+ struct pci_bus *bus;
+};
+
+struct test_pci_dev {
+ struct list_head node;
+ u32 mbdf;
+ int space_size; /* 256 or 4096 */
+ unsigned char *reg;
+
+ int mask_size;
+ unsigned char *mask;
+
+ int invisiable;
+ struct test_pci_dev *parent; /* device on root bus has no parent */
+ struct list_head dev_list; /* node in children devices */
+ int bridge;
+ struct resource secondary;
+ struct resource c_pri; /* holder for child primary */
+ struct list_head children; /* bridge to point to children devices */
+};
+
+struct test_pci_mask {
+ struct list_head node;
+ u32 vendor_device_id;
+ int space_size; /* 256 or 4096 */
+ unsigned char *reg; /* for mask: bit set means rw */
+};
+
+static LIST_HEAD(test_pci_root_list);
+static LIST_HEAD(test_pci_dev_list);
+static LIST_HEAD(test_pci_mask_list);
+
+static struct test_pci_root *test_pci_get_root(int mn, int bn)
+{
+ struct test_pci_root *root;
+
+ list_for_each_entry(root, &test_pci_root_list, node)
+ if (root->segment == (mn & 0xffff) &&
+ root->busnumber == (bn & 0xff))
+ return root;
+
+ return NULL;
+}
+
+static struct test_pci_root *test_pci_add_root(int mn, int bn, int bn1, int bn2)
+{
+ struct test_pci_root *root;
+
+ if (bn > bn1 || bn1 > bn2)
+ return NULL;
+
+ root = test_pci_get_root(mn, bn);
+ if (root) /* bus come last ? */
+ goto set_secondary;
+
+ root = kzalloc(sizeof(struct test_pci_root), GFP_KERNEL);
+ if (!root)
+ return NULL;
+
+ INIT_LIST_HEAD(&root->root_res_list);
+ list_add_tail(&root->node, &test_pci_root_list);
+
+ root->segment = mn & 0xffff;
+ root->busnumber = bn & 0xff;
+
+set_secondary:
+ if (root->c_pri.parent)
+ release_resource(&root->c_pri);
+ root->secondary.flags = IORESOURCE_BUS;
+ root->secondary.start = bn1 & 0xff;
+ root->secondary.end = bn2 & 0xff;
+ root->c_pri.flags = IORESOURCE_BUS;
+ root->c_pri.start = root->secondary.start;
+ root->c_pri.end = root->secondary.start;
+ request_resource(&root->secondary, &root->c_pri);
+
+ /* for os */
+ root->secondary_os.flags = IORESOURCE_BUS;
+ root->secondary_os.start = bn1 & 0xff;
+ root->secondary_os.end = bn2 & 0xff;
+
+ return root;
+}
+
+static int test_pci_add_root_res(int mn, int bn,
+ resource_size_t start, resource_size_t end,
+ int flags, resource_size_t offset)
+{
+ struct resource_entry *entry;
+ struct test_pci_root *root;
+
+ root = test_pci_get_root(mn, bn);
+ if (!root) {
+ root = test_pci_add_root(mn, bn, bn, bn);
+ if (!root)
+ return -ENOMEM;
+ }
+
+ entry = resource_list_create_entry(NULL, 0);
+ if (!entry)
+ return -ENOMEM;
+
+ entry->res->start = start;
+ entry->res->end = end;
+ entry->res->flags = flags;
+ entry->offset = offset;
+ resource_list_add_tail(entry, &root->root_res_list);
+
+ return 0;
+}
+
+static void test_pci_free_all_root_res(struct list_head *head)
+{
+ struct resource_entry *entry, *tmp;
+
+ resource_list_for_each_entry_safe(entry, tmp, head)
+ resource_list_destroy_entry(entry);
+}
+
+#define MBDF(m, b, d, f) ((((m)&0xffff)<<16) | (((b)&0xff)<<8) | \
+ (((d)&0x1f)<<3) | ((f)&7))
+
+static struct test_pci_dev *test_pci_add_dev(int mn, int bn,
+ int dn, int fn, int space_size, int bn1, int bn2)
+{
+ u32 mbdf = MBDF(mn, bn, dn, fn);
+ struct test_pci_dev *dev;
+
+ dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+ if (!dev)
+ return NULL;
+
+ list_add_tail(&dev->node, &test_pci_dev_list);
+
+ dev->reg = kzalloc(space_size, GFP_KERNEL);
+ if (!dev->reg)
+ return NULL;
+
+ dev->mbdf = mbdf;
+ dev->space_size = space_size;
+
+ if (bn1 != -1) {
+ dev->secondary.flags = IORESOURCE_BUS;
+ dev->secondary.start = bn1;
+ dev->secondary.end = bn2;
+ dev->c_pri.flags = IORESOURCE_BUS;
+ dev->c_pri.start = bn1;
+ dev->c_pri.end = bn1;
+ }
+
+ return dev;
+}
+
+static int test_pci_relocate_dev_reg(struct test_pci_dev *dev,
+ int space_size)
+{
+ unsigned char *reg;
+
+ if (dev->space_size >= space_size)
+ return 0;
+
+ reg = kzalloc(space_size, GFP_KERNEL);
+ if (!reg)
+ return -ENOMEM;
+
+ memcpy(reg, dev->reg, dev->space_size);
+ kfree(dev->reg);
+ dev->space_size = space_size;
+ dev->reg = reg;
+
+ return 0;
+}
+
+static void test_pci_free_dev(void)
+{
+ struct test_pci_dev *dev, *tmp;
+
+ list_for_each_entry_safe(dev, tmp, &test_pci_dev_list, node) {
+ list_del(&dev->node);
+ kfree(dev->reg);
+ kfree(dev);
+ }
+}
+
+static struct test_pci_mask *test_pci_add_mask(int vendor_id,
+ int device_id, int space_size)
+{
+ u32 vendor_device_id = vendor_id | (device_id<<16);
+ struct test_pci_mask *mask;
+
+ mask = kzalloc(sizeof(*mask), GFP_KERNEL);
+ if (!mask)
+ return NULL;
+
+ list_add_tail(&mask->node, &test_pci_mask_list);
+
+ mask->reg = kzalloc(space_size, GFP_KERNEL);
+ if (!mask->reg)
+ return NULL;
+
+ mask->vendor_device_id = vendor_device_id;
+ mask->space_size = space_size;
+
+ return mask;
+}
+
+static int test_pci_relocate_mask_reg(struct test_pci_mask *mask,
+ int space_size)
+{
+ unsigned char *reg;
+
+ if (mask->space_size >= space_size)
+ return 0;
+
+ reg = kzalloc(space_size, GFP_KERNEL);
+ if (!reg)
+ return -ENOMEM;
+
+ memcpy(reg, mask->reg, mask->space_size);
+ kfree(mask->reg);
+ mask->space_size = space_size;
+ mask->reg = reg;
+
+ return 0;
+}
+
+static void test_pci_free_mask(void)
+{
+ struct test_pci_mask *mask, *tmp;
+
+ list_for_each_entry_safe(mask, tmp, &test_pci_mask_list, node) {
+ list_del(&mask->node);
+ kfree(mask->reg);
+ kfree(mask);
+ }
+}
+
+static void test_pci_free(void)
+{
+ struct test_pci_root *root, *tmp;
+
+ list_for_each_entry_safe(root, tmp, &test_pci_root_list, node) {
+ test_pci_free_all_root_res(&root->root_res_list);
+ kfree(root);
+ }
+
+ test_pci_free_dev();
+ test_pci_free_mask();
+}
+
+/* dump_validate and dump_init are adapted from pci_utils lib/dump.c */
+static int dump_validate(char *s, char *fmt)
+{
+ while (*fmt) {
+ if (*fmt == '#' ? !isxdigit(*s) : *fmt != *s)
+ return 0;
+ fmt++, s++;
+ }
+
+ return 1;
+}
+
+static int dump_init(const char *name, int mn_offset)
+{
+ struct file *f;
+ char buf[256];
+ struct test_pci_dev *dev = NULL;
+ int len, mn, bn, dn, fn, i, j;
+ int seg, bn1, bn2;
+ unsigned long rstart, rend, bstart, bend, offset;
+ int good;
+ loff_t pos = 0;
+
+ f = filp_open(name, O_RDONLY, 0);
+ if (!f) {
+ pr_err("pci_test: Cannot open %s", name);
+ return -ENOENT;
+ }
+
+ while (kernel_read(f, pos, buf, sizeof(buf)-1) > 0) {
+ char *z = strchr(buf, '\n');
+
+ if (!z) {
+ filp_close(f, 0);
+ pr_err("pci_test: line too long or unterminated");
+ return -EINVAL;
+ }
+ pos += z - buf + 1;
+
+ *z-- = 0;
+ if (z >= buf && *z == '\r')
+ *z-- = 0;
+ len = z - buf + 1;
+ mn = 0;
+ if (dump_validate(buf, "pci_bus ####:##: root bus resource [bus ##-##]") &&
+ sscanf(buf, "pci_bus %x:%x: root bus resource [bus %x-%x]",
+ &seg, &bn, &bn1, &bn2) == 4) {
+ if (!test_pci_add_root(seg + mn_offset, bn, bn1, bn2))
+ return -ENOMEM;
+ } else if (dump_validate(buf, "pci_bus ####:##: root bus resource [bus ##]") &&
+ sscanf(buf, "pci_bus %x:%x: root bus resource [bus %x]",
+ &seg, &bn, &bn1) == 3) {
+ if (!test_pci_add_root(seg + mn_offset, bn, bn1, bn1))
+ return -ENOMEM;
+ } else if (dump_validate(buf, "pci_bus ####:##: root bus resource [io")) {
+ offset = 0;
+ good = 0;
+ if (strstr(buf, "bus address") &&
+ sscanf(buf, "pci_bus %x:%x: root bus resource [io 0x%lx-0x%lx] (bus address [0x%lx-0x%lx])",
+ &seg, &bn, &rstart, &rend, &bstart, &bend) == 6) {
+ offset = rstart - bstart;
+ good = 1;
+ } else if (sscanf(buf, "pci_bus %x:%x: root bus resource [io 0x%lx-0x%lx]",
+ &seg, &bn, &rstart, &rend) == 4)
+ good = 1;
+
+ if (good && test_pci_add_root_res(seg + mn_offset,
+ bn, rstart, rend,
+ IORESOURCE_IO, offset))
+ return -ENOMEM;
+ } else if (dump_validate(buf, "pci_bus ####:##: root bus resource [mem")) {
+ offset = 0;
+ good = 0;
+ if (strstr(buf, "bus address") &&
+ sscanf(buf, "pci_bus %x:%x: root bus resource [mem 0x%lx-0x%lx] (bus address [0x%lx-0x%lx])",
+ &seg, &bn, &rstart, &rend, &bstart, &bend) == 6) {
+ offset = rstart - bstart;
+ good = 1;
+ } else if (sscanf(buf, "pci_bus %x:%x: root bus resource [mem 0x%lx-0x%lx]",
+ &seg, &bn, &rstart, &rend) == 4)
+ good = 1;
+
+ if (good && test_pci_add_root_res(seg + mn_offset,
+ bn, rstart, rend,
+ IORESOURCE_MEM, offset))
+ return -ENOMEM;
+ } else if ((dump_validate(buf, "##:##.# [##-##]") &&
+ sscanf(buf, "%x:%x.%d [%x-%x]", &bn, &dn, &fn, &bn1, &bn2) == 5) ||
+ (dump_validate(buf, "####:##:##.# [##-##]") &&
+ sscanf(buf, "%x:%x:%x.%d [%x-%x]", &mn, &bn, &dn, &fn, &bn1, &bn2) == 6)) {
+ dev = test_pci_add_dev(mn + mn_offset, bn,
+ dn, fn, 256, bn1, bn2);
+ if (!dev)
+ return -ENOMEM;
+ } else if ((dump_validate(buf, "##:##.# ") &&
+ sscanf(buf, "%x:%x.%d", &bn, &dn, &fn) == 3) ||
+ (dump_validate(buf, "####:##:##.# ") &&
+ sscanf(buf, "%x:%x:%x.%d", &mn, &bn, &dn, &fn) == 4)) {
+ dev = test_pci_add_dev(mn + mn_offset, bn,
+ dn, fn, 256, -1, -1);
+ if (!dev)
+ return -ENOMEM;
+ } else if (!len) {
+ dev = NULL;
+ } else if (dev &&
+ (dump_validate(buf, "##: ") ||
+ dump_validate(buf, "###: ")) &&
+ sscanf(buf, "%x: ", &i) == 1) {
+ z = strchr(buf, ' ') + 1;
+ while (isxdigit(z[0]) && isxdigit(z[1]) &&
+ (!z[2] || z[2] == ' ') &&
+ sscanf(z, "%x", &j) == 1 && j < 256) {
+ if (i >= 4096) {
+ filp_close(f, 0);
+ pr_err("pci_test: At most 4096 bytes of config space are supported");
+ }
+ if (i >= dev->space_size)
+ test_pci_relocate_dev_reg(dev, 4096);
+ dev->reg[i++] = j;
+ z += 2;
+ if (*z)
+ z++;
+ }
+
+ if (*z) {
+ filp_close(f, 0);
+ pr_err("pci_test: Malformed line");
+ return -EINVAL;
+ }
+ }
+ }
+
+ filp_close(f, 0);
+
+ return 0;
+}
+
+static int mask_dump_init(const char *name)
+{
+ struct file *f;
+ char buf[256];
+ struct test_pci_mask *mask = NULL;
+ int len, vendor_id, device_id, i, j;
+ loff_t pos = 0;
+
+ f = filp_open(name, O_RDONLY, 0);
+ if (!f) {
+ pr_err("pci_test: Cannot open %s", name);
+ return -ENOENT;
+ }
+
+ while (kernel_read(f, pos, buf, sizeof(buf)-1) > 0) {
+ char *z = strchr(buf, '\n');
+
+ if (!z) {
+ filp_close(f, 0);
+ pr_err("pci_test: line too long or unterminated");
+ return -EINVAL;
+ }
+ pos += z - buf + 1;
+
+ *z-- = 0;
+ if (z >= buf && *z == '\r')
+ *z-- = 0;
+ len = z - buf + 1;
+ if (dump_validate(buf, "mask: ####:####") &&
+ sscanf(buf, "mask: %x:%x", &vendor_id, &device_id) == 2) {
+ mask = test_pci_add_mask(vendor_id,
+ device_id, 256);
+ if (!mask)
+ return -ENOMEM;
+ } else if (!len) {
+ mask = NULL;
+ } else if (mask &&
+ (dump_validate(buf, "##: ") ||
+ dump_validate(buf, "###: ")) &&
+ sscanf(buf, "%x: ", &i) == 1) {
+ z = strchr(buf, ' ') + 1;
+ while (isxdigit(z[0]) && isxdigit(z[1]) &&
+ (!z[2] || z[2] == ' ') &&
+ sscanf(z, "%x", &j) == 1 && j < 256) {
+ if (i >= 4096) {
+ filp_close(f, 0);
+ pr_err("pci_test: At most 4096 bytes of config space are supported");
+ }
+ if (i >= mask->space_size)
+ test_pci_relocate_mask_reg(mask, 4096);
+ mask->reg[i++] = j;
+ z += 2;
+ if (*z)
+ z++;
+ }
+
+ if (*z) {
+ filp_close(f, 0);
+ pr_err("pci_test: Malformed line");
+ return -EINVAL;
+ }
+ }
+ }
+
+ filp_close(f, 0);
+
+ return 0;
+}
+
+#define MASK_WARN_NUM 512
+static u32 mask_warn[MASK_WARN_NUM];
+static void warn_mask_once(int vendor_id, int device_id)
+{
+ int i;
+ u32 mask = vendor_id | (device_id << 16);
+
+ for (i = 0; i < MASK_WARN_NUM; i++) {
+ if (mask_warn[i] == mask)
+ return;
+
+ if (!mask_warn[i]) {
+ mask_warn[i] = mask;
+ break;
+ }
+ }
+
+ pr_warn("pci_test: no mask for %04x:%04x\n", vendor_id, device_id);
+}
+
+static struct test_pci_mask *test_pci_get_mask(int vendor_id, int device_id)
+{
+ int vendor_device_id = vendor_id | (device_id << 16);
+ struct test_pci_mask *mask;
+
+ list_for_each_entry(mask, &test_pci_mask_list, node)
+ if (vendor_device_id == mask->vendor_device_id)
+ return mask;
+
+ return NULL;
+}
+
+static unsigned char bridge_mask[0x40] = {
+/*00:*/ 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x10, 0x00,
+ 0x04, 0x00, 0x04, 0x06, 0x10, 0x00, 0x81, 0x00,
+/*10:*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xff, 0xff, 0x00, 0xf0, 0xf0, 0x00, 0x20,
+/*20:*/ 0xf0, 0xff, 0xf0, 0xff, 0xf0, 0xff, 0xf0, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+/*30:*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x0b, 0x01, 0x13, 0x00,
+};
+
+static void test_pci_probe_mask(void)
+{
+ struct test_pci_dev *dev;
+
+ list_for_each_entry(dev, &test_pci_dev_list, node) {
+ unsigned char *reg = dev->reg;
+ u16 vendor_id = reg[0] | (reg[1] << 8);
+ u16 device_id = reg[2] | (reg[3] << 8);
+ struct test_pci_mask *mask;
+
+ mask = test_pci_get_mask(vendor_id, device_id);
+ if (!mask) {
+ u16 class = (reg[0xb] << 8) | reg[0xa];
+
+ warn_mask_once(vendor_id, device_id);
+ if (class == PCI_CLASS_BRIDGE_PCI) {
+ pr_warn("pci_test: use default bridge mask for %04x:%04x\n",
+ vendor_id, device_id);
+ dev->mask = bridge_mask;
+ dev->mask_size = ARRAY_SIZE(bridge_mask);
+ }
+ } else {
+ dev->mask = mask->reg;
+ dev->mask_size = mask->space_size;
+ }
+ }
+}
+
+static void test_pci_update_secondary_from_reg(struct test_pci_dev *parent)
+{
+ unsigned char *reg = parent->reg;
+
+ parent->secondary.flags = IORESOURCE_BUS;
+ parent->secondary.start = reg[0x19];
+ parent->secondary.end = reg[0x1a];
+ parent->c_pri.flags = IORESOURCE_BUS;
+ parent->c_pri.start = parent->c_pri.end = reg[0x19];
+}
+
+static void test_pci_link_devices(void)
+{
+ struct test_pci_dev *dev, *parent;
+
+ /* set mask and find out all bridges */
+ list_for_each_entry(dev, &test_pci_dev_list, node) {
+ unsigned char *reg = dev->reg;
+ u16 class = (reg[0xb] << 8) | reg[0xa];
+
+ if (class != PCI_CLASS_BRIDGE_PCI)
+ continue;
+
+ INIT_LIST_HEAD(&dev->children);
+ dev->bridge = 1;
+
+ /* if bus range is not passed from ##:##.0 [##-##] */
+ if (!dev->secondary.flags)
+ test_pci_update_secondary_from_reg(dev);
+ }
+
+ /* link children to parent */
+ list_for_each_entry(dev, &test_pci_dev_list, node) {
+ int mn = (dev->mbdf >> 16) & 0xffff;
+ int bn = (dev->mbdf >> 8) & 0xff;
+
+ /* check if it is on root bus */
+ if (test_pci_get_root(mn, bn))
+ continue;
+
+ /* find parent for it */
+ list_for_each_entry(parent, &test_pci_dev_list, node) {
+ int parent_mn;
+
+ if (!parent->bridge)
+ continue;
+
+ parent_mn = (parent->mbdf >> 16) & 0xffff;
+ if (parent_mn != mn)
+ continue;
+
+ if (bn != parent->secondary.start)
+ continue;
+
+ /* it is */
+ list_add_tail(&dev->dev_list, &parent->children);
+ dev->parent = parent;
+ break;
+ }
+
+ if (!dev->parent) {
+ int dn = (dev->mbdf >> 3) & 0x1f;
+ int fn = dev->mbdf & 0x07;
+
+ pr_warn("pci_test: no parent for %04x:%02x:%02x.%1x\n",
+ mn, bn, dn, fn);
+ }
+ }
+}
+
+static int pci_test_request_bus(struct resource *parent_res,
+ struct resource *child_res)
+{
+ int ret;
+
+ ret = request_resource(parent_res, child_res);
+ if (!ret)
+ return 0;
+
+ /* child_res could have 0xff for probing, so shrink it to parent's */
+ if (child_res->end != 0xff || child_res->start > parent_res->end)
+ return ret;
+
+ child_res->end = parent_res->end;
+ ret = request_resource(parent_res, child_res);
+ if (!ret)
+ return 0;
+
+ child_res->end = 0xff;
+
+ return ret;
+}
+
+static void test_pci_update_invisiable_bridge(struct test_pci_dev *parent)
+{
+ struct test_pci_dev *child;
+ int invisiable = 1;
+
+ if (parent->c_pri.parent)
+ invisiable = 0;
+
+ list_for_each_entry(child, &parent->children, dev_list) {
+ child->invisiable = invisiable;
+
+ if (!child->bridge)
+ continue;
+
+ if (!invisiable &&
+ !pci_test_request_bus(&parent->secondary,
+ &child->secondary))
+ request_resource(&child->secondary, &child->c_pri);
+
+ test_pci_update_invisiable_bridge(child);
+ }
+}
+
+static void test_pci_update_invisiable(void)
+{
+ struct test_pci_dev *parent;
+
+ /* read bus info from reg */
+ list_for_each_entry(parent, &test_pci_dev_list, node) {
+ if (!parent->bridge)
+ continue;
+
+ test_pci_update_secondary_from_reg(parent);
+ }
+
+ /* if can not allocate bridge secondary properly, then invisiable */
+ list_for_each_entry(parent, &test_pci_dev_list, node) {
+ int mn, bn;
+ struct test_pci_root *root;
+
+ if (!parent->bridge)
+ continue;
+
+ mn = (parent->mbdf >> 16) & 0xffff;
+ bn = (parent->mbdf >> 8) & 0xff;
+ root = test_pci_get_root(mn, bn);
+ if (!root)
+ continue;
+
+ if (!pci_test_request_bus(&root->secondary, &parent->secondary))
+ request_resource(&parent->secondary, &parent->c_pri);
+
+ test_pci_update_invisiable_bridge(parent);
+ }
+}
+
+static void test_pci_update_bus(struct test_pci_dev *parent, int b_19_orig,
+ int b_1a_orig, int b_19, int b_1a)
+{
+ struct test_pci_dev *child;
+ struct resource *parent_res;
+
+ if (!parent->bridge)
+ return;
+
+ if ((b_19_orig == b_19) && (b_1a_orig == b_1a))
+ return;
+
+ {
+ int mn = (parent->mbdf >> 16) & 0xffff;
+ int bn = (parent->mbdf >> 8) & 0xff;
+ int dn = (parent->mbdf >> 3) & 0x1f;
+ int fn = parent->mbdf & 0x07;
+
+ pr_warn("pci_test: %04x:%02x:%02x.%1x update bus [%02x-%02x] ==> [%02x-%02x]\n",
+ mn, bn, dn, fn, b_19_orig, b_1a_orig, b_19, b_1a);
+ }
+
+ parent_res = parent->secondary.parent;
+ if (parent_res) {
+ release_child_resources(&parent->secondary);
+ release_resource(&parent->secondary);
+ } else {
+ /* bridge on root bus */
+ struct test_pci_root *root;
+ int mn = (parent->mbdf >> 16) & 0xffff;
+ int bn = (parent->mbdf >> 8) & 0xff;
+
+ root = test_pci_get_root(mn, bn);
+ if (!root)
+ return;
+
+ parent_res = &root->secondary;
+ }
+
+ list_for_each_entry(child, &parent->children, dev_list) {
+ child->mbdf &= 0xffff00ff;
+ child->mbdf |= b_19 << 8;
+
+ if (child->bridge)
+ child->reg[0x18] = b_19;
+ }
+
+ test_pci_update_secondary_from_reg(parent);
+
+ if (!pci_test_request_bus(parent_res, &parent->secondary))
+ request_resource(&parent->secondary, &parent->c_pri);
+
+ test_pci_update_invisiable_bridge(parent);
+}
+
+static int test_pci_init(const char *fn, int domain_offset, const char *mask_fn)
+{
+ if (dump_init(fn, domain_offset)) {
+ test_pci_free();
+ return -EINVAL;
+ }
+
+ mask_dump_init(mask_fn);
+
+ test_pci_probe_mask();
+
+ test_pci_link_devices();
+
+ test_pci_update_invisiable();
+
+ return 0;
+}
+
+/*--------------------------------------------*/
+
+static struct test_pci_dev *test_pci_get_dev(int mn, int bn,
+ int dn, int fn)
+{
+ int mbdf = MBDF(mn, bn, dn, fn);
+ struct test_pci_dev *dev;
+
+ list_for_each_entry(dev, &test_pci_dev_list, node)
+ if (mbdf == dev->mbdf && !dev->invisiable)
+ return dev;
+
+ return NULL;
+}
+
+static int test_pci_read(struct test_pci_dev *dev,
+ int where, int size, u32 *val)
+{
+ int i;
+ unsigned char *buf = (unsigned char *)val;
+ unsigned char *reg = dev->reg;
+
+ for (i = 0; i < size; i++)
+ buf[i] = reg[where + i];
+
+ return 0;
+}
+
+static int test_pci_write(struct test_pci_dev *dev,
+ int where, int size, u32 val)
+{
+ int i;
+ unsigned char *buf = (unsigned char *)&val;
+ unsigned char *reg = dev->reg;
+ unsigned char mask;
+
+ /* bit set means: rw */
+ for (i = 0; i < size; i++) {
+ if (dev->mask && (where + i < dev->mask_size))
+ mask = dev->mask[where + i];
+ else {
+ /* just guess */
+ if (!reg[where + i])
+ mask = 0x00;
+ else
+ mask = 0xff;
+ }
+ reg[where + i] &= ~mask;
+ reg[where + i] |= buf[i] & mask;
+ }
+
+ return 0;
+}
+
+/*--------------------------------------------*/
+
+static int pci_test_read(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 *val)
+{
+ struct test_pci_dev *dev;
+
+ dev = test_pci_get_dev(pci_domain_nr(bus),
+ bus->number, devfn >> 3, devfn & 7);
+ if (!dev) {
+ *val = 0xffffffff; /* or 0 ? */
+
+ return -EINVAL;
+ }
+
+ return test_pci_read(dev, where, size, val);
+}
+
+static int pci_test_write(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 val)
+{
+ struct test_pci_dev *dev;
+ unsigned char b_19_orig, b_1a_orig, *reg;
+ int ret;
+
+ dev = test_pci_get_dev(pci_domain_nr(bus),
+ bus->number, devfn >> 3, devfn & 7);
+ if (!dev)
+ return -EINVAL;
+
+ reg = dev->reg;
+ b_19_orig = reg[0x19];
+ b_1a_orig = reg[0x1a];
+ ret = test_pci_write(dev, where, size, val);
+ test_pci_update_bus(dev, b_19_orig, b_1a_orig, reg[0x19], reg[0x1a]);
+
+ return ret;
+}
+
+static struct pci_ops pci_test_ops = {
+ .read = pci_test_read,
+ .write = pci_test_write,
+};
+
+static int pci_test_get_root_resources(struct test_pci_root *root,
+ struct list_head *list)
+{
+ struct resource_entry *src, *dst;
+
+ /* set the resource list */
+ resource_list_for_each_entry(src, &root->root_res_list) {
+ dst = resource_list_create_entry(NULL, 0);
+ if (!dst)
+ return -ENOMEM;
+
+ dst->res->start = src->res->start;
+ dst->res->end = src->res->end;
+ dst->res->flags = src->res->flags;
+ dst->offset = src->offset;
+ resource_list_add_tail(dst, list);
+ }
+
+ return 0;
+}
+
+/*--------------------------------------------*/
+static struct resource pci_test_ioport_resource = {
+ .name = "PCI IO",
+ .start = 0,
+ .end = IO_SPACE_LIMIT,
+ .flags = IORESOURCE_IO,
+};
+
+static struct resource pci_test_iomem_resource = {
+ .name = "PCI mem",
+ .start = 0,
+ .end = -1,
+ .flags = IORESOURCE_MEM,
+};
+
+struct pci_test_root_info;
+
+struct pci_test_root_ops {
+ struct pci_ops *pci_ops;
+ void (*release_info)(struct pci_test_root_info *info);
+ int (*prepare_resources)(struct pci_test_root_info *info);
+};
+
+struct pci_test_root_info {
+ struct test_pci_root *root;
+ struct pci_test_root_ops *ops;
+ struct list_head resources;
+ char name[16];
+};
+
+struct pci_root_info_ext {
+ struct pci_test_root_info common;
+ struct pci_sysdata sd;
+};
+
+static int pci_test_root_prepare_resources(struct pci_test_root_info *ci)
+{
+ int ret;
+ struct list_head *list = &ci->resources;
+ struct resource_entry *entry;
+
+ ret = pci_test_get_root_resources(ci->root, list);
+ resource_list_for_each_entry(entry, list)
+ entry->res->name = ci->name;
+
+ return ret;
+}
+
+static void pci_test_root_info_release(struct pci_test_root_info *ci)
+{
+ kfree(container_of(ci, struct pci_root_info_ext, common));
+}
+
+static struct pci_test_root_ops pci_test_root_ops = {
+ .pci_ops = &pci_test_ops,
+ .release_info = pci_test_root_info_release,
+ .prepare_resources = pci_test_root_prepare_resources,
+};
+
+static void __pci_test_root_release_info(struct pci_test_root_info *info)
+{
+ struct resource *res;
+ struct resource_entry *entry, *tmp;
+
+ if (!info)
+ return;
+
+ resource_list_for_each_entry_safe(entry, tmp, &info->resources) {
+ res = entry->res;
+ if (res->parent &&
+ (res->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
+ release_resource(res);
+ resource_list_destroy_entry(entry);
+ }
+
+ info->ops->release_info(info);
+}
+
+static void pci_test_root_release_info(struct pci_host_bridge *bridge)
+{
+ struct resource *res;
+ struct resource_entry *entry;
+
+ resource_list_for_each_entry(entry, &bridge->windows) {
+ res = entry->res;
+ if (res->parent &&
+ (res->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
+ release_resource(res);
+ }
+ __pci_test_root_release_info(bridge->release_data);
+}
+
+static void pci_test_root_add_resources(struct pci_test_root_info *info)
+{
+ struct resource_entry *entry, *tmp;
+ struct resource *res, *root = NULL;
+
+ resource_list_for_each_entry_safe(entry, tmp, &info->resources) {
+ res = entry->res;
+ if (res->flags & IORESOURCE_MEM)
+ root = &pci_test_iomem_resource;
+ else if (res->flags & IORESOURCE_IO)
+ root = &pci_test_ioport_resource;
+ else
+ continue;
+
+ if (res == root)
+ continue;
+
+ if (insert_resource(root, res)) {
+ pr_info("ignoring host bridge window %pR\n", res);
+ resource_list_destroy_entry(entry);
+ }
+ }
+}
+
+static struct pci_bus *pci_test_root_create(struct test_pci_root *root,
+ struct pci_test_root_ops *ops,
+ struct pci_test_root_info *info,
+ void *sysdata)
+{
+ int ret = -1, busnum = root->secondary.start;
+ struct pci_bus *bus;
+
+ info->root = root;
+ info->ops = ops;
+ INIT_LIST_HEAD(&info->resources);
+ snprintf(info->name, sizeof(info->name), "PCI Bus %04x:%02x",
+ root->segment, busnum);
+
+ if (ops->prepare_resources)
+ ret = ops->prepare_resources(info);
+ if (ret < 0)
+ goto out_release_info;
+
+ pci_test_root_add_resources(info);
+ pci_add_resource(&info->resources, &root->secondary_os);
+ bus = pci_create_root_bus(NULL, busnum, ops->pci_ops,
+ sysdata, &info->resources);
+ if (!bus)
+ goto out_release_info;
+
+ bus->ioport_res = &pci_test_ioport_resource;
+ bus->iomem_res = &pci_test_iomem_resource;
+
+ pci_scan_child_bus(bus);
+ pci_set_host_bridge_release(to_pci_host_bridge(bus->bridge),
+ pci_test_root_release_info, info);
+
+ return bus;
+
+out_release_info:
+ __pci_test_root_release_info(info);
+
+ return NULL;
+}
+
+static struct pci_bus *pci_test_scan_root(struct test_pci_root *root)
+{
+ struct pci_root_info_ext *info_ext;
+ struct pci_bus *bus;
+
+ info_ext = kzalloc(sizeof(*info_ext), GFP_KERNEL);
+ if (!info_ext)
+ return NULL;
+
+ info_ext->sd.domain = root->segment;
+ bus = pci_test_root_create(root, &pci_test_root_ops, &info_ext->common,
+ &info_ext->sd);
+
+ return bus;
+}
+
+static void pci_bus_disable_match_devices(struct pci_bus *bus)
+{
+ struct pci_dev *dev;
+ struct pci_bus *child;
+
+ list_for_each_entry(dev, &bus->devices, bus_list)
+ dev->match_driver = -1;
+
+ list_for_each_entry(dev, &bus->devices, bus_list) {
+ child = dev->subordinate;
+ if (child)
+ pci_bus_disable_match_devices(child);
+ }
+}
+
+static char *data_file;
+static int domain_nr_offset = 0xf000;
+static char *mask_file;
+static bool survey_first = true;
+module_param(data_file, charp, 0444);
+module_param(domain_nr_offset, int, 0444);
+module_param(mask_file, charp, 0444);
+module_param(survey_first, bool, 0444);
+MODULE_PARM_DESC(data_file, "data file for pci root bus res and register info");
+MODULE_PARM_DESC(domain_nr_offset, "offset for change domain_nr in data file");
+MODULE_PARM_DESC(mask_file, "mask file for register mask info");
+MODULE_PARM_DESC(survey_first, "survey BARs in register (from firmware) and reserve them at first");
+
+#ifdef CONFIG_PROC_FS
+static struct resource *next_resource(struct resource *p, bool sibling_only)
+{
+ /* Caller wants to traverse through siblings only */
+ if (sibling_only)
+ return p->sibling;
+
+ if (p->child)
+ return p->child;
+ while (!p->sibling && p->parent)
+ p = p->parent;
+ return p->sibling;
+}
+
+static void *r_next(struct seq_file *m, void *v, loff_t *pos)
+{
+ struct resource *p = v;
+ (*pos)++;
+ return (void *)next_resource(p, false);
+}
+
+enum { MAX_IORES_LEVEL = 5 };
+
+static void *r_start(struct seq_file *m, loff_t *pos)
+{
+ struct resource *p = m->private;
+ loff_t l = 0;
+
+ for (p = p->child; p && l < *pos; p = r_next(m, p, &l))
+ ;
+ return p;
+}
+
+static void r_stop(struct seq_file *m, void *v)
+{
+}
+
+static int r_show(struct seq_file *m, void *v)
+{
+ struct resource *root = m->private;
+ struct resource *r = v, *p;
+ int width = root->end < 0x10000 ? 4 : 8;
+ int depth;
+
+ for (depth = 0, p = r; depth < MAX_IORES_LEVEL; depth++, p = p->parent)
+ if (p->parent == root)
+ break;
+ seq_printf(m, "%*s%0*llx-%0*llx : %s\n",
+ depth * 2, "",
+ width, (unsigned long long) r->start,
+ width, (unsigned long long) r->end,
+ r->name ? r->name : "<BAD>");
+ return 0;
+}
+
+static const struct seq_operations resource_op = {
+ .start = r_start,
+ .next = r_next,
+ .stop = r_stop,
+ .show = r_show,
+};
+
+static int ioports_open(struct inode *inode, struct file *file)
+{
+ int res = seq_open(file, &resource_op);
+
+ if (!res) {
+ struct seq_file *m = file->private_data;
+
+ m->private = &pci_test_ioport_resource;
+ }
+ return res;
+}
+
+static int iomem_open(struct inode *inode, struct file *file)
+{
+ int res = seq_open(file, &resource_op);
+
+ if (!res) {
+ struct seq_file *m = file->private_data;
+
+ m->private = &pci_test_iomem_resource;
+ }
+ return res;
+}
+
+static const struct file_operations proc_ioports_operations = {
+ .open = ioports_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = seq_release,
+};
+
+static const struct file_operations proc_iomem_operations = {
+ .open = iomem_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = seq_release,
+};
+
+struct proc_dir_entry *ioports_proc;
+struct proc_dir_entry *iomem_proc;
+
+static void ioresources_init(void)
+{
+ ioports_proc = proc_create("ioports_test", 0, NULL,
+ &proc_ioports_operations);
+ iomem_proc = proc_create("iomem_test", 0, NULL,
+ &proc_iomem_operations);
+}
+
+static void ioresources_exit(void)
+{
+ proc_remove(ioports_proc);
+ proc_remove(iomem_proc);
+}
+#else
+static void ioresources_init(void)
+{
+}
+static void ioresources_exit(void)
+{
+}
+#endif /* CONFIG_PROC_FS */
+
+static __init int pci_test_init(void)
+{
+ struct test_pci_root *root;
+
+ if (!data_file)
+ return 0;
+
+ pr_info("data file: %s domain_nr_offset: %04x\n",
+ data_file, domain_nr_offset);
+
+ if (test_pci_init(data_file, domain_nr_offset, mask_file))
+ return 0;
+
+ list_for_each_entry(root, &test_pci_root_list, node) {
+ root->bus = pci_test_scan_root(root);
+ if (!root->bus)
+ continue;
+
+ if (survey_first)
+ pcibios_resource_survey_bus(root->bus);
+
+ pci_assign_unassigned_root_bus_resources(root->bus);
+ pci_bus_disable_match_devices(root->bus);
+ pci_bus_add_devices(root->bus);
+ }
+
+ ioresources_init();
+
+ return 0;
+}
+
+static void __exit pci_test_exit(void)
+{
+ struct test_pci_root *root;
+
+ list_for_each_entry(root, &test_pci_root_list, node)
+ if (root->bus) {
+ pci_stop_root_bus(root->bus);
+ pci_remove_root_bus(root->bus);
+ }
+
+ ioresources_exit();
+
+ test_pci_free();
+}
+
+module_init(pci_test_init);
+module_exit(pci_test_exit);
+
+MODULE_AUTHOR("Yinghai Lu <yinghai@kernel.org>");
+MODULE_DESCRIPTION("PCI test for resource allocation code");
+MODULE_LICENSE("GPL v2");
--
2.9.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 06/10] PCI: PCI_TEST simple data
2017-08-05 6:37 [PATCH 00/10] PCI: pci resource allocation test module Yinghai Lu
` (4 preceding siblings ...)
2017-08-05 6:37 ` [PATCH 05/10] PCI: Add PCI_TEST module for resource allocation Yinghai Lu
@ 2017-08-05 6:37 ` Yinghai Lu
2017-08-05 6:37 ` [PATCH 07/10] PCI: PCI_TEST data from x5-8 Yinghai Lu
2017-08-05 6:37 ` [PATCH 08/10] PCI: PCI_TEST data from x5-8 with zeroed bus number Yinghai Lu
7 siblings, 0 replies; 9+ messages in thread
From: Yinghai Lu @ 2017-08-05 6:37 UTC (permalink / raw)
To: Bjorn Helgaas; +Cc: Linus Torvalds, linux-pci, linux-kernel, Yinghai Lu
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
---
drivers/pci/pci_test_data.txt | 24 ++++++++++++++++++++++++
drivers/pci/pci_test_mask.txt | 5 +++++
2 files changed, 29 insertions(+)
create mode 100644 drivers/pci/pci_test_data.txt
create mode 100644 drivers/pci/pci_test_mask.txt
diff --git a/drivers/pci/pci_test_data.txt b/drivers/pci/pci_test_data.txt
new file mode 100644
index 0000000..a3cfd5d
--- /dev/null
+++ b/drivers/pci/pci_test_data.txt
@@ -0,0 +1,24 @@
+pci_bus 0000:00: root bus resource [bus 00-fe]
+pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7]
+pci_bus 0000:00: root bus resource [io 0x0d00-0xffff]
+pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff]
+pci_bus 0000:00: root bus resource [mem 0xbfa00000-0xfebfffff]
+pci_bus 0000:00: root bus resource [mem 0xfed40000-0xfed4bfff]
+
+00:1a.0 0c03: 8086:1c2d (rev 04) (prog-if 20 [EHCI])
+00: 86 80 2d 1c 06 00 90 02 04 20 03 0c 00 00 00 00
+10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 cf 21
+30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 00 00
+40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+50: 01 58 c2 c9 00 00 00 00 0a 98 a0 20 00 00 00 00
+60: 20 20 a7 07 00 00 00 00 01 00 00 00 00 00 08 c0
+70: 00 00 df 3f 00 00 00 00 00 00 00 00 00 00 00 00
+80: 00 00 80 00 11 88 0c 93 30 0d 00 24 00 00 00 00
+90: 00 00 00 00 00 00 00 00 13 00 06 03 00 00 00 00
+a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+d0: 00 00 00 00 00 aa ff 00 00 00 00 00 00 00 00 00
+e0: 00 00 00 00 01 44 00 9c 06 40 0b 28 b8 a1 18 09
+f0: 00 00 00 00 88 85 80 00 87 0f 06 08 08 17 5b 20
diff --git a/drivers/pci/pci_test_mask.txt b/drivers/pci/pci_test_mask.txt
new file mode 100644
index 0000000..824afab
--- /dev/null
+++ b/drivers/pci/pci_test_mask.txt
@@ -0,0 +1,5 @@
+mask: 8086:1c2d : 1:rw 0: readonly
+00: 00 00 00 00 ff ff ff 02 04 20 03 0c 00 00 00 00
+10: 00 fc ff ff 00 00 00 00 00 00 00 00 00 00 00 00
+20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
--
2.9.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 07/10] PCI: PCI_TEST data from x5-8
2017-08-05 6:37 [PATCH 00/10] PCI: pci resource allocation test module Yinghai Lu
` (5 preceding siblings ...)
2017-08-05 6:37 ` [PATCH 06/10] PCI: PCI_TEST simple data Yinghai Lu
@ 2017-08-05 6:37 ` Yinghai Lu
2017-08-05 6:37 ` [PATCH 08/10] PCI: PCI_TEST data from x5-8 with zeroed bus number Yinghai Lu
7 siblings, 0 replies; 9+ messages in thread
From: Yinghai Lu @ 2017-08-05 6:37 UTC (permalink / raw)
To: Bjorn Helgaas; +Cc: Linus Torvalds, linux-pci, linux-kernel, Yinghai Lu
data is from dmesg, and lspci -vvxxxx
mask is extract from lspci -vvxxxx and only have bit set for BAR sizing.
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
---
drivers/pci/pci_test_data_x5-8.txt | 5656 ++++++++++++++++++++++++++++++++++++
drivers/pci/pci_test_mask_x5-8.txt | 176 ++
2 files changed, 5832 insertions(+)
create mode 100644 drivers/pci/pci_test_data_x5-8.txt
create mode 100644 drivers/pci/pci_test_mask_x5-8.txt
diff --git a/drivers/pci/pci_test_data_x5-8.txt b/drivers/pci/pci_test_data_x5-8.txt
new file mode 100644
index 0000000..d41d37e
--- /dev/null
+++ b/drivers/pci/pci_test_data_x5-8.txt
@@ -0,0 +1,5656 @@
+pci_bus 0000:00: root bus resource [bus 00-1e]
+pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7 window]
+pci_bus 0000:00: root bus resource [io 0x1000-0x5fff window]
+pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window]
+pci_bus 0000:00: root bus resource [mem 0xfed8c000-0xfedfffff window]
+pci_bus 0000:00: root bus resource [mem 0x90000000-0x9fffbfff window]
+pci_bus 0000:00: root bus resource [mem 0x380000000000-0x381fffffffff window]
+
+00:00.0 Host bridge: Intel Corporation Xeon E5 v3/Core i7 DMI2 (rev 04)
+ Subsystem: Oracle/SUN Device 4800
+ Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Capabilities: [90] Express (v2) Root Port (Slot-), MSI 00
+ DevCap: MaxPayload 128 bytes, PhantFunc 0
+ ExtTag- RBE+
+ DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
+ MaxPayload 128 bytes, MaxReadReq 128 bytes
+ DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
+ LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM not supported, Exit Latency L0s <512ns, L1 <16us
+ ClockPM- Surprise+ LLActRep+ BwNot+ ASPMOptComp+
+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk-
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed unknown, Width x0, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt-
+ RootCtl: ErrCorrectable+ ErrNon-Fatal+ ErrFatal+ PMEIntEna- CRSVisible-
+ RootCap: CRSVisible-
+ RootSta: PME ReqID 0000, PMEStatus- PMEPending-
+ DevCap2: Completion Timeout: Range BCD, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd-
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd-
+ LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance De-emphasis: -6dB
+ LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
+ EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
+ Capabilities: [e0] Power Management version 3
+ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
+ Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [100 v1] Vendor Specific Information: ID=0002 Rev=0 Len=00c <?>
+ Capabilities: [144 v1] Vendor Specific Information: ID=0004 Rev=1 Len=03c <?>
+ Capabilities: [1d0 v1] Vendor Specific Information: ID=0003 Rev=1 Len=00a <?>
+ Capabilities: [280 v1] Vendor Specific Information: ID=0005 Rev=3 Len=018 <?>
+ Capabilities: [298 v1] Vendor Specific Information: ID=0007 Rev=0 Len=024 <?>
+ Capabilities: [300 v1] Vendor Specific Information: ID=0008 Rev=0 Len=038 <?>
+00: 86 80 00 2f 40 05 10 00 04 00 00 06 10 00 00 00
+10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+20: 00 00 00 00 00 00 00 00 00 00 00 00 8e 10 00 48
+30: 00 00 00 00 90 00 00 00 00 00 00 00 00 00 00 00
+40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+50: 00 e0 ff 9f 00 00 00 00 00 00 00 00 00 00 00 00
+60: 05 90 02 01 00 00 00 00 00 00 00 00 00 00 00 00
+70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+90: 10 e0 42 00 00 80 00 00 00 00 00 00 41 30 7a 00
+a0: 00 00 00 00 00 00 00 00 00 00 00 00 07 00 00 00
+b0: 00 00 00 00 9e 13 00 00 00 00 00 00 06 00 00 00
+c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+e0: 01 00 03 00 08 00 00 00 00 00 00 00 00 00 00 00
+f0: 0f 00 00 00 00 00 00 00 09 00 00 00 00 00 00 00
+100: 0b 00 41 14 02 00 c0 00 07 30 00 00 00 00 00 00
+110: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+120: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+130: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+
+00:02.0 PCI bridge: Intel Corporation Xeon E5 v3/Core i7 PCI Express Root Port 2 (rev 04) (prog-if 00 [Normal decode])
+ DeviceName: /SYS/DPCC0/PCIE1
+ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0, Cache Line Size: 64 bytes
+ Interrupt: pin A routed to IRQ 26
+ Bus: primary=00, secondary=01, subordinate=02, sec-latency=0
+ I/O behind bridge: 00005000-00005fff
+ Memory behind bridge: 9f400000-9f5fffff
+ Prefetchable memory behind bridge: 0000381ff8100000-0000381ff89fffff
+ Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
+ BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
+ PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
+ Capabilities: [40] Subsystem: Oracle/SUN Device 4800
+ Capabilities: [60] MSI: Enable+ Count=1/2 Maskable+ 64bit-
+ Address: fee00258 Data: 0000
+ Masking: 00000002 Pending: 00000000
+ Capabilities: [90] Express (v2) Root Port (Slot+), MSI 00
+ DevCap: MaxPayload 256 bytes, PhantFunc 0
+ ExtTag+ RBE+
+ DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
+ MaxPayload 256 bytes, MaxReadReq 128 bytes
+ DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
+ LnkCap: Port #3, Speed 8GT/s, Width x16, ASPM not supported, Exit Latency L0s <512ns, L1 <16us
+ ClockPM- Surprise+ LLActRep+ BwNot+ ASPMOptComp+
+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
+ SltCap: AttnBtn+ PwrCtrl+ MRL- AttnInd+ PwrInd+ HotPlug+ Surprise-
+ Slot #1, PowerLimit 25.000W; Interlock- NoCompl-
+ SltCtl: Enable: AttnBtn+ PwrFlt- MRL- PresDet- CmdCplt+ HPIrq+ LinkChg+
+ Control: AttnInd Off, PwrInd On, Power- Interlock-
+ SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
+ Changed: MRL- PresDet- LinkState-
+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible+
+ RootCap: CRSVisible+
+ RootSta: PME ReqID 0000, PMEStatus- PMEPending-
+ DevCap2: Completion Timeout: Range BCD, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd+
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd+
+ LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance De-emphasis: -6dB
+ LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
+ EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
+ Capabilities: [e0] Power Management version 3
+ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
+ Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [100 v1] Vendor Specific Information: ID=0002 Rev=0 Len=00c <?>
+ Capabilities: [110 v1] Access Control Services
+ ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans-
+ ACSCtl: SrcValid+ TransBlk- ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans-
+ Capabilities: [148 v1] Advanced Error Reporting
+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-
+ UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO+ CmpltAbrt+ UnxCmplt+ RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+ AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-
+ Capabilities: [1d0 v1] Vendor Specific Information: ID=0003 Rev=1 Len=00a <?>
+ Capabilities: [250 v1] #19
+ Capabilities: [280 v1] Vendor Specific Information: ID=0005 Rev=3 Len=018 <?>
+ Capabilities: [298 v1] Vendor Specific Information: ID=0007 Rev=0 Len=024 <?>
+ Capabilities: [300 v1] Vendor Specific Information: ID=0008 Rev=0 Len=038 <?>
+ Kernel driver in use: pcieport
+00: 86 80 04 2f 47 05 10 00 04 00 04 06 10 00 01 00
+10: 00 00 00 00 00 00 00 00 00 01 02 00 50 50 00 20
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+
+00:03.0 PCI bridge: Intel Corporation Xeon E5 v3/Core i7 PCI Express Root Port 3 (rev 04) (prog-if 00 [Normal decode])
+ DeviceName: /SYS/SMOD/HBA
+ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0, Cache Line Size: 64 bytes
+ Interrupt: pin A routed to IRQ 61
+ Bus: primary=00, secondary=03, subordinate=03, sec-latency=0
+ I/O behind bridge: 00004000-00004fff
+ Memory behind bridge: 9ee00000-9f0fffff
+ Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
+ BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
+ PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
+ Capabilities: [40] Subsystem: Oracle/SUN Device 4800
+ Capabilities: [60] MSI: Enable+ Count=1/2 Maskable+ 64bit-
+ Address: fee00318 Data: 0000
+ Masking: 00000002 Pending: 00000000
+ Capabilities: [90] Express (v2) Root Port (Slot-), MSI 00
+ DevCap: MaxPayload 256 bytes, PhantFunc 0
+ ExtTag+ RBE+
+ DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
+ MaxPayload 256 bytes, MaxReadReq 128 bytes
+ DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
+ LnkCap: Port #7, Speed 8GT/s, Width x8, ASPM not supported, Exit Latency L0s <512ns, L1 <16us
+ ClockPM- Surprise+ LLActRep+ BwNot+ ASPMOptComp+
+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 8GT/s, Width x8, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible+
+ RootCap: CRSVisible+
+ RootSta: PME ReqID 0000, PMEStatus- PMEPending-
+ DevCap2: Completion Timeout: Range BCD, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd+
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd+
+ LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance De-emphasis: -6dB
+ LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete+, EqualizationPhase1+
+ EqualizationPhase2+, EqualizationPhase3+, LinkEqualizationRequest+
+ Capabilities: [e0] Power Management version 3
+ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
+ Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [100 v1] Vendor Specific Information: ID=0002 Rev=0 Len=00c <?>
+ Capabilities: [110 v1] Access Control Services
+ ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans-
+ ACSCtl: SrcValid+ TransBlk- ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans-
+ Capabilities: [148 v1] Advanced Error Reporting
+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-
+ UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO+ CmpltAbrt+ UnxCmplt+ RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+ AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-
+ Capabilities: [1d0 v1] Vendor Specific Information: ID=0003 Rev=1 Len=00a <?>
+ Capabilities: [250 v1] #19
+ Capabilities: [280 v1] Vendor Specific Information: ID=0005 Rev=3 Len=018 <?>
+ Capabilities: [298 v1] Vendor Specific Information: ID=0007 Rev=0 Len=024 <?>
+ Capabilities: [300 v1] Vendor Specific Information: ID=0008 Rev=0 Len=038 <?>
+ Kernel driver in use: pcieport
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+
+00:03.2 PCI bridge: Intel Corporation Xeon E5 v3/Core i7 PCI Express Root Port 3 (rev 04) (prog-if 00 [Normal decode])
+ DeviceName: /SYS/DPCC0/PCIE2
+ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0, Cache Line Size: 64 bytes
+ Interrupt: pin A routed to IRQ 27
+ Bus: primary=00, secondary=04, subordinate=04, sec-latency=0
+ I/O behind bridge: 00001000-00001fff
+ Memory behind bridge: 9f600000-9f7fffff
+ Prefetchable memory behind bridge: 0000380000000000-000038020bffffff
+ Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
+ BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
+ PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
+ Capabilities: [40] Subsystem: Oracle/SUN Device 4800
+ Capabilities: [60] MSI: Enable+ Count=1/2 Maskable+ 64bit-
+ Address: fee00278 Data: 0000
+ Masking: 00000002 Pending: 00000000
+ Capabilities: [90] Express (v2) Root Port (Slot+), MSI 00
+ DevCap: MaxPayload 256 bytes, PhantFunc 0
+ ExtTag- RBE+
+ DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
+ MaxPayload 256 bytes, MaxReadReq 128 bytes
+ DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
+ LnkCap: Port #9, Speed 8GT/s, Width x8, ASPM not supported, Exit Latency L0s <512ns, L1 <16us
+ ClockPM- Surprise+ LLActRep+ BwNot+ ASPMOptComp+
+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 8GT/s, Width x8, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
+ SltCap: AttnBtn+ PwrCtrl+ MRL- AttnInd+ PwrInd+ HotPlug+ Surprise-
+ Slot #2, PowerLimit 25.000W; Interlock- NoCompl-
+ SltCtl: Enable: AttnBtn+ PwrFlt- MRL- PresDet- CmdCplt+ HPIrq+ LinkChg+
+ Control: AttnInd Off, PwrInd On, Power- Interlock-
+ SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
+ Changed: MRL- PresDet- LinkState-
+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible+
+ RootCap: CRSVisible+
+ RootSta: PME ReqID 0000, PMEStatus- PMEPending-
+ DevCap2: Completion Timeout: Range BCD, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd+
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd+
+ LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance De-emphasis: -6dB
+ LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete+, EqualizationPhase1+
+ EqualizationPhase2+, EqualizationPhase3+, LinkEqualizationRequest-
+ Capabilities: [e0] Power Management version 3
+ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
+ Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [100 v1] Vendor Specific Information: ID=0002 Rev=0 Len=00c <?>
+ Capabilities: [110 v1] Access Control Services
+ ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans-
+ ACSCtl: SrcValid+ TransBlk- ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans-
+ Capabilities: [148 v1] Advanced Error Reporting
+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UEMsk: DLP- SDES+ TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-
+ UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO+ CmpltAbrt+ UnxCmplt+ RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+ AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-
+ Capabilities: [1d0 v1] Vendor Specific Information: ID=0003 Rev=1 Len=00a <?>
+ Capabilities: [250 v1] #19
+ Capabilities: [280 v1] Vendor Specific Information: ID=0005 Rev=3 Len=018 <?>
+ Capabilities: [298 v1] Vendor Specific Information: ID=0007 Rev=0 Len=024 <?>
+ Capabilities: [300 v1] Vendor Specific Information: ID=0008 Rev=0 Len=038 <?>
+ Kernel driver in use: pcieport
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+
+00:05.0 System peripheral: Intel Corporation Xeon E5 v3/Core i7 Address Map, VTd_Misc, System Management (rev 04)
+ Subsystem: Oracle/SUN Device 4800
+ Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Capabilities: [40] Express (v2) Root Complex Integrated Endpoint, MSI 00
+ DevCap: MaxPayload 128 bytes, PhantFunc 0
+ ExtTag- RBE-
+ DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
+ MaxPayload 128 bytes, MaxReadReq 128 bytes
+ DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
+ DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR-, OBFF Not Supported
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
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+
+00:05.1 System peripheral: Intel Corporation Xeon E5 v3/Core i7 Hot Plug (rev 04)
+ Subsystem: Oracle/SUN Device 4800
+ Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Capabilities: [40] Express (v1) Root Complex Integrated Endpoint, MSI 00
+ DevCap: MaxPayload 128 bytes, PhantFunc 0
+ ExtTag- RBE-
+ DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
+ MaxPayload 128 bytes, MaxReadReq 128 bytes
+ DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
+ Capabilities: [80] MSI: Enable- Count=1/1 Maskable- 64bit+
+ Address: 0000000000000000 Data: 0000
+ Capabilities: [100 v1] Vendor Specific Information: ID=0006 Rev=1 Len=010 <?>
+ Capabilities: [110 v1] Vendor Specific Information: ID=0006 Rev=1 Len=010 <?>
+ Capabilities: [120 v1] Vendor Specific Information: ID=0006 Rev=1 Len=010 <?>
+ Capabilities: [130 v1] Vendor Specific Information: ID=0006 Rev=1 Len=010 <?>
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+
+00:05.2 System peripheral: Intel Corporation Xeon E5 v3/Core i7 RAS, Control Status and Global Errors (rev 04)
+ Subsystem: Oracle/SUN Device 4800
+ Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Capabilities: [40] Express (v2) Root Complex Integrated Endpoint, MSI 00
+ DevCap: MaxPayload 128 bytes, PhantFunc 0
+ ExtTag- RBE-
+ DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
+ RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
+ MaxPayload 128 bytes, MaxReadReq 128 bytes
+ DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
+ DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR-, OBFF Not Supported
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
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+
+00:05.4 PIC: Intel Corporation Xeon E5 v3/Core i7 I/O APIC (rev 04) (prog-if 20 [IO(X)-APIC])
+ Subsystem: Oracle/SUN Device 4800
+ Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0, Cache Line Size: 64 bytes
+ Region 0: Memory at 9f303000 (32-bit, non-prefetchable) [size=4K]
+ Capabilities: [44] Express (v1) Root Complex Integrated Endpoint, MSI 00
+ DevCap: MaxPayload 128 bytes, PhantFunc 0
+ ExtTag- RBE-
+ DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
+ MaxPayload 128 bytes, MaxReadReq 128 bytes
+ DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
+ Capabilities: [e0] Power Management version 3
+ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
+ Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
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+
+00:11.0 PCI bridge: Intel Corporation C600/X79 series chipset PCI Express Virtual Root Port (rev 06) (prog-if 00 [Normal decode])
+ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0, Cache Line Size: 64 bytes
+ Interrupt: pin A routed to IRQ 63
+ Bus: primary=00, secondary=05, subordinate=05, sec-latency=0
+ Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
+ BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
+ PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
+ Capabilities: [40] Express (v2) Root Port (Slot-), MSI 00
+ DevCap: MaxPayload 128 bytes, PhantFunc 0
+ ExtTag- RBE+
+ DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
+ MaxPayload 128 bytes, MaxReadReq 512 bytes
+ DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
+ LnkCap: Port #17, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <64ns, L1 <1us
+ ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk-
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible-
+ RootCap: CRSVisible-
+ RootSta: PME ReqID 0000, PMEStatus- PMEPending-
+ DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR-, OBFF Not Supported ARIFwd+
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd-
+ LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance De-emphasis: -6dB
+ LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
+ EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
+ Capabilities: [80] Power Management version 3
+ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
+ Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [88] Subsystem: Oracle/SUN Device 4800
+ Capabilities: [90] MSI: Enable+ Count=1/1 Maskable- 64bit-
+ Address: fee00358 Data: 0000
+ Capabilities: [100 v1] Advanced Error Reporting
+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UEMsk: DLP- SDES- TLP+ FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP+ ECRC- UnsupReq+ ACSViol+
+ UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+ AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-
+ Capabilities: [138 v1] Access Control Services
+ ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans+
+ ACSCtl: SrcValid+ TransBlk- ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans-
+ Kernel driver in use: pcieport
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+f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+
+00:1a.0 USB controller: Intel Corporation C600/X79 series chipset USB2 Enhanced Host Controller #2 (rev 06) (prog-if 20 [EHCI])
+ Subsystem: Oracle/SUN Device 4800
+ Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
+ Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0
+ Interrupt: pin A routed to IRQ 16
+ Region 0: Memory at 9f301000 (32-bit, non-prefetchable) [size=1K]
+ Capabilities: [50] Power Management version 2
+ Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
+ Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [58] Debug port: BAR=1 offset=00a0
+ Capabilities: [98] PCI Advanced Features
+ AFCap: TP+ FLR+
+ AFCtrl: FLR-
+ AFStatus: TP-
+ Kernel driver in use: ehci-pci
+00: 86 80 2d 1d 46 01 90 02 06 20 03 0c 00 00 00 00
+10: 00 10 30 9f 00 00 00 00 00 00 00 00 00 00 00 00
+20: 00 00 00 00 00 00 00 00 00 00 00 00 8e 10 00 48
+30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 00 00
+40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+50: 01 58 c2 c9 00 00 00 00 0a 98 a0 20 00 00 00 00
+60: 20 20 ff 07 00 00 00 00 01 00 00 01 00 00 00 c0
+70: 00 00 df 3f 00 00 00 00 00 00 00 00 00 00 00 00
+80: 00 00 80 00 11 88 0c 93 30 0d 00 24 00 00 00 00
+90: 00 00 00 00 00 00 00 00 13 00 06 03 00 00 00 00
+a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+d0: 00 00 00 00 00 aa ff 00 00 00 00 00 00 00 00 00
+e0: 00 00 00 00 22 40 00 00 01 0a 00 05 44 4d 43 d0
+f0: 00 00 00 00 88 85 80 00 87 0f 08 08 08 17 5b 20
+
+00:1c.0 PCI bridge: Intel Corporation C600/X79 series chipset PCI Express Root Port 1 (rev b6) (prog-if 00 [Normal decode])
+ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0, Cache Line Size: 64 bytes
+ Interrupt: pin A routed to IRQ 64
+ Bus: primary=00, secondary=06, subordinate=07, sec-latency=0
+ I/O behind bridge: 00003000-00003fff
+ Memory behind bridge: 9f100000-9f1fffff
+ Prefetchable memory behind bridge: 0000381ff8000000-0000381ff80fffff
+ Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
+ BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
+ PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
+ Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00
+ DevCap: MaxPayload 128 bytes, PhantFunc 0
+ ExtTag- RBE+
+ DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
+ MaxPayload 128 bytes, MaxReadReq 128 bytes
+ DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
+ LnkCap: Port #1, Speed 5GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <512ns, L1 <16us
+ ClockPM- Surprise- LLActRep+ BwNot- ASPMOptComp-
+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- CommClk+
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt+
+ SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
+ Slot #0, PowerLimit 25.000W; Interlock- NoCompl+
+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
+ Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
+ SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
+ Changed: MRL- PresDet- LinkState-
+ RootCtl: ErrCorrectable+ ErrNon-Fatal+ ErrFatal+ PMEIntEna+ CRSVisible-
+ RootCap: CRSVisible-
+ RootSta: PME ReqID 0000, PMEStatus- PMEPending-
+ DevCap2: Completion Timeout: Range BC, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd-
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd-
+ LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance De-emphasis: -6dB
+ LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
+ EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
+ Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit-
+ Address: fee00378 Data: 0000
+ Capabilities: [90] Subsystem: Oracle/SUN Device 4800
+ Capabilities: [a0] Power Management version 2
+ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
+ Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
+ Kernel driver in use: pcieport
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+f20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+00:1c.7 PCI bridge: Intel Corporation C600/X79 series chipset PCI Express Root Port 8 (rev b6) (prog-if 00 [Normal decode])
+ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0, Cache Line Size: 64 bytes
+ Interrupt: pin D routed to IRQ 28
+ Bus: primary=00, secondary=08, subordinate=08, sec-latency=0
+ Memory behind bridge: 90000000-91bfffff
+ Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
+ BridgeCtl: Parity- SERR- NoISA- VGA+ MAbort- >Reset- FastB2B-
+ PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
+ Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00
+ DevCap: MaxPayload 128 bytes, PhantFunc 0
+ ExtTag- RBE+
+ DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported-
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
+ MaxPayload 128 bytes, MaxReadReq 128 bytes
+ DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
+ LnkCap: Port #8, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <512ns, L1 <16us
+ ClockPM- Surprise- LLActRep+ BwNot- ASPMOptComp-
+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
+ SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
+ Slot #0, PowerLimit 10.000W; Interlock- NoCompl+
+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
+ Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
+ SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
+ Changed: MRL- PresDet- LinkState-
+ RootCtl: ErrCorrectable+ ErrNon-Fatal+ ErrFatal+ PMEIntEna+ CRSVisible-
+ RootCap: CRSVisible-
+ RootSta: PME ReqID 0000, PMEStatus- PMEPending-
+ DevCap2: Completion Timeout: Range BC, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd-
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd-
+ LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance De-emphasis: -6dB
+ LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1-
+ EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
+ Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit-
+ Address: fee002d8 Data: 0000
+ Capabilities: [90] Subsystem: Oracle/SUN Device 4800
+ Capabilities: [a0] Power Management version 2
+ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
+ Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
+ Kernel driver in use: pcieport
+00: 86 80 1e 1d 47 05 10 00 b6 00 04 06 10 00 81 00
+10: 00 00 00 00 00 00 00 00 00 08 08 00 f0 00 00 00
+20: 00 90 b0 91 f1 ff 01 00 00 00 00 00 00 00 00 00
+30: 00 00 00 00 40 00 00 00 00 00 00 00 05 04 18 00
+40: 10 80 42 01 00 80 00 00 07 00 10 00 12 3c 12 08
+50: 40 00 11 70 00 b2 04 00 00 00 40 00 0f 00 00 00
+60: 00 00 00 00 16 00 00 00 00 00 00 00 00 00 00 00
+70: 02 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00
+80: 05 90 01 00 d8 02 e0 fe 00 00 00 00 00 00 00 00
+90: 0d a0 00 00 8e 10 00 48 00 00 00 00 00 00 00 00
+a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00
+b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+d0: 00 00 00 01 00 0b 00 00 00 80 11 01 00 00 00 00
+e0: 00 03 00 00 00 00 00 00 01 00 00 00 00 00 00 00
+f0: 00 00 00 00 00 00 00 00 87 0f 08 08 00 00 00 00
+100: 00 00 00 00 00 80 00 00 00 80 10 00 11 00 06 00
+110: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+120: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+130: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+140: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+150: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+160: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+170: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+180: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+190: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+1a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+1b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+1c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+1d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+1e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+1f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+200: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+210: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+220: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+230: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+240: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+250: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+260: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+270: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+280: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+290: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+2a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+2b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+2c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+2e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+2f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+300: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+310: 00 00 00 00 1b 36 3a 74 00 00 14 14 31 17 42 00
+320: 5b 60 09 00 20 20 00 0a 5a 19 b8 04 59 09 c8 05
+330: 16 00 00 28 bc b5 bc 4a 00 00 00 00 74 4c 85 00
+340: e4 02 92 00 f4 02 9a 00 30 00 0c 00 6b 09 c8 00
+350: 6c 09 c9 00 01 00 08 00 00 00 00 00 00 00 00 00
+360: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+3a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+850: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+860: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+b30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+b40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+b50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+b60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+b70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+b80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+b90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+d00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+d10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+d20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+ec0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ed0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ee0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+f00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+f20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+f70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+00:1d.0 USB controller: Intel Corporation C600/X79 series chipset USB2 Enhanced Host Controller #1 (rev 06) (prog-if 20 [EHCI])
+ Subsystem: Oracle/SUN Device 4800
+ Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
+ Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0
+ Interrupt: pin A routed to IRQ 23
+ Region 0: Memory at 9f300000 (32-bit, non-prefetchable) [size=1K]
+ Capabilities: [50] Power Management version 2
+ Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
+ Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [58] Debug port: BAR=1 offset=00a0
+ Capabilities: [98] PCI Advanced Features
+ AFCap: TP+ FLR+
+ AFCtrl: FLR-
+ AFStatus: TP-
+ Kernel driver in use: ehci-pci
+00: 86 80 26 1d 46 01 90 02 06 20 03 0c 00 00 00 00
+10: 00 00 30 9f 00 00 00 00 00 00 00 00 00 00 00 00
+20: 00 00 00 00 00 00 00 00 00 00 00 00 8e 10 00 48
+30: 00 00 00 00 50 00 00 00 00 00 00 00 07 01 00 00
+40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+50: 01 58 c2 c9 00 00 00 00 0a 98 a0 20 00 00 00 00
+60: 20 20 ff 07 00 00 00 00 01 00 00 01 00 00 08 c0
+70: 00 00 df 3f 00 00 00 00 00 00 00 00 00 00 00 00
+80: 00 00 80 00 11 88 0c 93 30 0d 00 24 00 00 00 00
+90: 00 00 00 00 00 00 00 00 13 00 06 03 00 00 00 00
+a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+d0: 00 00 00 00 00 aa ff 00 00 00 00 00 00 00 00 00
+e0: 00 00 00 00 00 e4 45 18 41 04 00 02 04 b0 f3 60
+f0: 00 00 00 00 88 85 80 00 87 0f 08 08 08 17 5b 20
+
+00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev a6) (prog-if 01 [Subtractive decode])
+ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0
+ Bus: primary=00, secondary=09, subordinate=09, sec-latency=32
+ Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
+ BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
+ PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
+ Capabilities: [50] Subsystem: Oracle/SUN Device 4800
+00: 86 80 4e 24 47 01 10 00 a6 01 04 06 00 00 01 00
+10: 00 00 00 00 00 00 00 00 00 09 09 20 f0 00 80 22
+20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00
+30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 13 00
+40: 00 00 00 00 00 00 00 00 00 00 00 00 00 12 00 00
+50: 0d 00 00 00 8e 10 00 48 00 00 00 00 00 00 00 00
+60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f0: 00 00 00 00 00 00 00 00 87 0f 08 08 00 00 00 00
+
+00:1f.0 ISA bridge: Intel Corporation C600/X79 series chipset LPC Controller (rev 06)
+ Subsystem: Oracle/SUN Device 4800
+ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0
+ Capabilities: [e0] Vendor Specific Information: Len=0c <?>
+00: 86 80 41 1d 47 01 10 02 06 00 01 06 00 00 80 00
+10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+20: 00 00 00 00 00 00 00 00 00 00 00 00 8e 10 00 48
+30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00
+40: 01 04 00 00 80 00 00 00 01 05 00 00 10 00 00 00
+50: f8 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+60: 8b 8a 83 85 90 00 00 00 80 80 80 87 ff f0 00 00
+70: 78 f0 78 f0 78 f0 78 f0 78 f0 78 f0 78 f0 78 f0
+80: 10 00 0f 34 00 00 00 00 81 0c 3c 00 01 06 00 00
+90: 00 00 00 00 00 05 00 00 00 00 00 00 00 00 00 00
+a0: 10 0a 20 00 09 18 06 00 00 47 00 00 00 00 00 80
+b0: 00 00 00 00 00 00 00 00 00 0c 00 00 00 00 00 00
+c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+d0: 33 22 11 00 67 45 00 00 cf ff 00 00 2a 00 00 00
+e0: 09 00 0c 10 10 00 00 00 13 18 fc 0c 00 00 00 00
+f0: 01 c0 d1 fe 00 00 00 00 87 0f 08 08 00 00 00 00
+
+00:1f.3 SMBus: Intel Corporation C600/X79 series chipset SMBus Host Controller (rev 06)
+ Subsystem: Oracle/SUN Device 4800
+ Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
+ Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Interrupt: pin C routed to IRQ 3
+ Region 0: Memory at 381ff8a00000 (64-bit, non-prefetchable) [disabled] [size=256]
+ Region 4: I/O ports at 2000 [disabled] [size=32]
+00: 86 80 22 1d 40 01 80 02 06 00 05 0c 00 00 00 00
+10: 04 00 a0 f8 1f 38 00 00 00 00 00 00 00 00 00 00
+20: 01 20 00 00 00 00 00 00 00 00 00 00 8e 10 00 48
+30: 00 00 00 00 00 00 00 00 00 00 00 00 03 03 00 00
+40: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+60: 03 04 04 00 00 00 08 08 00 00 00 00 00 00 00 00
+70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+80: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f0: 00 00 00 00 00 00 00 00 87 0f 08 08 00 00 00 00
+
+01:00.0 Ethernet controller: Intel Corporation Ethernet Controller 10-Gigabit X540-AT2 (rev 01)
+ Subsystem: Oracle/SUN Sun Dual Port 10 GbE PCIe 2.0 Low Profile Adapter, Base-T
+ Physical Slot: 1
+ Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0, Cache Line Size: 64 bytes
+ Interrupt: pin B routed to IRQ 30
+ Region 0: Memory at 381ff8200000 (64-bit, prefetchable) [size=2M]
+ Region 2: I/O ports at 5000 [disabled] [size=32]
+ Region 4: Memory at 381ff8100000 (64-bit, prefetchable) [size=16K]
+ Expansion ROM at 9f400000 [disabled] [size=512K]
+ Capabilities: [40] Power Management version 3
+ Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold-)
+ Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME-
+ Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+
+ Address: 0000000000000000 Data: 0000
+ Masking: 00000000 Pending: 00000000
+ Capabilities: [70] MSI-X: Enable+ Count=64 Masked-
+ Vector table: BAR=4 offset=00000000
+ PBA: BAR=4 offset=00002000
+ Capabilities: [a0] Express (v2) Endpoint, MSI 00
+ DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us
+ ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset+
+ DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ FLReset-
+ MaxPayload 256 bytes, MaxReadReq 512 bytes
+ DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend-
+ LnkCap: Port #0, Speed 5GT/s, Width x8, ASPM L0s L1, Exit Latency L0s <1us, L1 <8us
+ ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
+ DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not Supported
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
+ LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance De-emphasis: -6dB
+ LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
+ EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
+ Capabilities: [e0] Vital Product Data
+ Product Name: Sun Dual Port 10 Gbe PCIe 2.0 Low Profile Adapter
+ Read-only fields:
+ [PN] Part number: 7014741 Rev.01
+ [EC] Engineering changes: G45101-006
+ [SN] Serial number: 159048B+1227A0369F0EF82C
+ [V1] Vendor specific: Intel Corporation
+ [V2] Vendor specific: 8086
+ [V3] Vendor specific: 1528
+ [V4] Vendor specific: 108E
+ [V5] Vendor specific: 7B15
+ [V6] Vendor specific: 16.3W
+ [V7] Vendor specific: 0.0W
+ [V8] Vendor specific: 0.0W
+ [RV] Reserved: checksum good, 0 byte(s) reserved
+ Read/write fields:
+ [YA] Asset tag: N/A
+ End
+ Capabilities: [100 v2] Advanced Error Reporting
+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+ AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
+ Capabilities: [140 v1] Device Serial Number a0-36-9f-ff-ff-0e-f8-2c
+ Capabilities: [150 v1] Alternative Routing-ID Interpretation (ARI)
+ ARICap: MFVC- ACS-, Next Function: 1
+ ARICtl: MFVC- ACS-, Function Group: 0
+ Capabilities: [160 v1] Single Root I/O Virtualization (SR-IOV)
+ IOVCap: Migration-, Interrupt Message Number: 000
+ IOVCtl: Enable- Migration- Interrupt- MSE- ARIHierarchy+
+ IOVSta: Migration-
+ Initial VFs: 64, Total VFs: 64, Number of VFs: 64, Function Dependency Link: 00
+ VF offset: 128, stride: 2, Device ID: 1515
+ Supported Page Size: 00000553, System Page Size: 00000001
+ Region 0: Memory at 0000381ff8600000 (64-bit, non-prefetchable)
+ Region 3: Memory at 0000381ff8700000 (64-bit, non-prefetchable)
+ VF Migration: offset: 00000000, BIR: 0
+ Capabilities: [1d0 v1] Access Control Services
+ ACSCap: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
+ ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
+ Kernel driver in use: ixgbe
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+10: 0c 00 20 f8 1f 38 00 00 01 50 00 00 00 00 00 00
+20: 0c 00 10 f8 1f 38 00 00 00 00 00 00 8e 10 15 7b
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+a0: 10 e0 02 00 c2 8c 00 10 2f 28 09 00 82 cc 41 00
+b0: 40 00 82 10 00 00 00 00 00 00 00 00 00 00 00 00
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+
+01:00.1 Ethernet controller: Intel Corporation Ethernet Controller 10-Gigabit X540-AT2 (rev 01)
+ Subsystem: Oracle/SUN Sun Dual Port 10 GbE PCIe 2.0 Low Profile Adapter, Base-T
+ Physical Slot: 1
+ Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0, Cache Line Size: 64 bytes
+ Interrupt: pin A routed to IRQ 24
+ Region 0: Memory at 381ff8400000 (64-bit, prefetchable) [size=2M]
+ Region 2: I/O ports at 5020 [disabled] [size=32]
+ Region 4: Memory at 381ff8104000 (64-bit, prefetchable) [size=16K]
+ Expansion ROM at 9f480000 [disabled] [size=512K]
+ Capabilities: [40] Power Management version 3
+ Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold-)
+ Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME-
+ Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+
+ Address: 0000000000000000 Data: 0000
+ Masking: 00000000 Pending: 00000000
+ Capabilities: [70] MSI-X: Enable+ Count=64 Masked-
+ Vector table: BAR=4 offset=00000000
+ PBA: BAR=4 offset=00002000
+ Capabilities: [a0] Express (v2) Endpoint, MSI 00
+ DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us
+ ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset+
+ DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ FLReset-
+ MaxPayload 256 bytes, MaxReadReq 512 bytes
+ DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend-
+ LnkCap: Port #0, Speed 5GT/s, Width x8, ASPM L0s L1, Exit Latency L0s <1us, L1 <8us
+ ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
+ DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not Supported
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
+ LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
+ EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
+ Capabilities: [e0] Vital Product Data
+ Product Name: Sun Dual Port 10 Gbe PCIe 2.0 Low Profile Adapter
+ Read-only fields:
+ [PN] Part number: 7014741 Rev.01
+ [EC] Engineering changes: G45101-006
+ [SN] Serial number: 159048B+1227A0369F0EF82C
+ [V1] Vendor specific: Intel Corporation
+ [V2] Vendor specific: 8086
+ [V3] Vendor specific: 1528
+ [V4] Vendor specific: 108E
+ [V5] Vendor specific: 7B15
+ [V6] Vendor specific: 16.3W
+ [V7] Vendor specific: 0.0W
+ [V8] Vendor specific: 0.0W
+ [RV] Reserved: checksum good, 0 byte(s) reserved
+ Read/write fields:
+ [YA] Asset tag: N/A
+ End
+ Capabilities: [100 v2] Advanced Error Reporting
+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+ AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
+ Capabilities: [140 v1] Device Serial Number a0-36-9f-ff-ff-0e-f8-2c
+ Capabilities: [150 v1] Alternative Routing-ID Interpretation (ARI)
+ ARICap: MFVC- ACS-, Next Function: 0
+ ARICtl: MFVC- ACS-, Function Group: 0
+ Capabilities: [160 v1] Single Root I/O Virtualization (SR-IOV)
+ IOVCap: Migration-, Interrupt Message Number: 000
+ IOVCtl: Enable- Migration- Interrupt- MSE- ARIHierarchy-
+ IOVSta: Migration-
+ Initial VFs: 64, Total VFs: 64, Number of VFs: 64, Function Dependency Link: 01
+ VF offset: 128, stride: 2, Device ID: 1515
+ Supported Page Size: 00000553, System Page Size: 00000001
+ Region 0: Memory at 0000381ff8800000 (64-bit, non-prefetchable)
+ Region 3: Memory at 0000381ff8900000 (64-bit, non-prefetchable)
+ VF Migration: offset: 00000000, BIR: 0
+ Capabilities: [1d0 v1] Access Control Services
+ ACSCap: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
+ ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
+ Kernel driver in use: ixgbe
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+ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+03:00.0 RAID bus controller: LSI Logic / Symbios Logic MegaRAID SAS-3 3108 [Invader] (rev 02)
+ Subsystem: LSI Logic / Symbios Logic Device 9361
+ Physical Slot: 0
+ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0, Cache Line Size: 64 bytes
+ Interrupt: pin A routed to IRQ 25
+ Region 0: I/O ports at 4000 [size=256]
+ Region 1: Memory at 9f000000 (64-bit, non-prefetchable) [size=64K]
+ Region 3: Memory at 9ef00000 (64-bit, non-prefetchable) [size=1M]
+ Expansion ROM at 9ee00000 [disabled] [size=1M]
+ Capabilities: [50] Power Management version 3
+ Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
+ Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [68] Express (v2) Endpoint, MSI 00
+ DevCap: MaxPayload 4096 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
+ ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset+
+ DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported-
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ FLReset-
+ MaxPayload 256 bytes, MaxReadReq 512 bytes
+ DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend-
+ LnkCap: Port #0, Speed 8GT/s, Width x8, ASPM L0s, Exit Latency L0s <2us, L1 <4us
+ ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 8GT/s, Width x8, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
+ DevCap2: Completion Timeout: Range BC, TimeoutDis+, LTR-, OBFF Not Supported
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
+ LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance De-emphasis: -6dB
+ LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete+, EqualizationPhase1+
+ EqualizationPhase2+, EqualizationPhase3+, LinkEqualizationRequest+
+ Capabilities: [d0] Vital Product Data
+ Not readable
+ Capabilities: [a8] MSI: Enable- Count=1/1 Maskable+ 64bit+
+ Address: 0000000000000000 Data: 0000
+ Masking: 00000000 Pending: 00000000
+ Capabilities: [c0] MSI-X: Enable+ Count=97 Masked-
+ Vector table: BAR=1 offset=0000e000
+ PBA: BAR=1 offset=0000f000
+ Capabilities: [100 v2] Advanced Error Reporting
+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-
+ UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO+ CmpltAbrt+ UnxCmplt+ RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+ AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
+ Capabilities: [1e0 v1] #19
+ Capabilities: [1c0 v1] Power Budgeting <?>
+ Capabilities: [190 v1] #16
+ Capabilities: [148 v1] Alternative Routing-ID Interpretation (ARI)
+ ARICap: MFVC- ACS-, Next Function: 0
+ ARICtl: MFVC- ACS-, Function Group: 0
+ Kernel driver in use: megaraid_sas
+00: 00 10 5d 00 47 05 10 00 02 00 04 01 10 00 00 00
+10: 01 40 00 00 04 00 00 9f 00 00 00 00 04 00 f0 9e
+20: 00 00 00 00 00 00 00 00 00 00 00 00 00 10 61 93
+30: 00 00 e0 9e 50 00 00 00 00 00 00 00 0b 01 00 00
+40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+50: 01 68 03 06 08 00 00 00 00 00 00 00 00 00 00 00
+60: 00 00 00 00 00 03 00 00 10 d0 02 00 25 80 00 10
+70: 27 28 09 00 83 54 41 00 40 00 83 10 00 00 00 00
+80: 00 00 00 00 00 00 00 00 00 00 00 00 16 00 00 00
+90: 00 00 00 00 0e 00 00 00 03 00 3e 00 00 00 00 00
+a0: 00 00 00 00 00 00 00 00 05 c0 80 01 00 00 00 00
+b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+c0: 11 00 60 80 01 e0 00 00 01 f0 00 00 00 00 00 00
+d0: 03 a8 20 00 96 00 20 80 00 00 00 00 00 00 00 00
+e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+100: 01 00 02 1e 00 00 00 00 00 00 10 00 31 e0 47 00
+110: 00 20 00 00 00 20 00 00 a0 00 00 00 01 00 00 44
+120: 0f 00 18 00 00 00 01 03 00 00 00 00 00 00 00 00
+130: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+140: 00 00 00 00 00 00 00 00 0e 00 01 00 00 00 00 00
+150: 10 00 01 00 02 00 00 00 00 00 00 00 00 00 00 00
+160: 00 00 00 00 01 00 01 00 00 00 5d 00 53 05 00 00
+170: 01 00 00 00 04 00 00 00 00 00 00 00 04 00 00 00
+180: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+190: 16 00 81 14 00 00 00 00 00 00 00 00 00 01 00 00
+1a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+1b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+1c0: 04 00 01 19 00 00 00 00 00 00 00 00 00 00 00 00
+1d0: 17 00 01 00 01 00 00 00 00 00 00 00 00 00 00 00
+1e0: 19 00 01 1c 00 00 00 00 00 00 00 00 00 39 00 39
+1f0: 00 39 00 39 00 39 00 39 00 39 00 39 00 00 00 00
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+ed0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+f40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+04:00.0 InfiniBand: Mellanox Technologies MT27500 Family [ConnectX-3]
+ Subsystem: Mellanox Technologies Device 0090
+ Physical Slot: 2
+ Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0, Cache Line Size: 64 bytes
+ Interrupt: pin A routed to IRQ 297
+ Region 0: Memory at 380208000000 (64-bit, non-prefetchable) [size=1M]
+ Region 2: Memory at 380000000000 (64-bit, prefetchable) [size=128M]
+ Capabilities: [40] Power Management version 3
+ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
+ Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [48] Vital Product Data
+ Product Name: CX354A - ConnectX-3 QSFP
+ Read-only fields:
+ [PN] Part number: MCX354A-FCBT
+ [EC] Engineering changes: A4
+ [SN] Serial number: MT1247U02303
+ [V0] Vendor specific: PCIe Gen3 x8
+ [RV] Reserved: checksum good, 0 byte(s) reserved
+ Read/write fields:
+ [V1] Vendor specific: N/A
+ [YA] Asset tag: N/A
+ [RW] Read-write area: 105 byte(s) free
+ [RW] Read-write area: 253 byte(s) free
+ [RW] Read-write area: 253 byte(s) free
+ [RW] Read-write area: 253 byte(s) free
+ [RW] Read-write area: 253 byte(s) free
+ [RW] Read-write area: 253 byte(s) free
+ [RW] Read-write area: 253 byte(s) free
+ [RW] Read-write area: 253 byte(s) free
+ [RW] Read-write area: 253 byte(s) free
+ [RW] Read-write area: 253 byte(s) free
+ [RW] Read-write area: 253 byte(s) free
+ [RW] Read-write area: 253 byte(s) free
+ [RW] Read-write area: 253 byte(s) free
+ [RW] Read-write area: 253 byte(s) free
+ [RW] Read-write area: 253 byte(s) free
+ [RW] Read-write area: 252 byte(s) free
+ End
+ Capabilities: [9c] MSI-X: Enable+ Count=128 Masked-
+ Vector table: BAR=0 offset=0007c000
+ PBA: BAR=0 offset=0007d000
+ Capabilities: [60] Express (v2) Endpoint, MSI 00
+ DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 unlimited
+ ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset+
+ DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- FLReset-
+ MaxPayload 256 bytes, MaxReadReq 512 bytes
+ DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
+ LnkCap: Port #8, Speed 8GT/s, Width x8, ASPM L0s, Exit Latency L0s unlimited, L1 unlimited
+ ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 8GT/s, Width x8, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
+ DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not Supported
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
+ LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance De-emphasis: -6dB
+ LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
+ EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
+ Capabilities: [100 v1] Alternative Routing-ID Interpretation (ARI)
+ ARICap: MFVC- ACS-, Next Function: 0
+ ARICtl: MFVC- ACS-, Function Group: 0
+ Capabilities: [148 v1] Device Serial Number 00-02-c9-03-00-a3-d9-30
+ Capabilities: [108 v1] Single Root I/O Virtualization (SR-IOV)
+ IOVCap: Migration-, Interrupt Message Number: 000
+ IOVCtl: Enable- Migration- Interrupt- MSE- ARIHierarchy+
+ IOVSta: Migration-
+ Initial VFs: 64, Total VFs: 64, Number of VFs: 64, Function Dependency Link: 00
+ VF offset: 1, stride: 1, Device ID: 1004
+ Supported Page Size: 000007ff, System Page Size: 00000001
+ Region 2: Memory at 0000380008000000 (64-bit, prefetchable)
+ VF Migration: offset: 00000000, BIR: 0
+ Capabilities: [154 v2] Advanced Error Reporting
+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+ AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-
+ Capabilities: [18c v1] #19
+ Kernel driver in use: mlx4_core
+00: b3 15 03 10 46 05 10 00 00 00 06 0c 10 00 00 00
+10: 04 00 00 08 02 38 00 00 0c 00 00 00 00 38 00 00
+20: 00 00 00 00 00 00 00 00 00 00 00 00 b3 15 90 00
+30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 00 00
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+70: 40 00 83 10 00 00 00 00 00 00 00 00 00 00 00 00
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+fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+
+06:00.0 Ethernet controller: Intel Corporation I350 Gigabit Network Connection (rev 01)
+ DeviceName: /SYS/SMOD/NET0
+ Subsystem: Oracle/SUN Device 4800
+ Physical Slot: 0-2
+ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0, Cache Line Size: 64 bytes
+ Interrupt: pin A routed to IRQ 16
+ Region 0: Memory at 9f120000 (32-bit, non-prefetchable) [size=128K]
+ Region 2: I/O ports at 3020 [size=32]
+ Region 3: Memory at 9f144000 (32-bit, non-prefetchable) [size=16K]
+ Capabilities: [40] Power Management version 3
+ Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
+ Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=1 PME-
+ Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+
+ Address: 0000000000000000 Data: 0000
+ Masking: 00000000 Pending: 00000000
+ Capabilities: [70] MSI-X: Enable+ Count=10 Masked-
+ Vector table: BAR=3 offset=00000000
+ PBA: BAR=3 offset=00002000
+ Capabilities: [a0] Express (v2) Endpoint, MSI 00
+ DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us
+ ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset+
+ DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ FLReset-
+ MaxPayload 128 bytes, MaxReadReq 512 bytes
+ DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr+ TransPend-
+ LnkCap: Port #0, Speed 5GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <4us, L1 <32us
+ ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- CommClk+
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
+ DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR+, OBFF Not Supported
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
+ LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance De-emphasis: -6dB
+ LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
+ EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
+ Capabilities: [100 v2] Advanced Error Reporting
+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-
+ UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO+ CmpltAbrt+ UnxCmplt+ RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+ AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
+ Capabilities: [140 v1] Device Serial Number 00-10-e0-ff-ff-5b-d4-0c
+ Capabilities: [150 v1] Alternative Routing-ID Interpretation (ARI)
+ ARICap: MFVC- ACS-, Next Function: 1
+ ARICtl: MFVC- ACS-, Function Group: 0
+ Capabilities: [160 v1] Single Root I/O Virtualization (SR-IOV)
+ IOVCap: Migration-, Interrupt Message Number: 000
+ IOVCtl: Enable- Migration- Interrupt- MSE- ARIHierarchy-
+ IOVSta: Migration-
+ Initial VFs: 8, Total VFs: 8, Number of VFs: 8, Function Dependency Link: 00
+ VF offset: 384, stride: 4, Device ID: 1520
+ Supported Page Size: 00000553, System Page Size: 00000001
+ Region 0: Memory at 0000381ff8060000 (64-bit, prefetchable)
+ Region 3: Memory at 0000381ff8040000 (64-bit, prefetchable)
+ VF Migration: offset: 00000000, BIR: 0
+ Capabilities: [1a0 v1] Transaction Processing Hints
+ Device specific mode supported
+ Steering table in TPH capability structure
+ Capabilities: [1c0 v1] Latency Tolerance Reporting
+ Max snoop latency: 0ns
+ Max no snoop latency: 0ns
+ Capabilities: [1d0 v1] Access Control Services
+ ACSCap: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
+ ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
+ Kernel driver in use: igb
+00: 86 80 21 15 47 05 10 00 01 00 00 02 10 00 80 00
+10: 00 00 12 9f 00 00 00 00 21 30 00 00 00 40 14 9f
+20: 00 00 00 00 00 00 00 00 00 00 00 00 8e 10 00 48
+30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 00 00
+40: 01 50 23 c8 08 20 00 00 00 00 00 00 00 00 00 00
+50: 05 70 80 01 00 00 00 00 00 00 00 00 00 00 00 00
+60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+
+06:00.1 Ethernet controller: Intel Corporation I350 Gigabit Network Connection (rev 01)
+ DeviceName: /SYS/SMOD/NET1
+ Subsystem: Oracle/SUN Device 4800
+ Physical Slot: 0-2
+ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0, Cache Line Size: 64 bytes
+ Interrupt: pin B routed to IRQ 17
+ Region 0: Memory at 9f100000 (32-bit, non-prefetchable) [size=128K]
+ Region 2: I/O ports at 3000 [size=32]
+ Region 3: Memory at 9f140000 (32-bit, non-prefetchable) [size=16K]
+ Capabilities: [40] Power Management version 3
+ Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
+ Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=1 PME-
+ Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+
+ Address: 0000000000000000 Data: 0000
+ Masking: 00000000 Pending: 00000000
+ Capabilities: [70] MSI-X: Enable+ Count=10 Masked-
+ Vector table: BAR=3 offset=00000000
+ PBA: BAR=3 offset=00002000
+ Capabilities: [a0] Express (v2) Endpoint, MSI 00
+ DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us
+ ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset+
+ DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ FLReset-
+ MaxPayload 128 bytes, MaxReadReq 512 bytes
+ DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr+ TransPend-
+ LnkCap: Port #0, Speed 5GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <4us, L1 <32us
+ ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- CommClk+
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
+ DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR+, OBFF Not Supported
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
+ LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
+ EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
+ Capabilities: [100 v2] Advanced Error Reporting
+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-
+ UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO+ CmpltAbrt+ UnxCmplt+ RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+ AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
+ Capabilities: [140 v1] Device Serial Number 00-10-e0-ff-ff-5b-d4-0c
+ Capabilities: [150 v1] Alternative Routing-ID Interpretation (ARI)
+ ARICap: MFVC- ACS-, Next Function: 0
+ ARICtl: MFVC- ACS-, Function Group: 0
+ Capabilities: [160 v1] Single Root I/O Virtualization (SR-IOV)
+ IOVCap: Migration-, Interrupt Message Number: 000
+ IOVCtl: Enable- Migration- Interrupt- MSE- ARIHierarchy-
+ IOVSta: Migration-
+ Initial VFs: 8, Total VFs: 8, Number of VFs: 8, Function Dependency Link: 01
+ VF offset: 384, stride: 4, Device ID: 1520
+ Supported Page Size: 00000553, System Page Size: 00000001
+ Region 0: Memory at 0000381ff8020000 (64-bit, prefetchable)
+ Region 3: Memory at 0000381ff8000000 (64-bit, prefetchable)
+ VF Migration: offset: 00000000, BIR: 0
+ Capabilities: [1a0 v1] Transaction Processing Hints
+ Device specific mode supported
+ Steering table in TPH capability structure
+ Capabilities: [1d0 v1] Access Control Services
+ ACSCap: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
+ ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
+ Kernel driver in use: igb
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+
+08:00.0 VGA compatible controller: Matrox Electronics Systems Ltd. MGA G200e [Pilot] ServerEngines (SEP1) (rev 05) (prog-if 00 [VGA controller])
+ DeviceName: Pilot3 VGA
+ Subsystem: Oracle/SUN Device 4860
+ Physical Slot: 0-3
+ Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Interrupt: pin A routed to IRQ 16
+ Region 0: Memory at 90000000 (32-bit, non-prefetchable) [size=16M]
+ Region 1: Memory at 91810000 (32-bit, non-prefetchable) [size=16K]
+ Region 2: Memory at 91000000 (32-bit, non-prefetchable) [size=8M]
+ Expansion ROM at 91800000 [disabled] [size=64K]
+ Capabilities: [dc] Power Management version 2
+ Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
+ Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [e4] Express (v1) Legacy Endpoint, MSI 00
+ DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
+ ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset-
+ DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported-
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
+ MaxPayload 128 bytes, MaxReadReq 128 bytes
+ DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
+ LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s, Exit Latency L0s <64ns, L1 <1us
+ ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp-
+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
+ Capabilities: [54] MSI: Enable- Count=1/1 Maskable- 64bit-
+ Address: 00000000 Data: 0000
+00: 2b 10 22 05 43 01 10 00 05 00 00 03 10 00 00 00
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+ec0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+ee0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ef0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/drivers/pci/pci_test_mask_x5-8.txt b/drivers/pci/pci_test_mask_x5-8.txt
new file mode 100644
index 0000000..6428d7a
--- /dev/null
+++ b/drivers/pci/pci_test_mask_x5-8.txt
@@ -0,0 +1,176 @@
+mask: 8086:2f00 00:00.0 Host bridge: Intel Corporation Xeon E5 v3/Core i7 DMI2 (rev 04)
+00: 00 00 00 00 ff ff 10 00 04 00 00 06 10 00 00 00
+10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+30: 00 00 00 00 90 00 00 00 00 00 00 00 00 00 00 00
+
+mask: 8086:2f04 00:02.0 PCI bridge: Intel Corporation Xeon E5 v3/Core i7 PCI Express Root Port 2 (rev 04) (prog-if 00 [Normal decode])
+ Bus: primary=00, secondary=01, subordinate=02, sec-latency=0
+ I/O behind bridge: 00005000-00005fff
+ Memory behind bridge: 9f400000-9f5fffff
+ Prefetchable memory behind bridge: 0000381ff8100000-0000381ff89fffff
+00: 00 00 00 00 ff ff 10 00 04 00 04 06 10 00 01 00
+10: 00 00 00 00 00 00 00 00 00 ff ff 00 f0 f0 00 20
+20: f0 ff f0 ff f0 ff f0 ff ff ff ff ff ff ff ff ff
+30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 13 00
+
+mask: 8086:2f08 00:03.0 PCI bridge: Intel Corporation Xeon E5 v3/Core i7 PCI Express Root Port 3 (rev 04) (prog-if 00 [Normal decode])
+ Bus: primary=00, secondary=03, subordinate=03, sec-latency=0
+ I/O behind bridge: 00004000-00004fff
+ Memory behind bridge: 9ee00000-9f0fffff
+00: 00 00 00 00 ff ff 10 00 04 00 04 06 10 00 81 00
+10: 00 00 00 00 00 00 00 00 00 ff ff 00 f0 f0 00 20
+20: f0 ff f0 ff f0 ff f0 ff ff ff ff ff ff ff ff ff
+30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 13 00
+
+mask: 8086:2f0a 00:03.2 PCI bridge: Intel Corporation Xeon E5 v3/Core i7 PCI Express Root Port 3 (rev 04) (prog-if 00 [Normal decode])
+ Bus: primary=00, secondary=04, subordinate=04, sec-latency=0
+ I/O behind bridge: 00001000-00001fff
+ Memory behind bridge: 9f600000-9f7fffff
+ Prefetchable memory behind bridge: 0000380000000000-000038020bffffff
+00: 00 00 00 00 ff ff 10 00 04 00 04 06 10 00 81 00
+10: 00 00 00 00 00 00 00 00 00 ff ff 00 f0 f0 00 20
+20: f0 ff f0 ff f0 ff f0 ff ff ff ff ff ff ff ff ff
+30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 13 00
+
+mask: 8086:2f28 00:05.0 System peripheral: Intel Corporation Xeon E5 v3/Core i7 Address Map, VTd_Misc, System Management (rev 04)
+00: 00 00 00 00 ff ff 10 00 04 00 80 08 10 00 80 00
+10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+mask: 8086:2f29 00:05.1 System peripheral: Intel Corporation Xeon E5 v3/Core i7 Hot Plug (rev 04)
+00: 00 00 00 00 ff ff 10 00 04 00 80 08 10 00 00 00
+10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+mask: 8086:2f2a 00:05.2 System peripheral: Intel Corporation Xeon E5 v3/Core i7 RAS, Control Status and Global Errors (rev 04)
+00: 00 00 00 00 ff ff 10 00 04 00 80 08 10 00 80 00
+10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+mask: 8086:2f2c 00:05.4 PIC: Intel Corporation Xeon E5 v3/Core i7 I/O APIC (rev 04) (prog-if 20 [IO(X)-APIC])
+ Region 0: Memory at 9f303000 (32-bit, non-prefetchable) [size=4K]
+00: 00 00 00 00 ff ff 10 00 04 20 00 08 10 00 80 00
+10: 00 f0 ff ff 00 00 00 00 00 00 00 00 00 00 00 00
+20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+mask: 8086:1d3e 00:11.0 PCI bridge: Intel Corporation C600/X79 series chipset PCI Express Virtual Root Port (rev 06) (prog-if 00 [Normal decode])
+ Bus: primary=00, secondary=05, subordinate=05, sec-latency=0
+00: 00 00 00 00 ff ff 10 00 06 00 04 06 10 00 01 00
+10: 00 00 00 00 00 00 00 00 00 ff ff 00 f0 f0 00 20
+20: f0 ff f0 ff f0 ff f0 ff ff ff ff ff ff ff ff ff
+30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 13 00
+
+mask: 8086:1d2d 00:1a.0 USB controller: Intel Corporation C600/X79 series chipset USB2 Enhanced Host Controller #2 (rev 06) (prog-if 20 [EHCI])
+ Region 0: Memory at 9f301000 (32-bit, non-prefetchable) [size=1K]
+00: 86 80 2d 1d 46 01 90 02 06 20 03 0c 00 00 00 00
+10: 00 fc ff ff 00 00 00 00 00 00 00 00 00 00 00 00
+20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 00 00
+
+mask: 8086:1d10 00:1c.0 PCI bridge: Intel Corporation C600/X79 series chipset PCI Express Root Port 1 (rev b6) (prog-if 00 [Normal decode])
+ Bus: primary=00, secondary=06, subordinate=07, sec-latency=0
+ I/O behind bridge: 00003000-00003fff
+ Memory behind bridge: 9f100000-9f1fffff
+ Prefetchable memory behind bridge: 0000381ff8000000-0000381ff80fffff
+00: 00 00 00 00 ff ff 10 00 b6 00 04 06 10 00 81 00
+10: 00 00 00 00 00 00 00 00 00 ff ff 00 f0 f0 00 20
+20: f0 ff f0 ff f0 ff f0 ff ff ff ff ff ff ff ff ff
+30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 13 00
+
+mask: 8086:1d1e 00:1c.7 PCI bridge: Intel Corporation C600/X79 series chipset PCI Express Root Port 8 (rev b6) (prog-if 00 [Normal decode])
+ Bus: primary=00, secondary=08, subordinate=08, sec-latency=0
+ Memory behind bridge: 90000000-91bfffff
+00: 00 00 00 00 ff ff 10 00 b6 00 04 06 10 00 81 00
+10: 00 00 00 00 00 00 00 00 00 ff ff 00 f0 f0 00 00
+20: f0 ff f0 ff f0 ff f0 ff ff ff ff ff ff ff ff ff
+30: 00 00 00 00 00 00 00 00 00 00 00 00 05 04 18 00
+
+mask: 8086:1d26 00:1d.0 USB controller: Intel Corporation C600/X79 series chipset USB2 Enhanced Host Controller #1 (rev 06) (prog-if 20 [EHCI])
+ Region 0: Memory at 9f300000 (32-bit, non-prefetchable) [size=1K]
+00: 00 00 00 00 ff ff 90 02 06 20 03 0c 00 00 00 00
+10: 00 fc ff ff 00 00 00 00 00 00 00 00 00 00 00 00
+20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+30: 00 00 00 00 00 00 00 00 00 00 00 00 07 01 00 00
+
+mask: 8086:244e 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev a6) (prog-if 01 [Subtractive decode])
+ Bus: primary=00, secondary=09, subordinate=09, sec-latency=32
+00: 00 00 00 00 ff ff 10 00 a6 01 04 06 00 00 01 00
+10: 00 00 00 00 00 00 00 00 00 ff ff 20 f0 f0 80 22
+20: f0 ff f0 ff f0 ff f0 ff ff ff ff ff ff ff ff ff
+30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 13 00
+
+mask: 8086:1d41 00:1f.0 ISA bridge: Intel Corporation C600/X79 series chipset LPC Controller (rev 06)
+00: 00 00 00 00 ff ff 10 02 06 00 01 06 00 00 80 00
+10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+mask: 8086:1d22 00:1f.3 SMBus: Intel Corporation C600/X79 series chipset SMBus Host Controller (rev 06)
+ Region 0: Memory at 381ff8a00000 (64-bit, non-prefetchable) [disabled] [size=256]
+ Region 4: I/O ports at 2000 [disabled] [size=32]
+00: 00 00 00 00 ff ff 80 02 06 00 05 0c 00 00 00 00
+10: 00 ff ff ff ff ff ff ff 00 00 00 00 00 00 00 00
+20: e0 ff ff ff 00 00 00 00 00 00 00 00 00 00 00 00
+30: 00 00 00 00 00 00 00 00 00 00 00 00 03 03 00 00
+
+mask: 8086:1528 01:00.0 Ethernet controller: Intel Corporation Ethernet Controller 10-Gigabit X540-AT2 (rev 01)
+ Region 0: Memory at 381ff8200000 (64-bit, prefetchable) [size=2M]
+ Region 2: I/O ports at 5000 [disabled] [size=32]
+ Region 4: Memory at 381ff8100000 (64-bit, prefetchable) [size=16K]
+ Expansion ROM at 9f400000 [disabled] [size=512K]
+ Region 0: Memory at 0000381ff8600000 (64-bit, non-prefetchable)
+ Region 3: Memory at 0000381ff8700000 (64-bit, non-prefetchable)
+00: 00 00 00 00 ff ff 10 00 01 00 00 02 10 00 80 00
+10: 00 00 e0 ff ff ff ff ff e0 ff ff ff 00 00 00 00
+20: 00 c0 ff ff ff ff ff ff 00 00 00 00 00 00 00 00
+30: 00 00 f8 ff 00 00 00 00 00 00 00 00 0a 02 00 00
+180: 00 00 00 00 00 c0 ff ff ff ff ff ff 00 00 00 00
+190: 00 c0 ff ff ff ff ff ff 00 00 00 00 00 00 00 00
+
+mask: 1000:005d 03:00.0 RAID bus controller: LSI Logic / Symbios Logic MegaRAID SAS-3 3108 [Invader] (rev 02)
+ Region 0: I/O ports at 4000 [size=256]
+ Region 1: Memory at 9f000000 (64-bit, non-prefetchable) [size=64K]
+ Region 3: Memory at 9ef00000 (64-bit, non-prefetchable) [size=1M]
+ Expansion ROM at 9ee00000 [disabled] [size=1M]
+00: 00 00 00 00 ff ff 10 00 02 00 04 01 10 00 00 00
+10: 00 ff ff ff 00 00 ff ff ff ff ff ff 00 00 f0 ff
+20: ff ff ff ff 00 00 00 00 00 00 00 00 00 10 61 93
+30: 00 00 f0 ff 00 00 00 00 00 00 00 00 0b 01 00 00
+
+mask: 15b3:1003 04:00.0 InfiniBand: Mellanox Technologies MT27500 Family [ConnectX-3]
+ Region 0: Memory at 380208000000 (64-bit, non-prefetchable) [size=1M]
+ Region 2: Memory at 380000000000 (64-bit, prefetchable) [size=128M]
+ Region 2: Memory at 0000380008000000 (64-bit, prefetchable)
+00: 00 00 00 00 ff ff 10 00 00 00 06 0c 10 00 00 00
+10: 00 00 f0 ff ff ff ff ff 00 00 00 f8 ff ff ff ff
+20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 00 00
+130: 00 00 00 00 00 00 00 f8 ff ff ff ff 00 00 00 00
+
+mask: 8086:1521 06:00.0 Ethernet controller: Intel Corporation I350 Gigabit Network Connection (rev 01)
+ Region 0: Memory at 9f120000 (32-bit, non-prefetchable) [size=128K]
+ Region 2: I/O ports at 3020 [size=32]
+ Region 3: Memory at 9f144000 (32-bit, non-prefetchable) [size=16K]
+ Region 0: Memory at 0000381ff8060000 (64-bit, prefetchable)
+ Region 3: Memory at 0000381ff8040000 (64-bit, prefetchable)
+00: 00 00 00 00 ff ff 10 00 01 00 00 02 10 00 80 00
+10: 00 00 fe ff 00 00 00 00 e0 ff ff ff 00 c0 ff ff
+20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 00 00
+180: 00 00 00 00 00 c0 ff ff ff ff ff ff 00 00 00 00
+190: 00 c0 ff ff ff ff ff ff 00 00 00 00 00 00 00 00
+
+mask: 102b:0522 08:00.0 VGA compatible controller: Matrox Electronics Systems Ltd. MGA G200e [Pilot] ServerEngines (SEP1) (rev 05) (prog-if 00 [VGA controller])
+ Region 0: Memory at 90000000 (32-bit, non-prefetchable) [size=16M]
+ Region 1: Memory at 91810000 (32-bit, non-prefetchable) [size=16K]
+ Region 2: Memory at 91000000 (32-bit, non-prefetchable) [size=8M]
+ Expansion ROM at 91800000 [disabled] [size=64K]
+00: 00 00 00 00 ff ff 10 00 05 00 00 03 10 00 00 00
+10: 00 00 00 ff 00 c0 ff ff 00 00 80 ff 00 00 00 00
+20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+30: 00 00 ff ff dc 00 00 00 00 00 00 00 0b 01 00 00
--
2.9.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 08/10] PCI: PCI_TEST data from x5-8 with zeroed bus number
2017-08-05 6:37 [PATCH 00/10] PCI: pci resource allocation test module Yinghai Lu
` (6 preceding siblings ...)
2017-08-05 6:37 ` [PATCH 07/10] PCI: PCI_TEST data from x5-8 Yinghai Lu
@ 2017-08-05 6:37 ` Yinghai Lu
7 siblings, 0 replies; 9+ messages in thread
From: Yinghai Lu @ 2017-08-05 6:37 UTC (permalink / raw)
To: Bjorn Helgaas; +Cc: Linus Torvalds, linux-pci, linux-kernel, Yinghai Lu
data is from dmesg, and lspci -vvxxxx
pci bridge bus number register are cleared, and device titile line
take extra bus number range.
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
---
drivers/pci/pci_test_data_x5-8_bus.txt | 5656 ++++++++++++++++++++++++++++++++
1 file changed, 5656 insertions(+)
create mode 100644 drivers/pci/pci_test_data_x5-8_bus.txt
diff --git a/drivers/pci/pci_test_data_x5-8_bus.txt b/drivers/pci/pci_test_data_x5-8_bus.txt
new file mode 100644
index 0000000..2cd2724
--- /dev/null
+++ b/drivers/pci/pci_test_data_x5-8_bus.txt
@@ -0,0 +1,5656 @@
+pci_bus 0000:00: root bus resource [bus 00-1e]
+pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7 window]
+pci_bus 0000:00: root bus resource [io 0x1000-0x5fff window]
+pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window]
+pci_bus 0000:00: root bus resource [mem 0xfed8c000-0xfedfffff window]
+pci_bus 0000:00: root bus resource [mem 0x90000000-0x9fffbfff window]
+pci_bus 0000:00: root bus resource [mem 0x380000000000-0x381fffffffff window]
+
+00:00.0 Host bridge: Intel Corporation Xeon E5 v3/Core i7 DMI2 (rev 04)
+ Subsystem: Oracle/SUN Device 4800
+ Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Capabilities: [90] Express (v2) Root Port (Slot-), MSI 00
+ DevCap: MaxPayload 128 bytes, PhantFunc 0
+ ExtTag- RBE+
+ DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
+ MaxPayload 128 bytes, MaxReadReq 128 bytes
+ DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
+ LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM not supported, Exit Latency L0s <512ns, L1 <16us
+ ClockPM- Surprise+ LLActRep+ BwNot+ ASPMOptComp+
+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk-
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed unknown, Width x0, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt-
+ RootCtl: ErrCorrectable+ ErrNon-Fatal+ ErrFatal+ PMEIntEna- CRSVisible-
+ RootCap: CRSVisible-
+ RootSta: PME ReqID 0000, PMEStatus- PMEPending-
+ DevCap2: Completion Timeout: Range BCD, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd-
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd-
+ LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance De-emphasis: -6dB
+ LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
+ EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
+ Capabilities: [e0] Power Management version 3
+ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
+ Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [100 v1] Vendor Specific Information: ID=0002 Rev=0 Len=00c <?>
+ Capabilities: [144 v1] Vendor Specific Information: ID=0004 Rev=1 Len=03c <?>
+ Capabilities: [1d0 v1] Vendor Specific Information: ID=0003 Rev=1 Len=00a <?>
+ Capabilities: [280 v1] Vendor Specific Information: ID=0005 Rev=3 Len=018 <?>
+ Capabilities: [298 v1] Vendor Specific Information: ID=0007 Rev=0 Len=024 <?>
+ Capabilities: [300 v1] Vendor Specific Information: ID=0008 Rev=0 Len=038 <?>
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+
+00:02.0 [01-02] PCI bridge: Intel Corporation Xeon E5 v3/Core i7 PCI Express Root Port 2 (rev 04) (prog-if 00 [Normal decode])
+ DeviceName: /SYS/DPCC0/PCIE1
+ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0, Cache Line Size: 64 bytes
+ Interrupt: pin A routed to IRQ 26
+ Bus: primary=00, secondary=01, subordinate=02, sec-latency=0
+ I/O behind bridge: 00005000-00005fff
+ Memory behind bridge: 9f400000-9f5fffff
+ Prefetchable memory behind bridge: 0000381ff8100000-0000381ff89fffff
+ Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
+ BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
+ PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
+ Capabilities: [40] Subsystem: Oracle/SUN Device 4800
+ Capabilities: [60] MSI: Enable+ Count=1/2 Maskable+ 64bit-
+ Address: fee00258 Data: 0000
+ Masking: 00000002 Pending: 00000000
+ Capabilities: [90] Express (v2) Root Port (Slot+), MSI 00
+ DevCap: MaxPayload 256 bytes, PhantFunc 0
+ ExtTag+ RBE+
+ DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
+ MaxPayload 256 bytes, MaxReadReq 128 bytes
+ DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
+ LnkCap: Port #3, Speed 8GT/s, Width x16, ASPM not supported, Exit Latency L0s <512ns, L1 <16us
+ ClockPM- Surprise+ LLActRep+ BwNot+ ASPMOptComp+
+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
+ SltCap: AttnBtn+ PwrCtrl+ MRL- AttnInd+ PwrInd+ HotPlug+ Surprise-
+ Slot #1, PowerLimit 25.000W; Interlock- NoCompl-
+ SltCtl: Enable: AttnBtn+ PwrFlt- MRL- PresDet- CmdCplt+ HPIrq+ LinkChg+
+ Control: AttnInd Off, PwrInd On, Power- Interlock-
+ SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
+ Changed: MRL- PresDet- LinkState-
+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible+
+ RootCap: CRSVisible+
+ RootSta: PME ReqID 0000, PMEStatus- PMEPending-
+ DevCap2: Completion Timeout: Range BCD, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd+
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd+
+ LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance De-emphasis: -6dB
+ LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
+ EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
+ Capabilities: [e0] Power Management version 3
+ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
+ Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [100 v1] Vendor Specific Information: ID=0002 Rev=0 Len=00c <?>
+ Capabilities: [110 v1] Access Control Services
+ ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans-
+ ACSCtl: SrcValid+ TransBlk- ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans-
+ Capabilities: [148 v1] Advanced Error Reporting
+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-
+ UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO+ CmpltAbrt+ UnxCmplt+ RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+ AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-
+ Capabilities: [1d0 v1] Vendor Specific Information: ID=0003 Rev=1 Len=00a <?>
+ Capabilities: [250 v1] #19
+ Capabilities: [280 v1] Vendor Specific Information: ID=0005 Rev=3 Len=018 <?>
+ Capabilities: [298 v1] Vendor Specific Information: ID=0007 Rev=0 Len=024 <?>
+ Capabilities: [300 v1] Vendor Specific Information: ID=0008 Rev=0 Len=038 <?>
+ Kernel driver in use: pcieport
+00: 86 80 04 2f 47 05 10 00 04 00 04 06 10 00 01 00
+10: 00 00 00 00 00 00 00 00 00 00 00 00 50 50 00 20
+20: 40 9f 50 9f 11 f8 91 f8 1f 38 00 00 1f 38 00 00
+30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 13 00
+40: 0d 60 00 00 8e 10 00 48 00 00 00 00 00 00 00 00
+50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+60: 05 90 03 01 58 02 e0 fe 00 00 00 00 02 00 00 00
+70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+90: 10 e0 42 01 21 80 00 00 2f 00 00 00 03 31 7a 03
+a0: 40 00 82 70 db 0c 08 00 f1 11 40 00 18 00 01 00
+b0: 00 00 00 00 be 13 00 00 20 00 00 00 0e 00 00 00
+c0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+e0: 01 00 03 c8 08 00 00 00 00 00 00 00 00 00 00 00
+f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+100: 0b 00 01 11 02 00 c0 00 07 33 00 00 00 00 00 00
+110: 0d 00 81 14 1f 00 1d 00 00 00 00 00 00 00 00 00
+120: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+130: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+140: 00 00 00 00 00 00 00 00 01 00 01 1d 00 00 00 00
+150: 00 00 10 00 30 e0 07 00 00 00 00 00 00 20 00 00
+160: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+170: 00 00 00 00 07 00 00 00 00 00 00 00 00 00 00 00
+180: 91 30 18 00 00 00 00 00 40 10 10 e4 28 00 00 00
+190: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+
+00:03.0 [03-03] PCI bridge: Intel Corporation Xeon E5 v3/Core i7 PCI Express Root Port 3 (rev 04) (prog-if 00 [Normal decode])
+ DeviceName: /SYS/SMOD/HBA
+ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0, Cache Line Size: 64 bytes
+ Interrupt: pin A routed to IRQ 61
+ Bus: primary=00, secondary=03, subordinate=03, sec-latency=0
+ I/O behind bridge: 00004000-00004fff
+ Memory behind bridge: 9ee00000-9f0fffff
+ Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
+ BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
+ PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
+ Capabilities: [40] Subsystem: Oracle/SUN Device 4800
+ Capabilities: [60] MSI: Enable+ Count=1/2 Maskable+ 64bit-
+ Address: fee00318 Data: 0000
+ Masking: 00000002 Pending: 00000000
+ Capabilities: [90] Express (v2) Root Port (Slot-), MSI 00
+ DevCap: MaxPayload 256 bytes, PhantFunc 0
+ ExtTag+ RBE+
+ DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
+ MaxPayload 256 bytes, MaxReadReq 128 bytes
+ DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
+ LnkCap: Port #7, Speed 8GT/s, Width x8, ASPM not supported, Exit Latency L0s <512ns, L1 <16us
+ ClockPM- Surprise+ LLActRep+ BwNot+ ASPMOptComp+
+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 8GT/s, Width x8, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible+
+ RootCap: CRSVisible+
+ RootSta: PME ReqID 0000, PMEStatus- PMEPending-
+ DevCap2: Completion Timeout: Range BCD, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd+
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd+
+ LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance De-emphasis: -6dB
+ LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete+, EqualizationPhase1+
+ EqualizationPhase2+, EqualizationPhase3+, LinkEqualizationRequest+
+ Capabilities: [e0] Power Management version 3
+ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
+ Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [100 v1] Vendor Specific Information: ID=0002 Rev=0 Len=00c <?>
+ Capabilities: [110 v1] Access Control Services
+ ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans-
+ ACSCtl: SrcValid+ TransBlk- ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans-
+ Capabilities: [148 v1] Advanced Error Reporting
+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-
+ UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO+ CmpltAbrt+ UnxCmplt+ RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+ AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-
+ Capabilities: [1d0 v1] Vendor Specific Information: ID=0003 Rev=1 Len=00a <?>
+ Capabilities: [250 v1] #19
+ Capabilities: [280 v1] Vendor Specific Information: ID=0005 Rev=3 Len=018 <?>
+ Capabilities: [298 v1] Vendor Specific Information: ID=0007 Rev=0 Len=024 <?>
+ Capabilities: [300 v1] Vendor Specific Information: ID=0008 Rev=0 Len=038 <?>
+ Kernel driver in use: pcieport
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+10: 00 00 00 00 00 00 00 00 00 00 00 00 40 40 00 20
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+
+00:03.2 [04-04] PCI bridge: Intel Corporation Xeon E5 v3/Core i7 PCI Express Root Port 3 (rev 04) (prog-if 00 [Normal decode])
+ DeviceName: /SYS/DPCC0/PCIE2
+ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0, Cache Line Size: 64 bytes
+ Interrupt: pin A routed to IRQ 27
+ Bus: primary=00, secondary=04, subordinate=04, sec-latency=0
+ I/O behind bridge: 00001000-00001fff
+ Memory behind bridge: 9f600000-9f7fffff
+ Prefetchable memory behind bridge: 0000380000000000-000038020bffffff
+ Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
+ BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
+ PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
+ Capabilities: [40] Subsystem: Oracle/SUN Device 4800
+ Capabilities: [60] MSI: Enable+ Count=1/2 Maskable+ 64bit-
+ Address: fee00278 Data: 0000
+ Masking: 00000002 Pending: 00000000
+ Capabilities: [90] Express (v2) Root Port (Slot+), MSI 00
+ DevCap: MaxPayload 256 bytes, PhantFunc 0
+ ExtTag- RBE+
+ DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
+ MaxPayload 256 bytes, MaxReadReq 128 bytes
+ DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
+ LnkCap: Port #9, Speed 8GT/s, Width x8, ASPM not supported, Exit Latency L0s <512ns, L1 <16us
+ ClockPM- Surprise+ LLActRep+ BwNot+ ASPMOptComp+
+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 8GT/s, Width x8, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
+ SltCap: AttnBtn+ PwrCtrl+ MRL- AttnInd+ PwrInd+ HotPlug+ Surprise-
+ Slot #2, PowerLimit 25.000W; Interlock- NoCompl-
+ SltCtl: Enable: AttnBtn+ PwrFlt- MRL- PresDet- CmdCplt+ HPIrq+ LinkChg+
+ Control: AttnInd Off, PwrInd On, Power- Interlock-
+ SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
+ Changed: MRL- PresDet- LinkState-
+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible+
+ RootCap: CRSVisible+
+ RootSta: PME ReqID 0000, PMEStatus- PMEPending-
+ DevCap2: Completion Timeout: Range BCD, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd+
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd+
+ LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance De-emphasis: -6dB
+ LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete+, EqualizationPhase1+
+ EqualizationPhase2+, EqualizationPhase3+, LinkEqualizationRequest-
+ Capabilities: [e0] Power Management version 3
+ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
+ Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [100 v1] Vendor Specific Information: ID=0002 Rev=0 Len=00c <?>
+ Capabilities: [110 v1] Access Control Services
+ ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans-
+ ACSCtl: SrcValid+ TransBlk- ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans-
+ Capabilities: [148 v1] Advanced Error Reporting
+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UEMsk: DLP- SDES+ TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-
+ UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO+ CmpltAbrt+ UnxCmplt+ RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+ AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-
+ Capabilities: [1d0 v1] Vendor Specific Information: ID=0003 Rev=1 Len=00a <?>
+ Capabilities: [250 v1] #19
+ Capabilities: [280 v1] Vendor Specific Information: ID=0005 Rev=3 Len=018 <?>
+ Capabilities: [298 v1] Vendor Specific Information: ID=0007 Rev=0 Len=024 <?>
+ Capabilities: [300 v1] Vendor Specific Information: ID=0008 Rev=0 Len=038 <?>
+ Kernel driver in use: pcieport
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+
+00:05.0 System peripheral: Intel Corporation Xeon E5 v3/Core i7 Address Map, VTd_Misc, System Management (rev 04)
+ Subsystem: Oracle/SUN Device 4800
+ Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Capabilities: [40] Express (v2) Root Complex Integrated Endpoint, MSI 00
+ DevCap: MaxPayload 128 bytes, PhantFunc 0
+ ExtTag- RBE-
+ DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
+ MaxPayload 128 bytes, MaxReadReq 128 bytes
+ DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
+ DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR-, OBFF Not Supported
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
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+
+00:05.1 System peripheral: Intel Corporation Xeon E5 v3/Core i7 Hot Plug (rev 04)
+ Subsystem: Oracle/SUN Device 4800
+ Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Capabilities: [40] Express (v1) Root Complex Integrated Endpoint, MSI 00
+ DevCap: MaxPayload 128 bytes, PhantFunc 0
+ ExtTag- RBE-
+ DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
+ MaxPayload 128 bytes, MaxReadReq 128 bytes
+ DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
+ Capabilities: [80] MSI: Enable- Count=1/1 Maskable- 64bit+
+ Address: 0000000000000000 Data: 0000
+ Capabilities: [100 v1] Vendor Specific Information: ID=0006 Rev=1 Len=010 <?>
+ Capabilities: [110 v1] Vendor Specific Information: ID=0006 Rev=1 Len=010 <?>
+ Capabilities: [120 v1] Vendor Specific Information: ID=0006 Rev=1 Len=010 <?>
+ Capabilities: [130 v1] Vendor Specific Information: ID=0006 Rev=1 Len=010 <?>
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+
+00:05.2 System peripheral: Intel Corporation Xeon E5 v3/Core i7 RAS, Control Status and Global Errors (rev 04)
+ Subsystem: Oracle/SUN Device 4800
+ Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Capabilities: [40] Express (v2) Root Complex Integrated Endpoint, MSI 00
+ DevCap: MaxPayload 128 bytes, PhantFunc 0
+ ExtTag- RBE-
+ DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
+ RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
+ MaxPayload 128 bytes, MaxReadReq 128 bytes
+ DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
+ DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR-, OBFF Not Supported
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
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+
+00:05.4 PIC: Intel Corporation Xeon E5 v3/Core i7 I/O APIC (rev 04) (prog-if 20 [IO(X)-APIC])
+ Subsystem: Oracle/SUN Device 4800
+ Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0, Cache Line Size: 64 bytes
+ Region 0: Memory at 9f303000 (32-bit, non-prefetchable) [size=4K]
+ Capabilities: [44] Express (v1) Root Complex Integrated Endpoint, MSI 00
+ DevCap: MaxPayload 128 bytes, PhantFunc 0
+ ExtTag- RBE-
+ DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
+ MaxPayload 128 bytes, MaxReadReq 128 bytes
+ DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
+ Capabilities: [e0] Power Management version 3
+ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
+ Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
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+
+00:11.0 [05-05] PCI bridge: Intel Corporation C600/X79 series chipset PCI Express Virtual Root Port (rev 06) (prog-if 00 [Normal decode])
+ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0, Cache Line Size: 64 bytes
+ Interrupt: pin A routed to IRQ 63
+ Bus: primary=00, secondary=05, subordinate=05, sec-latency=0
+ Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
+ BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
+ PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
+ Capabilities: [40] Express (v2) Root Port (Slot-), MSI 00
+ DevCap: MaxPayload 128 bytes, PhantFunc 0
+ ExtTag- RBE+
+ DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
+ MaxPayload 128 bytes, MaxReadReq 512 bytes
+ DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
+ LnkCap: Port #17, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <64ns, L1 <1us
+ ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk-
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible-
+ RootCap: CRSVisible-
+ RootSta: PME ReqID 0000, PMEStatus- PMEPending-
+ DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR-, OBFF Not Supported ARIFwd+
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd-
+ LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance De-emphasis: -6dB
+ LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
+ EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
+ Capabilities: [80] Power Management version 3
+ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
+ Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [88] Subsystem: Oracle/SUN Device 4800
+ Capabilities: [90] MSI: Enable+ Count=1/1 Maskable- 64bit-
+ Address: fee00358 Data: 0000
+ Capabilities: [100 v1] Advanced Error Reporting
+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UEMsk: DLP- SDES- TLP+ FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP+ ECRC- UnsupReq+ ACSViol+
+ UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+ AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-
+ Capabilities: [138 v1] Access Control Services
+ ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans+
+ ACSCtl: SrcValid+ TransBlk- ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans-
+ Kernel driver in use: pcieport
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+
+00:1a.0 USB controller: Intel Corporation C600/X79 series chipset USB2 Enhanced Host Controller #2 (rev 06) (prog-if 20 [EHCI])
+ Subsystem: Oracle/SUN Device 4800
+ Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
+ Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0
+ Interrupt: pin A routed to IRQ 16
+ Region 0: Memory at 9f301000 (32-bit, non-prefetchable) [size=1K]
+ Capabilities: [50] Power Management version 2
+ Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
+ Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [58] Debug port: BAR=1 offset=00a0
+ Capabilities: [98] PCI Advanced Features
+ AFCap: TP+ FLR+
+ AFCtrl: FLR-
+ AFStatus: TP-
+ Kernel driver in use: ehci-pci
+00: 86 80 2d 1d 46 01 90 02 06 20 03 0c 00 00 00 00
+10: 00 10 30 9f 00 00 00 00 00 00 00 00 00 00 00 00
+20: 00 00 00 00 00 00 00 00 00 00 00 00 8e 10 00 48
+30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 00 00
+40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+50: 01 58 c2 c9 00 00 00 00 0a 98 a0 20 00 00 00 00
+60: 20 20 ff 07 00 00 00 00 01 00 00 01 00 00 00 c0
+70: 00 00 df 3f 00 00 00 00 00 00 00 00 00 00 00 00
+80: 00 00 80 00 11 88 0c 93 30 0d 00 24 00 00 00 00
+90: 00 00 00 00 00 00 00 00 13 00 06 03 00 00 00 00
+a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+d0: 00 00 00 00 00 aa ff 00 00 00 00 00 00 00 00 00
+e0: 00 00 00 00 22 40 00 00 01 0a 00 05 44 4d 43 d0
+f0: 00 00 00 00 88 85 80 00 87 0f 08 08 08 17 5b 20
+
+00:1c.0 [06-07] PCI bridge: Intel Corporation C600/X79 series chipset PCI Express Root Port 1 (rev b6) (prog-if 00 [Normal decode])
+ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0, Cache Line Size: 64 bytes
+ Interrupt: pin A routed to IRQ 64
+ Bus: primary=00, secondary=06, subordinate=07, sec-latency=0
+ I/O behind bridge: 00003000-00003fff
+ Memory behind bridge: 9f100000-9f1fffff
+ Prefetchable memory behind bridge: 0000381ff8000000-0000381ff80fffff
+ Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
+ BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
+ PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
+ Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00
+ DevCap: MaxPayload 128 bytes, PhantFunc 0
+ ExtTag- RBE+
+ DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
+ MaxPayload 128 bytes, MaxReadReq 128 bytes
+ DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
+ LnkCap: Port #1, Speed 5GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <512ns, L1 <16us
+ ClockPM- Surprise- LLActRep+ BwNot- ASPMOptComp-
+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- CommClk+
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt+
+ SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
+ Slot #0, PowerLimit 25.000W; Interlock- NoCompl+
+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
+ Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
+ SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
+ Changed: MRL- PresDet- LinkState-
+ RootCtl: ErrCorrectable+ ErrNon-Fatal+ ErrFatal+ PMEIntEna+ CRSVisible-
+ RootCap: CRSVisible-
+ RootSta: PME ReqID 0000, PMEStatus- PMEPending-
+ DevCap2: Completion Timeout: Range BC, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd-
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd-
+ LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance De-emphasis: -6dB
+ LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
+ EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
+ Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit-
+ Address: fee00378 Data: 0000
+ Capabilities: [90] Subsystem: Oracle/SUN Device 4800
+ Capabilities: [a0] Power Management version 2
+ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
+ Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
+ Kernel driver in use: pcieport
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+d60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+d70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+d80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+d90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+da0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+db0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+dc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+dd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+de0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+df0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+e00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+e10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+e20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+e30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+e40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+e50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+e60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+e70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+e80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+e90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ea0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+eb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ec0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ed0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ee0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ef0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+00:1c.7 [08-08] PCI bridge: Intel Corporation C600/X79 series chipset PCI Express Root Port 8 (rev b6) (prog-if 00 [Normal decode])
+ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0, Cache Line Size: 64 bytes
+ Interrupt: pin D routed to IRQ 28
+ Bus: primary=00, secondary=08, subordinate=08, sec-latency=0
+ Memory behind bridge: 90000000-91bfffff
+ Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
+ BridgeCtl: Parity- SERR- NoISA- VGA+ MAbort- >Reset- FastB2B-
+ PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
+ Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00
+ DevCap: MaxPayload 128 bytes, PhantFunc 0
+ ExtTag- RBE+
+ DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported-
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
+ MaxPayload 128 bytes, MaxReadReq 128 bytes
+ DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
+ LnkCap: Port #8, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <512ns, L1 <16us
+ ClockPM- Surprise- LLActRep+ BwNot- ASPMOptComp-
+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
+ SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
+ Slot #0, PowerLimit 10.000W; Interlock- NoCompl+
+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
+ Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
+ SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
+ Changed: MRL- PresDet- LinkState-
+ RootCtl: ErrCorrectable+ ErrNon-Fatal+ ErrFatal+ PMEIntEna+ CRSVisible-
+ RootCap: CRSVisible-
+ RootSta: PME ReqID 0000, PMEStatus- PMEPending-
+ DevCap2: Completion Timeout: Range BC, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd-
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd-
+ LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance De-emphasis: -6dB
+ LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1-
+ EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
+ Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit-
+ Address: fee002d8 Data: 0000
+ Capabilities: [90] Subsystem: Oracle/SUN Device 4800
+ Capabilities: [a0] Power Management version 2
+ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
+ Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
+ Kernel driver in use: pcieport
+00: 86 80 1e 1d 47 05 10 00 b6 00 04 06 10 00 81 00
+10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00
+20: 00 90 b0 91 f1 ff 01 00 00 00 00 00 00 00 00 00
+30: 00 00 00 00 40 00 00 00 00 00 00 00 05 04 18 00
+40: 10 80 42 01 00 80 00 00 07 00 10 00 12 3c 12 08
+50: 40 00 11 70 00 b2 04 00 00 00 40 00 0f 00 00 00
+60: 00 00 00 00 16 00 00 00 00 00 00 00 00 00 00 00
+70: 02 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00
+80: 05 90 01 00 d8 02 e0 fe 00 00 00 00 00 00 00 00
+90: 0d a0 00 00 8e 10 00 48 00 00 00 00 00 00 00 00
+a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00
+b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+d0: 00 00 00 01 00 0b 00 00 00 80 11 01 00 00 00 00
+e0: 00 03 00 00 00 00 00 00 01 00 00 00 00 00 00 00
+f0: 00 00 00 00 00 00 00 00 87 0f 08 08 00 00 00 00
+100: 00 00 00 00 00 80 00 00 00 80 10 00 11 00 06 00
+110: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+120: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+130: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+140: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+150: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+160: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+170: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+180: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+190: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+1a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+1b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+00:1d.0 USB controller: Intel Corporation C600/X79 series chipset USB2 Enhanced Host Controller #1 (rev 06) (prog-if 20 [EHCI])
+ Subsystem: Oracle/SUN Device 4800
+ Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
+ Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0
+ Interrupt: pin A routed to IRQ 23
+ Region 0: Memory at 9f300000 (32-bit, non-prefetchable) [size=1K]
+ Capabilities: [50] Power Management version 2
+ Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
+ Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [58] Debug port: BAR=1 offset=00a0
+ Capabilities: [98] PCI Advanced Features
+ AFCap: TP+ FLR+
+ AFCtrl: FLR-
+ AFStatus: TP-
+ Kernel driver in use: ehci-pci
+00: 86 80 26 1d 46 01 90 02 06 20 03 0c 00 00 00 00
+10: 00 00 30 9f 00 00 00 00 00 00 00 00 00 00 00 00
+20: 00 00 00 00 00 00 00 00 00 00 00 00 8e 10 00 48
+30: 00 00 00 00 50 00 00 00 00 00 00 00 07 01 00 00
+40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+50: 01 58 c2 c9 00 00 00 00 0a 98 a0 20 00 00 00 00
+60: 20 20 ff 07 00 00 00 00 01 00 00 01 00 00 08 c0
+70: 00 00 df 3f 00 00 00 00 00 00 00 00 00 00 00 00
+80: 00 00 80 00 11 88 0c 93 30 0d 00 24 00 00 00 00
+90: 00 00 00 00 00 00 00 00 13 00 06 03 00 00 00 00
+a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+d0: 00 00 00 00 00 aa ff 00 00 00 00 00 00 00 00 00
+e0: 00 00 00 00 00 e4 45 18 41 04 00 02 04 b0 f3 60
+f0: 00 00 00 00 88 85 80 00 87 0f 08 08 08 17 5b 20
+
+00:1e.0 [09-09] PCI bridge: Intel Corporation 82801 PCI Bridge (rev a6) (prog-if 01 [Subtractive decode])
+ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0
+ Bus: primary=00, secondary=09, subordinate=09, sec-latency=32
+ Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
+ BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
+ PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
+ Capabilities: [50] Subsystem: Oracle/SUN Device 4800
+00: 86 80 4e 24 47 01 10 00 a6 01 04 06 00 00 01 00
+10: 00 00 00 00 00 00 00 00 00 00 00 20 f0 00 80 22
+20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00
+30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 13 00
+40: 00 00 00 00 00 00 00 00 00 00 00 00 00 12 00 00
+50: 0d 00 00 00 8e 10 00 48 00 00 00 00 00 00 00 00
+60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f0: 00 00 00 00 00 00 00 00 87 0f 08 08 00 00 00 00
+
+00:1f.0 ISA bridge: Intel Corporation C600/X79 series chipset LPC Controller (rev 06)
+ Subsystem: Oracle/SUN Device 4800
+ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0
+ Capabilities: [e0] Vendor Specific Information: Len=0c <?>
+00: 86 80 41 1d 47 01 10 02 06 00 01 06 00 00 80 00
+10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+20: 00 00 00 00 00 00 00 00 00 00 00 00 8e 10 00 48
+30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00
+40: 01 04 00 00 80 00 00 00 01 05 00 00 10 00 00 00
+50: f8 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+60: 8b 8a 83 85 90 00 00 00 80 80 80 87 ff f0 00 00
+70: 78 f0 78 f0 78 f0 78 f0 78 f0 78 f0 78 f0 78 f0
+80: 10 00 0f 34 00 00 00 00 81 0c 3c 00 01 06 00 00
+90: 00 00 00 00 00 05 00 00 00 00 00 00 00 00 00 00
+a0: 10 0a 20 00 09 18 06 00 00 47 00 00 00 00 00 80
+b0: 00 00 00 00 00 00 00 00 00 0c 00 00 00 00 00 00
+c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+d0: 33 22 11 00 67 45 00 00 cf ff 00 00 2a 00 00 00
+e0: 09 00 0c 10 10 00 00 00 13 18 fc 0c 00 00 00 00
+f0: 01 c0 d1 fe 00 00 00 00 87 0f 08 08 00 00 00 00
+
+00:1f.3 SMBus: Intel Corporation C600/X79 series chipset SMBus Host Controller (rev 06)
+ Subsystem: Oracle/SUN Device 4800
+ Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
+ Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Interrupt: pin C routed to IRQ 3
+ Region 0: Memory at 381ff8a00000 (64-bit, non-prefetchable) [disabled] [size=256]
+ Region 4: I/O ports at 2000 [disabled] [size=32]
+00: 86 80 22 1d 40 01 80 02 06 00 05 0c 00 00 00 00
+10: 04 00 a0 f8 1f 38 00 00 00 00 00 00 00 00 00 00
+20: 01 20 00 00 00 00 00 00 00 00 00 00 8e 10 00 48
+30: 00 00 00 00 00 00 00 00 00 00 00 00 03 03 00 00
+40: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+60: 03 04 04 00 00 00 08 08 00 00 00 00 00 00 00 00
+70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+80: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f0: 00 00 00 00 00 00 00 00 87 0f 08 08 00 00 00 00
+
+01:00.0 Ethernet controller: Intel Corporation Ethernet Controller 10-Gigabit X540-AT2 (rev 01)
+ Subsystem: Oracle/SUN Sun Dual Port 10 GbE PCIe 2.0 Low Profile Adapter, Base-T
+ Physical Slot: 1
+ Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0, Cache Line Size: 64 bytes
+ Interrupt: pin B routed to IRQ 30
+ Region 0: Memory at 381ff8200000 (64-bit, prefetchable) [size=2M]
+ Region 2: I/O ports at 5000 [disabled] [size=32]
+ Region 4: Memory at 381ff8100000 (64-bit, prefetchable) [size=16K]
+ Expansion ROM at 9f400000 [disabled] [size=512K]
+ Capabilities: [40] Power Management version 3
+ Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold-)
+ Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME-
+ Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+
+ Address: 0000000000000000 Data: 0000
+ Masking: 00000000 Pending: 00000000
+ Capabilities: [70] MSI-X: Enable+ Count=64 Masked-
+ Vector table: BAR=4 offset=00000000
+ PBA: BAR=4 offset=00002000
+ Capabilities: [a0] Express (v2) Endpoint, MSI 00
+ DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us
+ ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset+
+ DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ FLReset-
+ MaxPayload 256 bytes, MaxReadReq 512 bytes
+ DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend-
+ LnkCap: Port #0, Speed 5GT/s, Width x8, ASPM L0s L1, Exit Latency L0s <1us, L1 <8us
+ ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
+ DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not Supported
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
+ LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance De-emphasis: -6dB
+ LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
+ EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
+ Capabilities: [e0] Vital Product Data
+ Product Name: Sun Dual Port 10 Gbe PCIe 2.0 Low Profile Adapter
+ Read-only fields:
+ [PN] Part number: 7014741 Rev.01
+ [EC] Engineering changes: G45101-006
+ [SN] Serial number: 159048B+1227A0369F0EF82C
+ [V1] Vendor specific: Intel Corporation
+ [V2] Vendor specific: 8086
+ [V3] Vendor specific: 1528
+ [V4] Vendor specific: 108E
+ [V5] Vendor specific: 7B15
+ [V6] Vendor specific: 16.3W
+ [V7] Vendor specific: 0.0W
+ [V8] Vendor specific: 0.0W
+ [RV] Reserved: checksum good, 0 byte(s) reserved
+ Read/write fields:
+ [YA] Asset tag: N/A
+ End
+ Capabilities: [100 v2] Advanced Error Reporting
+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+ AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
+ Capabilities: [140 v1] Device Serial Number a0-36-9f-ff-ff-0e-f8-2c
+ Capabilities: [150 v1] Alternative Routing-ID Interpretation (ARI)
+ ARICap: MFVC- ACS-, Next Function: 1
+ ARICtl: MFVC- ACS-, Function Group: 0
+ Capabilities: [160 v1] Single Root I/O Virtualization (SR-IOV)
+ IOVCap: Migration-, Interrupt Message Number: 000
+ IOVCtl: Enable- Migration- Interrupt- MSE- ARIHierarchy+
+ IOVSta: Migration-
+ Initial VFs: 64, Total VFs: 64, Number of VFs: 64, Function Dependency Link: 00
+ VF offset: 128, stride: 2, Device ID: 1515
+ Supported Page Size: 00000553, System Page Size: 00000001
+ Region 0: Memory at 0000381ff8600000 (64-bit, non-prefetchable)
+ Region 3: Memory at 0000381ff8700000 (64-bit, non-prefetchable)
+ VF Migration: offset: 00000000, BIR: 0
+ Capabilities: [1d0 v1] Access Control Services
+ ACSCap: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
+ ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
+ Kernel driver in use: ixgbe
+00: 86 80 28 15 46 05 10 00 01 00 00 02 10 00 80 00
+10: 0c 00 20 f8 1f 38 00 00 01 50 00 00 00 00 00 00
+20: 0c 00 10 f8 1f 38 00 00 00 00 00 00 8e 10 15 7b
+30: 00 00 98 9e 40 00 00 00 00 00 00 00 0a 02 00 00
+40: 01 50 23 48 00 20 00 00 00 00 00 00 00 00 00 00
+50: 05 70 80 01 00 00 00 00 00 00 00 00 00 00 00 00
+60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+70: 11 a0 3f 80 04 00 00 00 04 20 00 00 00 00 00 00
+80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+a0: 10 e0 02 00 c2 8c 00 10 2f 28 09 00 82 cc 41 00
+b0: 40 00 82 10 00 00 00 00 00 00 00 00 00 00 00 00
+c0: 00 00 00 00 1f 00 00 00 00 00 00 00 00 00 00 00
+d0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+e0: 03 00 c0 80 4e 2f 41 78 00 00 00 00 00 00 00 00
+f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+100: 01 00 02 14 00 00 00 00 00 00 00 00 31 20 46 00
+110: 00 20 00 00 00 20 00 00 a0 00 00 00 00 00 00 00
+120: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+130: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+140: 03 00 01 15 2c f8 0e ff ff 9f 36 a0 00 00 00 00
+150: 0e 00 01 16 00 01 00 00 00 00 00 00 00 00 00 00
+160: 10 00 01 1d 02 00 00 00 10 00 00 00 40 00 40 00
+170: 40 00 00 00 80 00 02 00 00 00 15 15 53 05 00 00
+180: 01 00 00 00 04 00 60 f8 1f 38 00 00 00 00 00 00
+190: 04 00 70 f8 1f 38 00 00 00 00 00 00 00 00 00 00
+1a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+1b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+
+01:00.1 Ethernet controller: Intel Corporation Ethernet Controller 10-Gigabit X540-AT2 (rev 01)
+ Subsystem: Oracle/SUN Sun Dual Port 10 GbE PCIe 2.0 Low Profile Adapter, Base-T
+ Physical Slot: 1
+ Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0, Cache Line Size: 64 bytes
+ Interrupt: pin A routed to IRQ 24
+ Region 0: Memory at 381ff8400000 (64-bit, prefetchable) [size=2M]
+ Region 2: I/O ports at 5020 [disabled] [size=32]
+ Region 4: Memory at 381ff8104000 (64-bit, prefetchable) [size=16K]
+ Expansion ROM at 9f480000 [disabled] [size=512K]
+ Capabilities: [40] Power Management version 3
+ Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold-)
+ Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME-
+ Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+
+ Address: 0000000000000000 Data: 0000
+ Masking: 00000000 Pending: 00000000
+ Capabilities: [70] MSI-X: Enable+ Count=64 Masked-
+ Vector table: BAR=4 offset=00000000
+ PBA: BAR=4 offset=00002000
+ Capabilities: [a0] Express (v2) Endpoint, MSI 00
+ DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us
+ ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset+
+ DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ FLReset-
+ MaxPayload 256 bytes, MaxReadReq 512 bytes
+ DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend-
+ LnkCap: Port #0, Speed 5GT/s, Width x8, ASPM L0s L1, Exit Latency L0s <1us, L1 <8us
+ ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
+ DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not Supported
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
+ LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
+ EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
+ Capabilities: [e0] Vital Product Data
+ Product Name: Sun Dual Port 10 Gbe PCIe 2.0 Low Profile Adapter
+ Read-only fields:
+ [PN] Part number: 7014741 Rev.01
+ [EC] Engineering changes: G45101-006
+ [SN] Serial number: 159048B+1227A0369F0EF82C
+ [V1] Vendor specific: Intel Corporation
+ [V2] Vendor specific: 8086
+ [V3] Vendor specific: 1528
+ [V4] Vendor specific: 108E
+ [V5] Vendor specific: 7B15
+ [V6] Vendor specific: 16.3W
+ [V7] Vendor specific: 0.0W
+ [V8] Vendor specific: 0.0W
+ [RV] Reserved: checksum good, 0 byte(s) reserved
+ Read/write fields:
+ [YA] Asset tag: N/A
+ End
+ Capabilities: [100 v2] Advanced Error Reporting
+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+ AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
+ Capabilities: [140 v1] Device Serial Number a0-36-9f-ff-ff-0e-f8-2c
+ Capabilities: [150 v1] Alternative Routing-ID Interpretation (ARI)
+ ARICap: MFVC- ACS-, Next Function: 0
+ ARICtl: MFVC- ACS-, Function Group: 0
+ Capabilities: [160 v1] Single Root I/O Virtualization (SR-IOV)
+ IOVCap: Migration-, Interrupt Message Number: 000
+ IOVCtl: Enable- Migration- Interrupt- MSE- ARIHierarchy-
+ IOVSta: Migration-
+ Initial VFs: 64, Total VFs: 64, Number of VFs: 64, Function Dependency Link: 01
+ VF offset: 128, stride: 2, Device ID: 1515
+ Supported Page Size: 00000553, System Page Size: 00000001
+ Region 0: Memory at 0000381ff8800000 (64-bit, non-prefetchable)
+ Region 3: Memory at 0000381ff8900000 (64-bit, non-prefetchable)
+ VF Migration: offset: 00000000, BIR: 0
+ Capabilities: [1d0 v1] Access Control Services
+ ACSCap: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
+ ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
+ Kernel driver in use: ixgbe
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+e30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+e40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+e50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+e60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+e70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+e80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+e90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ea0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+eb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ec0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ed0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ee0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ef0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+03:00.0 RAID bus controller: LSI Logic / Symbios Logic MegaRAID SAS-3 3108 [Invader] (rev 02)
+ Subsystem: LSI Logic / Symbios Logic Device 9361
+ Physical Slot: 0
+ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0, Cache Line Size: 64 bytes
+ Interrupt: pin A routed to IRQ 25
+ Region 0: I/O ports at 4000 [size=256]
+ Region 1: Memory at 9f000000 (64-bit, non-prefetchable) [size=64K]
+ Region 3: Memory at 9ef00000 (64-bit, non-prefetchable) [size=1M]
+ Expansion ROM at 9ee00000 [disabled] [size=1M]
+ Capabilities: [50] Power Management version 3
+ Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
+ Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [68] Express (v2) Endpoint, MSI 00
+ DevCap: MaxPayload 4096 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
+ ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset+
+ DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported-
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ FLReset-
+ MaxPayload 256 bytes, MaxReadReq 512 bytes
+ DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend-
+ LnkCap: Port #0, Speed 8GT/s, Width x8, ASPM L0s, Exit Latency L0s <2us, L1 <4us
+ ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 8GT/s, Width x8, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
+ DevCap2: Completion Timeout: Range BC, TimeoutDis+, LTR-, OBFF Not Supported
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
+ LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance De-emphasis: -6dB
+ LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete+, EqualizationPhase1+
+ EqualizationPhase2+, EqualizationPhase3+, LinkEqualizationRequest+
+ Capabilities: [d0] Vital Product Data
+ Not readable
+ Capabilities: [a8] MSI: Enable- Count=1/1 Maskable+ 64bit+
+ Address: 0000000000000000 Data: 0000
+ Masking: 00000000 Pending: 00000000
+ Capabilities: [c0] MSI-X: Enable+ Count=97 Masked-
+ Vector table: BAR=1 offset=0000e000
+ PBA: BAR=1 offset=0000f000
+ Capabilities: [100 v2] Advanced Error Reporting
+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-
+ UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO+ CmpltAbrt+ UnxCmplt+ RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+ AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
+ Capabilities: [1e0 v1] #19
+ Capabilities: [1c0 v1] Power Budgeting <?>
+ Capabilities: [190 v1] #16
+ Capabilities: [148 v1] Alternative Routing-ID Interpretation (ARI)
+ ARICap: MFVC- ACS-, Next Function: 0
+ ARICtl: MFVC- ACS-, Function Group: 0
+ Kernel driver in use: megaraid_sas
+00: 00 10 5d 00 47 05 10 00 02 00 04 01 10 00 00 00
+10: 01 40 00 00 04 00 00 9f 00 00 00 00 04 00 f0 9e
+20: 00 00 00 00 00 00 00 00 00 00 00 00 00 10 61 93
+30: 00 00 e0 9e 50 00 00 00 00 00 00 00 0b 01 00 00
+40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+50: 01 68 03 06 08 00 00 00 00 00 00 00 00 00 00 00
+60: 00 00 00 00 00 03 00 00 10 d0 02 00 25 80 00 10
+70: 27 28 09 00 83 54 41 00 40 00 83 10 00 00 00 00
+80: 00 00 00 00 00 00 00 00 00 00 00 00 16 00 00 00
+90: 00 00 00 00 0e 00 00 00 03 00 3e 00 00 00 00 00
+a0: 00 00 00 00 00 00 00 00 05 c0 80 01 00 00 00 00
+b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+c0: 11 00 60 80 01 e0 00 00 01 f0 00 00 00 00 00 00
+d0: 03 a8 20 00 96 00 20 80 00 00 00 00 00 00 00 00
+e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+100: 01 00 02 1e 00 00 00 00 00 00 10 00 31 e0 47 00
+110: 00 20 00 00 00 20 00 00 a0 00 00 00 01 00 00 44
+120: 0f 00 18 00 00 00 01 03 00 00 00 00 00 00 00 00
+130: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+140: 00 00 00 00 00 00 00 00 0e 00 01 00 00 00 00 00
+150: 10 00 01 00 02 00 00 00 00 00 00 00 00 00 00 00
+160: 00 00 00 00 01 00 01 00 00 00 5d 00 53 05 00 00
+170: 01 00 00 00 04 00 00 00 00 00 00 00 04 00 00 00
+180: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+190: 16 00 81 14 00 00 00 00 00 00 00 00 00 01 00 00
+1a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+1b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+1c0: 04 00 01 19 00 00 00 00 00 00 00 00 00 00 00 00
+1d0: 17 00 01 00 01 00 00 00 00 00 00 00 00 00 00 00
+1e0: 19 00 01 1c 00 00 00 00 00 00 00 00 00 39 00 39
+1f0: 00 39 00 39 00 39 00 39 00 39 00 39 00 00 00 00
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+f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+04:00.0 InfiniBand: Mellanox Technologies MT27500 Family [ConnectX-3]
+ Subsystem: Mellanox Technologies Device 0090
+ Physical Slot: 2
+ Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0, Cache Line Size: 64 bytes
+ Interrupt: pin A routed to IRQ 297
+ Region 0: Memory at 380208000000 (64-bit, non-prefetchable) [size=1M]
+ Region 2: Memory at 380000000000 (64-bit, prefetchable) [size=128M]
+ Capabilities: [40] Power Management version 3
+ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
+ Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [48] Vital Product Data
+ Product Name: CX354A - ConnectX-3 QSFP
+ Read-only fields:
+ [PN] Part number: MCX354A-FCBT
+ [EC] Engineering changes: A4
+ [SN] Serial number: MT1247U02303
+ [V0] Vendor specific: PCIe Gen3 x8
+ [RV] Reserved: checksum good, 0 byte(s) reserved
+ Read/write fields:
+ [V1] Vendor specific: N/A
+ [YA] Asset tag: N/A
+ [RW] Read-write area: 105 byte(s) free
+ [RW] Read-write area: 253 byte(s) free
+ [RW] Read-write area: 253 byte(s) free
+ [RW] Read-write area: 253 byte(s) free
+ [RW] Read-write area: 253 byte(s) free
+ [RW] Read-write area: 253 byte(s) free
+ [RW] Read-write area: 253 byte(s) free
+ [RW] Read-write area: 253 byte(s) free
+ [RW] Read-write area: 253 byte(s) free
+ [RW] Read-write area: 253 byte(s) free
+ [RW] Read-write area: 253 byte(s) free
+ [RW] Read-write area: 253 byte(s) free
+ [RW] Read-write area: 253 byte(s) free
+ [RW] Read-write area: 253 byte(s) free
+ [RW] Read-write area: 253 byte(s) free
+ [RW] Read-write area: 252 byte(s) free
+ End
+ Capabilities: [9c] MSI-X: Enable+ Count=128 Masked-
+ Vector table: BAR=0 offset=0007c000
+ PBA: BAR=0 offset=0007d000
+ Capabilities: [60] Express (v2) Endpoint, MSI 00
+ DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 unlimited
+ ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset+
+ DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- FLReset-
+ MaxPayload 256 bytes, MaxReadReq 512 bytes
+ DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
+ LnkCap: Port #8, Speed 8GT/s, Width x8, ASPM L0s, Exit Latency L0s unlimited, L1 unlimited
+ ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 8GT/s, Width x8, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
+ DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not Supported
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
+ LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance De-emphasis: -6dB
+ LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
+ EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
+ Capabilities: [100 v1] Alternative Routing-ID Interpretation (ARI)
+ ARICap: MFVC- ACS-, Next Function: 0
+ ARICtl: MFVC- ACS-, Function Group: 0
+ Capabilities: [148 v1] Device Serial Number 00-02-c9-03-00-a3-d9-30
+ Capabilities: [108 v1] Single Root I/O Virtualization (SR-IOV)
+ IOVCap: Migration-, Interrupt Message Number: 000
+ IOVCtl: Enable- Migration- Interrupt- MSE- ARIHierarchy+
+ IOVSta: Migration-
+ Initial VFs: 64, Total VFs: 64, Number of VFs: 64, Function Dependency Link: 00
+ VF offset: 1, stride: 1, Device ID: 1004
+ Supported Page Size: 000007ff, System Page Size: 00000001
+ Region 2: Memory at 0000380008000000 (64-bit, prefetchable)
+ VF Migration: offset: 00000000, BIR: 0
+ Capabilities: [154 v2] Advanced Error Reporting
+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+ AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-
+ Capabilities: [18c v1] #19
+ Kernel driver in use: mlx4_core
+00: b3 15 03 10 46 05 10 00 00 00 06 0c 10 00 00 00
+10: 04 00 00 08 02 38 00 00 0c 00 00 00 00 38 00 00
+20: 00 00 00 00 00 00 00 00 00 00 00 00 b3 15 90 00
+30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 00 00
+40: 01 48 03 00 00 00 00 00 03 9c fc 8f 00 00 00 78
+50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+60: 10 00 02 00 01 8e d0 11 20 20 00 00 83 f4 43 08
+70: 40 00 83 10 00 00 00 00 00 00 00 00 00 00 00 00
+80: 00 00 00 00 1f 00 00 00 00 00 00 00 0e 00 00 00
+90: 03 00 00 00 00 00 00 00 00 00 00 00 11 60 7f 80
+a0: 00 c0 07 00 00 d0 07 00 05 00 8a 00 00 00 00 00
+b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+100: 0e 00 81 14 00 00 00 00 10 00 41 15 00 00 00 00
+110: 10 00 00 00 40 00 40 00 40 00 00 00 01 00 01 00
+120: 00 00 04 10 ff 07 00 00 01 00 00 00 00 00 00 00
+130: 00 00 00 00 0c 00 00 08 00 38 00 00 00 00 00 00
+140: 00 00 00 00 00 00 00 00 03 00 81 10 30 d9 a3 00
+150: 03 c9 02 00 01 00 c2 18 00 00 00 00 00 00 00 00
+160: 10 20 06 00 00 00 00 00 00 20 00 00 00 00 00 00
+170: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+180: 00 00 00 00 00 00 00 00 00 00 00 00 19 00 01 00
+190: 00 00 00 00 00 00 00 00 7f 27 7f 27 7f 27 7f 27
+1a0: 7f 27 7f 27 7f 27 7f 27 00 00 00 00 00 00 00 00
+1b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+1c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+
+06:00.0 Ethernet controller: Intel Corporation I350 Gigabit Network Connection (rev 01)
+ DeviceName: /SYS/SMOD/NET0
+ Subsystem: Oracle/SUN Device 4800
+ Physical Slot: 0-2
+ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0, Cache Line Size: 64 bytes
+ Interrupt: pin A routed to IRQ 16
+ Region 0: Memory at 9f120000 (32-bit, non-prefetchable) [size=128K]
+ Region 2: I/O ports at 3020 [size=32]
+ Region 3: Memory at 9f144000 (32-bit, non-prefetchable) [size=16K]
+ Capabilities: [40] Power Management version 3
+ Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
+ Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=1 PME-
+ Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+
+ Address: 0000000000000000 Data: 0000
+ Masking: 00000000 Pending: 00000000
+ Capabilities: [70] MSI-X: Enable+ Count=10 Masked-
+ Vector table: BAR=3 offset=00000000
+ PBA: BAR=3 offset=00002000
+ Capabilities: [a0] Express (v2) Endpoint, MSI 00
+ DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us
+ ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset+
+ DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ FLReset-
+ MaxPayload 128 bytes, MaxReadReq 512 bytes
+ DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr+ TransPend-
+ LnkCap: Port #0, Speed 5GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <4us, L1 <32us
+ ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- CommClk+
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
+ DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR+, OBFF Not Supported
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
+ LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance De-emphasis: -6dB
+ LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
+ EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
+ Capabilities: [100 v2] Advanced Error Reporting
+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-
+ UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO+ CmpltAbrt+ UnxCmplt+ RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+ AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
+ Capabilities: [140 v1] Device Serial Number 00-10-e0-ff-ff-5b-d4-0c
+ Capabilities: [150 v1] Alternative Routing-ID Interpretation (ARI)
+ ARICap: MFVC- ACS-, Next Function: 1
+ ARICtl: MFVC- ACS-, Function Group: 0
+ Capabilities: [160 v1] Single Root I/O Virtualization (SR-IOV)
+ IOVCap: Migration-, Interrupt Message Number: 000
+ IOVCtl: Enable- Migration- Interrupt- MSE- ARIHierarchy-
+ IOVSta: Migration-
+ Initial VFs: 8, Total VFs: 8, Number of VFs: 8, Function Dependency Link: 00
+ VF offset: 384, stride: 4, Device ID: 1520
+ Supported Page Size: 00000553, System Page Size: 00000001
+ Region 0: Memory at 0000381ff8060000 (64-bit, prefetchable)
+ Region 3: Memory at 0000381ff8040000 (64-bit, prefetchable)
+ VF Migration: offset: 00000000, BIR: 0
+ Capabilities: [1a0 v1] Transaction Processing Hints
+ Device specific mode supported
+ Steering table in TPH capability structure
+ Capabilities: [1c0 v1] Latency Tolerance Reporting
+ Max snoop latency: 0ns
+ Max no snoop latency: 0ns
+ Capabilities: [1d0 v1] Access Control Services
+ ACSCap: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
+ ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
+ Kernel driver in use: igb
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+
+06:00.1 Ethernet controller: Intel Corporation I350 Gigabit Network Connection (rev 01)
+ DeviceName: /SYS/SMOD/NET1
+ Subsystem: Oracle/SUN Device 4800
+ Physical Slot: 0-2
+ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0, Cache Line Size: 64 bytes
+ Interrupt: pin B routed to IRQ 17
+ Region 0: Memory at 9f100000 (32-bit, non-prefetchable) [size=128K]
+ Region 2: I/O ports at 3000 [size=32]
+ Region 3: Memory at 9f140000 (32-bit, non-prefetchable) [size=16K]
+ Capabilities: [40] Power Management version 3
+ Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
+ Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=1 PME-
+ Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+
+ Address: 0000000000000000 Data: 0000
+ Masking: 00000000 Pending: 00000000
+ Capabilities: [70] MSI-X: Enable+ Count=10 Masked-
+ Vector table: BAR=3 offset=00000000
+ PBA: BAR=3 offset=00002000
+ Capabilities: [a0] Express (v2) Endpoint, MSI 00
+ DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us
+ ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset+
+ DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ FLReset-
+ MaxPayload 128 bytes, MaxReadReq 512 bytes
+ DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr+ TransPend-
+ LnkCap: Port #0, Speed 5GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <4us, L1 <32us
+ ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- CommClk+
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
+ DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR+, OBFF Not Supported
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
+ LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
+ EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
+ Capabilities: [100 v2] Advanced Error Reporting
+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-
+ UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO+ CmpltAbrt+ UnxCmplt+ RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+ AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
+ Capabilities: [140 v1] Device Serial Number 00-10-e0-ff-ff-5b-d4-0c
+ Capabilities: [150 v1] Alternative Routing-ID Interpretation (ARI)
+ ARICap: MFVC- ACS-, Next Function: 0
+ ARICtl: MFVC- ACS-, Function Group: 0
+ Capabilities: [160 v1] Single Root I/O Virtualization (SR-IOV)
+ IOVCap: Migration-, Interrupt Message Number: 000
+ IOVCtl: Enable- Migration- Interrupt- MSE- ARIHierarchy-
+ IOVSta: Migration-
+ Initial VFs: 8, Total VFs: 8, Number of VFs: 8, Function Dependency Link: 01
+ VF offset: 384, stride: 4, Device ID: 1520
+ Supported Page Size: 00000553, System Page Size: 00000001
+ Region 0: Memory at 0000381ff8020000 (64-bit, prefetchable)
+ Region 3: Memory at 0000381ff8000000 (64-bit, prefetchable)
+ VF Migration: offset: 00000000, BIR: 0
+ Capabilities: [1a0 v1] Transaction Processing Hints
+ Device specific mode supported
+ Steering table in TPH capability structure
+ Capabilities: [1d0 v1] Access Control Services
+ ACSCap: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
+ ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
+ Kernel driver in use: igb
+00: 86 80 21 15 47 05 10 00 01 00 00 02 10 00 80 00
+10: 00 00 10 9f 00 00 00 00 01 30 00 00 00 00 14 9f
+20: 00 00 00 00 00 00 00 00 00 00 00 00 8e 10 00 48
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+40: 01 50 23 c8 08 20 00 00 00 00 00 00 00 00 00 00
+50: 05 70 80 01 00 00 00 00 00 00 00 00 00 00 00 00
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+70: 11 a0 09 80 03 00 00 00 03 20 00 00 00 00 00 00
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+90: 00 00 00 00 00 00 00 00 00 00 00 00 ff ff ff ff
+a0: 10 00 02 00 c2 8c 00 10 0f 28 19 00 42 ec 42 00
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+180: 01 00 00 00 0c 00 02 f8 1f 38 00 00 00 00 00 00
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+
+08:00.0 VGA compatible controller: Matrox Electronics Systems Ltd. MGA G200e [Pilot] ServerEngines (SEP1) (rev 05) (prog-if 00 [VGA controller])
+ DeviceName: Pilot3 VGA
+ Subsystem: Oracle/SUN Device 4860
+ Physical Slot: 0-3
+ Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Interrupt: pin A routed to IRQ 16
+ Region 0: Memory at 90000000 (32-bit, non-prefetchable) [size=16M]
+ Region 1: Memory at 91810000 (32-bit, non-prefetchable) [size=16K]
+ Region 2: Memory at 91000000 (32-bit, non-prefetchable) [size=8M]
+ Expansion ROM at 91800000 [disabled] [size=64K]
+ Capabilities: [dc] Power Management version 2
+ Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
+ Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [e4] Express (v1) Legacy Endpoint, MSI 00
+ DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
+ ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset-
+ DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported-
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
+ MaxPayload 128 bytes, MaxReadReq 128 bytes
+ DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
+ LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s, Exit Latency L0s <64ns, L1 <1us
+ ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp-
+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
+ Capabilities: [54] MSI: Enable- Count=1/1 Maskable- 64bit-
+ Address: 00000000 Data: 0000
+00: 2b 10 22 05 43 01 10 00 05 00 00 03 10 00 00 00
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--
2.9.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
end of thread, other threads:[~2017-08-05 6:40 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-08-05 6:37 [PATCH 00/10] PCI: pci resource allocation test module Yinghai Lu
2017-08-05 6:37 ` [PATCH 01/10] PCI: avoid arch_remove_reservations() for PCI_TEST Yinghai Lu
2017-08-05 6:37 ` [PATCH 02/10] PCI: introduce ioport_res/iomem_res " Yinghai Lu
2017-08-05 6:37 ` [PATCH 03/10] PCI: export symbol for PCI_TEST module Yinghai Lu
2017-08-05 6:37 ` [PATCH 04/10] PCI: extend pci device match_driver state Yinghai Lu
2017-08-05 6:37 ` [PATCH 05/10] PCI: Add PCI_TEST module for resource allocation Yinghai Lu
2017-08-05 6:37 ` [PATCH 06/10] PCI: PCI_TEST simple data Yinghai Lu
2017-08-05 6:37 ` [PATCH 07/10] PCI: PCI_TEST data from x5-8 Yinghai Lu
2017-08-05 6:37 ` [PATCH 08/10] PCI: PCI_TEST data from x5-8 with zeroed bus number Yinghai Lu
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