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* [PATCH igt] tools/null_state_gen: Add proper color calc and depth stencil states
@ 2017-08-09  9:27 Mika Kuoppala
  2017-08-09 10:30 ` ✓ Fi.CI.BAT: success for " Patchwork
  0 siblings, 1 reply; 2+ messages in thread
From: Mika Kuoppala @ 2017-08-09  9:27 UTC (permalink / raw)
  To: intel-gfx

We were just pointing these states blindly into the 1k offset
in the bb. Make a suitable sized and aligned null block and
point both indirect state pointers to that block.

v2: move blend state generation into the same function

Reported-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 tools/null_state_gen/intel_renderstate_gen6.c | 64 ++++++++++++++++-----------
 1 file changed, 39 insertions(+), 25 deletions(-)

diff --git a/tools/null_state_gen/intel_renderstate_gen6.c b/tools/null_state_gen/intel_renderstate_gen6.c
index 5c1b7f97..1aa97d39 100644
--- a/tools/null_state_gen/intel_renderstate_gen6.c
+++ b/tools/null_state_gen/intel_renderstate_gen6.c
@@ -216,13 +216,46 @@ gen6_emit_invariant(struct intel_batchbuffer *batch)
 	OUT_BATCH(1);
 }
 
+static uint32_t
+gen6_create_cc_blend(struct intel_batchbuffer *batch)
+{
+	struct gen6_blend_state blend;
+
+	memset(&blend, 0, sizeof(blend));
+
+	blend.blend0.dest_blend_factor = GEN6_BLENDFACTOR_ZERO;
+	blend.blend0.source_blend_factor = GEN6_BLENDFACTOR_ONE;
+	blend.blend0.blend_func = GEN6_BLENDFUNCTION_ADD;
+	blend.blend0.blend_enable = 1;
+
+	blend.blend1.post_blend_clamp_enable = 1;
+	blend.blend1.pre_blend_clamp_enable = 1;
+
+	return OUT_STATE_STRUCT(blend, 64);
+}
+
 static void
-gen6_emit_cc(struct intel_batchbuffer *batch, uint32_t blend)
+gen6_emit_cc(struct intel_batchbuffer *batch)
 {
+	struct null_blk_s {
+		union {
+			struct gen6_depth_stencil_state s_state;
+			struct gen6_color_calc_state c_state;
+		};
+	} null_block;
+	uint32_t null_block_offset, blend_offset;
+
+	memset(&null_block, 0, sizeof(null_block));
+
+	blend_offset = gen6_create_cc_blend(batch);
+	null_block_offset = OUT_STATE_STRUCT(null_block, 64);
+
 	OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS | (4 - 2));
-	OUT_BATCH_STATE_OFFSET(blend | 1);
-	OUT_BATCH(1024 | 1);
-	OUT_BATCH(1024 | 1);
+	OUT_BATCH_STATE_OFFSET(blend_offset | 1);
+	/* color calc state */
+	OUT_BATCH_STATE_OFFSET(null_block_offset | 1);
+	/* depth stencil state */
+	OUT_BATCH_STATE_OFFSET(null_block_offset | 1);
 }
 
 static void
@@ -354,24 +387,6 @@ gen6_create_cc_viewport(struct intel_batchbuffer *batch)
 }
 
 static uint32_t
-gen6_create_cc_blend(struct intel_batchbuffer *batch)
-{
-	struct gen6_blend_state blend;
-
-	memset(&blend, 0, sizeof(blend));
-
-	blend.blend0.dest_blend_factor = GEN6_BLENDFACTOR_ZERO;
-	blend.blend0.source_blend_factor = GEN6_BLENDFACTOR_ONE;
-	blend.blend0.blend_func = GEN6_BLENDFUNCTION_ADD;
-	blend.blend0.blend_enable = 1;
-
-	blend.blend1.post_blend_clamp_enable = 1;
-	blend.blend1.pre_blend_clamp_enable = 1;
-
-	return OUT_STATE_STRUCT(blend, 64);
-}
-
-static uint32_t
 gen6_create_kernel(struct intel_batchbuffer *batch)
 {
 	return intel_batch_state_copy(batch, ps_kernel_nomask_affine,
@@ -463,7 +478,7 @@ static void gen6_emit_vertex_buffer(struct intel_batchbuffer *batch)
 void gen6_setup_null_render_state(struct intel_batchbuffer *batch)
 {
 	uint32_t wm_state, wm_kernel, wm_table;
-	uint32_t cc_vp, cc_blend;
+	uint32_t cc_vp;
 
 	wm_table  = gen6_bind_surfaces(batch);
 	wm_kernel = gen6_create_kernel(batch);
@@ -472,7 +487,6 @@ void gen6_setup_null_render_state(struct intel_batchbuffer *batch)
 					SAMPLER_EXTEND_NONE);
 
 	cc_vp = gen6_create_cc_viewport(batch);
-	cc_blend = gen6_create_cc_blend(batch);
 
 	gen6_emit_invariant(batch);
 	gen6_emit_state_base_address(batch);
@@ -488,7 +502,7 @@ void gen6_setup_null_render_state(struct intel_batchbuffer *batch)
 	gen6_emit_null_depth_buffer(batch);
 
 	gen6_emit_drawing_rectangle(batch);
-	gen6_emit_cc(batch, cc_blend);
+	gen6_emit_cc(batch);
 	gen6_emit_sampler(batch, wm_state);
 	gen6_emit_sf(batch);
 	gen6_emit_wm(batch, wm_kernel);
-- 
2.11.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 2+ messages in thread

* ✓ Fi.CI.BAT: success for tools/null_state_gen: Add proper color calc and depth stencil states
  2017-08-09  9:27 [PATCH igt] tools/null_state_gen: Add proper color calc and depth stencil states Mika Kuoppala
@ 2017-08-09 10:30 ` Patchwork
  0 siblings, 0 replies; 2+ messages in thread
From: Patchwork @ 2017-08-09 10:30 UTC (permalink / raw)
  To: Mika Kuoppala; +Cc: intel-gfx

== Series Details ==

Series: tools/null_state_gen: Add proper color calc and depth stencil states
URL   : https://patchwork.freedesktop.org/series/28542/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
c129026622accef6f54c0cfb0dc55e930cfa60b5 igt: add syncobj_basic.

with latest DRM-Tip kernel build CI_DRM_2937
4641b60d14c7 drm-tip: 2017y-08m-09d-08h-53m-33s UTC integration manifest

Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-b:
                pass       -> DMESG-WARN (fi-byt-n2820) fdo#101705

fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705

fi-bdw-5557u     total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  time:438s
fi-bdw-gvtdvm    total:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  time:418s
fi-blb-e6850     total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  time:358s
fi-bsw-n3050     total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  time:499s
fi-bxt-j4205     total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:493s
fi-byt-j1900     total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  time:522s
fi-byt-n2820     total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  time:513s
fi-glk-2a        total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:585s
fi-hsw-4770      total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:442s
fi-hsw-4770r     total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:412s
fi-ilk-650       total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  time:416s
fi-ivb-3520m     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:512s
fi-ivb-3770      total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:480s
fi-kbl-7500u     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:468s
fi-kbl-7560u     total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:566s
fi-kbl-r         total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:570s
fi-pnv-d510      total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  time:520s
fi-skl-6260u     total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:446s
fi-skl-6700k     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:645s
fi-skl-6770hq    total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:463s
fi-skl-gvtdvm    total:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  time:422s
fi-skl-x1585l    total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:483s
fi-snb-2520m     total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  time:547s
fi-snb-2600      total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  time:412s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_36/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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2017-08-09  9:27 [PATCH igt] tools/null_state_gen: Add proper color calc and depth stencil states Mika Kuoppala
2017-08-09 10:30 ` ✓ Fi.CI.BAT: success for " Patchwork

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