* [PATCH v2 0/3] drm/i915: add register macro definition style guide
@ 2017-08-10 12:29 Jani Nikula
2017-08-10 12:29 ` [PATCH v2 1/3] Documentation/i915: remove sphinx conversion artefact Jani Nikula
` (3 more replies)
0 siblings, 4 replies; 10+ messages in thread
From: Jani Nikula @ 2017-08-10 12:29 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Pandiyan Dhinakaran
This is v2 of [1], with minor tweaks and bolting the document into the
Sphinx build.
BR,
Jani.
[1] http://patchwork.freedesktop.org/patch/msgid/20170804103836.17629-1-jani.nikula@intel.com
Jani Nikula (3):
Documentation/i915: remove sphinx conversion artefact
drm/i915: enum i915_power_well_id is not proper kernel-doc
drm/i915: add register macro definition style guide
Documentation/gpu/i915.rst | 14 ++++++-
drivers/gpu/drm/i915/i915_reg.h | 93 ++++++++++++++++++++++++++++++++++++++++-
2 files changed, 105 insertions(+), 2 deletions(-)
--
2.11.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 1/3] Documentation/i915: remove sphinx conversion artefact
2017-08-10 12:29 [PATCH v2 0/3] drm/i915: add register macro definition style guide Jani Nikula
@ 2017-08-10 12:29 ` Jani Nikula
2017-08-10 15:19 ` Rodrigo Vivi
2017-08-10 12:29 ` [PATCH v2 2/3] drm/i915: enum i915_power_well_id is not proper kernel-doc Jani Nikula
` (2 subsequent siblings)
3 siblings, 1 reply; 10+ messages in thread
From: Jani Nikula @ 2017-08-10 12:29 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Pandiyan Dhinakaran
Remove old warning about docproc directive that's not supported in the
Sphinx toolchain.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
Documentation/gpu/i915.rst | 2 --
1 file changed, 2 deletions(-)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 46875c2bcc31..32c32b89e2e5 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -480,5 +480,3 @@ specific details than found in the more high-level sections.
.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
:internal:
-
-.. WARNING: DOCPROC directive not supported: !Cdrivers/gpu/drm/i915/i915_irq.c
--
2.11.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 2/3] drm/i915: enum i915_power_well_id is not proper kernel-doc
2017-08-10 12:29 [PATCH v2 0/3] drm/i915: add register macro definition style guide Jani Nikula
2017-08-10 12:29 ` [PATCH v2 1/3] Documentation/i915: remove sphinx conversion artefact Jani Nikula
@ 2017-08-10 12:29 ` Jani Nikula
2017-08-10 15:17 ` Rodrigo Vivi
2017-08-10 12:29 ` [PATCH v2 3/3] drm/i915: add register macro definition style guide Jani Nikula
2017-08-10 12:55 ` ✗ Fi.CI.BAT: failure for drm/i915: add register macro definition style guide (rev2) Patchwork
3 siblings, 1 reply; 10+ messages in thread
From: Jani Nikula @ 2017-08-10 12:29 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Pandiyan Dhinakaran
Revert to a normal comment, as the enum isn't properly documented
anyway.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 56df86ef5a4d..3b42ba9fa473 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1127,7 +1127,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
#define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
-/**
+/*
* i915_power_well_id:
*
* Platform specific IDs used to look up power wells and - except for custom
--
2.11.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 3/3] drm/i915: add register macro definition style guide
2017-08-10 12:29 [PATCH v2 0/3] drm/i915: add register macro definition style guide Jani Nikula
2017-08-10 12:29 ` [PATCH v2 1/3] Documentation/i915: remove sphinx conversion artefact Jani Nikula
2017-08-10 12:29 ` [PATCH v2 2/3] drm/i915: enum i915_power_well_id is not proper kernel-doc Jani Nikula
@ 2017-08-10 12:29 ` Jani Nikula
2017-08-10 12:55 ` ✗ Fi.CI.BAT: failure for drm/i915: add register macro definition style guide (rev2) Patchwork
3 siblings, 0 replies; 10+ messages in thread
From: Jani Nikula @ 2017-08-10 12:29 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Pandiyan Dhinakaran, Daniel Vetter
This is not to try to force a new style; this is my interpretation of
what the most common existing style is.
With hopes I don't need to answer so many questions about style going
forward.
Start a new style section in the i915 document to bolt the register
style guide into.
v2: vertical alignment, incorporate to kernel-doc, and more
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
Documentation/gpu/i915.rst | 14 +++++++
drivers/gpu/drm/i915/i915_reg.h | 91 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 105 insertions(+)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 32c32b89e2e5..2e7ee0313c1c 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -480,3 +480,17 @@ specific details than found in the more high-level sections.
.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
:internal:
+
+Style
+=====
+
+The drm/i915 driver codebase has some style rules in addition to (and, in some
+cases, deviating from) the kernel coding style.
+
+Register macro definition style
+-------------------------------
+
+The style guide for ``i915_reg.h``.
+
+.. kernel-doc:: drivers/gpu/drm/i915/i915_reg.h
+ :doc: The i915 register macro definition style guide
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3b42ba9fa473..1c74bcb1660b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -25,6 +25,97 @@
#ifndef _I915_REG_H_
#define _I915_REG_H_
+/**
+ * DOC: The i915 register macro definition style guide
+ *
+ * Follow the style described here for new macros, and while changing existing
+ * macros. Do **not** mass change existing definitions just to update the style.
+ *
+ * Layout
+ * ''''''
+ *
+ * Keep helper macros near the top. For example, _PIPE() and friends.
+ *
+ * Prefix macros that generally should not be used outside of this file with
+ * underscore '_'. For example, _PIPE() and friends, single instances of
+ * registers that are defined solely for the use by function-like macros.
+ *
+ * Avoid using the underscore prefixed macros outside of this file. There are
+ * exceptions, but keep them to a minimum.
+ *
+ * There are two basic types of register definitions: Single registers and
+ * register groups. Register groups are registers which have two or more
+ * instances, for example one per pipe, port, transcoder, etc. Register groups
+ * should be defined using function-like macros.
+ *
+ * For single registers, define the register offset first, followed by register
+ * contents.
+ *
+ * For register groups, define the register instance offsets first, prefixed
+ * with underscore, followed by a function-like macro choosing the right
+ * instance based on the parameter, followed by register contents.
+ *
+ * Define the register contents (i.e. bit and bit field macros) from most
+ * significant to least significant bit. Indent the register content macros
+ * using two extra spaces between ``#define`` and the macro name.
+ *
+ * For bit fields, define a ``_MASK`` and a ``_SHIFT`` macro. Define bit field
+ * contents so that they are already shifted in place, and can be directly
+ * OR'd. For convenience, function-like macros may be used to define bit fields,
+ * but do note that the macros may be needed to read as well as write the
+ * register contents.
+ *
+ * Define bits using ``(1 << N)`` instead of ``BIT(N)``. We may change this in
+ * the future, but this is the prevailing style. Do **not** add ``_BIT`` suffix
+ * to the name.
+ *
+ * Group the register and its contents together without blank lines, separate
+ * from other registers and their contents with one blank line.
+ *
+ * Indent macro values from macro names using TABs. Align values vertically. Use
+ * braces in macro values as needed to avoid unintended precedence after macro
+ * substitution. Use spaces in macro values according to kernel coding
+ * style. Use lower case in hexadecimal values.
+ *
+ * Naming
+ * ''''''
+ *
+ * Try to name registers according to the specs. If the register name changes in
+ * the specs from platform to another, stick to the original name.
+ *
+ * Try to re-use existing register macro definitions. Only add new macros for
+ * new register offsets, or when the register contents have changed enough to
+ * warrant a full redefinition.
+ *
+ * When a register macro changes for a new platform, prefix the new macro using
+ * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The
+ * prefix signifies the start platform/generation using the register.
+ *
+ * When a bit (field) macro changes or gets added for a new platform, while
+ * retaining the existing register macro, add a platform acronym or generation
+ * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
+ *
+ * Examples
+ * ''''''''
+ *
+ * (Note that the values in the example are indented using spaces instead of
+ * TABs to avoid misalignment in generated documentation. Use TABs in the
+ * definitions.)::
+ *
+ * #define _FOO_A 0xf000
+ * #define _FOO_B 0xf001
+ * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
+ * #define FOO_ENABLE (1 << 31)
+ * #define FOO_MODE_MASK (0xf << 16)
+ * #define FOO_MODE_SHIFT 16
+ * #define FOO_MODE_BAR (0 << 16)
+ * #define FOO_MODE_BAZ (1 << 16)
+ * #define FOO_MODE_QUX_SNB (2 << 16)
+ *
+ * #define BAR _MMIO(0xb000)
+ * #define GEN8_BAR _MMIO(0xb888)
+ */
+
typedef struct {
uint32_t reg;
} i915_reg_t;
--
2.11.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915: add register macro definition style guide (rev2)
2017-08-10 12:29 [PATCH v2 0/3] drm/i915: add register macro definition style guide Jani Nikula
` (2 preceding siblings ...)
2017-08-10 12:29 ` [PATCH v2 3/3] drm/i915: add register macro definition style guide Jani Nikula
@ 2017-08-10 12:55 ` Patchwork
2017-08-10 20:11 ` Jani Nikula
3 siblings, 1 reply; 10+ messages in thread
From: Patchwork @ 2017-08-10 12:55 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: add register macro definition style guide (rev2)
URL : https://patchwork.freedesktop.org/series/28370/
State : failure
== Summary ==
Series 28370v2 drm/i915: add register macro definition style guide
https://patchwork.freedesktop.org/api/1.0/series/28370/revisions/2/mbox/
Test gem_exec_nop:
Subgroup basic-parallel:
pass -> INCOMPLETE (fi-byt-j1900)
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
fail -> PASS (fi-snb-2600) fdo#100215
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fi-bdw-5557u total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:438s
fi-bdw-gvtdvm total:279 pass:265 dwarn:0 dfail:0 fail:0 skip:14 time:419s
fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:363s
fi-bsw-n3050 total:279 pass:243 dwarn:0 dfail:0 fail:0 skip:36 time:501s
fi-bxt-j4205 total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:485s
fi-byt-j1900 total:67 pass:57 dwarn:0 dfail:0 fail:0 skip:9
fi-byt-n2820 total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:514s
fi-glk-2a total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:578s
fi-hsw-4770 total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:432s
fi-hsw-4770r total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:410s
fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:416s
fi-ivb-3520m total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:516s
fi-ivb-3770 total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:480s
fi-kbl-7500u total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:459s
fi-kbl-7560u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:564s
fi-kbl-r total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:577s
fi-pnv-d510 total:279 pass:223 dwarn:1 dfail:0 fail:0 skip:55 time:522s
fi-skl-6260u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:447s
fi-skl-6700k total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:645s
fi-skl-6770hq total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:466s
fi-skl-gvtdvm total:279 pass:266 dwarn:0 dfail:0 fail:0 skip:13 time:424s
fi-skl-x1585l total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:465s
fi-snb-2520m total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:551s
fi-snb-2600 total:279 pass:250 dwarn:0 dfail:0 fail:0 skip:29 time:411s
0f3edcc5d40749f2ddddd26f5ada55a145e20350 drm-tip: 2017y-08m-10d-11h-21m-35s UTC integration manifest
22c6121825a3 drm/i915: add register macro definition style guide
fcb595e35f95 drm/i915: enum i915_power_well_id is not proper kernel-doc
351d78b35d17 Documentation/i915: remove sphinx conversion artefact
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5366/
_______________________________________________
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 2/3] drm/i915: enum i915_power_well_id is not proper kernel-doc
2017-08-10 12:29 ` [PATCH v2 2/3] drm/i915: enum i915_power_well_id is not proper kernel-doc Jani Nikula
@ 2017-08-10 15:17 ` Rodrigo Vivi
0 siblings, 0 replies; 10+ messages in thread
From: Rodrigo Vivi @ 2017-08-10 15:17 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, Pandiyan Dhinakaran
On Thu, Aug 10, 2017 at 5:29 AM, Jani Nikula <jani.nikula@intel.com> wrote:
> Revert to a normal comment, as the enum isn't properly documented
> anyway.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 56df86ef5a4d..3b42ba9fa473 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1127,7 +1127,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
> #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
>
> -/**
> +/*
> * i915_power_well_id:
this part would definitely deserve a space on the doc, but in the
current way it is I agree
that it better to remove.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> *
> * Platform specific IDs used to look up power wells and - except for custom
> --
> 2.11.0
>
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 1/3] Documentation/i915: remove sphinx conversion artefact
2017-08-10 12:29 ` [PATCH v2 1/3] Documentation/i915: remove sphinx conversion artefact Jani Nikula
@ 2017-08-10 15:19 ` Rodrigo Vivi
2017-08-10 16:13 ` Jani Nikula
0 siblings, 1 reply; 10+ messages in thread
From: Rodrigo Vivi @ 2017-08-10 15:19 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, Pandiyan Dhinakaran
On Thu, Aug 10, 2017 at 5:29 AM, Jani Nikula <jani.nikula@intel.com> wrote:
> Remove old warning about docproc directive that's not supported in the
> Sphinx toolchain.
I got confused... the warning is not supported by sphinx or docproc?
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> Documentation/gpu/i915.rst | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
> index 46875c2bcc31..32c32b89e2e5 100644
> --- a/Documentation/gpu/i915.rst
> +++ b/Documentation/gpu/i915.rst
> @@ -480,5 +480,3 @@ specific details than found in the more high-level sections.
>
> .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
> :internal:
> -
> -.. WARNING: DOCPROC directive not supported: !Cdrivers/gpu/drm/i915/i915_irq.c
> --
> 2.11.0
>
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 1/3] Documentation/i915: remove sphinx conversion artefact
2017-08-10 15:19 ` Rodrigo Vivi
@ 2017-08-10 16:13 ` Jani Nikula
2017-08-10 19:31 ` Rodrigo Vivi
0 siblings, 1 reply; 10+ messages in thread
From: Jani Nikula @ 2017-08-10 16:13 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, Pandiyan Dhinakaran
On Thu, 10 Aug 2017, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
> On Thu, Aug 10, 2017 at 5:29 AM, Jani Nikula <jani.nikula@intel.com> wrote:
>> Remove old warning about docproc directive that's not supported in the
>> Sphinx toolchain.
>
> I got confused... the warning is not supported by sphinx or docproc?
There used to be a docproc directive !C to ensure all (documented?)
functions in the specified file were used in the docbook build. The
docbook -> sphinx conversion retained those as commented out warnings in
the rst source. I don't think we'll have similar functionality in sphinx
anytime soon. So just nuke it.
BR,
Jani.
>
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> Documentation/gpu/i915.rst | 2 --
>> 1 file changed, 2 deletions(-)
>>
>> diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
>> index 46875c2bcc31..32c32b89e2e5 100644
>> --- a/Documentation/gpu/i915.rst
>> +++ b/Documentation/gpu/i915.rst
>> @@ -480,5 +480,3 @@ specific details than found in the more high-level sections.
>>
>> .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
>> :internal:
>> -
>> -.. WARNING: DOCPROC directive not supported: !Cdrivers/gpu/drm/i915/i915_irq.c
>> --
>> 2.11.0
>>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 1/3] Documentation/i915: remove sphinx conversion artefact
2017-08-10 16:13 ` Jani Nikula
@ 2017-08-10 19:31 ` Rodrigo Vivi
0 siblings, 0 replies; 10+ messages in thread
From: Rodrigo Vivi @ 2017-08-10 19:31 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, Pandiyan Dhinakaran
On Thu, Aug 10, 2017 at 9:13 AM, Jani Nikula <jani.nikula@intel.com> wrote:
> On Thu, 10 Aug 2017, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
>> On Thu, Aug 10, 2017 at 5:29 AM, Jani Nikula <jani.nikula@intel.com> wrote:
>>> Remove old warning about docproc directive that's not supported in the
>>> Sphinx toolchain.
>>
>> I got confused... the warning is not supported by sphinx or docproc?
>
> There used to be a docproc directive !C to ensure all (documented?)
> functions in the specified file were used in the docbook build. The
> docbook -> sphinx conversion retained those as commented out warnings in
> the rst source. I don't think we'll have similar functionality in sphinx
> anytime soon. So just nuke it.
Oh I see... makes sense
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> BR,
> Jani.
>
>>
>>>
>>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>>> ---
>>> Documentation/gpu/i915.rst | 2 --
>>> 1 file changed, 2 deletions(-)
>>>
>>> diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
>>> index 46875c2bcc31..32c32b89e2e5 100644
>>> --- a/Documentation/gpu/i915.rst
>>> +++ b/Documentation/gpu/i915.rst
>>> @@ -480,5 +480,3 @@ specific details than found in the more high-level sections.
>>>
>>> .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
>>> :internal:
>>> -
>>> -.. WARNING: DOCPROC directive not supported: !Cdrivers/gpu/drm/i915/i915_irq.c
>>> --
>>> 2.11.0
>>>
>
> --
> Jani Nikula, Intel Open Source Technology Center
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for drm/i915: add register macro definition style guide (rev2)
2017-08-10 12:55 ` ✗ Fi.CI.BAT: failure for drm/i915: add register macro definition style guide (rev2) Patchwork
@ 2017-08-10 20:11 ` Jani Nikula
0 siblings, 0 replies; 10+ messages in thread
From: Jani Nikula @ 2017-08-10 20:11 UTC (permalink / raw)
To: Patchwork; +Cc: intel-gfx
On Thu, 10 Aug 2017, Patchwork <patchwork@emeril.freedesktop.org> wrote:
> == Series Details ==
>
> Series: drm/i915: add register macro definition style guide (rev2)
> URL : https://patchwork.freedesktop.org/series/28370/
> State : failure
>
> == Summary ==
>
> Series 28370v2 drm/i915: add register macro definition style guide
> https://patchwork.freedesktop.org/api/1.0/series/28370/revisions/2/mbox/
>
> Test gem_exec_nop:
> Subgroup basic-parallel:
> pass -> INCOMPLETE (fi-byt-j1900)
Pushed, thanks for the review. I took a leap of faith and decided
comment and documentation changes didn't blow up the byt.
BR,
Jani.
> Test kms_cursor_legacy:
> Subgroup basic-busy-flip-before-cursor-atomic:
> fail -> PASS (fi-snb-2600) fdo#100215
>
> fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
>
> fi-bdw-5557u total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:438s
> fi-bdw-gvtdvm total:279 pass:265 dwarn:0 dfail:0 fail:0 skip:14 time:419s
> fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:363s
> fi-bsw-n3050 total:279 pass:243 dwarn:0 dfail:0 fail:0 skip:36 time:501s
> fi-bxt-j4205 total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:485s
> fi-byt-j1900 total:67 pass:57 dwarn:0 dfail:0 fail:0 skip:9
> fi-byt-n2820 total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:514s
> fi-glk-2a total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:578s
> fi-hsw-4770 total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:432s
> fi-hsw-4770r total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:410s
> fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:416s
> fi-ivb-3520m total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:516s
> fi-ivb-3770 total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:480s
> fi-kbl-7500u total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:459s
> fi-kbl-7560u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:564s
> fi-kbl-r total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:577s
> fi-pnv-d510 total:279 pass:223 dwarn:1 dfail:0 fail:0 skip:55 time:522s
> fi-skl-6260u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:447s
> fi-skl-6700k total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:645s
> fi-skl-6770hq total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:466s
> fi-skl-gvtdvm total:279 pass:266 dwarn:0 dfail:0 fail:0 skip:13 time:424s
> fi-skl-x1585l total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:465s
> fi-snb-2520m total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:551s
> fi-snb-2600 total:279 pass:250 dwarn:0 dfail:0 fail:0 skip:29 time:411s
>
> 0f3edcc5d40749f2ddddd26f5ada55a145e20350 drm-tip: 2017y-08m-10d-11h-21m-35s UTC integration manifest
> 22c6121825a3 drm/i915: add register macro definition style guide
> fcb595e35f95 drm/i915: enum i915_power_well_id is not proper kernel-doc
> 351d78b35d17 Documentation/i915: remove sphinx conversion artefact
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5366/
--
Jani Nikula, Intel Open Source Technology Center
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^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2017-08-10 20:11 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-08-10 12:29 [PATCH v2 0/3] drm/i915: add register macro definition style guide Jani Nikula
2017-08-10 12:29 ` [PATCH v2 1/3] Documentation/i915: remove sphinx conversion artefact Jani Nikula
2017-08-10 15:19 ` Rodrigo Vivi
2017-08-10 16:13 ` Jani Nikula
2017-08-10 19:31 ` Rodrigo Vivi
2017-08-10 12:29 ` [PATCH v2 2/3] drm/i915: enum i915_power_well_id is not proper kernel-doc Jani Nikula
2017-08-10 15:17 ` Rodrigo Vivi
2017-08-10 12:29 ` [PATCH v2 3/3] drm/i915: add register macro definition style guide Jani Nikula
2017-08-10 12:55 ` ✗ Fi.CI.BAT: failure for drm/i915: add register macro definition style guide (rev2) Patchwork
2017-08-10 20:11 ` Jani Nikula
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