[PATCH 0/3] Add SDHI Support

[PATCH 0/3] Add SDHI Support

[Biju Das]

This series aims to add SDHI support for r8a7743 SoC.

This series has been compiled and tested against renesas-dev tag
renesas-devel-20170814-v4.13-rc5.

There is no compile time dependencies.It has run time dependency on
[PATCH ] mmc: renesas_sdhi: Add r8a7743/5 support.
https://patchwork.kernel.org/patch/9898611/ 

Biju Das (3):
  ARM: dts: r8a7743: Add SDHI controllers
  ARM: dts: iwg20m: Enable SDHI0 controller
  ARM: dts: iwg20d-q7: Add SDHI1 support

 arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 48 +++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/r8a7743-iwg20m.dtsi   | 17 ++++++++++++
 arch/arm/boot/dts/r8a7743.dtsi          | 42 +++++++++++++++++++++++++++++
 3 files changed, 107 insertions(+)

-- 
1.9.1

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[PATCH 0/3] Add SDHI Support

[Biju Das]

This series aims to add SDHI support for r8a7743 SoC.

This series has been compiled and tested against renesas-dev tag
renesas-devel-20170814-v4.13-rc5.

There is no compile time dependencies.It has run time dependency on
[PATCH ] mmc: renesas_sdhi: Add r8a7743/5 support.
https://patchwork.kernel.org/patch/9898611/ 

Biju Das (3):
  ARM: dts: r8a7743: Add SDHI controllers
  ARM: dts: iwg20m: Enable SDHI0 controller
  ARM: dts: iwg20d-q7: Add SDHI1 support

 arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 48 +++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/r8a7743-iwg20m.dtsi   | 17 ++++++++++++
 arch/arm/boot/dts/r8a7743.dtsi          | 42 +++++++++++++++++++++++++++++
 3 files changed, 107 insertions(+)

-- 
1.9.1

[PATCH 0/3] Add SDHI Support

[Biju Das]

This series aims to add SDHI support for r8a7743 SoC.

This series has been compiled and tested against renesas-dev tag
renesas-devel-20170814-v4.13-rc5.

There is no compile time dependencies.It has run time dependency on
[PATCH ] mmc: renesas_sdhi: Add r8a7743/5 support.
https://patchwork.kernel.org/patch/9898611/ 

Biju Das (3):
  ARM: dts: r8a7743: Add SDHI controllers
  ARM: dts: iwg20m: Enable SDHI0 controller
  ARM: dts: iwg20d-q7: Add SDHI1 support

 arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 48 +++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/r8a7743-iwg20m.dtsi   | 17 ++++++++++++
 arch/arm/boot/dts/r8a7743.dtsi          | 42 +++++++++++++++++++++++++++++
 3 files changed, 107 insertions(+)

-- 
1.9.1

[PATCH 1/3] ARM: dts: r8a7743: Add SDHI controllers

[Biju Das]

Add the SDHI controllers to the r8a7743 device tree.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 arch/arm/boot/dts/r8a7743.dtsi | 42 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index ce80a26..3bd3ab5 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -754,6 +754,48 @@
 			max-frequency = <97500000>;
 			status = "disabled";
 		};
+
+		sdhi0: sd@ee100000 {
+			compatible = "renesas,sdhi-r8a7743";
+			reg = <0 0xee100000 0 0x328>;
+			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 314>;
+			dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+			       <&dmac1 0xcd>, <&dmac1 0xce>;
+			dma-names = "tx", "rx", "tx", "rx";
+			max-frequency = <195000000>;
+			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+			resets = <&cpg 314>;
+			status = "disabled";
+		};
+
+		sdhi1: sd@ee140000 {
+			compatible = "renesas,sdhi-r8a7743";
+			reg = <0 0xee140000 0 0x100>;
+			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 312>;
+			dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+			       <&dmac1 0xc1>, <&dmac1 0xc2>;
+			dma-names = "tx", "rx", "tx", "rx";
+			max-frequency = <97500000>;
+			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+			resets = <&cpg 312>;
+			status = "disabled";
+		};
+
+		sdhi2: sd@ee160000 {
+			compatible = "renesas,sdhi-r8a7743";
+			reg = <0 0xee160000 0 0x100>;
+			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 311>;
+			dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+			       <&dmac1 0xd3>, <&dmac1 0xd4>;
+			dma-names = "tx", "rx", "tx", "rx";
+			max-frequency = <97500000>;
+			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+			resets = <&cpg 311>;
+			status = "disabled";
+		};
 	};
 
 	/* External root clock */
-- 
1.9.1

[PATCH 1/3] ARM: dts: r8a7743: Add SDHI controllers

[Biju Das]

Add the SDHI controllers to the r8a7743 device tree.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 arch/arm/boot/dts/r8a7743.dtsi | 42 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index ce80a26..3bd3ab5 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -754,6 +754,48 @@
 			max-frequency = <97500000>;
 			status = "disabled";
 		};
+
+		sdhi0: sd at ee100000 {
+			compatible = "renesas,sdhi-r8a7743";
+			reg = <0 0xee100000 0 0x328>;
+			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 314>;
+			dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+			       <&dmac1 0xcd>, <&dmac1 0xce>;
+			dma-names = "tx", "rx", "tx", "rx";
+			max-frequency = <195000000>;
+			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+			resets = <&cpg 314>;
+			status = "disabled";
+		};
+
+		sdhi1: sd at ee140000 {
+			compatible = "renesas,sdhi-r8a7743";
+			reg = <0 0xee140000 0 0x100>;
+			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 312>;
+			dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+			       <&dmac1 0xc1>, <&dmac1 0xc2>;
+			dma-names = "tx", "rx", "tx", "rx";
+			max-frequency = <97500000>;
+			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+			resets = <&cpg 312>;
+			status = "disabled";
+		};
+
+		sdhi2: sd at ee160000 {
+			compatible = "renesas,sdhi-r8a7743";
+			reg = <0 0xee160000 0 0x100>;
+			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 311>;
+			dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+			       <&dmac1 0xd3>, <&dmac1 0xd4>;
+			dma-names = "tx", "rx", "tx", "rx";
+			max-frequency = <97500000>;
+			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+			resets = <&cpg 311>;
+			status = "disabled";
+		};
 	};
 
 	/* External root clock */
-- 
1.9.1

[PATCH 2/3] ARM: dts: iwg20m: Enable SDHI0 controller

[Biju Das]

Enable the SDHI0 controller on iWave RZG1M Qseven SOM.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 arch/arm/boot/dts/r8a7743-iwg20m.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
index ff79938..4119737 100644
--- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
+++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
@@ -9,6 +9,7 @@
  */
 
 #include "r8a7743.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	compatible = "iwave,g20m", "renesas,r8a7743";
@@ -42,6 +43,12 @@
 		groups = "mmc_data8_b", "mmc_ctrl";
 		function = "mmc";
 	};
+
+	sdhi0_pins: sd0 {
+		groups = "sdhi0_data4", "sdhi0_ctrl";
+		function = "sdhi0";
+		power-source = <3300>;
+	};
 };
 
 &mmcif0 {
@@ -53,3 +60,13 @@
 	non-removable;
 	status = "okay";
 };
+
+&sdhi0 {
+	pinctrl-0 = <&sdhi0_pins>;
+	pinctrl-names = "default";
+
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_3p3v>;
+	cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
-- 
1.9.1

[PATCH 2/3] ARM: dts: iwg20m: Enable SDHI0 controller

[Biju Das]

Enable the SDHI0 controller on iWave RZG1M Qseven SOM.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 arch/arm/boot/dts/r8a7743-iwg20m.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
index ff79938..4119737 100644
--- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
+++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
@@ -9,6 +9,7 @@
  */
 
 #include "r8a7743.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	compatible = "iwave,g20m", "renesas,r8a7743";
@@ -42,6 +43,12 @@
 		groups = "mmc_data8_b", "mmc_ctrl";
 		function = "mmc";
 	};
+
+	sdhi0_pins: sd0 {
+		groups = "sdhi0_data4", "sdhi0_ctrl";
+		function = "sdhi0";
+		power-source = <3300>;
+	};
 };
 
 &mmcif0 {
@@ -53,3 +60,13 @@
 	non-removable;
 	status = "okay";
 };
+
+&sdhi0 {
+	pinctrl-0 = <&sdhi0_pins>;
+	pinctrl-names = "default";
+
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_3p3v>;
+	cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
-- 
1.9.1

[PATCH 3/3] ARM: dts: iwg20d-q7: Add SDHI1 support

[Biju Das]

Define the iWave RainboW-G20D-Qseven board dependent part of the
SDHI1 device node.

Signed-off-by: Biju Das <biju.das-kTT6dE0pTRh9uiUsa/gSgQ@public.gmane.org>
---
 arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 48 +++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
index b3a1efa..b5ac0ff 100644
--- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
+++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
@@ -19,6 +19,29 @@
 		serial0 = &scif0;
 		ethernet0 = &avb;
 	};
+
+	vcc_sdhi1: regulator-vcc-sdhi1 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "SDHI1 Vcc";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;
+	};
+
+	vccq_sdhi1: regulator-vccq-sdhi1 {
+		compatible = "regulator-gpio";
+
+		regulator-name = "SDHI1 VccQ";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
+		gpios-states = <1>;
+		states = <3300000 1
+			  1800000 0>;
+	};
 };
 
 &pfc {
@@ -36,6 +59,18 @@
 		groups = "i2c2";
 		function = "i2c2";
 	};
+
+	sdhi1_pins: sd1 {
+		groups = "sdhi1_data4", "sdhi1_ctrl";
+		function = "sdhi1";
+		power-source = <3300>;
+	};
+
+	sdhi1_pins_uhs: sd1_uhs {
+		groups = "sdhi1_data4", "sdhi1_ctrl";
+		function = "sdhi1";
+		power-source = <1800>;
+	};
 };
 
 &scif0 {
@@ -72,3 +107,16 @@
 		reg = <0x68>;
 	};
 };
+
+&sdhi1 {
+	pinctrl-0 = <&sdhi1_pins>;
+	pinctrl-1 = <&sdhi1_pins_uhs>;
+	pinctrl-names = "default", "state_uhs";
+
+	vmmc-supply = <&vcc_sdhi1>;
+	vqmmc-supply = <&vccq_sdhi1>;
+	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+	sd-uhs-sdr50;
+	status = "okay";
+};
-- 
1.9.1

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[PATCH 3/3] ARM: dts: iwg20d-q7: Add SDHI1 support

[Biju Das]

Define the iWave RainboW-G20D-Qseven board dependent part of the
SDHI1 device node.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 48 +++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
index b3a1efa..b5ac0ff 100644
--- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
+++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
@@ -19,6 +19,29 @@
 		serial0 = &scif0;
 		ethernet0 = &avb;
 	};
+
+	vcc_sdhi1: regulator-vcc-sdhi1 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "SDHI1 Vcc";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;
+	};
+
+	vccq_sdhi1: regulator-vccq-sdhi1 {
+		compatible = "regulator-gpio";
+
+		regulator-name = "SDHI1 VccQ";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
+		gpios-states = <1>;
+		states = <3300000 1
+			  1800000 0>;
+	};
 };
 
 &pfc {
@@ -36,6 +59,18 @@
 		groups = "i2c2";
 		function = "i2c2";
 	};
+
+	sdhi1_pins: sd1 {
+		groups = "sdhi1_data4", "sdhi1_ctrl";
+		function = "sdhi1";
+		power-source = <3300>;
+	};
+
+	sdhi1_pins_uhs: sd1_uhs {
+		groups = "sdhi1_data4", "sdhi1_ctrl";
+		function = "sdhi1";
+		power-source = <1800>;
+	};
 };
 
 &scif0 {
@@ -72,3 +107,16 @@
 		reg = <0x68>;
 	};
 };
+
+&sdhi1 {
+	pinctrl-0 = <&sdhi1_pins>;
+	pinctrl-1 = <&sdhi1_pins_uhs>;
+	pinctrl-names = "default", "state_uhs";
+
+	vmmc-supply = <&vcc_sdhi1>;
+	vqmmc-supply = <&vccq_sdhi1>;
+	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+	sd-uhs-sdr50;
+	status = "okay";
+};
-- 
1.9.1

[PATCH 3/3] ARM: dts: iwg20d-q7: Add SDHI1 support

[Biju Das]

Define the iWave RainboW-G20D-Qseven board dependent part of the
SDHI1 device node.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 48 +++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
index b3a1efa..b5ac0ff 100644
--- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
+++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
@@ -19,6 +19,29 @@
 		serial0 = &scif0;
 		ethernet0 = &avb;
 	};
+
+	vcc_sdhi1: regulator-vcc-sdhi1 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "SDHI1 Vcc";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;
+	};
+
+	vccq_sdhi1: regulator-vccq-sdhi1 {
+		compatible = "regulator-gpio";
+
+		regulator-name = "SDHI1 VccQ";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
+		gpios-states = <1>;
+		states = <3300000 1
+			  1800000 0>;
+	};
 };
 
 &pfc {
@@ -36,6 +59,18 @@
 		groups = "i2c2";
 		function = "i2c2";
 	};
+
+	sdhi1_pins: sd1 {
+		groups = "sdhi1_data4", "sdhi1_ctrl";
+		function = "sdhi1";
+		power-source = <3300>;
+	};
+
+	sdhi1_pins_uhs: sd1_uhs {
+		groups = "sdhi1_data4", "sdhi1_ctrl";
+		function = "sdhi1";
+		power-source = <1800>;
+	};
 };
 
 &scif0 {
@@ -72,3 +107,16 @@
 		reg = <0x68>;
 	};
 };
+
+&sdhi1 {
+	pinctrl-0 = <&sdhi1_pins>;
+	pinctrl-1 = <&sdhi1_pins_uhs>;
+	pinctrl-names = "default", "state_uhs";
+
+	vmmc-supply = <&vcc_sdhi1>;
+	vqmmc-supply = <&vccq_sdhi1>;
+	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+	sd-uhs-sdr50;
+	status = "okay";
+};
-- 
1.9.1

Re: [PATCH 2/3] ARM: dts: iwg20m: Enable SDHI0 controller

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 315 bytes --]

> +
> +&sdhi0 {
> +	pinctrl-0 = <&sdhi0_pins>;
> +	pinctrl-names = "default";
> +
> +	vmmc-supply = <&reg_3p3v>;
> +	vqmmc-supply = <&reg_3p3v>;
> +	cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>;
> +	status = "okay";
> +};

Just to make sure: No 1.8V and UHS support (SDR50/104)? Or is this to be
tested and added later?


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

[PATCH 2/3] ARM: dts: iwg20m: Enable SDHI0 controller

[Wolfram Sang]

> +
> +&sdhi0 {
> +	pinctrl-0 = <&sdhi0_pins>;
> +	pinctrl-names = "default";
> +
> +	vmmc-supply = <&reg_3p3v>;
> +	vqmmc-supply = <&reg_3p3v>;
> +	cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>;
> +	status = "okay";
> +};

Just to make sure: No 1.8V and UHS support (SDR50/104)? Or is this to be
tested and added later?

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RE: [PATCH 2/3] ARM: dts: iwg20m: Enable SDHI0 controller

[Biju Das]

> -----Original Message-----
> From: Wolfram Sang [mailto:wsa@the-dreams.de]
> Sent: 21 August 2017 09:29
> To: Biju Das <biju.das@bp.renesas.com>
> Cc: Rob Herring <robh+dt@kernel.org>; Mark Rutland
> <mark.rutland@arm.com>; Simon Horman <horms@verge.net.au>; Magnus
> Damm <magnus.damm@gmail.com>; Chris Paterson
> <Chris.Paterson2@renesas.com>; Wolfram Sang <wsa+renesas@sang-
> engineering.com>; devicetree@vger.kernel.org; linux-renesas-
> soc@vger.kernel.org; linux-arm-kernel@lists.infradead.org
> Subject: Re: [PATCH 2/3] ARM: dts: iwg20m: Enable SDHI0 controller
>
> > +
> > +&sdhi0 {
> > +pinctrl-0 = <&sdhi0_pins>;
> > +pinctrl-names = "default";
> > +
> > +vmmc-supply = <&reg_3p3v>;
> > +vqmmc-supply = <&reg_3p3v>;
> > +cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>;
> > +status = "okay";
> > +};
>
> Just to make sure: No 1.8V and UHS support (SDR50/104)? Or is this to be
> tested and added later?

Thanks. The current hardware doesn't support 1.8V switching for SDHI0. There is a plan to
add this in future board varient, at that time we will add UHS support.







Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

[PATCH 2/3] ARM: dts: iwg20m: Enable SDHI0 controller

[Biju Das]

> -----Original Message-----
> From: Wolfram Sang [mailto:wsa at the-dreams.de]
> Sent: 21 August 2017 09:29
> To: Biju Das <biju.das@bp.renesas.com>
> Cc: Rob Herring <robh+dt@kernel.org>; Mark Rutland
> <mark.rutland@arm.com>; Simon Horman <horms@verge.net.au>; Magnus
> Damm <magnus.damm@gmail.com>; Chris Paterson
> <Chris.Paterson2@renesas.com>; Wolfram Sang <wsa+renesas@sang-
> engineering.com>; devicetree at vger.kernel.org; linux-renesas-
> soc at vger.kernel.org; linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH 2/3] ARM: dts: iwg20m: Enable SDHI0 controller
>
> > +
> > +&sdhi0 {
> > +pinctrl-0 = <&sdhi0_pins>;
> > +pinctrl-names = "default";
> > +
> > +vmmc-supply = <&reg_3p3v>;
> > +vqmmc-supply = <&reg_3p3v>;
> > +cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>;
> > +status = "okay";
> > +};
>
> Just to make sure: No 1.8V and UHS support (SDR50/104)? Or is this to be
> tested and added later?

Thanks. The current hardware doesn't support 1.8V switching for SDHI0. There is a plan to
add this in future board varient, at that time we will add UHS support.







Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

Re: [PATCH 2/3] ARM: dts: iwg20m: Enable SDHI0 controller

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 480 bytes --]


> > > +vmmc-supply = <&reg_3p3v>;
> > > +vqmmc-supply = <&reg_3p3v>;
> >
> > Just to make sure: No 1.8V and UHS support (SDR50/104)? Or is this to be
> > tested and added later?
> 
> Thanks. The current hardware doesn't support 1.8V switching for SDHI0. There is a plan to
> add this in future board varient, at that time we will add UHS support.

I see. Thanks for the info, patch looks good to me then:

Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>


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[PATCH 2/3] ARM: dts: iwg20m: Enable SDHI0 controller

[Wolfram Sang]

> > > +vmmc-supply = <&reg_3p3v>;
> > > +vqmmc-supply = <&reg_3p3v>;
> >
> > Just to make sure: No 1.8V and UHS support (SDR50/104)? Or is this to be
> > tested and added later?
> 
> Thanks. The current hardware doesn't support 1.8V switching for SDHI0. There is a plan to
> add this in future board varient, at that time we will add UHS support.

I see. Thanks for the info, patch looks good to me then:

Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

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Re: [PATCH 3/3] ARM: dts: iwg20d-q7: Add SDHI1 support

[Wolfram Sang]

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On Mon, Aug 14, 2017 at 12:49:49PM +0100, Biju Das wrote:
> Define the iWave RainboW-G20D-Qseven board dependent part of the
> SDHI1 device node.
> 
> Signed-off-by: Biju Das <biju.das-kTT6dE0pTRh9uiUsa/gSgQ@public.gmane.org>

Acked-by: Wolfram Sang <wsa+renesas-jBu1N2QxHDJrcw3mvpCnnVaTQe2KTcn/@public.gmane.org>


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Re: [PATCH 3/3] ARM: dts: iwg20d-q7: Add SDHI1 support

[Wolfram Sang]

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On Mon, Aug 14, 2017 at 12:49:49PM +0100, Biju Das wrote:
> Define the iWave RainboW-G20D-Qseven board dependent part of the
> SDHI1 device node.
> 
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>

Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>


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[PATCH 3/3] ARM: dts: iwg20d-q7: Add SDHI1 support

[Wolfram Sang]

On Mon, Aug 14, 2017 at 12:49:49PM +0100, Biju Das wrote:
> Define the iWave RainboW-G20D-Qseven board dependent part of the
> SDHI1 device node.
> 
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>

Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

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Re: [PATCH 0/3] Add SDHI Support

[Simon Horman]

On Mon, Aug 14, 2017 at 12:49:46PM +0100, Biju Das wrote:
> This series aims to add SDHI support for r8a7743 SoC.
> 
> This series has been compiled and tested against renesas-dev tag
> renesas-devel-20170814-v4.13-rc5.
> 
> There is no compile time dependencies.It has run time dependency on
> [PATCH ] mmc: renesas_sdhi: Add r8a7743/5 support.
> https://patchwork.kernel.org/patch/9898611/ 
> 
> Biju Das (3):
>   ARM: dts: r8a7743: Add SDHI controllers
>   ARM: dts: iwg20m: Enable SDHI0 controller
>   ARM: dts: iwg20d-q7: Add SDHI1 support

Thanks, applied for v4.15 with Wolfram's tags.

There was some fuzz when applying the last patch.
Please check that is is correct once I push today's devel tag
to the renesas tree.

[PATCH 0/3] Add SDHI Support

[Simon Horman]

On Mon, Aug 14, 2017 at 12:49:46PM +0100, Biju Das wrote:
> This series aims to add SDHI support for r8a7743 SoC.
> 
> This series has been compiled and tested against renesas-dev tag
> renesas-devel-20170814-v4.13-rc5.
> 
> There is no compile time dependencies.It has run time dependency on
> [PATCH ] mmc: renesas_sdhi: Add r8a7743/5 support.
> https://patchwork.kernel.org/patch/9898611/ 
> 
> Biju Das (3):
>   ARM: dts: r8a7743: Add SDHI controllers
>   ARM: dts: iwg20m: Enable SDHI0 controller
>   ARM: dts: iwg20d-q7: Add SDHI1 support

Thanks, applied for v4.15 with Wolfram's tags.

There was some fuzz when applying the last patch.
Please check that is is correct once I push today's devel tag
to the renesas tree.

RE: [PATCH 0/3] Add SDHI Support

[Biju Das]

> -----Original Message-----
> From: Simon Horman [mailto:horms-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org]
> Sent: 22 August 2017 09:03
> To: Biju Das <biju.das-kTT6dE0pTRh9uiUsa/gSgQ@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>; Mark Rutland
> <mark.rutland-5wv7dgnIgG8@public.gmane.org>; Magnus Damm <magnus.damm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>;
> Chris Paterson <Chris.Paterson2-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>; Wolfram Sang
> <wsa+renesas-jBu1N2QxHDJrcw3mvpCnnVaTQe2KTcn/@public.gmane.org>; devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-
> renesas-soc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Subject: Re: [PATCH 0/3] Add SDHI Support
>
> On Mon, Aug 14, 2017 at 12:49:46PM +0100, Biju Das wrote:
> > This series aims to add SDHI support for r8a7743 SoC.
> >
> > This series has been compiled and tested against renesas-dev tag
> > renesas-devel-20170814-v4.13-rc5.
> >
> > There is no compile time dependencies.It has run time dependency on
> > [PATCH ] mmc: renesas_sdhi: Add r8a7743/5 support.
> > https://patchwork.kernel.org/patch/9898611/
> >
> > Biju Das (3):
> >   ARM: dts: r8a7743: Add SDHI controllers
> >   ARM: dts: iwg20m: Enable SDHI0 controller
> >   ARM: dts: iwg20d-q7: Add SDHI1 support
>
> Thanks, applied for v4.15 with Wolfram's tags.
>
> There was some fuzz when applying the last patch.
> Please check that is is correct once I push today's devel tag to the renesas tree.

Thanks. I will check and let you know if there is any issues.




Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
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RE: [PATCH 0/3] Add SDHI Support

[Biju Das]

> -----Original Message-----
> From: Simon Horman [mailto:horms@verge.net.au]
> Sent: 22 August 2017 09:03
> To: Biju Das <biju.das@bp.renesas.com>
> Cc: Rob Herring <robh+dt@kernel.org>; Mark Rutland
> <mark.rutland@arm.com>; Magnus Damm <magnus.damm@gmail.com>;
> Chris Paterson <Chris.Paterson2@renesas.com>; Wolfram Sang
> <wsa+renesas@sang-engineering.com>; devicetree@vger.kernel.org; linux-
> renesas-soc@vger.kernel.org; linux-arm-kernel@lists.infradead.org
> Subject: Re: [PATCH 0/3] Add SDHI Support
>
> On Mon, Aug 14, 2017 at 12:49:46PM +0100, Biju Das wrote:
> > This series aims to add SDHI support for r8a7743 SoC.
> >
> > This series has been compiled and tested against renesas-dev tag
> > renesas-devel-20170814-v4.13-rc5.
> >
> > There is no compile time dependencies.It has run time dependency on
> > [PATCH ] mmc: renesas_sdhi: Add r8a7743/5 support.
> > https://patchwork.kernel.org/patch/9898611/
> >
> > Biju Das (3):
> >   ARM: dts: r8a7743: Add SDHI controllers
> >   ARM: dts: iwg20m: Enable SDHI0 controller
> >   ARM: dts: iwg20d-q7: Add SDHI1 support
>
> Thanks, applied for v4.15 with Wolfram's tags.
>
> There was some fuzz when applying the last patch.
> Please check that is is correct once I push today's devel tag to the renesas tree.

Thanks. I will check and let you know if there is any issues.




Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

[PATCH 0/3] Add SDHI Support

[Biju Das]

> -----Original Message-----
> From: Simon Horman [mailto:horms at verge.net.au]
> Sent: 22 August 2017 09:03
> To: Biju Das <biju.das@bp.renesas.com>
> Cc: Rob Herring <robh+dt@kernel.org>; Mark Rutland
> <mark.rutland@arm.com>; Magnus Damm <magnus.damm@gmail.com>;
> Chris Paterson <Chris.Paterson2@renesas.com>; Wolfram Sang
> <wsa+renesas@sang-engineering.com>; devicetree at vger.kernel.org; linux-
> renesas-soc at vger.kernel.org; linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH 0/3] Add SDHI Support
>
> On Mon, Aug 14, 2017 at 12:49:46PM +0100, Biju Das wrote:
> > This series aims to add SDHI support for r8a7743 SoC.
> >
> > This series has been compiled and tested against renesas-dev tag
> > renesas-devel-20170814-v4.13-rc5.
> >
> > There is no compile time dependencies.It has run time dependency on
> > [PATCH ] mmc: renesas_sdhi: Add r8a7743/5 support.
> > https://patchwork.kernel.org/patch/9898611/
> >
> > Biju Das (3):
> >   ARM: dts: r8a7743: Add SDHI controllers
> >   ARM: dts: iwg20m: Enable SDHI0 controller
> >   ARM: dts: iwg20d-q7: Add SDHI1 support
>
> Thanks, applied for v4.15 with Wolfram's tags.
>
> There was some fuzz when applying the last patch.
> Please check that is is correct once I push today's devel tag to the renesas tree.

Thanks. I will check and let you know if there is any issues.




Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.