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From: Roger Pau Monne <roger.pau@citrix.com>
To: Jan Beulich <JBeulich@suse.com>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v2 1/4] x86/dom0: prevent access to MMCFG areas for PVH Dom0
Date: Tue, 22 Aug 2017 14:54:21 +0100	[thread overview]
Message-ID: <20170822135421.mv6uzpsysn7xlpmh@MacBook-Pro-de-Roger.local> (raw)
In-Reply-To: <599C3F0F0200007800171FCF@prv-mh.provo.novell.com>

On Tue, Aug 22, 2017 at 06:26:23AM -0600, Jan Beulich wrote:
> >>> On 11.08.17 at 18:43, <roger.pau@citrix.com> wrote:
> > They are emulated by Xen, so they must not be mapped into Dom0 p2m.
> > Introduce a helper function to add the MMCFG areas to the list of
> > denied iomem regions for PVH Dom0.
> 
> "They are" or "They are going to be"?

This started as a series on top of vPCI, but I think it has a chance
of getting in before vPCI. I will change it.

> > --- a/xen/arch/x86/dom0_build.c
> > +++ b/xen/arch/x86/dom0_build.c
> > @@ -440,6 +440,10 @@ int __init dom0_setup_permissions(struct domain *d)
> >              rc |= rangeset_add_singleton(mmio_ro_ranges, mfn);
> >      }
> >  
> > +    /* For PVH prevent access to the MMCFG areas. */
> > +    if ( dom0_pvh )
> > +        rc |= pci_mmcfg_set_domain_permissions(d);
> 
> What about ones reported by Dom0 later on? Which then raises the
> question whether ...

This should be dealt with in the PHYSDEVOP_pci_mmcfg_reserved handler.
But since you propose to do white listing, I guess it doesn't matter
that much anymore.

> > @@ -175,6 +177,25 @@ void pci_mmcfg_arch_disable(unsigned int idx)
> >             cfg->pci_segment, cfg->start_bus_number, cfg->end_bus_number);
> >  }
> >  
> > +int pci_mmcfg_set_domain_permissions(struct domain *d)
> > +{
> > +    unsigned int idx;
> > +    int rc = 0;
> > +
> > +    for ( idx = 0; idx < pci_mmcfg_config_num; idx++ )
> > +    {
> > +        const struct acpi_mcfg_allocation *cfg = pci_mmcfg_virt[idx].cfg;
> > +        unsigned long start = PFN_DOWN(cfg->address) +
> > +                              PCI_BDF(cfg->start_bus_number, 0, 0);
> > +        unsigned long end = PFN_DOWN(cfg->address) +
> > +                            PCI_BDF(cfg->end_bus_number, ~0, ~0);
> > +
> > +        rc |= iomem_deny_access(d, start, end);
> 
> ... this shouldn't be unnecessary by, other than PV Dom0,
> starting out with no I/O memory being made accessible (i.e.
> white listing just like we decided we would do for other
> properties for PVH).

So would you like to switch to this white listing mode even for PV
Dom0, or just for PVH?

Should reserved regions and holes be added to it? Maybe only reserved
regions?

> Additionally while in the code that dom0_setup_permissions()
> was broken out from using |= was fine, there and here it's not
> really appropriate unless we want to continue to bake in the
> assumption that either iomem_deny_access() can only ever
> return a single error indicator or (b) the callers only care about
> the value being (non-)zero.

Right, I can fix that.

Thanks, Roger.

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  reply	other threads:[~2017-08-22 13:54 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-08-11 16:43 [PATCH v2 0/4] x86/pvh: implement iommu_inclusive_mapping for PVH Dom0 Roger Pau Monne
2017-08-11 16:43 ` [PATCH v2 1/4] x86/dom0: prevent access to MMCFG areas " Roger Pau Monne
2017-08-17  3:12   ` Tian, Kevin
2017-08-17  9:32     ` Roger Pau Monne
2017-08-28  6:04       ` Tian, Kevin
2017-08-22 12:26   ` Jan Beulich
2017-08-22 13:54     ` Roger Pau Monne [this message]
2017-08-23  8:16       ` Jan Beulich
2017-08-25 12:15         ` Roger Pau Monne
2017-08-25 12:25           ` Jan Beulich
2017-08-25 13:58             ` Roger Pau Monne
2017-08-28  6:18               ` Tian, Kevin
2017-08-29  7:33                 ` Roger Pau Monne
2017-08-31  7:32                   ` Chao Gao
2017-08-31  8:53                     ` Roger Pau Monne
2017-08-31  9:03                     ` Roger Pau Monne
2017-08-31  8:45                       ` Chao Gao
2017-08-31 10:09                         ` Roger Pau Monne
2017-09-04  6:25                           ` Chao Gao
2017-09-04  9:00                             ` Roger Pau Monné
2017-09-04  9:26                               ` Roger Pau Monné
2017-09-04  8:52                                 ` Chao Gao
2017-09-04 15:06                                   ` Roger Pau Monné
2017-09-04 15:19                                     ` Roger Pau Monné
2017-09-04 15:39                                     ` Jan Beulich
2017-08-11 16:43 ` [PATCH v2 2/4] x86/dom0: prevent PVH Dom0 from mapping read-only the IO APIC area Roger Pau Monne
2017-08-17  3:12   ` Tian, Kevin
2017-08-17  9:35     ` Roger Pau Monne
2017-08-28  6:07       ` Tian, Kevin
2017-08-22 12:28   ` Jan Beulich
2017-08-11 16:43 ` [PATCH v2 3/4] x86/vtd: introduce a PVH implementation of iommu_inclusive_mapping Roger Pau Monne
2017-08-17  3:28   ` Tian, Kevin
2017-08-17  9:39     ` Roger Pau Monne
2017-08-28  6:13       ` Tian, Kevin
2017-08-22 12:31   ` Jan Beulich
2017-08-22 14:01     ` Roger Pau Monne
2017-08-23  8:18       ` Jan Beulich
2017-08-28  6:14         ` Tian, Kevin
2017-08-29  7:39           ` Roger Pau Monne
2017-08-11 16:43 ` [PATCH v2 4/4] x86/dom0: re-order DMA remapping enabling for PVH Dom0 Roger Pau Monne
2017-08-22 12:37   ` Jan Beulich
2017-08-22 14:05     ` Roger Pau Monne
2017-08-23  8:21       ` Jan Beulich
2017-08-17  3:10 ` [PATCH v2 0/4] x86/pvh: implement iommu_inclusive_mapping " Tian, Kevin
2017-08-17  9:28   ` Roger Pau Monne

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