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* [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent
@ 2017-08-22 23:27 Rodrigo Vivi
  2017-08-22 23:43 ` ✓ Fi.CI.BAT: success for " Patchwork
                   ` (3 more replies)
  0 siblings, 4 replies; 13+ messages in thread
From: Rodrigo Vivi @ 2017-08-22 23:27 UTC (permalink / raw)
  To: intel-gfx; +Cc: Rodrigo Vivi

To avoid a potential hang condition with TLB invalidation
we need to enable masked bit 5 of MMIO 0xE5F0 at boot.

Same workaround was in place for previous platforms,
but the change for CNL is more on the register offset.
But also BSpec doesn't mention the bit 15 as set on gen9
platforms and mark bit as reserved on CNL.

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h        | 1 +
 drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d4ecb1905ad8..f31fab2651fb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7024,6 +7024,7 @@ enum {
 
 /* GEN8 chicken */
 #define HDC_CHICKEN0				_MMIO(0x7300)
+#define CNL_HDC_CHICKEN0			_MMIO(0xE5F0)
 #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE	(1<<15)
 #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
 #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index d23f18874309..26c35ce5f240 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1070,6 +1070,10 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
 	struct drm_i915_private *dev_priv = engine->i915;
 	int ret;
 
+	/* WaForceContextSaveRestoreNonCoherent:cnl */
+	WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
+			  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
+
 	/* WaDisableReplayBufferBankArbitrationOptimization:cnl */
 	WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
 			  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
-- 
2.13.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/cnl: WaForceContextSaveRestoreNonCoherent
  2017-08-22 23:27 [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent Rodrigo Vivi
@ 2017-08-22 23:43 ` Patchwork
  2017-08-23 20:00 ` [PATCH] " Oscar Mateo
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2017-08-22 23:43 UTC (permalink / raw)
  To: Rodrigo Vivi; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/cnl: WaForceContextSaveRestoreNonCoherent
URL   : https://patchwork.freedesktop.org/series/29184/
State : success

== Summary ==

Series 29184v1 drm/i915/cnl: WaForceContextSaveRestoreNonCoherent
https://patchwork.freedesktop.org/api/1.0/series/29184/revisions/1/mbox/

Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-b:
                dmesg-warn -> PASS       (fi-byt-n2820) fdo#101705

fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705

fi-bdw-5557u     total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  time:451s
fi-bdw-gvtdvm    total:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  time:433s
fi-blb-e6850     total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  time:355s
fi-bsw-n3050     total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  time:554s
fi-bwr-2160      total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  time:252s
fi-bxt-j4205     total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:525s
fi-byt-j1900     total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  time:525s
fi-byt-n2820     total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  time:509s
fi-elk-e7500     total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  time:432s
fi-glk-2a        total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:614s
fi-hsw-4770      total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:449s
fi-hsw-4770r     total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:423s
fi-ilk-650       total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  time:419s
fi-ivb-3520m     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:494s
fi-ivb-3770      total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:483s
fi-kbl-7260u     total:279  pass:268  dwarn:1   dfail:0   fail:0   skip:10  time:495s
fi-kbl-7500u     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:478s
fi-kbl-7560u     total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:597s
fi-kbl-r         total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:603s
fi-pnv-d510      total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  time:529s
fi-skl-6260u     total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:467s
fi-skl-6700k     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:480s
fi-skl-6770hq    total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:485s
fi-skl-gvtdvm    total:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  time:443s
fi-skl-x1585l    total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  time:491s
fi-snb-2520m     total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  time:546s
fi-snb-2600      total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  time:405s

489147dfdcc735baf773a6ec3698cf85a01d7008 drm-tip: 2017y-08m-22d-18h-44m-32s UTC integration manifest
81dc69b366f2 drm/i915/cnl: WaForceContextSaveRestoreNonCoherent

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5470/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 13+ messages in thread
* Re: [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent
  2017-08-22 23:27 [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent Rodrigo Vivi
  2017-08-22 23:43 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2017-08-23 20:00 ` Oscar Mateo
  2017-08-23 20:35   ` Rodrigo Vivi
  2017-08-23 21:30 ` ✓ Fi.CI.BAT: success for drm/i915/cnl: WaForceContextSaveRestoreNonCoherent (rev2) Patchwork
  2017-09-27  9:19 ` [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent Chris Wilson
  3 siblings, 1 reply; 13+ messages in thread
From: Oscar Mateo @ 2017-08-23 20:00 UTC (permalink / raw)
  To: Rodrigo Vivi, intel-gfx



On 08/22/2017 04:27 PM, Rodrigo Vivi wrote:
> To avoid a potential hang condition with TLB invalidation
> we need to enable masked bit 5 of MMIO 0xE5F0 at boot.
>
> Same workaround was in place for previous platforms,
> but the change for CNL is more on the register offset.

"but the register offset has changed for CNL"?

> But also BSpec doesn't mention the bit 15 as set on gen9
> platforms and mark bit as reserved on CNL.
>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h        | 1 +
>   drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
>   2 files changed, 5 insertions(+)

Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>

> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d4ecb1905ad8..f31fab2651fb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7024,6 +7024,7 @@ enum {
>   
>   /* GEN8 chicken */
>   #define HDC_CHICKEN0				_MMIO(0x7300)
> +#define CNL_HDC_CHICKEN0			_MMIO(0xE5F0)
>   #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE	(1<<15)
>   #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
>   #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index d23f18874309..26c35ce5f240 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1070,6 +1070,10 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
>   	struct drm_i915_private *dev_priv = engine->i915;
>   	int ret;
>   
> +	/* WaForceContextSaveRestoreNonCoherent:cnl */
> +	WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
> +			  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
> +
>   	/* WaDisableReplayBufferBankArbitrationOptimization:cnl */
>   	WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
>   			  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 13+ messages in thread
* [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent
  2017-08-23 20:00 ` [PATCH] " Oscar Mateo
@ 2017-08-23 20:35   ` Rodrigo Vivi
  2017-08-23 21:48     ` Rodrigo Vivi
  0 siblings, 1 reply; 13+ messages in thread
From: Rodrigo Vivi @ 2017-08-23 20:35 UTC (permalink / raw)
  To: intel-gfx; +Cc: Rodrigo Vivi

To avoid a potential hang condition with TLB invalidation
we need to enable masked bit 5 of MMIO 0xE5F0 at boot.

Same workaround was in place for previous platforms,
but the register offset has changed for CNL.
But also BSpec doesn't mention the bit 15 as set on gen9
platforms and mark bit as reserved on CNL.

v2: Improve commit message accepting Oscar's suggestion.

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170822232715.3220-1-rodrigo.vivi@intel.com
---
 drivers/gpu/drm/i915/i915_reg.h        | 1 +
 drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d9b0249fe5a1..c59c590e45c4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7024,6 +7024,7 @@ enum {
 
 /* GEN8 chicken */
 #define HDC_CHICKEN0				_MMIO(0x7300)
+#define CNL_HDC_CHICKEN0			_MMIO(0xE5F0)
 #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE	(1<<15)
 #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
 #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index d7e1ccf778a2..a6ac9d0a4156 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1070,6 +1070,10 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
 	struct drm_i915_private *dev_priv = engine->i915;
 	int ret;
 
+	/* WaForceContextSaveRestoreNonCoherent:cnl */
+	WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
+			  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
+
 	/* WaDisableReplayBufferBankArbitrationOptimization:cnl */
 	WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
 			  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
-- 
2.13.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/cnl: WaForceContextSaveRestoreNonCoherent (rev2)
  2017-08-22 23:27 [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent Rodrigo Vivi
  2017-08-22 23:43 ` ✓ Fi.CI.BAT: success for " Patchwork
  2017-08-23 20:00 ` [PATCH] " Oscar Mateo
@ 2017-08-23 21:30 ` Patchwork
  2017-09-27  9:19 ` [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent Chris Wilson
  3 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2017-08-23 21:30 UTC (permalink / raw)
  To: Rodrigo Vivi; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/cnl: WaForceContextSaveRestoreNonCoherent (rev2)
URL   : https://patchwork.freedesktop.org/series/29184/
State : success

== Summary ==

Series 29184v2 drm/i915/cnl: WaForceContextSaveRestoreNonCoherent
https://patchwork.freedesktop.org/api/1.0/series/29184/revisions/2/mbox/

Test kms_flip:
        Subgroup basic-flip-vs-modeset:
                skip       -> PASS       (fi-skl-x1585l) fdo#101781
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-b:
                dmesg-warn -> PASS       (fi-byt-n2820) fdo#101705

fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705

fi-bdw-5557u     total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  time:458s
fi-bdw-gvtdvm    total:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  time:442s
fi-blb-e6850     total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  time:362s
fi-bsw-n3050     total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  time:551s
fi-bwr-2160      total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  time:253s
fi-bxt-j4205     total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:524s
fi-byt-j1900     total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  time:529s
fi-byt-n2820     total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  time:517s
fi-elk-e7500     total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  time:434s
fi-glk-2a        total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:611s
fi-hsw-4770      total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:451s
fi-hsw-4770r     total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:424s
fi-ilk-650       total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  time:427s
fi-ivb-3520m     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:498s
fi-ivb-3770      total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:478s
fi-kbl-7500u     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:475s
fi-kbl-7560u     total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:594s
fi-kbl-r         total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:597s
fi-pnv-d510      total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  time:525s
fi-skl-6260u     total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:477s
fi-skl-6700k     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:484s
fi-skl-6770hq    total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:487s
fi-skl-gvtdvm    total:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  time:443s
fi-skl-x1585l    total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:517s
fi-snb-2520m     total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  time:570s
fi-snb-2600      total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  time:406s

66e54f108e4fdf9209b4e2a6bd58450d4d74c4f7 drm-tip: 2017y-08m-23d-20h-35m-42s UTC integration manifest
ac58ab675453 drm/i915/cnl: WaForceContextSaveRestoreNonCoherent

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5479/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 13+ messages in thread
* Re: [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent
  2017-08-23 20:35   ` Rodrigo Vivi
@ 2017-08-23 21:48     ` Rodrigo Vivi
  0 siblings, 0 replies; 13+ messages in thread
From: Rodrigo Vivi @ 2017-08-23 21:48 UTC (permalink / raw)
  To: Rodrigo Vivi; +Cc: intel-gfx

patch merged to dinq. thanks for the review and suggestion.


On Wed, Aug 23, 2017 at 1:35 PM, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> To avoid a potential hang condition with TLB invalidation
> we need to enable masked bit 5 of MMIO 0xE5F0 at boot.
>
> Same workaround was in place for previous platforms,
> but the register offset has changed for CNL.
> But also BSpec doesn't mention the bit 15 as set on gen9
> platforms and mark bit as reserved on CNL.
>
> v2: Improve commit message accepting Oscar's suggestion.
>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
> Link: https://patchwork.freedesktop.org/patch/msgid/20170822232715.3220-1-rodrigo.vivi@intel.com

with proper link fixed when merging, instead of this one...

> ---
>  drivers/gpu/drm/i915/i915_reg.h        | 1 +
>  drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
>  2 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d9b0249fe5a1..c59c590e45c4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7024,6 +7024,7 @@ enum {
>
>  /* GEN8 chicken */
>  #define HDC_CHICKEN0                           _MMIO(0x7300)
> +#define CNL_HDC_CHICKEN0                       _MMIO(0xE5F0)
>  #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE        (1<<15)
>  #define  HDC_FENCE_DEST_SLM_DISABLE            (1<<14)
>  #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED       (1<<11)
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index d7e1ccf778a2..a6ac9d0a4156 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1070,6 +1070,10 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
>         struct drm_i915_private *dev_priv = engine->i915;
>         int ret;
>
> +       /* WaForceContextSaveRestoreNonCoherent:cnl */
> +       WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
> +                         HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
> +
>         /* WaDisableReplayBufferBankArbitrationOptimization:cnl */
>         WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
>                           GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
> --
> 2.13.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 13+ messages in thread
* Re: [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent
  2017-08-22 23:27 [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent Rodrigo Vivi
                   ` (2 preceding siblings ...)
  2017-08-23 21:30 ` ✓ Fi.CI.BAT: success for drm/i915/cnl: WaForceContextSaveRestoreNonCoherent (rev2) Patchwork
@ 2017-09-27  9:19 ` Chris Wilson
  2017-09-27 10:37   ` Mika Kuoppala
  3 siblings, 1 reply; 13+ messages in thread
From: Chris Wilson @ 2017-09-27  9:19 UTC (permalink / raw)
  To: intel-gfx; +Cc: Rodrigo Vivi

Quoting Rodrigo Vivi (2017-08-23 00:27:15)
> To avoid a potential hang condition with TLB invalidation
> we need to enable masked bit 5 of MMIO 0xE5F0 at boot.
> 
> Same workaround was in place for previous platforms,
> but the change for CNL is more on the register offset.
> But also BSpec doesn't mention the bit 15 as set on gen9
> platforms and mark bit as reserved on CNL.
> 
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h        | 1 +
>  drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
>  2 files changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d4ecb1905ad8..f31fab2651fb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7024,6 +7024,7 @@ enum {
>  
>  /* GEN8 chicken */
>  #define HDC_CHICKEN0                           _MMIO(0x7300)
> +#define CNL_HDC_CHICKEN0                       _MMIO(0xE5F0)
>  #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE        (1<<15)
>  #define  HDC_FENCE_DEST_SLM_DISABLE            (1<<14)
>  #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED       (1<<11)
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index d23f18874309..26c35ce5f240 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1070,6 +1070,10 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
>         struct drm_i915_private *dev_priv = engine->i915;
>         int ret;
>  
> +       /* WaForceContextSaveRestoreNonCoherent:cnl */
> +       WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
> +                         HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);

This register is not sticky (i.e. does not retain its value even with a
powercontext loaded). Does it even exist?
-Chris
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^ permalink raw reply	[flat|nested] 13+ messages in thread
* Re: [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent
  2017-09-27  9:19 ` [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent Chris Wilson
@ 2017-09-27 10:37   ` Mika Kuoppala
  2017-09-27 17:37     ` Oscar Mateo
  0 siblings, 1 reply; 13+ messages in thread
From: Mika Kuoppala @ 2017-09-27 10:37 UTC (permalink / raw)
  To: Chris Wilson, intel-gfx; +Cc: Rodrigo Vivi

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Quoting Rodrigo Vivi (2017-08-23 00:27:15)
>> To avoid a potential hang condition with TLB invalidation
>> we need to enable masked bit 5 of MMIO 0xE5F0 at boot.
>> 
>> Same workaround was in place for previous platforms,
>> but the change for CNL is more on the register offset.
>> But also BSpec doesn't mention the bit 15 as set on gen9
>> platforms and mark bit as reserved on CNL.
>> 
>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> Cc: Oscar Mateo <oscar.mateo@intel.com>
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h        | 1 +
>>  drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
>>  2 files changed, 5 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index d4ecb1905ad8..f31fab2651fb 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -7024,6 +7024,7 @@ enum {
>>  
>>  /* GEN8 chicken */
>>  #define HDC_CHICKEN0                           _MMIO(0x7300)
>> +#define CNL_HDC_CHICKEN0                       _MMIO(0xE5F0)
>>  #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE        (1<<15)
>>  #define  HDC_FENCE_DEST_SLM_DISABLE            (1<<14)
>>  #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED       (1<<11)
>> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
>> index d23f18874309..26c35ce5f240 100644
>> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
>> @@ -1070,6 +1070,10 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
>>         struct drm_i915_private *dev_priv = engine->i915;
>>         int ret;
>>  
>> +       /* WaForceContextSaveRestoreNonCoherent:cnl */
>> +       WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
>> +                         HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
>
> This register is not sticky (i.e. does not retain its value even with a
> powercontext loaded). Does it even exist?
> -Chris

That is a good question. The documentation indicates it does
and evidence indicates that it doesn't.

I will check when I get cnl unless someone beats me to it.

-Mika

> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply	[flat|nested] 13+ messages in thread
* Re: [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent
  2017-09-27 10:37   ` Mika Kuoppala
@ 2017-09-27 17:37     ` Oscar Mateo
  2017-09-27 17:42       ` Chris Wilson
  2017-09-28  9:46       ` Chris Wilson
  0 siblings, 2 replies; 13+ messages in thread
From: Oscar Mateo @ 2017-09-27 17:37 UTC (permalink / raw)
  To: Mika Kuoppala, Chris Wilson, Rodrigo Vivi, intel-gfx



On 09/27/2017 03:37 AM, Mika Kuoppala wrote:
> Chris Wilson <chris@chris-wilson.co.uk> writes:
>
>> Quoting Rodrigo Vivi (2017-08-23 00:27:15)
>>> To avoid a potential hang condition with TLB invalidation
>>> we need to enable masked bit 5 of MMIO 0xE5F0 at boot.
>>>
>>> Same workaround was in place for previous platforms,
>>> but the change for CNL is more on the register offset.
>>> But also BSpec doesn't mention the bit 15 as set on gen9
>>> platforms and mark bit as reserved on CNL.
>>>
>>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>>> Cc: Oscar Mateo <oscar.mateo@intel.com>
>>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/i915_reg.h        | 1 +
>>>   drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
>>>   2 files changed, 5 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>> index d4ecb1905ad8..f31fab2651fb 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -7024,6 +7024,7 @@ enum {
>>>   
>>>   /* GEN8 chicken */
>>>   #define HDC_CHICKEN0                           _MMIO(0x7300)
>>> +#define CNL_HDC_CHICKEN0                       _MMIO(0xE5F0)
>>>   #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE        (1<<15)
>>>   #define  HDC_FENCE_DEST_SLM_DISABLE            (1<<14)
>>>   #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED       (1<<11)
>>> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
>>> index d23f18874309..26c35ce5f240 100644
>>> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
>>> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
>>> @@ -1070,6 +1070,10 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
>>>          struct drm_i915_private *dev_priv = engine->i915;
>>>          int ret;
>>>   
>>> +       /* WaForceContextSaveRestoreNonCoherent:cnl */
>>> +       WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
>>> +                         HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
>> This register is not sticky (i.e. does not retain its value even with a
>> powercontext loaded). Does it even exist?
>> -Chris
> That is a good question. The documentation indicates it does
> and evidence indicates that it doesn't.
>
> I will check when I get cnl unless someone beats me to it.
>
> -Mika

Hmmmm... there is a "programming note" in the BSpec for CNL+ that says:

"The register is write-only from LRI command. However, it is readable 
for context save."

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^ permalink raw reply	[flat|nested] 13+ messages in thread
* Re: [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent
  2017-09-27 17:37     ` Oscar Mateo
@ 2017-09-27 17:42       ` Chris Wilson
  2017-09-28  9:46       ` Chris Wilson
  1 sibling, 0 replies; 13+ messages in thread
From: Chris Wilson @ 2017-09-27 17:42 UTC (permalink / raw)
  To: Oscar Mateo, Mika Kuoppala, Rodrigo Vivi, intel-gfx

Quoting Oscar Mateo (2017-09-27 18:37:07)
> 
> 
> On 09/27/2017 03:37 AM, Mika Kuoppala wrote:
> > Chris Wilson <chris@chris-wilson.co.uk> writes:
> >
> >> Quoting Rodrigo Vivi (2017-08-23 00:27:15)
> >>> To avoid a potential hang condition with TLB invalidation
> >>> we need to enable masked bit 5 of MMIO 0xE5F0 at boot.
> >>>
> >>> Same workaround was in place for previous platforms,
> >>> but the change for CNL is more on the register offset.
> >>> But also BSpec doesn't mention the bit 15 as set on gen9
> >>> platforms and mark bit as reserved on CNL.
> >>>
> >>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> >>> Cc: Oscar Mateo <oscar.mateo@intel.com>
> >>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >>> ---
> >>>   drivers/gpu/drm/i915/i915_reg.h        | 1 +
> >>>   drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
> >>>   2 files changed, 5 insertions(+)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >>> index d4ecb1905ad8..f31fab2651fb 100644
> >>> --- a/drivers/gpu/drm/i915/i915_reg.h
> >>> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >>> @@ -7024,6 +7024,7 @@ enum {
> >>>   
> >>>   /* GEN8 chicken */
> >>>   #define HDC_CHICKEN0                           _MMIO(0x7300)
> >>> +#define CNL_HDC_CHICKEN0                       _MMIO(0xE5F0)
> >>>   #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE        (1<<15)
> >>>   #define  HDC_FENCE_DEST_SLM_DISABLE            (1<<14)
> >>>   #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED       (1<<11)
> >>> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> >>> index d23f18874309..26c35ce5f240 100644
> >>> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> >>> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> >>> @@ -1070,6 +1070,10 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
> >>>          struct drm_i915_private *dev_priv = engine->i915;
> >>>          int ret;
> >>>   
> >>> +       /* WaForceContextSaveRestoreNonCoherent:cnl */
> >>> +       WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
> >>> +                         HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
> >> This register is not sticky (i.e. does not retain its value even with a
> >> powercontext loaded). Does it even exist?
> >> -Chris
> > That is a good question. The documentation indicates it does
> > and evidence indicates that it doesn't.
> >
> > I will check when I get cnl unless someone beats me to it.
> >
> > -Mika
> 
> Hmmmm... there is a "programming note" in the BSpec for CNL+ that says:
> 
> "The register is write-only from LRI command. However, it is readable 
> for context save."

Ugh. So gem_workarounds can't read it directly or via SRM to check we
set it. But if we dumped the context image, we could find it. The test
will just have to learn to live without it.
-Chris
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^ permalink raw reply	[flat|nested] 13+ messages in thread
* Re: [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent
  2017-09-27 17:37     ` Oscar Mateo
  2017-09-27 17:42       ` Chris Wilson
@ 2017-09-28  9:46       ` Chris Wilson
  2017-09-28 20:56         ` Oscar Mateo
  1 sibling, 1 reply; 13+ messages in thread
From: Chris Wilson @ 2017-09-28  9:46 UTC (permalink / raw)
  To: Oscar Mateo, Mika Kuoppala, Rodrigo Vivi, intel-gfx

Stealing the thread for another gem_workarounds conundrum.

After a reset, we lose the RING_FORCE_TO_NONPRIV registers. If they
where in the context image as we presumed, the values would be retained
and they can be read back from before reset, so it's not the case of
write-only register!

So are they the mythical powercontext but require an LRI after reset to
restore the settings for all logical contexts? Or can we make those into
regular MMIO?
-Chris
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^ permalink raw reply	[flat|nested] 13+ messages in thread
* Re: [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent
  2017-09-28  9:46       ` Chris Wilson
@ 2017-09-28 20:56         ` Oscar Mateo
  2017-09-28 21:38           ` Oscar Mateo
  0 siblings, 1 reply; 13+ messages in thread
From: Oscar Mateo @ 2017-09-28 20:56 UTC (permalink / raw)
  To: Chris Wilson, Mika Kuoppala, Rodrigo Vivi, intel-gfx



On 09/28/2017 02:46 AM, Chris Wilson wrote:
> Stealing the thread for another gem_workarounds conundrum.
>
> After a reset, we lose the RING_FORCE_TO_NONPRIV registers. If they
> where in the context image as we presumed, the values would be retained
> and they can be read back from before reset, so it's not the case of
> write-only register!
>
> So are they the mythical powercontext but require an LRI after reset to
> restore the settings for all logical contexts? Or can we make those into
> regular MMIO?
> -Chris

I cannot see these in any the context image formats, no matter the GEN, 
so I suspect they are regular (but privileged) MMIO registers. I think 
by "These are global registers and power context save/restored" they 
simply mean that they survive RC6.
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^ permalink raw reply	[flat|nested] 13+ messages in thread
* Re: [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent
  2017-09-28 20:56         ` Oscar Mateo
@ 2017-09-28 21:38           ` Oscar Mateo
  0 siblings, 0 replies; 13+ messages in thread
From: Oscar Mateo @ 2017-09-28 21:38 UTC (permalink / raw)
  To: Chris Wilson, Mika Kuoppala, Rodrigo Vivi, intel-gfx



On 09/28/2017 01:56 PM, Oscar Mateo wrote:
>
>
> On 09/28/2017 02:46 AM, Chris Wilson wrote:
>> Stealing the thread for another gem_workarounds conundrum.
>>
>> After a reset, we lose the RING_FORCE_TO_NONPRIV registers. If they
>> where in the context image as we presumed, the values would be retained
>> and they can be read back from before reset, so it's not the case of
>> write-only register!
>>
>> So are they the mythical powercontext but require an LRI after reset to
>> restore the settings for all logical contexts? Or can we make those into
>> regular MMIO?
>> -Chris
>
> I cannot see these in any the context image formats, no matter the 
> GEN, so I suspect they are regular (but privileged) MMIO registers. I 
> think by "These are global registers and power context save/restored" 
> they simply mean that they survive RC6.

And, sure enough, these registers do appear in the "Render Engine Power 
Context" (save/restored by PM), not to be confused with the "Register 
State Context" (the usual HW context)
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^ permalink raw reply	[flat|nested] 13+ messages in thread
end of thread, other threads:[~2017-09-28 21:38 UTC | newest]

Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-08-22 23:27 [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent Rodrigo Vivi
2017-08-22 23:43 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-08-23 20:00 ` [PATCH] " Oscar Mateo
2017-08-23 20:35   ` Rodrigo Vivi
2017-08-23 21:48     ` Rodrigo Vivi
2017-08-23 21:30 ` ✓ Fi.CI.BAT: success for drm/i915/cnl: WaForceContextSaveRestoreNonCoherent (rev2) Patchwork
2017-09-27  9:19 ` [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent Chris Wilson
2017-09-27 10:37   ` Mika Kuoppala
2017-09-27 17:37     ` Oscar Mateo
2017-09-27 17:42       ` Chris Wilson
2017-09-28  9:46       ` Chris Wilson
2017-09-28 20:56         ` Oscar Mateo
2017-09-28 21:38           ` Oscar Mateo

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