* [PATCH 1/4] drm/i915: Introduce intel_ddi_dp_level.
@ 2017-08-16 20:19 Rodrigo Vivi
2017-08-16 20:19 ` [PATCH 2/4] drm/i915: decouple gen9 and gen10 dp signal levels Rodrigo Vivi
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Rodrigo Vivi @ 2017-08-16 20:19 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
No functional changes. This only moves the DP level
selection to a separated function that will be later
used to organize better the vswing sequences.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 4b4fd1f8110b..dd2bdbe82b47 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2054,18 +2054,22 @@ static uint32_t translate_signal_level(int signal_levels)
return 0;
}
+static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
+{
+ uint8_t train_set = intel_dp->train_set[0];
+ int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
+ DP_TRAIN_PRE_EMPHASIS_MASK);
+
+ return translate_signal_level(signal_levels);
+}
+
uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
{
struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
struct intel_encoder *encoder = &dport->base;
- uint8_t train_set = intel_dp->train_set[0];
- int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
- DP_TRAIN_PRE_EMPHASIS_MASK);
enum port port = dport->port;
- uint32_t level;
-
- level = translate_signal_level(signal_levels);
+ uint32_t level = intel_ddi_dp_level(intel_dp);
if (IS_GEN9_BC(dev_priv))
skl_ddi_set_iboost(encoder, level);
--
2.13.2
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^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/4] drm/i915: decouple gen9 and gen10 dp signal levels.
2017-08-16 20:19 [PATCH 1/4] drm/i915: Introduce intel_ddi_dp_level Rodrigo Vivi
@ 2017-08-16 20:19 ` Rodrigo Vivi
2017-08-25 12:46 ` Ville Syrjälä
2017-08-16 20:19 ` [PATCH 3/4] drm/i915: Align vswing sequences with old ddi buffer registers Rodrigo Vivi
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: Rodrigo Vivi @ 2017-08-16 20:19 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
Let's decouple bxt, glk and cnl dp signal levels
from other DDIs to avoid confusion.
No functional change. Only a reorg to avoid messing
with currently working DP signal levels when
moving voltage swing sequences around to match spec.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 26 ++++++++++++++++----------
drivers/gpu/drm/i915/intel_dp.c | 10 ++++------
drivers/gpu/drm/i915/intel_drv.h | 1 +
3 files changed, 21 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index dd2bdbe82b47..9891ad40d1dc 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2063,23 +2063,29 @@ static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
return translate_signal_level(signal_levels);
}
-uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
+u32 bxt_signal_levels(struct intel_dp *intel_dp)
{
struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
struct intel_encoder *encoder = &dport->base;
enum port port = dport->port;
- uint32_t level = intel_ddi_dp_level(intel_dp);
+ u32 level = intel_ddi_dp_level(intel_dp);
- if (IS_GEN9_BC(dev_priv))
- skl_ddi_set_iboost(encoder, level);
- else if (IS_GEN9_LP(dev_priv))
- bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
- else if (IS_CANNONLAKE(dev_priv)) {
+ if (IS_CANNONLAKE(dev_priv))
cnl_ddi_vswing_sequence(encoder, level);
- /* DDI_BUF_CTL bits 27:24 are reserved on CNL */
- return 0;
- }
+ else
+ bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
+
+ return 0;
+}
+
+uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
+ struct intel_encoder *encoder = &dport->base;
+ uint32_t level = intel_ddi_dp_level(intel_dp);
+
+ skl_ddi_set_iboost(encoder, level);
return DDI_BUF_TRANS_SELECT(level);
}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4fd4853b2250..1af4b227e758 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3506,13 +3506,11 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
uint32_t signal_levels, mask = 0;
uint8_t train_set = intel_dp->train_set[0];
- if (HAS_DDI(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+ signal_levels = bxt_signal_levels(intel_dp);
+ } else if (HAS_DDI(dev_priv)) {
signal_levels = ddi_signal_levels(intel_dp);
-
- if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv))
- signal_levels = 0;
- else
- mask = DDI_BUF_EMP_MASK;
+ mask = DDI_BUF_EMP_MASK;
} else if (IS_CHERRYVIEW(dev_priv)) {
signal_levels = chv_signal_levels(intel_dp);
} else if (IS_VALLEYVIEW(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index fa47285918f4..913cccc54ad2 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1272,6 +1272,7 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config);
void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
bool state);
+u32 bxt_signal_levels(struct intel_dp *intel_dp);
uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
--
2.13.2
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/4] drm/i915: Align vswing sequences with old ddi buffer registers.
2017-08-16 20:19 [PATCH 1/4] drm/i915: Introduce intel_ddi_dp_level Rodrigo Vivi
2017-08-16 20:19 ` [PATCH 2/4] drm/i915: decouple gen9 and gen10 dp signal levels Rodrigo Vivi
@ 2017-08-16 20:19 ` Rodrigo Vivi
2017-08-16 20:19 ` [RFC PATCH 4/4] drm/i915: Enable voltage swing before enabling DDI_BUF_CTL Rodrigo Vivi
2017-08-16 20:37 ` ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Introduce intel_ddi_dp_level Patchwork
3 siblings, 0 replies; 9+ messages in thread
From: Rodrigo Vivi @ 2017-08-16 20:19 UTC (permalink / raw)
To: intel-gfx; +Cc: Vandana Kannan, Rodrigo Vivi
Vswing sequences on BXT and CNL are equivalent
to the ddi buffer registers setting on other platforms.
For some reason it got aligned with skl_ddi_set_iboost what
is semantically incorrect. This forced us to keep skipping
ddi buffer translation tables on the platforms that has
the vswing sequences.
v2: Don't mess with DP signal levels on this patch.
Cc: Vandana Kannan <vandana.kannan@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 22 ++++++++++------------
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 9891ad40d1dc..a6056bb4f801 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -688,9 +688,6 @@ static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
enum port port = intel_ddi_get_encoder_port(encoder);
const struct ddi_buf_trans *ddi_translations;
- if (IS_GEN9_LP(dev_priv))
- return;
-
switch (encoder->type) {
case INTEL_OUTPUT_EDP:
ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv,
@@ -741,9 +738,6 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder)
enum port port = intel_ddi_get_encoder_port(encoder);
const struct ddi_buf_trans *ddi_translations_hdmi;
- if (IS_GEN9_LP(dev_priv))
- return;
-
hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
if (IS_GEN9_BC(dev_priv)) {
@@ -2151,7 +2145,9 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
- intel_prepare_dp_ddi_buffers(encoder);
+ if (!IS_GEN9_LP(dev_priv) && !IS_CANNONLAKE(dev_priv))
+ intel_prepare_dp_ddi_buffers(encoder);
+
intel_ddi_init_dp_buf_reg(encoder);
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
intel_dp_start_link_train(intel_dp);
@@ -2177,14 +2173,16 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
- intel_prepare_hdmi_ddi_buffers(encoder);
- if (IS_GEN9_BC(dev_priv))
- skl_ddi_set_iboost(encoder, level);
+ if (IS_CANNONLAKE(dev_priv))
+ cnl_ddi_vswing_sequence(encoder, level);
else if (IS_GEN9_LP(dev_priv))
bxt_ddi_vswing_sequence(dev_priv, level, port,
INTEL_OUTPUT_HDMI);
- else if (IS_CANNONLAKE(dev_priv))
- cnl_ddi_vswing_sequence(encoder, level);
+ else
+ intel_prepare_hdmi_ddi_buffers(encoder);
+
+ if (IS_GEN9_BC(dev_priv))
+ skl_ddi_set_iboost(encoder, level);
intel_hdmi->set_infoframes(drm_encoder,
has_hdmi_sink,
--
2.13.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [RFC PATCH 4/4] drm/i915: Enable voltage swing before enabling DDI_BUF_CTL.
2017-08-16 20:19 [PATCH 1/4] drm/i915: Introduce intel_ddi_dp_level Rodrigo Vivi
2017-08-16 20:19 ` [PATCH 2/4] drm/i915: decouple gen9 and gen10 dp signal levels Rodrigo Vivi
2017-08-16 20:19 ` [PATCH 3/4] drm/i915: Align vswing sequences with old ddi buffer registers Rodrigo Vivi
@ 2017-08-16 20:19 ` Rodrigo Vivi
2017-08-25 13:02 ` Ville Syrjälä
2017-08-16 20:37 ` ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Introduce intel_ddi_dp_level Patchwork
3 siblings, 1 reply; 9+ messages in thread
From: Rodrigo Vivi @ 2017-08-16 20:19 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
Sequences for DisplayPort asks us to
" Configure voltage swing and related IO settings.
Refer to DDI Buffer section."
before "Configure and enable DDI_BUF_CTL"
On BXT and CNL this means to execute the ddi vswing sequences.
At this point these sequences calls are getting duplicated for DP
because they are all called from DP link trainning sequences.
However this patch is not yet removing it before a futher discussion
since spec also allows that during link training without disabling
anything:
"
Notes
Changing voltage swing during link training:
Change the swing setting following the DDI Buffer section.
The port does not need to be disabled.
"
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index a6056bb4f801..8ea0368e15b1 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2133,6 +2133,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = intel_ddi_get_encoder_port(encoder);
struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
+ uint32_t level = intel_ddi_dp_level(intel_dp);
WARN_ON(link_mst && (port == PORT_A || port == PORT_E));
@@ -2145,7 +2146,11 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
- if (!IS_GEN9_LP(dev_priv) && !IS_CANNONLAKE(dev_priv))
+ if (IS_CANNONLAKE(dev_priv))
+ cnl_ddi_vswing_sequence(encoder, level);
+ else if (IS_GEN9_LP(dev_priv))
+ bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
+ else
intel_prepare_dp_ddi_buffers(encoder);
intel_ddi_init_dp_buf_reg(encoder);
--
2.13.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Introduce intel_ddi_dp_level.
2017-08-16 20:19 [PATCH 1/4] drm/i915: Introduce intel_ddi_dp_level Rodrigo Vivi
` (2 preceding siblings ...)
2017-08-16 20:19 ` [RFC PATCH 4/4] drm/i915: Enable voltage swing before enabling DDI_BUF_CTL Rodrigo Vivi
@ 2017-08-16 20:37 ` Patchwork
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2017-08-16 20:37 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm/i915: Introduce intel_ddi_dp_level.
URL : https://patchwork.freedesktop.org/series/28883/
State : success
== Summary ==
Series 28883v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/28883/revisions/1/mbox/
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass -> DMESG-WARN (fi-byt-n2820) fdo#101705
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705
fi-bdw-5557u total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:447s
fi-bdw-gvtdvm total:279 pass:265 dwarn:0 dfail:0 fail:0 skip:14 time:436s
fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:363s
fi-bsw-n3050 total:279 pass:243 dwarn:0 dfail:0 fail:0 skip:36 time:547s
fi-bxt-j4205 total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:516s
fi-byt-j1900 total:279 pass:254 dwarn:1 dfail:0 fail:0 skip:24 time:530s
fi-byt-n2820 total:279 pass:250 dwarn:1 dfail:0 fail:0 skip:28 time:513s
fi-glk-2a total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:613s
fi-hsw-4770 total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:441s
fi-hsw-4770r total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:423s
fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:428s
fi-ivb-3520m total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:514s
fi-ivb-3770 total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:474s
fi-kbl-7500u total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:477s
fi-kbl-7560u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:591s
fi-kbl-r total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:599s
fi-pnv-d510 total:279 pass:223 dwarn:1 dfail:0 fail:0 skip:55 time:530s
fi-skl-6260u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:465s
fi-skl-6700k total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:475s
fi-skl-6770hq total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:491s
fi-skl-gvtdvm total:279 pass:266 dwarn:0 dfail:0 fail:0 skip:13 time:441s
fi-skl-x1585l total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:485s
fi-snb-2520m total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:544s
fi-snb-2600 total:279 pass:250 dwarn:0 dfail:0 fail:0 skip:29 time:407s
ada53b43f81fe618f3f0f1dfbd3dd776bb277323 drm-tip: 2017y-08m-16d-15h-18m-56s UTC integration manifest
b8e68d8b5ca9 drm/i915: Enable voltage swing before enabling DDI_BUF_CTL.
11ece39d2894 drm/i915: Align vswing sequences with old ddi buffer registers.
e244f9770ac8 drm/i915: decouple gen9 and gen10 dp signal levels.
d6ca027ec20b drm/i915: Introduce intel_ddi_dp_level.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5417/
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/4] drm/i915: decouple gen9 and gen10 dp signal levels.
2017-08-16 20:19 ` [PATCH 2/4] drm/i915: decouple gen9 and gen10 dp signal levels Rodrigo Vivi
@ 2017-08-25 12:46 ` Ville Syrjälä
2017-08-25 13:04 ` Ville Syrjälä
0 siblings, 1 reply; 9+ messages in thread
From: Ville Syrjälä @ 2017-08-25 12:46 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Wed, Aug 16, 2017 at 01:19:49PM -0700, Rodrigo Vivi wrote:
> Let's decouple bxt, glk and cnl dp signal levels
> from other DDIs to avoid confusion.
>
> No functional change. Only a reorg to avoid messing
> with currently working DP signal levels when
> moving voltage swing sequences around to match spec.
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 26 ++++++++++++++++----------
> drivers/gpu/drm/i915/intel_dp.c | 10 ++++------
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> 3 files changed, 21 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index dd2bdbe82b47..9891ad40d1dc 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2063,23 +2063,29 @@ static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
> return translate_signal_level(signal_levels);
> }
>
> -uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
> +u32 bxt_signal_levels(struct intel_dp *intel_dp)
> {
> struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
> struct intel_encoder *encoder = &dport->base;
> enum port port = dport->port;
> - uint32_t level = intel_ddi_dp_level(intel_dp);
> + u32 level = intel_ddi_dp_level(intel_dp);
>
> - if (IS_GEN9_BC(dev_priv))
> - skl_ddi_set_iboost(encoder, level);
> - else if (IS_GEN9_LP(dev_priv))
> - bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
> - else if (IS_CANNONLAKE(dev_priv)) {
> + if (IS_CANNONLAKE(dev_priv))
> cnl_ddi_vswing_sequence(encoder, level);
> - /* DDI_BUF_CTL bits 27:24 are reserved on CNL */
> - return 0;
> - }
> + else
> + bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
> +
> + return 0;
> +}
> +
> +uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
skl_signal_levels() perhaps?
> +{
> + struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> + struct intel_encoder *encoder = &dport->base;
> + uint32_t level = intel_ddi_dp_level(intel_dp);
> +
> + skl_ddi_set_iboost(encoder, level);
> return DDI_BUF_TRANS_SELECT(level);
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 4fd4853b2250..1af4b227e758 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3506,13 +3506,11 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
> uint32_t signal_levels, mask = 0;
> uint8_t train_set = intel_dp->train_set[0];
>
> - if (HAS_DDI(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> + signal_levels = bxt_signal_levels(intel_dp);
> + } else if (HAS_DDI(dev_priv)) {
> signal_levels = ddi_signal_levels(intel_dp);
> -
> - if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv))
> - signal_levels = 0;
> - else
> - mask = DDI_BUF_EMP_MASK;
> + mask = DDI_BUF_EMP_MASK;
> } else if (IS_CHERRYVIEW(dev_priv)) {
> signal_levels = chv_signal_levels(intel_dp);
> } else if (IS_VALLEYVIEW(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index fa47285918f4..913cccc54ad2 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1272,6 +1272,7 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config);
> void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
> bool state);
> +u32 bxt_signal_levels(struct intel_dp *intel_dp);
> uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
> u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
>
> --
> 2.13.2
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [RFC PATCH 4/4] drm/i915: Enable voltage swing before enabling DDI_BUF_CTL.
2017-08-16 20:19 ` [RFC PATCH 4/4] drm/i915: Enable voltage swing before enabling DDI_BUF_CTL Rodrigo Vivi
@ 2017-08-25 13:02 ` Ville Syrjälä
0 siblings, 0 replies; 9+ messages in thread
From: Ville Syrjälä @ 2017-08-25 13:02 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Wed, Aug 16, 2017 at 01:19:51PM -0700, Rodrigo Vivi wrote:
> Sequences for DisplayPort asks us to
> " Configure voltage swing and related IO settings.
> Refer to DDI Buffer section."
>
> before "Configure and enable DDI_BUF_CTL"
>
> On BXT and CNL this means to execute the ddi vswing sequences.
>
> At this point these sequences calls are getting duplicated for DP
> because they are all called from DP link trainning sequences.
>
> However this patch is not yet removing it before a futher discussion
> since spec also allows that during link training without disabling
> anything:
>
> "
> Notes
> Changing voltage swing during link training:
> Change the swing setting following the DDI Buffer section.
> The port does not need to be disabled.
> "
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index a6056bb4f801..8ea0368e15b1 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2133,6 +2133,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> enum port port = intel_ddi_get_encoder_port(encoder);
> struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
> + uint32_t level = intel_ddi_dp_level(intel_dp);
>
> WARN_ON(link_mst && (port == PORT_A || port == PORT_E));
>
> @@ -2145,7 +2146,11 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
>
> intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
>
> - if (!IS_GEN9_LP(dev_priv) && !IS_CANNONLAKE(dev_priv))
> + if (IS_CANNONLAKE(dev_priv))
> + cnl_ddi_vswing_sequence(encoder, level);
> + else if (IS_GEN9_LP(dev_priv))
> + bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
Hmm. Yeah, I guess it would make sense to set these up already before we
enable DDI_BUF_CTL, which I think would happend from the
.prepare_link_retrain() hook on DDI, and that does get called before the
signal levels have been set up.
So I'm fine with this change. Imre, any thoughts?
> + else
> intel_prepare_dp_ddi_buffers(encoder);
>
> intel_ddi_init_dp_buf_reg(encoder);
> --
> 2.13.2
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/4] drm/i915: decouple gen9 and gen10 dp signal levels.
2017-08-25 12:46 ` Ville Syrjälä
@ 2017-08-25 13:04 ` Ville Syrjälä
2017-08-25 20:55 ` [PATCH 02/10] " Rodrigo Vivi
0 siblings, 1 reply; 9+ messages in thread
From: Ville Syrjälä @ 2017-08-25 13:04 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Fri, Aug 25, 2017 at 03:46:33PM +0300, Ville Syrjälä wrote:
> On Wed, Aug 16, 2017 at 01:19:49PM -0700, Rodrigo Vivi wrote:
> > Let's decouple bxt, glk and cnl dp signal levels
> > from other DDIs to avoid confusion.
> >
> > No functional change. Only a reorg to avoid messing
> > with currently working DP signal levels when
> > moving voltage swing sequences around to match spec.
> >
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_ddi.c | 26 ++++++++++++++++----------
> > drivers/gpu/drm/i915/intel_dp.c | 10 ++++------
> > drivers/gpu/drm/i915/intel_drv.h | 1 +
> > 3 files changed, 21 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index dd2bdbe82b47..9891ad40d1dc 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -2063,23 +2063,29 @@ static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
> > return translate_signal_level(signal_levels);
> > }
> >
> > -uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
> > +u32 bxt_signal_levels(struct intel_dp *intel_dp)
> > {
> > struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> > struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
> > struct intel_encoder *encoder = &dport->base;
> > enum port port = dport->port;
> > - uint32_t level = intel_ddi_dp_level(intel_dp);
> > + u32 level = intel_ddi_dp_level(intel_dp);
> >
> > - if (IS_GEN9_BC(dev_priv))
> > - skl_ddi_set_iboost(encoder, level);
> > - else if (IS_GEN9_LP(dev_priv))
> > - bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
> > - else if (IS_CANNONLAKE(dev_priv)) {
> > + if (IS_CANNONLAKE(dev_priv))
> > cnl_ddi_vswing_sequence(encoder, level);
> > - /* DDI_BUF_CTL bits 27:24 are reserved on CNL */
> > - return 0;
> > - }
> > + else
> > + bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
> > +
> > + return 0;
> > +}
> > +
> > +uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
>
> skl_signal_levels() perhaps?
Oh, it actuall gets called on all older DDI platforms. So I guess the
name is OK, but the iboost call needs a platform check then,
>
> > +{
> > + struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> > + struct intel_encoder *encoder = &dport->base;
> > + uint32_t level = intel_ddi_dp_level(intel_dp);
> > +
> > + skl_ddi_set_iboost(encoder, level);
> > return DDI_BUF_TRANS_SELECT(level);
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 4fd4853b2250..1af4b227e758 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -3506,13 +3506,11 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
> > uint32_t signal_levels, mask = 0;
> > uint8_t train_set = intel_dp->train_set[0];
> >
> > - if (HAS_DDI(dev_priv)) {
> > + if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> > + signal_levels = bxt_signal_levels(intel_dp);
> > + } else if (HAS_DDI(dev_priv)) {
> > signal_levels = ddi_signal_levels(intel_dp);
> > -
> > - if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv))
> > - signal_levels = 0;
> > - else
> > - mask = DDI_BUF_EMP_MASK;
> > + mask = DDI_BUF_EMP_MASK;
> > } else if (IS_CHERRYVIEW(dev_priv)) {
> > signal_levels = chv_signal_levels(intel_dp);
> > } else if (IS_VALLEYVIEW(dev_priv)) {
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index fa47285918f4..913cccc54ad2 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1272,6 +1272,7 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
> > struct intel_crtc_state *pipe_config);
> > void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
> > bool state);
> > +u32 bxt_signal_levels(struct intel_dp *intel_dp);
> > uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
> > u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
> >
> > --
> > 2.13.2
>
> --
> Ville Syrjälä
> Intel OTC
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 02/10] drm/i915: decouple gen9 and gen10 dp signal levels.
2017-08-25 13:04 ` Ville Syrjälä
@ 2017-08-25 20:55 ` Rodrigo Vivi
0 siblings, 0 replies; 9+ messages in thread
From: Rodrigo Vivi @ 2017-08-25 20:55 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
Let's decouple bxt, glk and cnl dp signal levels
from other DDIs to avoid confusion.
No functional change. Only a reorg to avoid messing
with currently working DP signal levels when
moving voltage swing sequences around to match spec.
v2: ddi_signal_levels is also called from other ddi
platforms, so don't remove IS_GEN9_BC check from
skl_ddi_set_iboos. (Ville).
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 27 ++++++++++++++++++---------
drivers/gpu/drm/i915/intel_dp.c | 10 ++++------
drivers/gpu/drm/i915/intel_drv.h | 1 +
3 files changed, 23 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 7e875e05d053..9a887780f99f 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2063,23 +2063,32 @@ static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
return translate_signal_level(signal_levels);
}
-uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
+u32 bxt_signal_levels(struct intel_dp *intel_dp)
{
struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
struct intel_encoder *encoder = &dport->base;
enum port port = dport->port;
+ u32 level = intel_ddi_dp_level(intel_dp);
+
+ if (IS_CANNONLAKE(dev_priv))
+ cnl_ddi_vswing_sequence(encoder, level);
+ else
+ bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
+
+ return 0;
+}
+
+uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
+ struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
+ struct intel_encoder *encoder = &dport->base;
uint32_t level = intel_ddi_dp_level(intel_dp);
if (IS_GEN9_BC(dev_priv))
- skl_ddi_set_iboost(encoder, level);
- else if (IS_GEN9_LP(dev_priv))
- bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
- else if (IS_CANNONLAKE(dev_priv)) {
- cnl_ddi_vswing_sequence(encoder, level);
- /* DDI_BUF_CTL bits 27:24 are reserved on CNL */
- return 0;
- }
+ skl_ddi_set_iboost(encoder, level);
+
return DDI_BUF_TRANS_SELECT(level);
}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d3e5fdf0d2fa..49a8c339b2b0 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3506,13 +3506,11 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
uint32_t signal_levels, mask = 0;
uint8_t train_set = intel_dp->train_set[0];
- if (HAS_DDI(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+ signal_levels = bxt_signal_levels(intel_dp);
+ } else if (HAS_DDI(dev_priv)) {
signal_levels = ddi_signal_levels(intel_dp);
-
- if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv))
- signal_levels = 0;
- else
- mask = DDI_BUF_EMP_MASK;
+ mask = DDI_BUF_EMP_MASK;
} else if (IS_CHERRYVIEW(dev_priv)) {
signal_levels = chv_signal_levels(intel_dp);
} else if (IS_VALLEYVIEW(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 17649f13091c..469c06000774 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1271,6 +1271,7 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config);
void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
bool state);
+u32 bxt_signal_levels(struct intel_dp *intel_dp);
uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
--
2.13.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
end of thread, other threads:[~2017-08-25 20:55 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-08-16 20:19 [PATCH 1/4] drm/i915: Introduce intel_ddi_dp_level Rodrigo Vivi
2017-08-16 20:19 ` [PATCH 2/4] drm/i915: decouple gen9 and gen10 dp signal levels Rodrigo Vivi
2017-08-25 12:46 ` Ville Syrjälä
2017-08-25 13:04 ` Ville Syrjälä
2017-08-25 20:55 ` [PATCH 02/10] " Rodrigo Vivi
2017-08-16 20:19 ` [PATCH 3/4] drm/i915: Align vswing sequences with old ddi buffer registers Rodrigo Vivi
2017-08-16 20:19 ` [RFC PATCH 4/4] drm/i915: Enable voltage swing before enabling DDI_BUF_CTL Rodrigo Vivi
2017-08-25 13:02 ` Ville Syrjälä
2017-08-16 20:37 ` ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Introduce intel_ddi_dp_level Patchwork
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