* [PATCH] drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix
@ 2017-08-29 23:07 Rodrigo Vivi
2017-08-29 23:26 ` ✓ Fi.CI.BAT: success for " Patchwork
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Rodrigo Vivi @ 2017-08-29 23:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Ben Widawsky, Mika Kuoppala, Anuj Phogat, Rodrigo Vivi
WA to enable HW L1 Banking fix that allows aniso to operate
at full sample rate.
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Ben Widawsky <ben@bwidawsk.net>
Cc: Anuj Phogat <anuj.phogat@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e2908ae34004..1ad22a824921 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8072,6 +8072,7 @@ enum {
#define HSW_SAMPLE_C_PERFORMANCE (1<<9)
#define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8)
#define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5)
+#define CNL_FAST_ANISO_L1_BANKING_FIX (1<<4)
#define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
#define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index a6ac9d0a4156..4b9b7828802d 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1090,6 +1090,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
/* WaPushConstantDereferenceHoldDisable:cnl */
WA_SET_BIT(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
+ /* FtrEnableFastAnisoL1BankingFix: cnl */
+ WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);
+
/* WaEnablePreemptionGranularityControlByUMD:cnl */
ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
if (ret)
--
2.13.2
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix
2017-08-29 23:07 [PATCH] drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix Rodrigo Vivi
@ 2017-08-29 23:26 ` Patchwork
2017-08-30 1:53 ` ✓ Fi.CI.IGT: " Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2017-08-29 23:26 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix
URL : https://patchwork.freedesktop.org/series/29505/
State : success
== Summary ==
Series 29505v1 drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix
https://patchwork.freedesktop.org/api/1.0/series/29505/revisions/1/mbox/
Test gem_ringfill:
Subgroup basic-default-hang:
incomplete -> DMESG-WARN (fi-pnv-d510) fdo#101600
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
pass -> FAIL (fi-snb-2600) fdo#100215
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass -> SKIP (fi-skl-x1585l) fdo#101781
Test kms_frontbuffer_tracking:
Subgroup basic:
dmesg-warn -> PASS (fi-bdw-5557u)
fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781
fi-bdw-5557u total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:460s
fi-bdw-gvtdvm total:279 pass:265 dwarn:0 dfail:0 fail:0 skip:14 time:445s
fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:363s
fi-bsw-n3050 total:279 pass:243 dwarn:0 dfail:0 fail:0 skip:36 time:561s
fi-bwr-2160 total:279 pass:184 dwarn:0 dfail:0 fail:0 skip:95 time:252s
fi-bxt-j4205 total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:521s
fi-byt-j1900 total:279 pass:254 dwarn:1 dfail:0 fail:0 skip:24 time:521s
fi-byt-n2820 total:279 pass:250 dwarn:1 dfail:0 fail:0 skip:28 time:523s
fi-elk-e7500 total:279 pass:230 dwarn:0 dfail:0 fail:0 skip:49 time:443s
fi-glk-2a total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:615s
fi-hsw-4770 total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:444s
fi-hsw-4770r total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:426s
fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:422s
fi-ivb-3520m total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:511s
fi-ivb-3770 total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:481s
fi-kbl-7500u total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:475s
fi-kbl-7560u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:599s
fi-kbl-r total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:600s
fi-pnv-d510 total:279 pass:223 dwarn:1 dfail:0 fail:0 skip:55 time:528s
fi-skl-6260u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:480s
fi-skl-6770hq total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:495s
fi-skl-gvtdvm total:279 pass:266 dwarn:0 dfail:0 fail:0 skip:13 time:452s
fi-skl-x1585l total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:493s
fi-snb-2520m total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:547s
fi-snb-2600 total:279 pass:249 dwarn:0 dfail:0 fail:1 skip:29 time:405s
fi-skl-6700k failed to connect after reboot
428ed27345fbf9be530d01ca6dc862eb5895db81 drm-tip: 2017y-08m-29d-17h-43m-11s UTC integration manifest
7f164562d87a drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5530/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread* ✓ Fi.CI.IGT: success for drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix
2017-08-29 23:07 [PATCH] drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix Rodrigo Vivi
2017-08-29 23:26 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2017-08-30 1:53 ` Patchwork
2017-08-30 8:55 ` [PATCH] " Mika Kuoppala
2017-09-05 20:17 ` Oscar Mateo
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2017-08-30 1:53 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix
URL : https://patchwork.freedesktop.org/series/29505/
State : success
== Summary ==
Test kms_cursor_legacy:
Subgroup short-flip-before-cursor-atomic-transitions-varying-size:
skip -> PASS (shard-hsw)
Test kms_setmode:
Subgroup basic:
fail -> PASS (shard-hsw) fdo#99912
Test perf:
Subgroup blocking:
fail -> PASS (shard-hsw) fdo#102252
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
shard-hsw total:2230 pass:1232 dwarn:0 dfail:0 fail:16 skip:982 time:9675s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5530/shards.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH] drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix
2017-08-29 23:07 [PATCH] drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix Rodrigo Vivi
2017-08-29 23:26 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-08-30 1:53 ` ✓ Fi.CI.IGT: " Patchwork
@ 2017-08-30 8:55 ` Mika Kuoppala
2017-08-31 4:59 ` Vivi, Rodrigo
2017-09-05 20:17 ` Oscar Mateo
3 siblings, 1 reply; 7+ messages in thread
From: Mika Kuoppala @ 2017-08-30 8:55 UTC (permalink / raw)
To: intel-gfx; +Cc: Ben Widawsky, Anuj Phogat, Rodrigo Vivi
Rodrigo Vivi <rodrigo.vivi@intel.com> writes:
> WA to enable HW L1 Banking fix that allows aniso to operate
> at full sample rate.
>
References: HSD#1937670
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Ben Widawsky <ben@bwidawsk.net>
> Cc: Anuj Phogat <anuj.phogat@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e2908ae34004..1ad22a824921 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8072,6 +8072,7 @@ enum {
> #define HSW_SAMPLE_C_PERFORMANCE (1<<9)
> #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8)
> #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5)
> +#define CNL_FAST_ANISO_L1_BANKING_FIX (1<<4)
> #define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
>
> #define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index a6ac9d0a4156..4b9b7828802d 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1090,6 +1090,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
> /* WaPushConstantDereferenceHoldDisable:cnl */
> WA_SET_BIT(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
>
> + /* FtrEnableFastAnisoL1BankingFix: cnl */
> + WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);
> +
> /* WaEnablePreemptionGranularityControlByUMD:cnl */
> ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
> if (ret)
> --
> 2.13.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH] drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix
2017-08-30 8:55 ` [PATCH] " Mika Kuoppala
@ 2017-08-31 4:59 ` Vivi, Rodrigo
0 siblings, 0 replies; 7+ messages in thread
From: Vivi, Rodrigo @ 2017-08-31 4:59 UTC (permalink / raw)
To: mika.kuoppala; +Cc: ben, Phogat, Anuj, intel-gfx
merged to dinq. thanks for the review
On Wed, 2017-08-30 at 11:55 +0300, Mika Kuoppala wrote:
> Rodrigo Vivi <rodrigo.vivi@intel.com> writes:
>
> > WA to enable HW L1 Banking fix that allows aniso to operate
> > at full sample rate.
> >
>
> References: HSD#1937670
>
> > Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> > Cc: Oscar Mateo <oscar.mateo@intel.com>
> > Cc: Ben Widawsky <ben@bwidawsk.net>
> > Cc: Anuj Phogat <anuj.phogat@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
> > 2 files changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index e2908ae34004..1ad22a824921 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -8072,6 +8072,7 @@ enum {
> > #define HSW_SAMPLE_C_PERFORMANCE (1<<9)
> > #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8)
> > #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5)
> > +#define CNL_FAST_ANISO_L1_BANKING_FIX (1<<4)
> > #define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
> >
> > #define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
> > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> > index a6ac9d0a4156..4b9b7828802d 100644
> > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > @@ -1090,6 +1090,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
> > /* WaPushConstantDereferenceHoldDisable:cnl */
> > WA_SET_BIT(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
> >
> > + /* FtrEnableFastAnisoL1BankingFix: cnl */
> > + WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);
> > +
> > /* WaEnablePreemptionGranularityControlByUMD:cnl */
> > ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
> > if (ret)
> > --
> > 2.13.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix
2017-08-29 23:07 [PATCH] drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix Rodrigo Vivi
` (2 preceding siblings ...)
2017-08-30 8:55 ` [PATCH] " Mika Kuoppala
@ 2017-09-05 20:17 ` Oscar Mateo
2017-09-05 22:03 ` Vivi, Rodrigo
3 siblings, 1 reply; 7+ messages in thread
From: Oscar Mateo @ 2017-09-05 20:17 UTC (permalink / raw)
To: Rodrigo Vivi, intel-gfx; +Cc: Ben Widawsky, Anuj Phogat, Mika Kuoppala
On 08/29/2017 04:07 PM, Rodrigo Vivi wrote:
> WA to enable HW L1 Banking fix that allows aniso to operate
> at full sample rate.
>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Ben Widawsky <ben@bwidawsk.net>
> Cc: Anuj Phogat <anuj.phogat@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e2908ae34004..1ad22a824921 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8072,6 +8072,7 @@ enum {
> #define HSW_SAMPLE_C_PERFORMANCE (1<<9)
> #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8)
> #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5)
> +#define CNL_FAST_ANISO_L1_BANKING_FIX (1<<4)
Why CNL_ instead of GEN10_ prefix? (out of curiosity)
> #define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
>
> #define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index a6ac9d0a4156..4b9b7828802d 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1090,6 +1090,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
> /* WaPushConstantDereferenceHoldDisable:cnl */
> WA_SET_BIT(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
>
> + /* FtrEnableFastAnisoL1BankingFix: cnl */
> + WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);
> +
I have this only for B0 onwards, but I guess you glossed over this
because you know more than me about which CNL stepping is the production
one, so:
Rviewed-by: Oscar Mateo <oscar.mateo@intel.com>
> /* WaEnablePreemptionGranularityControlByUMD:cnl */
> ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
> if (ret)
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH] drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix
2017-09-05 20:17 ` Oscar Mateo
@ 2017-09-05 22:03 ` Vivi, Rodrigo
0 siblings, 0 replies; 7+ messages in thread
From: Vivi, Rodrigo @ 2017-09-05 22:03 UTC (permalink / raw)
To: Mateo Lozano, Oscar; +Cc: intel-gfx, Phogat, Anuj, ben, Kuoppala, Mika
On Tue, 2017-09-05 at 13:17 -0700, Oscar Mateo wrote:
>
> On 08/29/2017 04:07 PM, Rodrigo Vivi wrote:
> > WA to enable HW L1 Banking fix that allows aniso to operate
> > at full sample rate.
> >
> > Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> > Cc: Oscar Mateo <oscar.mateo@intel.com>
> > Cc: Ben Widawsky <ben@bwidawsk.net>
> > Cc: Anuj Phogat <anuj.phogat@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
> > 2 files changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index e2908ae34004..1ad22a824921 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -8072,6 +8072,7 @@ enum {
> > #define HSW_SAMPLE_C_PERFORMANCE (1<<9)
> > #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8)
> > #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5)
> > +#define CNL_FAST_ANISO_L1_BANKING_FIX (1<<4)
>
> Why CNL_ instead of GEN10_ prefix? (out of curiosity)
hmm... I guess I should have used gen10 for compatibility with other
bits around this... :/
But I pick CNL instead because it is easier to match the spec that
has bit started for CNL as:
GEN:BUG:1937670 [CNL...
if it had started with GEN10:etc I would have picked the GEN10 I
guess...
>
> > #define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
> >
> > #define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
> > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> > index a6ac9d0a4156..4b9b7828802d 100644
> > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > @@ -1090,6 +1090,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
> > /* WaPushConstantDereferenceHoldDisable:cnl */
> > WA_SET_BIT(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
> >
> > + /* FtrEnableFastAnisoL1BankingFix: cnl */
> > + WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);
> > +
>
> I have this only for B0 onwards, but I guess you glossed over this
> because you know more than me about which CNL stepping is the production
> one, so:
yeap, we don't have A0 available anyways...
And with no A0 related wa implemented, so our support is B0+...
> Rviewed-by: Oscar Mateo <oscar.mateo@intel.com>
Thanks, although it is merged already...
>
> > /* WaEnablePreemptionGranularityControlByUMD:cnl */
> > ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
> > if (ret)
>
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2017-09-05 22:03 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
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2017-08-29 23:07 [PATCH] drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix Rodrigo Vivi
2017-08-29 23:26 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-08-30 1:53 ` ✓ Fi.CI.IGT: " Patchwork
2017-08-30 8:55 ` [PATCH] " Mika Kuoppala
2017-08-31 4:59 ` Vivi, Rodrigo
2017-09-05 20:17 ` Oscar Mateo
2017-09-05 22:03 ` Vivi, Rodrigo
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