From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: [PATCH] drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well.
Date: Tue, 29 Aug 2017 16:09:07 -0700 [thread overview]
Message-ID: <20170829230907.21363-1-rodrigo.vivi@intel.com> (raw)
In-Reply-To: <1502731451.3167.16.camel@rdvivi-vienna>
Driver’s CPU access to GTT is via the GTTMMADR BAR.
The current HW implementation of that BAR is to only
support <= DW (and maybe QW) writes—not 16/32/64B writes
that could occur with WC and/or SSE/AVX moves.
GTTMMADR must be marked uncacheable (UC).
Accesses to GTTMMADR(GTT), must be 64 bits or less (ie. 1 GTT entry).
v2: Get clarification on the reasons and spec is getting
updated to reflect it now.
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Suggested-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 708b95cd8c30..7da9621d2c60 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2790,13 +2790,13 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2;
/*
- * On BXT writes larger than 64 bit to the GTT pagetable range will be
- * dropped. For WC mappings in general we have 64 byte burst writes
- * when the WC buffer is flushed, so we can't use it, but have to
+ * On BXT+/CNL+ writes larger than 64 bit to the GTT pagetable range
+ * will be dropped. For WC mappings in general we have 64 byte burst
+ * writes when the WC buffer is flushed, so we can't use it, but have to
* resort to an uncached mapping. The WC issue is easily caught by the
* readback check when writing GTT PTE entries.
*/
- if (IS_GEN9_LP(dev_priv))
+ if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
ggtt->gsm = ioremap_nocache(phys_addr, size);
else
ggtt->gsm = ioremap_wc(phys_addr, size);
--
2.13.2
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next prev parent reply other threads:[~2017-08-29 23:09 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-11 23:39 [PATCH] drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well Rodrigo Vivi
2017-08-12 0:11 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-08-12 0:36 ` [PATCH] " Rodrigo Vivi
2017-08-14 12:13 ` Joonas Lahtinen
2017-08-14 17:24 ` Vivi, Rodrigo
2017-08-29 23:09 ` Rodrigo Vivi [this message]
2017-08-30 11:13 ` Joonas Lahtinen
2017-08-30 11:26 ` Chris Wilson
2017-08-30 11:38 ` Joonas Lahtinen
2017-08-30 17:58 ` Vivi, Rodrigo
2017-08-31 8:27 ` Joonas Lahtinen
2017-08-31 16:45 ` Vivi, Rodrigo
2017-08-30 0:16 ` ✓ Fi.CI.BAT: success for drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well. (rev2) Patchwork
2017-08-30 4:33 ` ✗ Fi.CI.IGT: warning " Patchwork
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