[PATCHv2 00/17] Fix missing device tree hwmods and IO ranges omap variants

[PATCHv2 00/17] Fix missing device tree hwmods and IO ranges omap variants

[Tony Lindgren]

Hi all,

While cleaning up legacy platform data I noticed to my horror that we
are in a "half-chicken, half-egg" state with with the legacy booting
vs device tree booting instead of dealing with just the traditional
"chicken or the egg" problem.

Basically we are missing some critical dts data for "ti,hwmods" and
IO ranges for example. This data is needed by the SoC interconnect
code and things just happen to work now with the legacy platform
data still around.

Note that the IO range in the dts should be for the interconnect
target module, typically sized 0x1000. Then there can be one or
more device instances as a child of the interconnect target module.

Mostly this is a problem on omap4, the other SoCs only have few
nodes and properties missing.

For the missing nodes and properties, I've also updated or added the
binding documentation. For some devices, there is currently no driver
available like is the case for face detect and GPU modules for
example.

Regards,

Tony

Changes since v1:

- Updated hsi, iss, fdif, gpu, and smartreflex patches based on
  the subsystem maintainer comments

- Added Rob and Mark in Cc for the patches touching binding
  documentation


Tony Lindgren (17):
  ARM: dts: Add missing dma hwmods property for omap3
  ARM: dts: Configure pmu without interrupt for omap4430
  ARM: dts: Add missing properties for omap4 control modules
  ARM: dts: Add missing hwmods property for omap4 dma
  ARM: dts: Add missing smartreflex node and binding for omap4
  ARM: dts: Add missing slimbus node and binding for omap4
  ARM: dts: Add missing onewire node for omap4
  ARM: dts: Add missing hsi node for omap4
  ARM: dts: Add missing iss node and binding for omap4
  ARM: dts: Add missing wdt3 node for omap4
  ARM: dts: Add missing mcasp node for omap4
  ARM: dts: Add missing aess node and binding for omap4
  ARM: dts: Add missing fdif node and binding for omap4
  ARM: dts: Add missing gpu node and binding for omap4
  ARM: dts: Add missing dma hwmod property for omap5
  ARM: dts: Add missing hwmod related nodes for am33xx
  ARM: dts: Add missing hwmod related properties for dra7

 .../devicetree/bindings/arm/omap/ctrl.txt          |   2 +
 .../devicetree/bindings/gpu/ti-powervr-sgx.txt     |  39 +++++
 Documentation/devicetree/bindings/hsi/omap-ssi.txt |   7 +-
 .../devicetree/bindings/media/ti-fdif.txt          |  29 ++++
 Documentation/devicetree/bindings/media/ti-iss.txt |  33 ++++
 .../bindings/memory-controllers/ti/emif.txt        |   6 +-
 .../devicetree/bindings/power/ti-smartreflex.txt   |  47 ++++++
 .../bindings/sound/davinci-mcasp-audio.txt         |   1 +
 .../devicetree/bindings/sound/ti-aess.txt          |  33 ++++
 .../devicetree/bindings/sound/ti-slimbus.txt       |  34 ++++
 arch/arm/boot/dts/am33xx.dtsi                      |  10 +-
 arch/arm/boot/dts/dra7.dtsi                        |   8 +
 arch/arm/boot/dts/omap3.dtsi                       |   1 +
 arch/arm/boot/dts/omap4.dtsi                       | 176 +++++++++++++++++++--
 arch/arm/boot/dts/omap5.dtsi                       |   1 +
 15 files changed, 413 insertions(+), 14 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/gpu/ti-powervr-sgx.txt
 create mode 100644 Documentation/devicetree/bindings/media/ti-fdif.txt
 create mode 100644 Documentation/devicetree/bindings/media/ti-iss.txt
 create mode 100644 Documentation/devicetree/bindings/power/ti-smartreflex.txt
 create mode 100644 Documentation/devicetree/bindings/sound/ti-aess.txt
 create mode 100644 Documentation/devicetree/bindings/sound/ti-slimbus.txt

-- 
2.14.1
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[PATCH 01/17] ARM: dts: Add missing dma hwmods property for omap3

[Tony Lindgren]

On omap3, we are missing a ti,hwmods property for dma that
the SoC interconnect code needs.

Note that this will only show up as a bug with "doesn't have
mpu register target base" boot errors when the legacy platform
data is removed.

Cc: Peter Ujfalusi <peter.ujfalusi-l0cyMroinI0@public.gmane.org>
Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
 arch/arm/boot/dts/omap3.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -215,6 +215,7 @@
 			#dma-cells = <1>;
 			dma-channels = <32>;
 			dma-requests = <96>;
+			ti,hwmods = "dma";
 		};
 
 		gpio1: gpio@48310000 {
-- 
2.14.1
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[PATCH 02/17] ARM: dts: Configure pmu without interrupt for omap4430

[Tony Lindgren]

On omap4430, the PMU is not configure unlike on omap4460 because
of the missing handling.

The missing pmu node with the missing ti,hwmods entry will cause
boot time errors when the legacy platform data is removed as
the SoC interconnect code needs it.

Note that this will only show up as a bug with "doesn't have
mpu register target base" boot errors when the legacy platform
data is removed.

Let's fix the issue by configuring PMU but without the interrupts.
Then when cross trigger interface (CTI) is supported, we can add
interrupts also for omap4430.

Cc: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>
Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
 arch/arm/boot/dts/omap4.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -51,6 +51,17 @@
 		};
 	};
 
+	/*
+	 * Note that 4430 needs cross trigger interface (CTI) supported
+	 * before we can configure the interrupts. This means sampling
+	 * events are not supported for pmu. Note that 4460 does not use
+	 * CTI, see also 4460.dtsi.
+	 */
+	pmu {
+		compatible = "arm,cortex-a9-pmu";
+		ti,hwmods = "debugss";
+	};
+
 	gic: interrupt-controller@48241000 {
 		compatible = "arm,cortex-a9-gic";
 		interrupt-controller;
-- 
2.14.1
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[PATCH 03/17] ARM: dts: Add missing properties for omap4 control modules

[Tony Lindgren]

On omap4, we are missing several ti,hwmods properties and IO
ranges for system control modules. These are needed by the SoC
interconnect code.

Note that this will only show up as a bug with "doesn't have
mpu register target base" boot errors when the legacy platform
data is removed.

In order to add these, we need to move omap4_pmx_wkup to be a
child of omap4_padconf_wkup.

On omap4 there are separate modules for control module and
control module pads. For control module core, we have this
already configured except for the missing ti,hwmods and reg
entries.

Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
 .../devicetree/bindings/arm/omap/ctrl.txt          |  2 ++
 arch/arm/boot/dts/omap4.dtsi                       | 39 ++++++++++++++++------
 2 files changed, 31 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/omap/ctrl.txt b/Documentation/devicetree/bindings/arm/omap/ctrl.txt
--- a/Documentation/devicetree/bindings/arm/omap/ctrl.txt
+++ b/Documentation/devicetree/bindings/arm/omap/ctrl.txt
@@ -21,6 +21,8 @@ Required properties:
 		"ti,omap3-scm"
 		"ti,omap4-scm-core"
 		"ti,omap4-scm-padconf-core"
+		"ti,omap4-scm-wkup"
+		"ti,omap4-scm-padconf-wkup"
 		"ti,omap5-scm-core"
 		"ti,omap5-scm-padconf-core"
 		"ti,dra7-scm-core"
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -174,6 +174,7 @@
 				#address-cells = <1>;
 				#size-cells = <1>;
 				ranges = <0 0x2000 0x1000>;
+				ti,hwmods = "ctrl_module_core";
 
 				scm_conf: scm_conf@0 {
 					compatible = "syscon";
@@ -186,9 +187,11 @@
 			omap4_padconf_core: scm@100000 {
 				compatible = "ti,omap4-scm-padconf-core",
 					     "simple-bus";
+				reg = <0x100000 0x1000>;
 				#address-cells = <1>;
 				#size-cells = <1>;
 				ranges = <0 0x100000 0x1000>;
+				ti,hwmods = "ctrl_module_pad_core";
 
 				omap4_pmx_core: pinmux@40 {
 					compatible = "ti,omap4-padconf",
@@ -263,17 +266,33 @@
 					};
 				};
 
-				omap4_pmx_wkup: pinmux@1e040 {
-					compatible = "ti,omap4-padconf",
-						     "pinctrl-single";
-					reg = <0x1e040 0x0038>;
+				omap4_scm_wkup: scm@c000 {
+					compatible = "ti,omap4-scm-wkup";
+					reg = <0xc000 0x1000>;
+					ti,hwmods = "ctrl_module_wkup";
+				};
+
+				omap4_padconf_wkup: padconf@1e000 {
+					compatible = "ti,omap4-scm-padconf-wkup",
+						     "simple-bus";
+					reg = <0x1e000 0x1000>;
 					#address-cells = <1>;
-					#size-cells = <0>;
-					#pinctrl-cells = <1>;
-					#interrupt-cells = <1>;
-					interrupt-controller;
-					pinctrl-single,register-width = <16>;
-					pinctrl-single,function-mask = <0x7fff>;
+					#size-cells = <1>;
+					ranges = <0 0x1e000 0x1000>;
+					ti,hwmods = "ctrl_module_pad_wkup";
+
+					omap4_pmx_wkup: pinmux@40 {
+						compatible = "ti,omap4-padconf",
+							     "pinctrl-single";
+						reg = <0x40 0x0038>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+						#pinctrl-cells = <1>;
+						#interrupt-cells = <1>;
+						interrupt-controller;
+						pinctrl-single,register-width = <16>;
+						pinctrl-single,function-mask = <0x7fff>;
+					};
 				};
 			};
 		};
-- 
2.14.1
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[PATCH 04/17] ARM: dts: Add missing hwmods property for omap4 dma

[Tony Lindgren]

On omap4, we are missing a ti,hwmods property for dma that the
that the SoC interconnect code needs.

Note that this will only show up as a bug with "doesn't have
mpu register target base" boot errors when the legacy platform
data is removed.

Cc: Peter Ujfalusi <peter.ujfalusi-l0cyMroinI0@public.gmane.org>
Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
 arch/arm/boot/dts/omap4.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -312,6 +312,7 @@
 			#dma-cells = <1>;
 			dma-channels = <32>;
 			dma-requests = <127>;
+			ti,hwmods = "dma_system";
 		};
 
 		gpio1: gpio@4a310000 {
-- 
2.14.1
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[PATCH 05/17] ARM: dts: Add missing smartreflex node and binding for omap4

[Tony Lindgren]

We are missing smartreflex device tree nodes for omap4 with
their related "ti,hwmods" properties that the SoC interconnect
code needs.

Note that this will only show up as a bug with "doesn't have
mpu register target base" boot errors when the legacy platform
data is removed.

And since we're missing the device tree binding for smartreflex,
let's also add it and document the existing omap3 use too.

Note that the related driver also needs to be updated to probe
using device tree and get the platform data passed to it using
auxdata with arch/arm/mach-omap2/pdata-quirks.c.

Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Nishanth Menon <nm-l0cyMroinI0@public.gmane.org>
Cc: Rafael J. Wysocki <rafael.j.wysocki-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
 .../devicetree/bindings/power/ti-smartreflex.txt   | 47 ++++++++++++++++++++++
 arch/arm/boot/dts/omap4.dtsi                       | 21 ++++++++++
 2 files changed, 68 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/power/ti-smartreflex.txt

diff --git a/Documentation/devicetree/bindings/power/ti-smartreflex.txt b/Documentation/devicetree/bindings/power/ti-smartreflex.txt
new file mode 100644
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/ti-smartreflex.txt
@@ -0,0 +1,47 @@
+Texas Instruments SmartReflex binding
+
+SmartReflex is used to set and adjust the SoC operating points.
+
+
+Required properties:
+
+compatible: Shall be one of the following:
+	    "ti,omap3-smartreflex-core"
+	    "ti,omap3-smartreflex-iva"
+	    "ti,omap4-smartreflex-core"
+	    "ti,omap4-smartreflex-mpu"
+	    "ti,omap4-smartreflex-iva"
+
+reg: Shall contain the device instance IO range
+
+interrupts: Shall contain the device instance interrupt
+
+
+Optional properties:
+
+ti,hwmods: Shall contain the TI interconnect module name if needed
+	   by the SoC
+
+
+Example:
+
+	smartreflex_iva: smartreflex@4a0db000 {
+		compatible = "ti,omap4-smartreflex-iva";
+		reg = <0x4a0db000 0x80>;
+		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+		ti,hwmods = "smartreflex_iva";
+	};
+
+	smartreflex_core: smartreflex4a0dd000 {
+		compatible = "ti,omap4-smartreflex-core";
+		reg = <0x4a0dd000 0x80>;
+		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+		ti,hwmods = "smartreflex_core";
+	};
+
+	smartreflex_mpu: smartreflex@4a0d9000 {
+		compatible = "ti,omap4-smartreflex-mpu";
+		reg = <0x4a0d9000 0x80>;
+		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+		ti,hwmods = "smartreflex_mpu";
+	};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -442,6 +442,27 @@
 			clock-frequency = <48000000>;
 		};
 
+		smartreflex_iva: smartreflex@4a0db000 {
+			compatible = "ti,omap4-smartreflex-iva";
+			reg = <0x4a0db000 0x80>;
+			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+			ti,hwmods = "smartreflex_iva";
+		};
+
+		smartreflex_core: smartreflex4a0dd000 {
+			compatible = "ti,omap4-smartreflex-core";
+			reg = <0x4a0dd000 0x80>;
+			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+			ti,hwmods = "smartreflex_core";
+		};
+
+		smartreflex_mpu: smartreflex@4a0d9000 {
+			compatible = "ti,omap4-smartreflex-mpu";
+			reg = <0x4a0d9000 0x80>;
+			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+			ti,hwmods = "smartreflex_mpu";
+		};
+
 		hwspinlock: spinlock@4a0f6000 {
 			compatible = "ti,omap4-hwspinlock";
 			reg = <0x4a0f6000 0x1000>;
-- 
2.14.1
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[PATCH 06/17] ARM: dts: Add missing slimbus node and binding for omap4

[Tony Lindgren]

On omap4 we're missing the slimbus node and it's related
"ti,hwmods" property that the SoC interconnect code needs.

Note that this will only show up as a bug with "doesn't have
mpu register target base" boot errors when the legacy platform
data is removed.

Let's also add the missing slimbus device tree binding
documentation while at it.

Cc: Liam Girdwood <lgirdwood-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Peter Ujfalusi <peter.ujfalusi-l0cyMroinI0@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
 .../devicetree/bindings/sound/ti-slimbus.txt       | 34 ++++++++++++++++++++++
 arch/arm/boot/dts/omap4.dtsi                       | 17 +++++++++++
 2 files changed, 51 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/sound/ti-slimbus.txt

diff --git a/Documentation/devicetree/bindings/sound/ti-slimbus.txt b/Documentation/devicetree/bindings/sound/ti-slimbus.txt
new file mode 100644
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/ti-slimbus.txt
@@ -0,0 +1,34 @@
+Texas Instruments Serial Low-power Inter-chip Media Bus (SLIMbus) binding
+
+SLIMbus is used for communication between digital audio components and the SoC.
+
+
+Required properties:
+
+compatible: Shall be one of the following:
+	    "ti,omap4-slimbus"
+
+reg: Shall contain the device instance IO range
+
+interrupts: Shall contain the device instance interrupt
+
+
+Optional properties:
+
+reg-names: Shall contain the IO range names if multiple IO
+	   ranges are used by the SoC
+
+ti,hwmods: Shall contain the TI interconnect module name if needed
+	   by the SoC
+
+
+Example:
+
+	slimbus1: slimbus@4012c000 {
+		compatible = "ti,omap4-slimbus";
+		reg = <0x4012c000 0x400>, /* MPU private access */
+		      <0x4902c000 0x400>; /* L3 Interconnect */
+		reg-names = "mpu", "dma";
+		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+		ti,hwmods = "slimbus1";
+	};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -382,6 +382,14 @@
 			#interrupt-cells = <2>;
 		};
 
+		slimbus2: slimbus@48076000 {
+			compatible = "ti,omap4-slimbus";
+			reg = <0x48076000 0x400>;
+			reg-names = "mpu";
+			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+			ti,hwmods = "slimbus2";
+		};
+
 		elm: elm@48078000 {
 			compatible = "ti,am3352-elm";
 			reg = <0x48078000 0x2000>;
@@ -711,6 +719,15 @@
 			status = "disabled";
 		};
 
+		slimbus1: slimbus@4012c000 {
+			compatible = "ti,omap4-slimbus";
+			reg = <0x4012c000 0x400>, /* MPU private access */
+			      <0x4902c000 0x400>; /* L3 Interconnect */
+			reg-names = "mpu", "dma";
+			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+			ti,hwmods = "slimbus1";
+		};
+
 		mcbsp4: mcbsp@48096000 {
 			compatible = "ti,omap4-mcbsp";
 			reg = <0x48096000 0xff>; /* L4 Interconnect */
-- 
2.14.1
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[PATCH 07/17] ARM: dts: Add missing onewire node for omap4

[Tony Lindgren]

On omap4 we're missing the onewire node with it's related "ti,hwmods"
property that the SoC interconnect code needs.

Note that this will only show up as a bug with "doesn't have
mpu register target base" boot errors when the legacy platform
data is removed.

Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
 arch/arm/boot/dts/omap4.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -549,6 +549,13 @@
 			dma-names = "tx0", "rx0", "tx1", "rx1";
 		};
 
+		hdqw1w: 1w@480b2000 {
+			compatible = "ti,omap3-1w";
+			reg = <0x480b2000 0x1000>;
+			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+			ti,hwmods = "hdq1w";
+		};
+
 		mcspi3: spi@480b8000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x480b8000 0x200>;
-- 
2.14.1
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[PATCH 08/17] ARM: dts: Add missing hsi node for omap4

[Tony Lindgren]

On omap4 we're missing the hsi node with it's related "ti,hwmods"
property that the SoC interconnect code needs.

Note that this will only show up as a bug with "doesn't have
mpu register target base" boot errors when the legacy platform
data is removed.

Let's also update the binding accrodingly while at it.

Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Sebastian Reichel <sre-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
 Documentation/devicetree/bindings/hsi/omap-ssi.txt |  7 ++++-
 arch/arm/boot/dts/omap4.dtsi                       | 34 ++++++++++++++++++++++
 2 files changed, 40 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/hsi/omap-ssi.txt b/Documentation/devicetree/bindings/hsi/omap-ssi.txt
--- a/Documentation/devicetree/bindings/hsi/omap-ssi.txt
+++ b/Documentation/devicetree/bindings/hsi/omap-ssi.txt
@@ -4,7 +4,7 @@ OMAP Synchronous Serial Interface (SSI) controller implements a legacy
 variant of MIPI's High Speed Synchronous Serial Interface (HSI).
 
 Required properties:
-- compatible:		Should include "ti,omap3-ssi".
+- compatible:		Should include "ti,omap3-ssi" or "ti,omap4-hsi"
 - reg-names:		Contains the values "sys" and "gdd" (in this order).
 - reg:			Contains a matching register specifier for each entry
 			in reg-names.
@@ -27,6 +27,7 @@ Each port is represented as a sub-node of the ti,omap3-ssi device.
 Required Port sub-node properties:
 - compatible:		Should be set to the following value
 			ti,omap3-ssi-port (applicable to OMAP34xx devices)
+			ti,omap4-ssi-port (applicable to OMAP44xx devices)
 - reg-names:		Contains the values "tx" and "rx" (in this order).
 - reg:			Contains a matching register specifier for each entry
 			in reg-names.
@@ -38,6 +39,10 @@ Required Port sub-node properties:
 			property. If it's missing the port will not be
 			enabled.
 
+Optional properties:
+- ti,hwmods:		Shall contain TI interconnect module name if needed
+			by the SoC
+
 Example for Nokia N900:
 
 ssi-controller@48058000 {
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -632,6 +632,40 @@
 			dma-names = "tx", "rx";
 		};
 
+		hsi: hsi@4a058000 {
+			compatible = "ti,omap4-hsi";
+			reg = <0x4a058000 0x4000>,
+			      <0x4a05c000 0x1000>;
+			reg-names = "sys", "gdd";
+			ti,hwmods = "hsi";
+
+			clocks = <&hsi_fck>;
+			clock-names = "hsi_fck";
+
+			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "gdd_mpu";
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x4a058000 0x4000>;
+
+			hsi_port1: hsi-port@2000 {
+				compatible = "ti,omap4-hsi-port";
+				reg = <0x2000 0x800>,
+				      <0x2800 0x800>;
+				reg-names = "tx", "rx";
+				interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			hsi_port2: hsi-port@3000 {
+				compatible = "ti,omap4-hsi-port";
+				reg = <0x3000 0x800>,
+				      <0x3800 0x800>;
+				reg-names = "tx", "rx";
+				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
 		mmu_dsp: mmu@4a066000 {
 			compatible = "ti,omap4-iommu";
 			reg = <0x4a066000 0x100>;
-- 
2.14.1
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[PATCH 09/17] ARM: dts: Add missing iss node and binding for omap4

[Tony Lindgren]

On omap4 we're missing the iss node with it's related "ti,hwmods"
property that the SoC interconnect code needs.

Note that this will only show up as a bug with "doesn't have
mpu register target base" boot errors when the legacy platform
data is removed.

Cc: Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Mauro Carvalho Chehab <mchehab-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Sakari Ailus <sakari.ailus-X3B1VOXEql0@public.gmane.org>
Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
 Documentation/devicetree/bindings/media/ti-iss.txt | 33 ++++++++++++++++++++++
 arch/arm/boot/dts/omap4.dtsi                       |  7 +++++
 2 files changed, 40 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/ti-iss.txt

diff --git a/Documentation/devicetree/bindings/media/ti-iss.txt b/Documentation/devicetree/bindings/media/ti-iss.txt
new file mode 100644
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/ti-iss.txt
@@ -0,0 +1,33 @@
+Texas Instruments Imaging Subsystem (ISS) binding
+
+ISS is used for cameras on Texas Instruments SoCs. Note that this
+binding is still missing the connections to the external devices
+modeled for the driver.
+
+Required properties:
+
+compatible: Shall be one of the following:
+	    "ti,omap4-iss"
+
+reg: Shall contain the device instance IO range
+
+interrupts: Shall contain the device instance interrupt
+
+
+Optional properties:
+
+reg-names: Shall contain the IO range names if multiple IO
+	   ranges are used by the SoC
+
+ti,hwmods: Shall contain the TI interconnect module name if needed
+	   by the SoC
+
+
+Example:
+
+	iss: iss@52000000 {
+		compatible = "ti,omap4-iss";
+		reg = <0x52000000 0x1000000>;
+		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+		ti,hwmods = "iss";
+	};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -674,6 +674,13 @@
 			#iommu-cells = <0>;
 		};
 
+		iss: iss@52000000 {
+			compatible = "ti,omap4-iss";
+			reg = <0x52000000 0x1000000>;
+			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+			ti,hwmods = "iss";
+		};
+
 		mmu_ipu: mmu@55082000 {
 			compatible = "ti,omap4-iommu";
 			reg = <0x55082000 0x100>;
-- 
2.14.1
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[PATCH 10/17] ARM: dts: Add missing wdt3 node for omap4

[Tony Lindgren]

On omap4 we're missing the wdt3 node with it's related "ti,hwmods"
property that the SoC interconnect code needs.

Note that this will only show up as a bug with "doesn't have
mpu register target base" boot errors when the legacy platform
data is removed.

Cc: Peter Ujfalusi <peter.ujfalusi-l0cyMroinI0@public.gmane.org>
Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
 arch/arm/boot/dts/omap4.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -697,6 +697,14 @@
 			ti,hwmods = "wd_timer2";
 		};
 
+		wdt3: wdt@40130000 {
+			compatible = "ti,omap4-wdt", "ti,omap3-wdt";
+			reg = <0x40130000 0x80>, /* MPU private access */
+			      <0x49030000 0x80>; /* L3 Interconnect */
+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+			ti,hwmods = "wd_timer3";
+		};
+
 		mcpdm: mcpdm@40132000 {
 			compatible = "ti,omap4-mcpdm";
 			reg = <0x40132000 0x7f>, /* MPU private access */
-- 
2.14.1
--
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[PATCH 11/17] ARM: dts: Add missing mcasp node for omap4

[Tony Lindgren]

On omap4 we're missing the mcasp node with it's related "ti,hwmods"
property that the SoC interconnect code needs.

Note that this will only show up as a bug with "doesn't have
mpu register target base" boot errors when the legacy platform
data is removed.

Cc: Liam Girdwood <lgirdwood-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Peter Ujfalusi <peter.ujfalusi-l0cyMroinI0@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
 Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt | 1 +
 arch/arm/boot/dts/omap4.dtsi                                    | 9 +++++++++
 2 files changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
--- a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
+++ b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
@@ -6,6 +6,7 @@ Required properties:
 	"ti,da830-mcasp-audio"	: for both DA830 & DA850 platforms
 	"ti,am33xx-mcasp-audio"	: for AM33xx platforms (AM33xx, AM43xx, TI81xx)
 	"ti,dra7-mcasp-audio"	: for DRA7xx platforms
+	"ti,omap4-mcasp-audio"	: for OMAP4 platforms
 
 - reg : Should contain reg specifiers for the entries in the reg-names property.
 - reg-names : Should contain:
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -775,6 +775,15 @@
 			status = "disabled";
 		};
 
+		mcasp: mcasp@40128000 {
+			compatible = "ti,omap4-mcasp-audio";
+			reg = <0x40128000 0x400>, /* MPU private access */
+			      <0x49028000 0x400>; /* L3 Interconnect */
+			reg-names = "mpu", "dma";
+			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+			ti,hwmods = "mcasp";
+		};
+
 		slimbus1: slimbus@4012c000 {
 			compatible = "ti,omap4-slimbus";
 			reg = <0x4012c000 0x400>, /* MPU private access */
-- 
2.14.1
--
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[PATCH 12/17] ARM: dts: Add missing aess node and binding for omap4

[Tony Lindgren]

On omap4 we're missing the aess node with it's related "ti,hwmods"
property that the SoC interconnect code needs.

Note that this will only show up as a bug with "doesn't have
mpu register target base" boot errors when the legacy platform
data is removed.

Cc: Liam Girdwood <lgirdwood-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Peter Ujfalusi <peter.ujfalusi-l0cyMroinI0@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
 .../devicetree/bindings/sound/ti-aess.txt          | 33 ++++++++++++++++++++++
 arch/arm/boot/dts/omap4.dtsi                       |  8 ++++++
 2 files changed, 41 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/sound/ti-aess.txt

diff --git a/Documentation/devicetree/bindings/sound/ti-aess.txt b/Documentation/devicetree/bindings/sound/ti-aess.txt
new file mode 100644
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/ti-aess.txt
@@ -0,0 +1,33 @@
+Texas Instruments Audio Engine Subsystem (AESS) binding
+
+AESS performs real-time signal processing on TI SoCs.
+
+
+Required properties:
+
+compatible: Shall be one of the following:
+	    "ti,omap4-aess"
+
+reg: Shall contain the device instance IO range
+
+interrupts: Shall contain the device instance interrupt
+
+
+Optional properties:
+
+reg-names: Shall contain the IO range names if multiple IO
+	   ranges are used by the SoC
+
+ti,hwmods: Shall contain the TI interconnect module name if needed
+	   by the SoC
+
+
+Example:
+
+	aess: aess@401f1000 {
+		compatible = "ti,omap4-aess";
+		reg = <0x401f1000 0x400>, /* MPU private access */
+		      <0x490f1000 0x400>; /* L3 Interconnect */
+		reg-names = "mpu", "dma";
+		ti,hwmods = "aess";
+	};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -793,6 +793,14 @@
 			ti,hwmods = "slimbus1";
 		};
 
+		aess: aess@401f1000 {
+			compatible = "ti,omap4-aess";
+			reg = <0x401f1000 0x400>, /* MPU private access */
+			      <0x490f1000 0x400>; /* L3 Interconnect */
+			reg-names = "mpu", "dma";
+			ti,hwmods = "aess";
+		};
+
 		mcbsp4: mcbsp@48096000 {
 			compatible = "ti,omap4-mcbsp";
 			reg = <0x48096000 0xff>; /* L4 Interconnect */
-- 
2.14.1
--
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[PATCH 13/17] ARM: dts: Add missing fdif node and binding for omap4

[Tony Lindgren]

On omap4 we're missing the fdif node with it's related "ti,hwmods"
property that the SoC interconnect code needs.

Note that this will only show up as a bug with "doesn't have
mpu register target base" boot errors when the legacy platform
data is removed.

Cc: Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Mauro Carvalho Chehab <mchehab-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Sakari Ailus <sakari.ailus-X3B1VOXEql0@public.gmane.org>
Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
 .../devicetree/bindings/media/ti-fdif.txt          | 29 ++++++++++++++++++++++
 arch/arm/boot/dts/omap4.dtsi                       |  7 ++++++
 2 files changed, 36 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/ti-fdif.txt

diff --git a/Documentation/devicetree/bindings/media/ti-fdif.txt b/Documentation/devicetree/bindings/media/ti-fdif.txt
new file mode 100644
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/ti-fdif.txt
@@ -0,0 +1,29 @@
+Texas Instruments Face Detect (FDIF) binding
+
+FDIF can be used for face detection on Texas Instruments SoCs.
+
+Required properties:
+
+compatible: Shall be one of the following:
+	    "ti,omap4-fdif"
+
+reg: Shall contain the device instance IO range
+
+interrupts: Shall contain the device instance interrupt
+
+
+Optional properties:
+
+ti,hwmods: Shall contain the TI interconnect module name if needed
+	   by the SoC
+
+
+Example:
+
+	fdif: fdif@4a10a000 {
+		compatible = "ti,omap4-fdif";
+		reg = <0x4a10a000 0x1000>;
+		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+		ti,hwmods = "fdif";
+	};
+
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -889,6 +889,13 @@
 			};
 		};
 
+		fdif: fdif@4a10a000 {
+			compatible = "ti,omap4-fdif";
+			reg = <0x4a10a000 0x1000>;
+			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+			ti,hwmods = "fdif";
+		};
+
 		timer1: timer@4a318000 {
 			compatible = "ti,omap3430-timer";
 			reg = <0x4a318000 0x80>;
-- 
2.14.1
--
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[PATCH 14/17] ARM: dts: Add missing gpu node and binding for omap4

[Tony Lindgren]

On omap4 we're missing the PowerVR SGX GPU node with it's related
"ti,hwmods" property that the SoC interconnect code needs.

Note that this will only show up as a bug with "doesn't have
mpu register target base" boot errors when the legacy platform
data is removed.

Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Tomi Valkeinen <tomi.valkeinen-l0cyMroinI0@public.gmane.org>
Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
 .../devicetree/bindings/gpu/ti-powervr-sgx.txt     | 39 ++++++++++++++++++++++
 arch/arm/boot/dts/omap4.dtsi                       |  7 ++++
 2 files changed, 46 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/gpu/ti-powervr-sgx.txt

diff --git a/Documentation/devicetree/bindings/gpu/ti-powervr-sgx.txt b/Documentation/devicetree/bindings/gpu/ti-powervr-sgx.txt
new file mode 100644
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/ti-powervr-sgx.txt
@@ -0,0 +1,39 @@
+Texas Instruments PowevVR SGX binding
+
+SGX can be used for graphics acceleration on Texas Instruments SoCs.
+
+Note that the SGX binding is currently only used by the SoC interconnect
+code to idle the module on init and no open source driver is available
+for SGX. The PowerVR model specific driver nodes should be child nodes
+of this instance, and a clock binding may need to be added.
+
+Required properties:
+
+compatible: Shall be one of the following:
+		"ti,omap3-sgx530"
+		"ti,am335-sgx530"
+		"ti,omap4-sgx540"
+		"ti,omap5-sgx544"
+		"ti,dra7-sgx544"
+
+reg: Shall contain the device instance IO range
+
+interrupts: Shall contain the device instance interrupt
+
+
+Optional properties:
+
+reg-names: Shall contain the IO range names if multiple IO
+	   ranges are used by the SoC
+
+ti,hwmods: Shall contain the TI interconnect module name if needed
+	   by the SoC
+
+
+Example:
+	gpu: gpu@56000000 {
+		compatible = "ti,omap4-sgx540";
+		reg = <0x56000000 0x10000>;
+		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+		ti,hwmods = "gpu";
+	};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -1111,6 +1111,13 @@
 			status = "disabled";
 		};
 
+		gpu: gpu@56000000 {
+			compatible = "ti,omap4-sgx540";
+			reg = <0x56000000 0x10000>;
+			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+			ti,hwmods = "gpu";
+		};
+
 		dss: dss@58000000 {
 			compatible = "ti,omap4-dss";
 			reg = <0x58000000 0x80>;
-- 
2.14.1
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[PATCH 15/17] ARM: dts: Add missing dma hwmod property for omap5

[Tony Lindgren]

On omap5 we're missing the dma "ti,hwmods" property that the
SoC interconnect code needs.

Note that this will only show up as a bug with "doesn't have
mpu register target base" boot errors when the legacy platform
data is removed.

Cc: Peter Ujfalusi <peter.ujfalusi-l0cyMroinI0@public.gmane.org>
Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
 arch/arm/boot/dts/omap5.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -295,6 +295,7 @@
 			#dma-cells = <1>;
 			dma-channels = <32>;
 			dma-requests = <127>;
+			ti,hwmods = "dma_system";
 		};
 
 		gpio1: gpio@4ae10000 {
-- 
2.14.1
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[PATCH 16/17] ARM: dts: Add missing hwmod related nodes for am33xx

[Tony Lindgren]

On am33xx we're missing the pmu and emif nodes with their related
"ti,hwmods" properties that the SoC interconnect code needs.

Note that this will only show up as a bug with "doesn't have
mpu register target base" boot errors when the legacy platform
data is removed.

Let's also update the related binding documentation while at it.

Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
 .../devicetree/bindings/memory-controllers/ti/emif.txt         |  6 ++++--
 arch/arm/boot/dts/am33xx.dtsi                                  | 10 +++++++++-
 2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
--- a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
@@ -7,8 +7,10 @@ of the EMIF IP and memory parts attached to it.
 
 Required properties:
 - compatible	: Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
-  is the IP revision of the specific EMIF instance.
-		  For am437x should be ti,emif-am4372.
+  is the IP revision of the specific EMIF instance. For newer controllers,
+  compatible should be one of the following:
+  	     "ti,emif-am3352"
+	     "ti,emif-am4372"
 
 - phy-type	: <u32> indicating the DDR phy type. Following are the
   allowed values
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -128,9 +128,11 @@
 		};
 	};
 
-	pmu {
+	pmu@4b000000 {
 		compatible = "arm,cortex-a8-pmu";
 		interrupts = <3>;
+		reg = <0x4b000000 0x1000000>;
+		ti,hwmods = "debugss";
 	};
 
 	/*
@@ -927,6 +929,12 @@
 			};
 		};
 
+		emif: emif@4c000000 {
+			compatible = "ti,emif-am3352";
+			reg = <0x4c000000 0x1000000>;
+			ti,hwmods = "emif";
+		};
+
 		gpmc: gpmc@50000000 {
 			compatible = "ti,am3352-gpmc";
 			ti,hwmods = "gpmc";
-- 
2.14.1
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[PATCH 17/17] ARM: dts: Add missing hwmod related properties for dra7

[Tony Lindgren]

On dra7 we're missing two "ti,hwmods" properties that the SoC
interconnect code needs. For hdq 1-wire, we need to add the
node for that.

Note that this will only show up as a bug with "doesn't have
mpu register target base" boot errors when the legacy platform
data is removed.

Cc: Nishanth Menon <nm-l0cyMroinI0@public.gmane.org>
Cc: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
 arch/arm/boot/dts/dra7.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -457,6 +457,7 @@
 			#dma-cells = <1>;
 			dma-channels = <32>;
 			dma-requests = <127>;
+			ti,hwmods = "dma_system";
 		};
 
 		edma: edma@43300000 {
@@ -1069,6 +1070,13 @@
 			max-frequency = <192000000>;
 		};
 
+		hdqw1w: 1w@480b2000 {
+			compatible = "ti,omap3-1w";
+			reg = <0x480b2000 0x1000>;
+			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+			ti,hwmods = "hdq1w";
+		};
+
 		mmc2: mmc@480b4000 {
 			compatible = "ti,omap4-hsmmc";
 			reg = <0x480b4000 0x400>;
-- 
2.14.1
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Re: [PATCH 13/17] ARM: dts: Add missing fdif node and binding for omap4

[Laurent Pinchart]

Hi Tony,

Thank you for the patch.

On Wednesday, 30 August 2017 18:19:49 EEST Tony Lindgren wrote:
> On omap4 we're missing the fdif node with it's related "ti,hwmods"
> property that the SoC interconnect code needs.
> 
> Note that this will only show up as a bug with "doesn't have
> mpu register target base" boot errors when the legacy platform
> data is removed.
> 
> Cc: Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Mauro Carvalho Chehab <mchehab-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Sakari Ailus <sakari.ailus-X3B1VOXEql0@public.gmane.org>
> Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>

Reviewed-by: Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>

> ---
>  .../devicetree/bindings/media/ti-fdif.txt          | 29 +++++++++++++++++++
>  arch/arm/boot/dts/omap4.dtsi                       |  7 ++++++
>  2 files changed, 36 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/media/ti-fdif.txt
> 
> diff --git a/Documentation/devicetree/bindings/media/ti-fdif.txt
> b/Documentation/devicetree/bindings/media/ti-fdif.txt new file mode 100644
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/ti-fdif.txt
> @@ -0,0 +1,29 @@
> +Texas Instruments Face Detect (FDIF) binding
> +
> +FDIF can be used for face detection on Texas Instruments SoCs.
> +
> +Required properties:
> +
> +compatible: Shall be one of the following:
> +	    "ti,omap4-fdif"
> +
> +reg: Shall contain the device instance IO range
> +
> +interrupts: Shall contain the device instance interrupt
> +
> +
> +Optional properties:
> +
> +ti,hwmods: Shall contain the TI interconnect module name if needed
> +	   by the SoC
> +
> +
> +Example:
> +
> +	fdif: fdif@4a10a000 {
> +		compatible = "ti,omap4-fdif";
> +		reg = <0x4a10a000 0x1000>;
> +		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> +		ti,hwmods = "fdif";
> +	};
> +
> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> --- a/arch/arm/boot/dts/omap4.dtsi
> +++ b/arch/arm/boot/dts/omap4.dtsi
> @@ -889,6 +889,13 @@
>  			};
>  		};
> 
> +		fdif: fdif@4a10a000 {
> +			compatible = "ti,omap4-fdif";
> +			reg = <0x4a10a000 0x1000>;
> +			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> +			ti,hwmods = "fdif";
> +		};
> +
>  		timer1: timer@4a318000 {
>  			compatible = "ti,omap3430-timer";
>  			reg = <0x4a318000 0x80>;


-- 
Regards,

Laurent Pinchart

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Re: [PATCH 08/17] ARM: dts: Add missing hsi node for omap4

[Sebastian Reichel]

[-- Attachment #1: Type: text/plain, Size: 4067 bytes --]

On Wed, Aug 30, 2017 at 08:19:44AM -0700, Tony Lindgren wrote:
> On omap4 we're missing the hsi node with it's related "ti,hwmods"
> property that the SoC interconnect code needs.
> 
> Note that this will only show up as a bug with "doesn't have
> mpu register target base" boot errors when the legacy platform
> data is removed.
> 
> Let's also update the binding accrodingly while at it.
> 
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Sebastian Reichel <sre-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/hsi/omap-ssi.txt |  7 ++++-
>  arch/arm/boot/dts/omap4.dtsi                       | 34 ++++++++++++++++++++++
>  2 files changed, 40 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/hsi/omap-ssi.txt b/Documentation/devicetree/bindings/hsi/omap-ssi.txt
> --- a/Documentation/devicetree/bindings/hsi/omap-ssi.txt
> +++ b/Documentation/devicetree/bindings/hsi/omap-ssi.txt
> @@ -4,7 +4,7 @@ OMAP Synchronous Serial Interface (SSI) controller implements a legacy
>  variant of MIPI's High Speed Synchronous Serial Interface (HSI).

Maybe change the leading text:

OMAP3's Synchronous Serial Interface (SSI) controller implements a
legacy variant of MIPI's High Speed Synchronous Serial Interface (HSI),
while the controller found inside OMAP4 is supposed to be fully compliant
with the HSI standard.

>  Required properties:
> -- compatible:		Should include "ti,omap3-ssi".
> +- compatible:		Should include "ti,omap3-ssi" or "ti,omap4-hsi"
>  - reg-names:		Contains the values "sys" and "gdd" (in this order).
>  - reg:			Contains a matching register specifier for each entry
>  			in reg-names.
> @@ -27,6 +27,7 @@ Each port is represented as a sub-node of the ti,omap3-ssi device.
>  Required Port sub-node properties:
>  - compatible:		Should be set to the following value
>  			ti,omap3-ssi-port (applicable to OMAP34xx devices)
> +			ti,omap4-ssi-port (applicable to OMAP44xx devices)
                     ^^^

this should be hsi.

>  - reg-names:		Contains the values "tx" and "rx" (in this order).
>  - reg:			Contains a matching register specifier for each entry
>  			in reg-names.
> @@ -38,6 +39,10 @@ Required Port sub-node properties:
>  			property. If it's missing the port will not be
>  			enabled.
>  
> +Optional properties:
> +- ti,hwmods:		Shall contain TI interconnect module name if needed
> +			by the SoC
> +
>  Example for Nokia N900:
>  
>  ssi-controller@48058000 {
> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> --- a/arch/arm/boot/dts/omap4.dtsi
> +++ b/arch/arm/boot/dts/omap4.dtsi
> @@ -632,6 +632,40 @@
>  			dma-names = "tx", "rx";
>  		};
>  
> +		hsi: hsi@4a058000 {
> +			compatible = "ti,omap4-hsi";
> +			reg = <0x4a058000 0x4000>,
> +			      <0x4a05c000 0x1000>;
> +			reg-names = "sys", "gdd";
> +			ti,hwmods = "hsi";
> +
> +			clocks = <&hsi_fck>;
> +			clock-names = "hsi_fck";
> +
> +			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "gdd_mpu";
> +
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0 0x4a058000 0x4000>;
> +
> +			hsi_port1: hsi-port@2000 {
> +				compatible = "ti,omap4-hsi-port";
> +				reg = <0x2000 0x800>,
> +				      <0x2800 0x800>;
> +				reg-names = "tx", "rx";
> +				interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			hsi_port2: hsi-port@3000 {
> +				compatible = "ti,omap4-hsi-port";
> +				reg = <0x3000 0x800>,
> +				      <0x3800 0x800>;
> +				reg-names = "tx", "rx";
> +				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
>  		mmu_dsp: mmu@4a066000 {
>  			compatible = "ti,omap4-iommu";
>  			reg = <0x4a066000 0x100>;

otherwise:

Reviewed-by: Sebastian Reichel <sre-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>

-- Sebastian

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Re: [PATCH 08/17] ARM: dts: Add missing hsi node for omap4

[Tony Lindgren]

* Sebastian Reichel <sre-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> [170830 12:38]:
> On Wed, Aug 30, 2017 at 08:19:44AM -0700, Tony Lindgren wrote:
> Maybe change the leading text:
> 
> OMAP3's Synchronous Serial Interface (SSI) controller implements a
> legacy variant of MIPI's High Speed Synchronous Serial Interface (HSI),
> while the controller found inside OMAP4 is supposed to be fully compliant
> with the HSI standard.

OK

> >  Required properties:
> > -- compatible:		Should include "ti,omap3-ssi".
> > +- compatible:		Should include "ti,omap3-ssi" or "ti,omap4-hsi"
> >  - reg-names:		Contains the values "sys" and "gdd" (in this order).
> >  - reg:			Contains a matching register specifier for each entry
> >  			in reg-names.
> > @@ -27,6 +27,7 @@ Each port is represented as a sub-node of the ti,omap3-ssi device.
> >  Required Port sub-node properties:
> >  - compatible:		Should be set to the following value
> >  			ti,omap3-ssi-port (applicable to OMAP34xx devices)
> > +			ti,omap4-ssi-port (applicable to OMAP44xx devices)
>                      ^^^
> 
> this should be hsi.

Oops fixed.

> otherwise:
> 
> Reviewed-by: Sebastian Reichel <sre-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>

Thanks, updated patch below.

Regards,

Tony

8< --------------------
>From tony Mon Sep 17 00:00:00 2001
From: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
Date: Wed, 30 Aug 2017 08:07:51 -0700
Subject: [PATCH] ARM: dts: Add missing hsi node for omap4

On omap4 we're missing the hsi node with it's related "ti,hwmods"
property that the SoC interconnect code needs.

Note that this will only show up as a bug with "doesn't have
mpu register target base" boot errors when the legacy platform
data is removed.

Let's also update the binding accrodingly while at it.

Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Reviewed-by: Sebastian Reichel <sre-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
 Documentation/devicetree/bindings/hsi/omap-ssi.txt | 13 +++++++--
 arch/arm/boot/dts/omap4.dtsi                       | 34 ++++++++++++++++++++++
 2 files changed, 44 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/hsi/omap-ssi.txt b/Documentation/devicetree/bindings/hsi/omap-ssi.txt
--- a/Documentation/devicetree/bindings/hsi/omap-ssi.txt
+++ b/Documentation/devicetree/bindings/hsi/omap-ssi.txt
@@ -1,10 +1,12 @@
 OMAP SSI controller bindings
 
-OMAP Synchronous Serial Interface (SSI) controller implements a legacy
-variant of MIPI's High Speed Synchronous Serial Interface (HSI).
+OMAP3's Synchronous Serial Interface (SSI) controller implements a
+legacy variant of MIPI's High Speed Synchronous Serial Interface (HSI),
+while the controller found inside OMAP4 is supposed to be fully compliant
+with the HSI standard.
 
 Required properties:
-- compatible:		Should include "ti,omap3-ssi".
+- compatible:		Should include "ti,omap3-ssi" or "ti,omap4-hsi"
 - reg-names:		Contains the values "sys" and "gdd" (in this order).
 - reg:			Contains a matching register specifier for each entry
 			in reg-names.
@@ -27,6 +29,7 @@ Each port is represented as a sub-node of the ti,omap3-ssi device.
 Required Port sub-node properties:
 - compatible:		Should be set to the following value
 			ti,omap3-ssi-port (applicable to OMAP34xx devices)
+			ti,omap4-hsi-port (applicable to OMAP44xx devices)
 - reg-names:		Contains the values "tx" and "rx" (in this order).
 - reg:			Contains a matching register specifier for each entry
 			in reg-names.
@@ -38,6 +41,10 @@ Required Port sub-node properties:
 			property. If it's missing the port will not be
 			enabled.
 
+Optional properties:
+- ti,hwmods:		Shall contain TI interconnect module name if needed
+			by the SoC
+
 Example for Nokia N900:
 
 ssi-controller@48058000 {
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -632,6 +632,40 @@
 			dma-names = "tx", "rx";
 		};
 
+		hsi: hsi@4a058000 {
+			compatible = "ti,omap4-hsi";
+			reg = <0x4a058000 0x4000>,
+			      <0x4a05c000 0x1000>;
+			reg-names = "sys", "gdd";
+			ti,hwmods = "hsi";
+
+			clocks = <&hsi_fck>;
+			clock-names = "hsi_fck";
+
+			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "gdd_mpu";
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x4a058000 0x4000>;
+
+			hsi_port1: hsi-port@2000 {
+				compatible = "ti,omap4-hsi-port";
+				reg = <0x2000 0x800>,
+				      <0x2800 0x800>;
+				reg-names = "tx", "rx";
+				interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			hsi_port2: hsi-port@3000 {
+				compatible = "ti,omap4-hsi-port";
+				reg = <0x3000 0x800>,
+				      <0x3800 0x800>;
+				reg-names = "tx", "rx";
+				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
 		mmu_dsp: mmu@4a066000 {
 			compatible = "ti,omap4-iommu";
 			reg = <0x4a066000 0x100>;
-- 
2.14.1
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Re: [PATCH 11/17] ARM: dts: Add missing mcasp node for omap4

[Peter Ujfalusi]




Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

On 2017-08-30 18:19, Tony Lindgren wrote:
> On omap4 we're missing the mcasp node with it's related "ti,hwmods"
> property that the SoC interconnect code needs.
> 
> Note that this will only show up as a bug with "doesn't have
> mpu register target base" boot errors when the legacy platform
> data is removed.
> 
> Cc: Liam Girdwood <lgirdwood-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Peter Ujfalusi <peter.ujfalusi-l0cyMroinI0@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt | 1 +
>  arch/arm/boot/dts/omap4.dtsi                                    | 9 +++++++++
>  2 files changed, 10 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
> --- a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
> +++ b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
> @@ -6,6 +6,7 @@ Required properties:
>  	"ti,da830-mcasp-audio"	: for both DA830 & DA850 platforms
>  	"ti,am33xx-mcasp-audio"	: for AM33xx platforms (AM33xx, AM43xx, TI81xx)
>  	"ti,dra7-mcasp-audio"	: for DRA7xx platforms
> +	"ti,omap4-mcasp-audio"	: for OMAP4 platforms
>  
>  - reg : Should contain reg specifiers for the entries in the reg-names property.
>  - reg-names : Should contain:
> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> --- a/arch/arm/boot/dts/omap4.dtsi
> +++ b/arch/arm/boot/dts/omap4.dtsi
> @@ -775,6 +775,15 @@
>  			status = "disabled";
>  		};
>  
> +		mcasp: mcasp@40128000 {
> +			compatible = "ti,omap4-mcasp-audio";
> +			reg = <0x40128000 0x400>, /* MPU private access */
> +			      <0x49028000 0x400>; /* L3 Interconnect */
> +			reg-names = "mpu", "dma";
> +			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
> +			ti,hwmods = "mcasp";
> +		};

I would not do this. We don't support the NcASP on OMAP4 or OMAP5 for
that matter.
In theory it is the same IP as found in other SoCs, but in OMAP4 the TX
path is disabled and (in theory) the i2s support is also a thing which
is not supported - only DIT mode.
We do not even have any hardware where it can be tested (Galaxy Nexus
uses McASP for S/PDIF output when it is docked.
For Android we have had omap-mcasp driver, but it is not upstream and is
never will as if we are going to support McASP it should be done via the
davinci-mcasp driver.

By adding the node we might give the impression that McASP on OMAP4/5 is
usable, which is not.

On the other hand, the DT describes the HW, so it should be OK to add
all peripherals even if there is no driver to support it. In this case
the status = "disabled"; must be there.

> +
>  		slimbus1: slimbus@4012c000 {
>  			compatible = "ti,omap4-slimbus";
>  			reg = <0x4012c000 0x400>, /* MPU private access */
> 

- Péter

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Re: [PATCH 12/17] ARM: dts: Add missing aess node and binding for omap4

[Peter Ujfalusi]




Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

On 2017-08-30 18:19, Tony Lindgren wrote:
> On omap4 we're missing the aess node with it's related "ti,hwmods"
> property that the SoC interconnect code needs.
> 
> Note that this will only show up as a bug with "doesn't have
> mpu register target base" boot errors when the legacy platform
> data is removed.
> 
> Cc: Liam Girdwood <lgirdwood-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Peter Ujfalusi <peter.ujfalusi-l0cyMroinI0@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
> ---
>  .../devicetree/bindings/sound/ti-aess.txt          | 33 ++++++++++++++++++++++
>  arch/arm/boot/dts/omap4.dtsi                       |  8 ++++++
>  2 files changed, 41 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/sound/ti-aess.txt
> 
> diff --git a/Documentation/devicetree/bindings/sound/ti-aess.txt b/Documentation/devicetree/bindings/sound/ti-aess.txt
> new file mode 100644
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sound/ti-aess.txt
> @@ -0,0 +1,33 @@
> +Texas Instruments Audio Engine Subsystem (AESS) binding
> +
> +AESS performs real-time signal processing on TI SoCs.
> +
> +
> +Required properties:
> +
> +compatible: Shall be one of the following:
> +	    "ti,omap4-aess"
> +
> +reg: Shall contain the device instance IO range
> +
> +interrupts: Shall contain the device instance interrupt
> +
> +
> +Optional properties:
> +
> +reg-names: Shall contain the IO range names if multiple IO
> +	   ranges are used by the SoC
> +
> +ti,hwmods: Shall contain the TI interconnect module name if needed
> +	   by the SoC
> +
> +
> +Example:
> +
> +	aess: aess@401f1000 {
> +		compatible = "ti,omap4-aess";
> +		reg = <0x401f1000 0x400>, /* MPU private access */
> +		      <0x490f1000 0x400>; /* L3 Interconnect */
> +		reg-names = "mpu", "dma";
> +		ti,hwmods = "aess";
> +	};
> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> --- a/arch/arm/boot/dts/omap4.dtsi
> +++ b/arch/arm/boot/dts/omap4.dtsi
> @@ -793,6 +793,14 @@
>  			ti,hwmods = "slimbus1";
>  		};
>  
> +		aess: aess@401f1000 {
> +			compatible = "ti,omap4-aess";
> +			reg = <0x401f1000 0x400>, /* MPU private access */
> +			      <0x490f1000 0x400>; /* L3 Interconnect */
> +			reg-names = "mpu", "dma";
> +			ti,hwmods = "aess";

status = "disabled"

> +		};

Similar comment applies to AESS as to the McASP. We don't have driver
for it and we most likely not going to have.
But the binding is not correct in any case. The latest official Android
kernel is 3.4(ish) to support AESS/ABE. I have rewritten the whole thing
as an effort to upstream it and maintained the code up to 3.15. There
the DT node looks like this:

aess: aess@0x401f1000 {
	compatible = "ti,omap4-aess";
	reg = <0x401f1000 0x3ff>, /* MPU private access */
		<0x40180000 0xffff>, /* DMEM - MPU */
		<0x401a0000 0x1fff>, /* CMEM - MPU */
		<0x401c0000 0x5fff>, /* SMEM - MPU */
		<0x401e0000 0x1fff>, /* PMEM - MPU */
		<0x490f1000 0x3ff>, /* L3 Interconnect */
		<0x49080000 0xffff>, /* DMEM - MPU */
		<0x490a0000 0x1fff>, /* CMEM - MPU */
		<0x490ce000 0x5fff>, /* SMEM - MPU */
		<0x490e0000 0x1fff>; /* PMEM - MPU */
	reg-names = "mpu", "dmem", "cmem", "smem", "pmem",
			"dma","dmem_dma", "cmem_dma", "smem_dma",
			"pmem_dma";
	interrupts = <0 99 0x4>;
	ti,hwmods = "aess";
	dmas = <&sdma 101>,
		<&sdma 102>,
		<&sdma 103>,
		<&sdma 104>,
		<&sdma 105>,
		<&sdma 106>,
		<&sdma 107>,
		<&sdma 108>;
	dma-names = "fifo0", "fifo1", "fifo2", "fifo3", "fifo4",
			"fifo5", "fifo6", "fifo7";
};

This is more closer to what we might need to describe AESS, but it might
be not correct if I ever have the time to forward port and convert it to
current upstream framework (DPCM, graph, whatever)

> +
>  		mcbsp4: mcbsp@48096000 {
>  			compatible = "ti,omap4-mcbsp";
>  			reg = <0x48096000 0xff>; /* L4 Interconnect */
> 

- Péter

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Re: [PATCH 11/17] ARM: dts: Add missing mcasp node for omap4

[Tony Lindgren]

* Peter Ujfalusi <peter.ujfalusi-l0cyMroinI0@public.gmane.org> [170830 22:48]:
> On 2017-08-30 18:19, Tony Lindgren wrote:
> > diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> > --- a/arch/arm/boot/dts/omap4.dtsi
> > +++ b/arch/arm/boot/dts/omap4.dtsi
> > @@ -775,6 +775,15 @@
> >  			status = "disabled";
> >  		};
> >  
> > +		mcasp: mcasp@40128000 {
> > +			compatible = "ti,omap4-mcasp-audio";
> > +			reg = <0x40128000 0x400>, /* MPU private access */
> > +			      <0x49028000 0x400>; /* L3 Interconnect */
> > +			reg-names = "mpu", "dma";
> > +			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
> > +			ti,hwmods = "mcasp";
> > +		};
> 
> I would not do this. We don't support the NcASP on OMAP4 or OMAP5 for
> that matter.
> In theory it is the same IP as found in other SoCs, but in OMAP4 the TX
> path is disabled and (in theory) the i2s support is also a thing which
> is not supported - only DIT mode.
> We do not even have any hardware where it can be tested (Galaxy Nexus
> uses McASP for S/PDIF output when it is docked.
> For Android we have had omap-mcasp driver, but it is not upstream and is
> never will as if we are going to support McASP it should be done via the
> davinci-mcasp driver.

OK

> By adding the node we might give the impression that McASP on OMAP4/5 is
> usable, which is not.

OK. Yeah we need to make sure this is for the interconnect
target module, and not for it's child device(s) mcasp.

> On the other hand, the DT describes the HW, so it should be OK to add
> all peripherals even if there is no driver to support it. In this case
> the status = "disabled"; must be there.

Yeah well this is for the interconnect target module that we are
already accessing during init to idle it. But it's actually the
children of this node that should have the status = "disabled"!

I think we can solve your concernd by adding the generic minimal
binding and compatible properites for the interconnect target
module for which I already posted an RFC a while back.

So we can just use compatibles "ti,sysc-type1", "ti,sysc-type2"
and "ti,sysc-type3" as are going to need those anyways soonish.

So the McASP interconnect target module would just become:

	target_module@40128000 {
		compatible = "ti,sysc-type2";
		reg = <0x40128000 0x400>, /* MPU private access */
		      <0x49028000 0x400>; /* L3 Interconnect */
		reg-names = "mpu", "dma";
		ti,hwmods = "mcasp";
	};

And if there ever is a McASP driver, it can be a child of
this node. And eventually we will just drop ti,hwmods too.

Regards,

Tony
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Re: [PATCH 12/17] ARM: dts: Add missing aess node and binding for omap4

[Tony Lindgren]

* Peter Ujfalusi <peter.ujfalusi-l0cyMroinI0@public.gmane.org> [170830 22:54]:
> On 2017-08-30 18:19, Tony Lindgren wrote:
> > +		aess: aess@401f1000 {
> > +			compatible = "ti,omap4-aess";
> > +			reg = <0x401f1000 0x400>, /* MPU private access */
> > +			      <0x490f1000 0x400>; /* L3 Interconnect */
> > +			reg-names = "mpu", "dma";
> > +			ti,hwmods = "aess";
> 
> status = "disabled"

That could be done for it's children if needed like I replied in
the McASP patch as this is for the interconnect target module.
And this will need to just use the "ti,sysc-type2" compatible.

> Similar comment applies to AESS as to the McASP. We don't have driver
> for it and we most likely not going to have.

OK

> But the binding is not correct in any case. The latest official Android
> kernel is 3.4(ish) to support AESS/ABE. I have rewritten the whole thing
> as an effort to upstream it and maintained the code up to 3.15. There
> the DT node looks like this:
> 
> aess: aess@0x401f1000 {
> 	compatible = "ti,omap4-aess";
> 	reg = <0x401f1000 0x3ff>, /* MPU private access */
> 		<0x40180000 0xffff>, /* DMEM - MPU */
> 		<0x401a0000 0x1fff>, /* CMEM - MPU */
> 		<0x401c0000 0x5fff>, /* SMEM - MPU */
> 		<0x401e0000 0x1fff>, /* PMEM - MPU */
> 		<0x490f1000 0x3ff>, /* L3 Interconnect */
> 		<0x49080000 0xffff>, /* DMEM - MPU */
> 		<0x490a0000 0x1fff>, /* CMEM - MPU */
> 		<0x490ce000 0x5fff>, /* SMEM - MPU */
> 		<0x490e0000 0x1fff>; /* PMEM - MPU */
> 	reg-names = "mpu", "dmem", "cmem", "smem", "pmem",
> 			"dma","dmem_dma", "cmem_dma", "smem_dma",
> 			"pmem_dma";
> 	interrupts = <0 99 0x4>;
> 	ti,hwmods = "aess";
> 	dmas = <&sdma 101>,
> 		<&sdma 102>,
> 		<&sdma 103>,
> 		<&sdma 104>,
> 		<&sdma 105>,
> 		<&sdma 106>,
> 		<&sdma 107>,
> 		<&sdma 108>;
> 	dma-names = "fifo0", "fifo1", "fifo2", "fifo3", "fifo4",
> 			"fifo5", "fifo6", "fifo7";
> };
> 
> This is more closer to what we might need to describe AESS, but it might
> be not correct if I ever have the time to forward port and convert it to
> current upstream framework (DPCM, graph, whatever)

Yeah OK thanks. If there ever is a driver for it, those can then
be added as child nodes of the "ti,sysc-type2" interconnect target
node.

Regards,

Tony
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Re: [PATCH 03/17] ARM: dts: Add missing properties for omap4 control modules

[Rob Herring]

On Wed, Aug 30, 2017 at 08:19:39AM -0700, Tony Lindgren wrote:
> On omap4, we are missing several ti,hwmods properties and IO
> ranges for system control modules. These are needed by the SoC
> interconnect code.
> 
> Note that this will only show up as a bug with "doesn't have
> mpu register target base" boot errors when the legacy platform
> data is removed.
> 
> In order to add these, we need to move omap4_pmx_wkup to be a
> child of omap4_padconf_wkup.
> 
> On omap4 there are separate modules for control module and
> control module pads. For control module core, we have this
> already configured except for the missing ti,hwmods and reg
> entries.
> 
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
> ---
>  .../devicetree/bindings/arm/omap/ctrl.txt          |  2 ++
>  arch/arm/boot/dts/omap4.dtsi                       | 39 ++++++++++++++++------
>  2 files changed, 31 insertions(+), 10 deletions(-)

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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Re: [PATCH 05/17] ARM: dts: Add missing smartreflex node and binding for omap4

[Rob Herring]

On Wed, Aug 30, 2017 at 08:19:41AM -0700, Tony Lindgren wrote:
> We are missing smartreflex device tree nodes for omap4 with
> their related "ti,hwmods" properties that the SoC interconnect
> code needs.
> 
> Note that this will only show up as a bug with "doesn't have
> mpu register target base" boot errors when the legacy platform
> data is removed.
> 
> And since we're missing the device tree binding for smartreflex,
> let's also add it and document the existing omap3 use too.
> 
> Note that the related driver also needs to be updated to probe
> using device tree and get the platform data passed to it using
> auxdata with arch/arm/mach-omap2/pdata-quirks.c.
> 
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Nishanth Menon <nm-l0cyMroinI0@public.gmane.org>
> Cc: Rafael J. Wysocki <rafael.j.wysocki-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
> Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
> ---
>  .../devicetree/bindings/power/ti-smartreflex.txt   | 47 ++++++++++++++++++++++
>  arch/arm/boot/dts/omap4.dtsi                       | 21 ++++++++++
>  2 files changed, 68 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/power/ti-smartreflex.txt
> 
> diff --git a/Documentation/devicetree/bindings/power/ti-smartreflex.txt b/Documentation/devicetree/bindings/power/ti-smartreflex.txt
> new file mode 100644
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/power/ti-smartreflex.txt
> @@ -0,0 +1,47 @@
> +Texas Instruments SmartReflex binding
> +
> +SmartReflex is used to set and adjust the SoC operating points.
> +
> +
> +Required properties:
> +
> +compatible: Shall be one of the following:
> +	    "ti,omap3-smartreflex-core"
> +	    "ti,omap3-smartreflex-iva"
> +	    "ti,omap4-smartreflex-core"
> +	    "ti,omap4-smartreflex-mpu"
> +	    "ti,omap4-smartreflex-iva"
> +
> +reg: Shall contain the device instance IO range
> +
> +interrupts: Shall contain the device instance interrupt
> +
> +
> +Optional properties:
> +
> +ti,hwmods: Shall contain the TI interconnect module name if needed
> +	   by the SoC
> +
> +
> +Example:
> +
> +	smartreflex_iva: smartreflex@4a0db000 {
> +		compatible = "ti,omap4-smartreflex-iva";
> +		reg = <0x4a0db000 0x80>;
> +		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
> +		ti,hwmods = "smartreflex_iva";
> +	};
> +
> +	smartreflex_core: smartreflex4a0dd000 {
                                     ^ missing '@'

> +		compatible = "ti,omap4-smartreflex-core";
> +		reg = <0x4a0dd000 0x80>;
> +		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> +		ti,hwmods = "smartreflex_core";
> +	};
> +
> +	smartreflex_mpu: smartreflex@4a0d9000 {
> +		compatible = "ti,omap4-smartreflex-mpu";
> +		reg = <0x4a0d9000 0x80>;
> +		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> +		ti,hwmods = "smartreflex_mpu";
> +	};
> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> --- a/arch/arm/boot/dts/omap4.dtsi
> +++ b/arch/arm/boot/dts/omap4.dtsi
> @@ -442,6 +442,27 @@
>  			clock-frequency = <48000000>;
>  		};
>  
> +		smartreflex_iva: smartreflex@4a0db000 {
> +			compatible = "ti,omap4-smartreflex-iva";
> +			reg = <0x4a0db000 0x80>;
> +			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
> +			ti,hwmods = "smartreflex_iva";
> +		};
> +
> +		smartreflex_core: smartreflex4a0dd000 {

Ditto. Build with W=2 and you should get a warning here.

With that fixed,

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>

> +			compatible = "ti,omap4-smartreflex-core";
> +			reg = <0x4a0dd000 0x80>;
> +			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> +			ti,hwmods = "smartreflex_core";
> +		};
> +
> +		smartreflex_mpu: smartreflex@4a0d9000 {
> +			compatible = "ti,omap4-smartreflex-mpu";
> +			reg = <0x4a0d9000 0x80>;
> +			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> +			ti,hwmods = "smartreflex_mpu";
> +		};
> +
>  		hwspinlock: spinlock@4a0f6000 {
>  			compatible = "ti,omap4-hwspinlock";
>  			reg = <0x4a0f6000 0x1000>;
> -- 
> 2.14.1
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Re: [PATCH 06/17] ARM: dts: Add missing slimbus node and binding for omap4

[Rob Herring]

On Wed, Aug 30, 2017 at 08:19:42AM -0700, Tony Lindgren wrote:
> On omap4 we're missing the slimbus node and it's related
> "ti,hwmods" property that the SoC interconnect code needs.
> 
> Note that this will only show up as a bug with "doesn't have
> mpu register target base" boot errors when the legacy platform
> data is removed.
> 
> Let's also add the missing slimbus device tree binding
> documentation while at it.
> 
> Cc: Liam Girdwood <lgirdwood-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Peter Ujfalusi <peter.ujfalusi-l0cyMroinI0@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
> ---
>  .../devicetree/bindings/sound/ti-slimbus.txt       | 34 ++++++++++++++++++++++
>  arch/arm/boot/dts/omap4.dtsi                       | 17 +++++++++++
>  2 files changed, 51 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/sound/ti-slimbus.txt
> 
> diff --git a/Documentation/devicetree/bindings/sound/ti-slimbus.txt b/Documentation/devicetree/bindings/sound/ti-slimbus.txt
> new file mode 100644
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sound/ti-slimbus.txt
> @@ -0,0 +1,34 @@
> +Texas Instruments Serial Low-power Inter-chip Media Bus (SLIMbus) binding
> +
> +SLIMbus is used for communication between digital audio components and the SoC.
> +
> +
> +Required properties:
> +
> +compatible: Shall be one of the following:
> +	    "ti,omap4-slimbus"
> +
> +reg: Shall contain the device instance IO range

If there's more than 1, you need to state how many.

> +
> +interrupts: Shall contain the device instance interrupt
> +
> +
> +Optional properties:
> +
> +reg-names: Shall contain the IO range names if multiple IO
> +	   ranges are used by the SoC

Need to define what the names are.

> +
> +ti,hwmods: Shall contain the TI interconnect module name if needed
> +	   by the SoC
> +
> +
> +Example:
> +
> +	slimbus1: slimbus@4012c000 {
> +		compatible = "ti,omap4-slimbus";
> +		reg = <0x4012c000 0x400>, /* MPU private access */
> +		      <0x4902c000 0x400>; /* L3 Interconnect */
> +		reg-names = "mpu", "dma";
> +		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
> +		ti,hwmods = "slimbus1";
> +	};
> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> --- a/arch/arm/boot/dts/omap4.dtsi
> +++ b/arch/arm/boot/dts/omap4.dtsi
> @@ -382,6 +382,14 @@
>  			#interrupt-cells = <2>;
>  		};
>  
> +		slimbus2: slimbus@48076000 {
> +			compatible = "ti,omap4-slimbus";
> +			reg = <0x48076000 0x400>;
> +			reg-names = "mpu";
> +			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> +			ti,hwmods = "slimbus2";
> +		};
> +
>  		elm: elm@48078000 {
>  			compatible = "ti,am3352-elm";
>  			reg = <0x48078000 0x2000>;
> @@ -711,6 +719,15 @@
>  			status = "disabled";
>  		};
>  
> +		slimbus1: slimbus@4012c000 {
> +			compatible = "ti,omap4-slimbus";
> +			reg = <0x4012c000 0x400>, /* MPU private access */
> +			      <0x4902c000 0x400>; /* L3 Interconnect */
> +			reg-names = "mpu", "dma";
> +			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
> +			ti,hwmods = "slimbus1";
> +		};
> +
>  		mcbsp4: mcbsp@48096000 {
>  			compatible = "ti,omap4-mcbsp";
>  			reg = <0x48096000 0xff>; /* L4 Interconnect */
> -- 
> 2.14.1
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Re: [PATCH 08/17] ARM: dts: Add missing hsi node for omap4

[Rob Herring]

On Wed, Aug 30, 2017 at 08:19:44AM -0700, Tony Lindgren wrote:
> On omap4 we're missing the hsi node with it's related "ti,hwmods"
> property that the SoC interconnect code needs.
> 
> Note that this will only show up as a bug with "doesn't have
> mpu register target base" boot errors when the legacy platform
> data is removed.
> 
> Let's also update the binding accrodingly while at it.
> 
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Sebastian Reichel <sre-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/hsi/omap-ssi.txt |  7 ++++-
>  arch/arm/boot/dts/omap4.dtsi                       | 34 ++++++++++++++++++++++
>  2 files changed, 40 insertions(+), 1 deletion(-)

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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Re: [PATCH 09/17] ARM: dts: Add missing iss node and binding for omap4

[Rob Herring]

On Wed, Aug 30, 2017 at 08:19:45AM -0700, Tony Lindgren wrote:
> On omap4 we're missing the iss node with it's related "ti,hwmods"
> property that the SoC interconnect code needs.
> 
> Note that this will only show up as a bug with "doesn't have
> mpu register target base" boot errors when the legacy platform
> data is removed.
> 
> Cc: Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Mauro Carvalho Chehab <mchehab-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Sakari Ailus <sakari.ailus-X3B1VOXEql0@public.gmane.org>
> Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/media/ti-iss.txt | 33 ++++++++++++++++++++++
>  arch/arm/boot/dts/omap4.dtsi                       |  7 +++++
>  2 files changed, 40 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/media/ti-iss.txt
> 
> diff --git a/Documentation/devicetree/bindings/media/ti-iss.txt b/Documentation/devicetree/bindings/media/ti-iss.txt
> new file mode 100644
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/ti-iss.txt
> @@ -0,0 +1,33 @@
> +Texas Instruments Imaging Subsystem (ISS) binding
> +
> +ISS is used for cameras on Texas Instruments SoCs. Note that this
> +binding is still missing the connections to the external devices
> +modeled for the driver.
> +
> +Required properties:
> +
> +compatible: Shall be one of the following:
> +	    "ti,omap4-iss"
> +
> +reg: Shall contain the device instance IO range
> +
> +interrupts: Shall contain the device instance interrupt
> +
> +
> +Optional properties:
> +
> +reg-names: Shall contain the IO range names if multiple IO
> +	   ranges are used by the SoC

Need to define how many. *-names is pointless if there's only ever 1 
entry.

> +
> +ti,hwmods: Shall contain the TI interconnect module name if needed
> +	   by the SoC
> +
> +
> +Example:
> +
> +	iss: iss@52000000 {
> +		compatible = "ti,omap4-iss";
> +		reg = <0x52000000 0x1000000>;
> +		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> +		ti,hwmods = "iss";
> +	};
> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> --- a/arch/arm/boot/dts/omap4.dtsi
> +++ b/arch/arm/boot/dts/omap4.dtsi
> @@ -674,6 +674,13 @@
>  			#iommu-cells = <0>;
>  		};
>  
> +		iss: iss@52000000 {
> +			compatible = "ti,omap4-iss";
> +			reg = <0x52000000 0x1000000>;
> +			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> +			ti,hwmods = "iss";
> +		};
> +
>  		mmu_ipu: mmu@55082000 {
>  			compatible = "ti,omap4-iommu";
>  			reg = <0x55082000 0x100>;
> -- 
> 2.14.1
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Re: [PATCH 13/17] ARM: dts: Add missing fdif node and binding for omap4

[Rob Herring]

On Wed, Aug 30, 2017 at 08:19:49AM -0700, Tony Lindgren wrote:
> On omap4 we're missing the fdif node with it's related "ti,hwmods"
> property that the SoC interconnect code needs.
> 
> Note that this will only show up as a bug with "doesn't have
> mpu register target base" boot errors when the legacy platform
> data is removed.
> 
> Cc: Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Mauro Carvalho Chehab <mchehab-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Sakari Ailus <sakari.ailus-X3B1VOXEql0@public.gmane.org>
> Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
> ---
>  .../devicetree/bindings/media/ti-fdif.txt          | 29 ++++++++++++++++++++++
>  arch/arm/boot/dts/omap4.dtsi                       |  7 ++++++
>  2 files changed, 36 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/media/ti-fdif.txt

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for omap4

[Rob Herring]

On Wed, Aug 30, 2017 at 08:19:50AM -0700, Tony Lindgren wrote:
> On omap4 we're missing the PowerVR SGX GPU node with it's related
> "ti,hwmods" property that the SoC interconnect code needs.
> 
> Note that this will only show up as a bug with "doesn't have
> mpu register target base" boot errors when the legacy platform
> data is removed.
> 
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Tomi Valkeinen <tomi.valkeinen-l0cyMroinI0@public.gmane.org>
> Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
> ---
>  .../devicetree/bindings/gpu/ti-powervr-sgx.txt     | 39 ++++++++++++++++++++++

While the compatible strings should be TI specific, the doc shouldn't 
be. 

>  arch/arm/boot/dts/omap4.dtsi                       |  7 ++++
>  2 files changed, 46 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/gpu/ti-powervr-sgx.txt
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Re: [PATCH 16/17] ARM: dts: Add missing hwmod related nodes for am33xx

[Rob Herring]

On Wed, Aug 30, 2017 at 08:19:52AM -0700, Tony Lindgren wrote:
> On am33xx we're missing the pmu and emif nodes with their related
> "ti,hwmods" properties that the SoC interconnect code needs.
> 
> Note that this will only show up as a bug with "doesn't have
> mpu register target base" boot errors when the legacy platform
> data is removed.
> 
> Let's also update the related binding documentation while at it.
> 
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
> ---
>  .../devicetree/bindings/memory-controllers/ti/emif.txt         |  6 ++++--
>  arch/arm/boot/dts/am33xx.dtsi                                  | 10 +++++++++-
>  2 files changed, 13 insertions(+), 3 deletions(-)

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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Re: [PATCH 08/17] ARM: dts: Add missing hsi node for omap4

[Sebastian Reichel]

[-- Attachment #1: Type: text/plain, Size: 4453 bytes --]

Hi,

On Wed, Aug 30, 2017 at 01:25:20PM -0700, Tony Lindgren wrote:
> Thanks, updated patch below.

Thanks, I applied the DT binding part to the HSI subsystem:

https://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-hsi.git/commit/?h=for-next&id=8635d6b3afe68cdde2f646c2a3bbd8149c031e8c

-- Sebastian

> 8< --------------------
> From tony Mon Sep 17 00:00:00 2001
> From: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
> Date: Wed, 30 Aug 2017 08:07:51 -0700
> Subject: [PATCH] ARM: dts: Add missing hsi node for omap4
> 
> On omap4 we're missing the hsi node with it's related "ti,hwmods"
> property that the SoC interconnect code needs.
> 
> Note that this will only show up as a bug with "doesn't have
> mpu register target base" boot errors when the legacy platform
> data is removed.
> 
> Let's also update the binding accrodingly while at it.
> 
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Reviewed-by: Sebastian Reichel <sre-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/hsi/omap-ssi.txt | 13 +++++++--
>  arch/arm/boot/dts/omap4.dtsi                       | 34 ++++++++++++++++++++++
>  2 files changed, 44 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/hsi/omap-ssi.txt b/Documentation/devicetree/bindings/hsi/omap-ssi.txt
> --- a/Documentation/devicetree/bindings/hsi/omap-ssi.txt
> +++ b/Documentation/devicetree/bindings/hsi/omap-ssi.txt
> @@ -1,10 +1,12 @@
>  OMAP SSI controller bindings
>  
> -OMAP Synchronous Serial Interface (SSI) controller implements a legacy
> -variant of MIPI's High Speed Synchronous Serial Interface (HSI).
> +OMAP3's Synchronous Serial Interface (SSI) controller implements a
> +legacy variant of MIPI's High Speed Synchronous Serial Interface (HSI),
> +while the controller found inside OMAP4 is supposed to be fully compliant
> +with the HSI standard.
>  
>  Required properties:
> -- compatible:		Should include "ti,omap3-ssi".
> +- compatible:		Should include "ti,omap3-ssi" or "ti,omap4-hsi"
>  - reg-names:		Contains the values "sys" and "gdd" (in this order).
>  - reg:			Contains a matching register specifier for each entry
>  			in reg-names.
> @@ -27,6 +29,7 @@ Each port is represented as a sub-node of the ti,omap3-ssi device.
>  Required Port sub-node properties:
>  - compatible:		Should be set to the following value
>  			ti,omap3-ssi-port (applicable to OMAP34xx devices)
> +			ti,omap4-hsi-port (applicable to OMAP44xx devices)
>  - reg-names:		Contains the values "tx" and "rx" (in this order).
>  - reg:			Contains a matching register specifier for each entry
>  			in reg-names.
> @@ -38,6 +41,10 @@ Required Port sub-node properties:
>  			property. If it's missing the port will not be
>  			enabled.
>  
> +Optional properties:
> +- ti,hwmods:		Shall contain TI interconnect module name if needed
> +			by the SoC
> +
>  Example for Nokia N900:
>  
>  ssi-controller@48058000 {
> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> --- a/arch/arm/boot/dts/omap4.dtsi
> +++ b/arch/arm/boot/dts/omap4.dtsi
> @@ -632,6 +632,40 @@
>  			dma-names = "tx", "rx";
>  		};
>  
> +		hsi: hsi@4a058000 {
> +			compatible = "ti,omap4-hsi";
> +			reg = <0x4a058000 0x4000>,
> +			      <0x4a05c000 0x1000>;
> +			reg-names = "sys", "gdd";
> +			ti,hwmods = "hsi";
> +
> +			clocks = <&hsi_fck>;
> +			clock-names = "hsi_fck";
> +
> +			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "gdd_mpu";
> +
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0 0x4a058000 0x4000>;
> +
> +			hsi_port1: hsi-port@2000 {
> +				compatible = "ti,omap4-hsi-port";
> +				reg = <0x2000 0x800>,
> +				      <0x2800 0x800>;
> +				reg-names = "tx", "rx";
> +				interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			hsi_port2: hsi-port@3000 {
> +				compatible = "ti,omap4-hsi-port";
> +				reg = <0x3000 0x800>,
> +				      <0x3800 0x800>;
> +				reg-names = "tx", "rx";
> +				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
>  		mmu_dsp: mmu@4a066000 {
>  			compatible = "ti,omap4-iommu";
>  			reg = <0x4a066000 0x100>;
> -- 
> 2.14.1

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Re: [PATCH 08/17] ARM: dts: Add missing hsi node for omap4

[Tony Lindgren]

* Sebastian Reichel <sre-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> [171001 08:26]:
> Hi,
> 
> On Wed, Aug 30, 2017 at 01:25:20PM -0700, Tony Lindgren wrote:
> > Thanks, updated patch below.
> 
> Thanks, I applied the DT binding part to the HSI subsystem:
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-hsi.git/commit/?h=for-next&id=8635d6b3afe68cdde2f646c2a3bbd8149c031e8c

OK thanks.

Tony
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Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for omap4

[Adam Ford]

On Mon, Sep 11, 2017 at 4:50 PM, Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> On Wed, Aug 30, 2017 at 08:19:50AM -0700, Tony Lindgren wrote:
>> On omap4 we're missing the PowerVR SGX GPU node with it's related
>> "ti,hwmods" property that the SoC interconnect code needs.
>>
>> Note that this will only show up as a bug with "doesn't have
>> mpu register target base" boot errors when the legacy platform
>> data is removed.
>>
>> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
>> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>> Cc: Tomi Valkeinen <tomi.valkeinen-l0cyMroinI0@public.gmane.org>
>> Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
>> ---

Out of curiosity, is anything being done with this?  I'm really
interested to see the PVR working in a modern kernel.  I'd like to
help more, but I am afraid I don't fully understand the interconnects
and how the driver componenets interact with the omap processor.

Please let me know if there are sub-tasks that I can assist.

adam

>>  .../devicetree/bindings/gpu/ti-powervr-sgx.txt     | 39 ++++++++++++++++++++++
>
> While the compatible strings should be TI specific, the doc shouldn't
> be.
>
>>  arch/arm/boot/dts/omap4.dtsi                       |  7 ++++
>>  2 files changed, 46 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/gpu/ti-powervr-sgx.txt
> --
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Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for omap4

[Tony Lindgren]

* Adam Ford <aford173-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> [171202 00:20]:
> On Mon, Sep 11, 2017 at 4:50 PM, Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> > On Wed, Aug 30, 2017 at 08:19:50AM -0700, Tony Lindgren wrote:
> >> On omap4 we're missing the PowerVR SGX GPU node with it's related
> >> "ti,hwmods" property that the SoC interconnect code needs.
> >>
> >> Note that this will only show up as a bug with "doesn't have
> >> mpu register target base" boot errors when the legacy platform
> >> data is removed.
> >>
> >> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> >> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> >> Cc: Tomi Valkeinen <tomi.valkeinen-l0cyMroinI0@public.gmane.org>
> >> Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
> >> ---
> 
> Out of curiosity, is anything being done with this?  I'm really
> interested to see the PVR working in a modern kernel.  I'd like to
> help more, but I am afraid I don't fully understand the interconnects
> and how the driver componenets interact with the omap processor.
> 
> Please let me know if there are sub-tasks that I can assist.

Well the powervr node should use a powervr generic binding that
does not yet exist. I think the TI tree binding could be easily
modified for a generic binding. So first doing a binding patch
for powervr and Cc dt list and SoC maintainers with powervr on
them would help.

And then eventually the powervr generic node should be a child
node under the "target-module" node in the dtsi file. See what
we have for gpu target-module@56000000 in omap4.dtsi.

Note that the interconnect target module does not yet work for
omap3 as the clocks are different. I'll be posting patches for
the clocks over next few weeks.

Regards,

Tony
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Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for omap4

[Tony Lindgren]

* Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org> [170829 08:58]:
> * Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org> [170829 07:35]:
> > * Tomi Valkeinen <tomi.valkeinen-l0cyMroinI0@public.gmane.org> [170829 05:25]:
> > > Maybe. At the moment we have this in TI's tree for DRA7:
> > > 
> > > gpu: gpu@56000000 {
> > > 	compatible = "ti,dra7-sgx544", "img,sgx544";
> 
> I'll leave out "img,sgx544" as that's the generic component
> that's really a child of this interconnect target module.

And for the gpu clock, on omap4, it seems that the clocks
are just the module clktrl with a mux option. So the top
level module driver implementing runtime PM should be
enough there. And on dra7, there are two functional clocks
maybe as the SGX instance is dual core. And the mainline
kernel is using "fck" naming vs "fclk" naming. So more
consideration is for the clocks and I'll leave them out
for now.

Regards,

Tony
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Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for omap4

[Tony Lindgren]

* Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org> [170829 07:35]:
> * Tomi Valkeinen <tomi.valkeinen-l0cyMroinI0@public.gmane.org> [170829 05:25]:
> > Maybe. At the moment we have this in TI's tree for DRA7:
> > 
> > gpu: gpu@56000000 {
> > 	compatible = "ti,dra7-sgx544", "img,sgx544";

I'll leave out "img,sgx544" as that's the generic component
that's really a child of this interconnect target module.

Regards,

Tony
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Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for omap4

[Tony Lindgren]

* Adam Ford <aford173-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> [170829 08:31]:
> On Tue, Aug 29, 2017 at 9:42 AM, Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org> wrote:
> > * Sebastian Reichel <sebastian.reichel-ZGY8ohtN/8pPYcu2f3hruQ@public.gmane.org> [170829 02:01]:
> >> Hi,
> >>
> >> On Mon, Aug 28, 2017 at 02:19:15PM -0700, Tony Lindgren wrote:
> >> > On omap4 we're missing the PowerVR SGX GPU node with it's related
> >> > "ti,hwmods" property that the SoC interconnect code needs.
> >> >
> >> > Note that this will only show up as a bug with "doesn't have
> >> > mpu register target base" boot errors when the legacy platform
> >> > data is removed.
> >>
> >> I think OMAP3 & OMAP5 should also be documented and getting a
> >> node in this series?
> >
> > Looks like we don't currently have any interconnect data defined
> > for those, but yeah sure I can add those.
> >
> 
> If there is anything I can test, I had modified the SGX driver for the
> OMAP36, but abandoned my attempts since much of the device tree and
> reset stuff was missing.  I'd love to see SGX work again.  :-)

Well the resets can be handled using platform data callbacks
for now with pdata-quirks.c. Then when the reset driver is available,
we can just remove the platform data.

And maybe push your changes to some tree so others can participate?
I'm sure the n900 users would like to see it working too.

Regards,

Tony
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Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for omap4

[Adam Ford]

On Tue, Aug 29, 2017 at 9:42 AM, Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org> wrote:
> * Sebastian Reichel <sebastian.reichel-ZGY8ohtN/8pPYcu2f3hruQ@public.gmane.org> [170829 02:01]:
>> Hi,
>>
>> On Mon, Aug 28, 2017 at 02:19:15PM -0700, Tony Lindgren wrote:
>> > On omap4 we're missing the PowerVR SGX GPU node with it's related
>> > "ti,hwmods" property that the SoC interconnect code needs.
>> >
>> > Note that this will only show up as a bug with "doesn't have
>> > mpu register target base" boot errors when the legacy platform
>> > data is removed.
>>
>> I think OMAP3 & OMAP5 should also be documented and getting a
>> node in this series?
>
> Looks like we don't currently have any interconnect data defined
> for those, but yeah sure I can add those.
>

If there is anything I can test, I had modified the SGX driver for the
OMAP36, but abandoned my attempts since much of the device tree and
reset stuff was missing.  I'd love to see SGX work again.  :-)

adam

> Regards,
>
> Tony
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Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for omap4

[Tony Lindgren]

* Sebastian Reichel <sebastian.reichel-ZGY8ohtN/8pPYcu2f3hruQ@public.gmane.org> [170829 02:01]:
> Hi,
> 
> On Mon, Aug 28, 2017 at 02:19:15PM -0700, Tony Lindgren wrote:
> > On omap4 we're missing the PowerVR SGX GPU node with it's related
> > "ti,hwmods" property that the SoC interconnect code needs.
> > 
> > Note that this will only show up as a bug with "doesn't have
> > mpu register target base" boot errors when the legacy platform
> > data is removed.
> 
> I think OMAP3 & OMAP5 should also be documented and getting a
> node in this series?

Looks like we don't currently have any interconnect data defined
for those, but yeah sure I can add those.

Regards,

Tony
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Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for omap4

[Tony Lindgren]

* Tomi Valkeinen <tomi.valkeinen-l0cyMroinI0@public.gmane.org> [170829 05:28]:
> 
> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
> 
> On 29/08/17 15:10, Sebastian Reichel wrote:
> 
> >> Do we even want to add SGX to the .dts? We don't have proper drivers for
> >> SGX. If we ever do, who knows what kind of DT data they need. I know the
> >> DT data for SGX in TI's kernel tree has changed at least once.
> > 
> > I don't think reg or interrupts will be removed, so the properties
> > added by Tony look pretty safe?. I guess if we ever have a driver
> 
> Oh, and one more thing about the regs. I believe SGX consists of
> multiple register blocks. But as it's not documented in any public docs,
> there's just that single block in the DT data. I'm not sure if single
> block or multiple blocks would be the right approach, but then, I guess
> we can always live with just a single block and if needed split the
> blocks inside the driver.

OK, those register blocks can easily be child nodes of the module
if needed. This is for the parent interconnect target module
revc/sysc/syss registers that we already have mapped in legacy
platform data for the interconnect code.

Regards,

Tony
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Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for omap4

[Tony Lindgren]

* Tomi Valkeinen <tomi.valkeinen-l0cyMroinI0@public.gmane.org> [170829 05:25]:
> 
> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
> 
> On 29/08/17 15:10, Sebastian Reichel wrote:
> 
> >> Do we even want to add SGX to the .dts? We don't have proper drivers for
> >> SGX. If we ever do, who knows what kind of DT data they need. I know the
> >> DT data for SGX in TI's kernel tree has changed at least once.
> > 
> > I don't think reg or interrupts will be removed, so the properties
> > added by Tony look pretty safe?. I guess if we ever have a driver
> 
> Maybe. At the moment we have this in TI's tree for DRA7:
> 
> gpu: gpu@56000000 {
> 	compatible = "ti,dra7-sgx544", "img,sgx544";
> 	reg = <0x56000000 0x10000>;
> 	reg-names = "gpu_ocp_base";
> 	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> 	ti,hwmods = "gpu";
> 	clocks = <&l3_iclk_div>, <&gpu_core_gclk_mux>,
> 		<&gpu_hyd_gclk_mux>;
> 	clock-names = "iclk", "fclk1", "fclk2";
> };
> 
> > it would need some more properties and would bail out. Having no
> > DT data is does not load at all, the result is the same. OTOH having
> > the node means the kernel can properly send the module to idle.
> 
> I just get uneasy when adding DT data that we're not really sure if it's
> ok or not. I've been fighting with such data for ages. But, as you say,
> this probably won't matter if the driver will just reject DT data that
> doesn't have all the details.

The above example looks OK to me, the interrupt is different for omap4.

> If we need the DT node to idle SGX, and we don't even mean to actually
> use an SGX driver with this data, it sounds fine to me.

Well ideally the SGX driver will make use of it too. Let me know
if you want to leave out some parts of the above example from
TI tree.

Regards,

Tony
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Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for omap4

[Tomi Valkeinen]


Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

On 29/08/17 15:10, Sebastian Reichel wrote:

>> Do we even want to add SGX to the .dts? We don't have proper drivers for
>> SGX. If we ever do, who knows what kind of DT data they need. I know the
>> DT data for SGX in TI's kernel tree has changed at least once.
> 
> I don't think reg or interrupts will be removed, so the properties
> added by Tony look pretty safe?. I guess if we ever have a driver

Oh, and one more thing about the regs. I believe SGX consists of
multiple register blocks. But as it's not documented in any public docs,
there's just that single block in the DT data. I'm not sure if single
block or multiple blocks would be the right approach, but then, I guess
we can always live with just a single block and if needed split the
blocks inside the driver.

 Tomi

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Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for omap4

[Tomi Valkeinen]


Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

On 29/08/17 15:10, Sebastian Reichel wrote:

>> Do we even want to add SGX to the .dts? We don't have proper drivers for
>> SGX. If we ever do, who knows what kind of DT data they need. I know the
>> DT data for SGX in TI's kernel tree has changed at least once.
> 
> I don't think reg or interrupts will be removed, so the properties
> added by Tony look pretty safe?. I guess if we ever have a driver

Maybe. At the moment we have this in TI's tree for DRA7:

gpu: gpu@56000000 {
	compatible = "ti,dra7-sgx544", "img,sgx544";
	reg = <0x56000000 0x10000>;
	reg-names = "gpu_ocp_base";
	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	ti,hwmods = "gpu";
	clocks = <&l3_iclk_div>, <&gpu_core_gclk_mux>,
		<&gpu_hyd_gclk_mux>;
	clock-names = "iclk", "fclk1", "fclk2";
};

> it would need some more properties and would bail out. Having no
> DT data is does not load at all, the result is the same. OTOH having
> the node means the kernel can properly send the module to idle.

I just get uneasy when adding DT data that we're not really sure if it's
ok or not. I've been fighting with such data for ages. But, as you say,
this probably won't matter if the driver will just reject DT data that
doesn't have all the details.

If we need the DT node to idle SGX, and we don't even mean to actually
use an SGX driver with this data, it sounds fine to me.

 Tomi

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Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for omap4

[Sebastian Reichel]

[-- Attachment #1: Type: text/plain, Size: 2164 bytes --]

Hi,

On Tue, Aug 29, 2017 at 02:35:09PM +0300, Tomi Valkeinen wrote:
> This message contains a digitally signed email which can be read by opening the attachment.
> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

> Date: Tue, 29 Aug 2017 14:35:09 +0300
> From: Tomi Valkeinen <tomi.valkeinen-l0cyMroinI0@public.gmane.org>
> To: Sebastian Reichel <sebastian.reichel-ZGY8ohtN/8pPYcu2f3hruQ@public.gmane.org>, Tony Lindgren
>  <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
> CC: linux-omap-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Benoît Cousson <bcousson-rdvid1DuHRDQFizaE/u3fw@public.gmane.orgm>,
>  devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Subject: Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for
>  omap4
> 
> On 29/08/17 12:00, Sebastian Reichel wrote:
> > Hi,
> > 
> > On Mon, Aug 28, 2017 at 02:19:15PM -0700, Tony Lindgren wrote:
> >> On omap4 we're missing the PowerVR SGX GPU node with it's related
> >> "ti,hwmods" property that the SoC interconnect code needs.
> >>
> >> Note that this will only show up as a bug with "doesn't have
> >> mpu register target base" boot errors when the legacy platform
> >> data is removed.
> >>
> >> Cc: Tomi Valkeinen <tomi.valkeinen-l0cyMroinI0@public.gmane.org>
> >> Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
> >> ---
> > 
> > I think OMAP3 & OMAP5 should also be documented and getting a
> > node in this series?
> 
> Do we even want to add SGX to the .dts? We don't have proper drivers for
> SGX. If we ever do, who knows what kind of DT data they need. I know the
> DT data for SGX in TI's kernel tree has changed at least once.

I don't think reg or interrupts will be removed, so the properties
added by Tony look pretty safe?. I guess if we ever have a driver
it would need some more properties and would bail out. Having no
DT data is does not load at all, the result is the same. OTOH having
the node means the kernel can properly send the module to idle.

I think this patchset should Cc Rob and Mark. 

-- Sebastian

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Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for omap4

[Tomi Valkeinen]

[-- Attachment #1: Type: text/plain, Size: 228 bytes --]

This message contains a digitally signed email which can be read by opening the attachment.
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki



[-- Attachment #2: Type: message/rfc822, Size: 4893 bytes --]

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On 29/08/17 12:00, Sebastian Reichel wrote:
> Hi,
> 
> On Mon, Aug 28, 2017 at 02:19:15PM -0700, Tony Lindgren wrote:
>> On omap4 we're missing the PowerVR SGX GPU node with it's related
>> "ti,hwmods" property that the SoC interconnect code needs.
>>
>> Note that this will only show up as a bug with "doesn't have
>> mpu register target base" boot errors when the legacy platform
>> data is removed.
>>
>> Cc: Tomi Valkeinen <tomi.valkeinen-l0cyMroinI0@public.gmane.org>
>> Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
>> ---
> 
> I think OMAP3 & OMAP5 should also be documented and getting a
> node in this series?

Do we even want to add SGX to the .dts? We don't have proper drivers for
SGX. If we ever do, who knows what kind of DT data they need. I know the
DT data for SGX in TI's kernel tree has changed at least once.

 Tomi


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Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for omap4

[Sebastian Reichel]

[-- Attachment #1: Type: text/plain, Size: 2905 bytes --]

Hi,

On Mon, Aug 28, 2017 at 02:19:15PM -0700, Tony Lindgren wrote:
> On omap4 we're missing the PowerVR SGX GPU node with it's related
> "ti,hwmods" property that the SoC interconnect code needs.
> 
> Note that this will only show up as a bug with "doesn't have
> mpu register target base" boot errors when the legacy platform
> data is removed.
> 
> Cc: Tomi Valkeinen <tomi.valkeinen-l0cyMroinI0@public.gmane.org>
> Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
> ---

I think OMAP3 & OMAP5 should also be documented and getting a
node in this series?

-- Sebastian

>  .../devicetree/bindings/gpu/ti-powervr-sgx.txt     | 34 ++++++++++++++++++++++
>  arch/arm/boot/dts/omap4.dtsi                       |  7 +++++
>  2 files changed, 41 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/gpu/ti-powervr-sgx.txt
> 
> diff --git a/Documentation/devicetree/bindings/gpu/ti-powervr-sgx.txt b/Documentation/devicetree/bindings/gpu/ti-powervr-sgx.txt
> new file mode 100644
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpu/ti-powervr-sgx.txt
> @@ -0,0 +1,34 @@
> +Texas Instruments PowevVR SGX binding
> +
> +SGX can be used for graphics acceleration on Texas Instruments SoCs.
> +
> +Note that the SGX binding is currently only used by the SoC interconnect
> +code to idle the module on init and no open source driver is available
> +for SGX. Please update this documentation if that changes.
> +
> +Required properties:
> +
> +compatible: Shall be one of the following:
> +	    "ti,omap4-gpu"
> +
> +reg: Shall contain the device instance IO range
> +
> +interrupts: Shall contain the device instance interrupt
> +
> +
> +Optional properties:
> +
> +reg-names: Shall contain the IO range names if multiple IO
> +	   ranges are used by the SoC
> +
> +ti,hwmods: Shall contain the TI interconnect module name if needed
> +	   by the SoC
> +
> +
> +Example:
> +	gpu: gpu@56000000 {
> +		compatible = "ti,omap4-gpu";
> +		reg = <0x56000000 0x10000>;
> +		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> +		ti,hwmods = "gpu";
> +	};
> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> --- a/arch/arm/boot/dts/omap4.dtsi
> +++ b/arch/arm/boot/dts/omap4.dtsi
> @@ -1086,6 +1086,13 @@
>  			status = "disabled";
>  		};
>  
> +		gpu: gpu@56000000 {
> +			compatible = "ti,omap4-gpu";
> +			reg = <0x56000000 0x10000>;
> +			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> +			ti,hwmods = "gpu";
> +		};
> +
>  		dss: dss@58000000 {
>  			compatible = "ti,omap4-dss";
>  			reg = <0x58000000 0x80>;
> -- 
> 2.14.1
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[PATCH 14/17] ARM: dts: Add missing gpu node and binding for omap4

[Tony Lindgren]

On omap4 we're missing the PowerVR SGX GPU node with it's related
"ti,hwmods" property that the SoC interconnect code needs.

Note that this will only show up as a bug with "doesn't have
mpu register target base" boot errors when the legacy platform
data is removed.

Cc: Tomi Valkeinen <tomi.valkeinen-l0cyMroinI0@public.gmane.org>
Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
 .../devicetree/bindings/gpu/ti-powervr-sgx.txt     | 34 ++++++++++++++++++++++
 arch/arm/boot/dts/omap4.dtsi                       |  7 +++++
 2 files changed, 41 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/gpu/ti-powervr-sgx.txt

diff --git a/Documentation/devicetree/bindings/gpu/ti-powervr-sgx.txt b/Documentation/devicetree/bindings/gpu/ti-powervr-sgx.txt
new file mode 100644
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/ti-powervr-sgx.txt
@@ -0,0 +1,34 @@
+Texas Instruments PowevVR SGX binding
+
+SGX can be used for graphics acceleration on Texas Instruments SoCs.
+
+Note that the SGX binding is currently only used by the SoC interconnect
+code to idle the module on init and no open source driver is available
+for SGX. Please update this documentation if that changes.
+
+Required properties:
+
+compatible: Shall be one of the following:
+	    "ti,omap4-gpu"
+
+reg: Shall contain the device instance IO range
+
+interrupts: Shall contain the device instance interrupt
+
+
+Optional properties:
+
+reg-names: Shall contain the IO range names if multiple IO
+	   ranges are used by the SoC
+
+ti,hwmods: Shall contain the TI interconnect module name if needed
+	   by the SoC
+
+
+Example:
+	gpu: gpu@56000000 {
+		compatible = "ti,omap4-gpu";
+		reg = <0x56000000 0x10000>;
+		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+		ti,hwmods = "gpu";
+	};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -1086,6 +1086,13 @@
 			status = "disabled";
 		};
 
+		gpu: gpu@56000000 {
+			compatible = "ti,omap4-gpu";
+			reg = <0x56000000 0x10000>;
+			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+			ti,hwmods = "gpu";
+		};
+
 		dss: dss@58000000 {
 			compatible = "ti,omap4-dss";
 			reg = <0x58000000 0x80>;
-- 
2.14.1
--
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