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* [PATCH] drm/i915: Stop using long platform names on clock gating functions.
@ 2017-08-29  5:20 Rodrigo Vivi
  2017-08-29  5:45 ` ✓ Fi.CI.BAT: success for " Patchwork
                   ` (2 more replies)
  0 siblings, 3 replies; 5+ messages in thread
From: Rodrigo Vivi @ 2017-08-29  5:20 UTC (permalink / raw)
  To: intel-gfx; +Cc: Dhinakaran Pandiyan, Rodrigo Vivi

No functional changes.

Our code was only a bit messy with mixed style there so
let's clean up a bit using the short codenames for the platforms.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 44 ++++++++++++++++++++---------------------
 1 file changed, 22 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d5ff0b9f999f..4bdf1fb1df7e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7981,7 +7981,7 @@ static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
 	 */
 }
 
-static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv)
+static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
 
@@ -8264,7 +8264,7 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
 	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 }
 
-static void cannonlake_init_clock_gating(struct drm_i915_private *dev_priv)
+static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	/* This is not an Wa. Enable for better image quality */
 	I915_WRITE(_3D_CHICKEN3,
@@ -8285,7 +8285,7 @@ static void cannonlake_init_clock_gating(struct drm_i915_private *dev_priv)
 			   SARBUNIT_CLKGATE_DIS);
 }
 
-static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
+static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	gen9_init_clock_gating(dev_priv);
 
@@ -8304,7 +8304,7 @@ static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
 		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
 }
 
-static void skylake_init_clock_gating(struct drm_i915_private *dev_priv)
+static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	gen9_init_clock_gating(dev_priv);
 
@@ -8317,7 +8317,7 @@ static void skylake_init_clock_gating(struct drm_i915_private *dev_priv)
 		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
 }
 
-static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
+static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	enum pipe pipe;
 
@@ -8375,7 +8375,7 @@ static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
 		   I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
 }
 
-static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
+static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	ilk_init_lp_watermarks(dev_priv);
 
@@ -8429,7 +8429,7 @@ static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
 	lpt_init_clock_gating(dev_priv);
 }
 
-static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv)
+static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	uint32_t snpcr;
 
@@ -8526,7 +8526,7 @@ static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv)
 	gen6_check_mch_setup(dev_priv);
 }
 
-static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv)
+static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	/* WaDisableEarlyCull:vlv */
 	I915_WRITE(_3D_CHICKEN3,
@@ -8606,7 +8606,7 @@ static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv)
 	I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
 }
 
-static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv)
+static void chv_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	/* WaVSRefCountFullforceMissDisable:chv */
 	/* WaDSRefCountFullforceMissDisable:chv */
@@ -8666,7 +8666,7 @@ static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
 	g4x_disable_trickle_feed(dev_priv);
 }
 
-static void crestline_init_clock_gating(struct drm_i915_private *dev_priv)
+static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
 	I915_WRITE(RENCLK_GATE_D2, 0);
@@ -8680,7 +8680,7 @@ static void crestline_init_clock_gating(struct drm_i915_private *dev_priv)
 	I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
 }
 
-static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv)
+static void i965g_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
 		   I965_RCC_CLOCK_GATE_DISABLE |
@@ -8766,35 +8766,35 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
 	if (IS_CANNONLAKE(dev_priv))
-		dev_priv->display.init_clock_gating = cannonlake_init_clock_gating;
+		dev_priv->display.init_clock_gating = cnl_init_clock_gating;
 	else if (IS_SKYLAKE(dev_priv))
-		dev_priv->display.init_clock_gating = skylake_init_clock_gating;
+		dev_priv->display.init_clock_gating = skl_init_clock_gating;
 	else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
-		dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
+		dev_priv->display.init_clock_gating = kbl_init_clock_gating;
 	else if (IS_BROXTON(dev_priv))
 		dev_priv->display.init_clock_gating = bxt_init_clock_gating;
 	else if (IS_GEMINILAKE(dev_priv))
 		dev_priv->display.init_clock_gating = glk_init_clock_gating;
 	else if (IS_BROADWELL(dev_priv))
-		dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
+		dev_priv->display.init_clock_gating = bdw_init_clock_gating;
 	else if (IS_CHERRYVIEW(dev_priv))
-		dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
+		dev_priv->display.init_clock_gating = chv_init_clock_gating;
 	else if (IS_HASWELL(dev_priv))
-		dev_priv->display.init_clock_gating = haswell_init_clock_gating;
+		dev_priv->display.init_clock_gating = hsw_init_clock_gating;
 	else if (IS_IVYBRIDGE(dev_priv))
-		dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
+		dev_priv->display.init_clock_gating = ivb_init_clock_gating;
 	else if (IS_VALLEYVIEW(dev_priv))
-		dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
+		dev_priv->display.init_clock_gating = vlv_init_clock_gating;
 	else if (IS_GEN6(dev_priv))
 		dev_priv->display.init_clock_gating = gen6_init_clock_gating;
 	else if (IS_GEN5(dev_priv))
-		dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
+		dev_priv->display.init_clock_gating = ilk_init_clock_gating;
 	else if (IS_G4X(dev_priv))
 		dev_priv->display.init_clock_gating = g4x_init_clock_gating;
 	else if (IS_I965GM(dev_priv))
-		dev_priv->display.init_clock_gating = crestline_init_clock_gating;
+		dev_priv->display.init_clock_gating = i965gm_init_clock_gating;
 	else if (IS_I965G(dev_priv))
-		dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
+		dev_priv->display.init_clock_gating = i965g_init_clock_gating;
 	else if (IS_GEN3(dev_priv))
 		dev_priv->display.init_clock_gating = gen3_init_clock_gating;
 	else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
-- 
2.13.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Stop using long platform names on clock gating functions.
  2017-08-29  5:20 [PATCH] drm/i915: Stop using long platform names on clock gating functions Rodrigo Vivi
@ 2017-08-29  5:45 ` Patchwork
  2017-08-29  6:43 ` [PATCH] " Jani Nikula
  2017-08-29  7:12 ` ✗ Fi.CI.IGT: warning for " Patchwork
  2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2017-08-29  5:45 UTC (permalink / raw)
  To: Rodrigo Vivi; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Stop using long platform names on clock gating functions.
URL   : https://patchwork.freedesktop.org/series/29453/
State : success

== Summary ==

Series 29453v1 drm/i915: Stop using long platform names on clock gating functions.
https://patchwork.freedesktop.org/api/1.0/series/29453/revisions/1/mbox/

Test kms_cursor_legacy:
        Subgroup basic-busy-flip-before-cursor-atomic:
                fail       -> PASS       (fi-snb-2600) fdo#100215 +1
        Subgroup basic-flip-after-cursor-varying-size:
                fail       -> PASS       (fi-hsw-4770) fdo#102402 +1
Test kms_flip:
        Subgroup basic-flip-vs-modeset:
                skip       -> PASS       (fi-skl-x1585l) fdo#101781

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102402 https://bugs.freedesktop.org/show_bug.cgi?id=102402
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u     total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  time:455s
fi-bdw-gvtdvm    total:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  time:444s
fi-blb-e6850     total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  time:360s
fi-bsw-n3050     total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  time:555s
fi-bwr-2160      total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  time:254s
fi-bxt-j4205     total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:517s
fi-byt-j1900     total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  time:519s
fi-byt-n2820     total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  time:509s
fi-elk-e7500     total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  time:438s
fi-glk-2a        total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:609s
fi-hsw-4770      total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:448s
fi-hsw-4770r     total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:421s
fi-ilk-650       total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  time:430s
fi-ivb-3520m     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:510s
fi-ivb-3770      total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:474s
fi-kbl-7500u     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:477s
fi-kbl-7560u     total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:596s
fi-kbl-r         total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:606s
fi-pnv-d510      total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  time:521s
fi-skl-6260u     total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:466s
fi-skl-6700k     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:474s
fi-skl-6770hq    total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:489s
fi-skl-gvtdvm    total:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  time:445s
fi-skl-x1585l    total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:509s
fi-snb-2520m     total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  time:544s
fi-snb-2600      total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  time:407s

ee53909d971df42daac0b870cf7c091f45f1f6b9 drm-tip: 2017y-08m-28d-15h-03m-59s UTC integration manifest
ff16968a8d96 drm/i915: Stop using long platform names on clock gating functions.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5515/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915: Stop using long platform names on clock gating functions.
  2017-08-29  5:20 [PATCH] drm/i915: Stop using long platform names on clock gating functions Rodrigo Vivi
  2017-08-29  5:45 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2017-08-29  6:43 ` Jani Nikula
  2017-08-31  4:42   ` Rodrigo Vivi
  2017-08-29  7:12 ` ✗ Fi.CI.IGT: warning for " Patchwork
  2 siblings, 1 reply; 5+ messages in thread
From: Jani Nikula @ 2017-08-29  6:43 UTC (permalink / raw)
  To: intel-gfx; +Cc: Dhinakaran Pandiyan, Rodrigo Vivi

On Tue, 29 Aug 2017, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> No functional changes.
>
> Our code was only a bit messy with mixed style there so
> let's clean up a bit using the short codenames for the platforms.
>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Acked-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/intel_pm.c | 44 ++++++++++++++++++++---------------------
>  1 file changed, 22 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d5ff0b9f999f..4bdf1fb1df7e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7981,7 +7981,7 @@ static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
>  	 */
>  }
>  
> -static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
>  	uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
>  
> @@ -8264,7 +8264,7 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
>  	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
>  }
>  
> -static void cannonlake_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
>  	/* This is not an Wa. Enable for better image quality */
>  	I915_WRITE(_3D_CHICKEN3,
> @@ -8285,7 +8285,7 @@ static void cannonlake_init_clock_gating(struct drm_i915_private *dev_priv)
>  			   SARBUNIT_CLKGATE_DIS);
>  }
>  
> -static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
>  	gen9_init_clock_gating(dev_priv);
>  
> @@ -8304,7 +8304,7 @@ static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
>  		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
>  }
>  
> -static void skylake_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
>  	gen9_init_clock_gating(dev_priv);
>  
> @@ -8317,7 +8317,7 @@ static void skylake_init_clock_gating(struct drm_i915_private *dev_priv)
>  		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
>  }
>  
> -static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
>  	enum pipe pipe;
>  
> @@ -8375,7 +8375,7 @@ static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
>  		   I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
>  }
>  
> -static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
>  	ilk_init_lp_watermarks(dev_priv);
>  
> @@ -8429,7 +8429,7 @@ static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
>  	lpt_init_clock_gating(dev_priv);
>  }
>  
> -static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
>  	uint32_t snpcr;
>  
> @@ -8526,7 +8526,7 @@ static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv)
>  	gen6_check_mch_setup(dev_priv);
>  }
>  
> -static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
>  	/* WaDisableEarlyCull:vlv */
>  	I915_WRITE(_3D_CHICKEN3,
> @@ -8606,7 +8606,7 @@ static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv)
>  	I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
>  }
>  
> -static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void chv_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
>  	/* WaVSRefCountFullforceMissDisable:chv */
>  	/* WaDSRefCountFullforceMissDisable:chv */
> @@ -8666,7 +8666,7 @@ static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
>  	g4x_disable_trickle_feed(dev_priv);
>  }
>  
> -static void crestline_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
>  	I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
>  	I915_WRITE(RENCLK_GATE_D2, 0);
> @@ -8680,7 +8680,7 @@ static void crestline_init_clock_gating(struct drm_i915_private *dev_priv)
>  	I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
>  }
>  
> -static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void i965g_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
>  	I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
>  		   I965_RCC_CLOCK_GATE_DISABLE |
> @@ -8766,35 +8766,35 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
>  void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
>  {
>  	if (IS_CANNONLAKE(dev_priv))
> -		dev_priv->display.init_clock_gating = cannonlake_init_clock_gating;
> +		dev_priv->display.init_clock_gating = cnl_init_clock_gating;
>  	else if (IS_SKYLAKE(dev_priv))
> -		dev_priv->display.init_clock_gating = skylake_init_clock_gating;
> +		dev_priv->display.init_clock_gating = skl_init_clock_gating;
>  	else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
> -		dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
> +		dev_priv->display.init_clock_gating = kbl_init_clock_gating;
>  	else if (IS_BROXTON(dev_priv))
>  		dev_priv->display.init_clock_gating = bxt_init_clock_gating;
>  	else if (IS_GEMINILAKE(dev_priv))
>  		dev_priv->display.init_clock_gating = glk_init_clock_gating;
>  	else if (IS_BROADWELL(dev_priv))
> -		dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
> +		dev_priv->display.init_clock_gating = bdw_init_clock_gating;
>  	else if (IS_CHERRYVIEW(dev_priv))
> -		dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
> +		dev_priv->display.init_clock_gating = chv_init_clock_gating;
>  	else if (IS_HASWELL(dev_priv))
> -		dev_priv->display.init_clock_gating = haswell_init_clock_gating;
> +		dev_priv->display.init_clock_gating = hsw_init_clock_gating;
>  	else if (IS_IVYBRIDGE(dev_priv))
> -		dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
> +		dev_priv->display.init_clock_gating = ivb_init_clock_gating;
>  	else if (IS_VALLEYVIEW(dev_priv))
> -		dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
> +		dev_priv->display.init_clock_gating = vlv_init_clock_gating;
>  	else if (IS_GEN6(dev_priv))
>  		dev_priv->display.init_clock_gating = gen6_init_clock_gating;
>  	else if (IS_GEN5(dev_priv))
> -		dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
> +		dev_priv->display.init_clock_gating = ilk_init_clock_gating;
>  	else if (IS_G4X(dev_priv))
>  		dev_priv->display.init_clock_gating = g4x_init_clock_gating;
>  	else if (IS_I965GM(dev_priv))
> -		dev_priv->display.init_clock_gating = crestline_init_clock_gating;
> +		dev_priv->display.init_clock_gating = i965gm_init_clock_gating;
>  	else if (IS_I965G(dev_priv))
> -		dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
> +		dev_priv->display.init_clock_gating = i965g_init_clock_gating;
>  	else if (IS_GEN3(dev_priv))
>  		dev_priv->display.init_clock_gating = gen3_init_clock_gating;
>  	else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread
* ✗ Fi.CI.IGT: warning for drm/i915: Stop using long platform names on clock gating functions.
  2017-08-29  5:20 [PATCH] drm/i915: Stop using long platform names on clock gating functions Rodrigo Vivi
  2017-08-29  5:45 ` ✓ Fi.CI.BAT: success for " Patchwork
  2017-08-29  6:43 ` [PATCH] " Jani Nikula
@ 2017-08-29  7:12 ` Patchwork
  2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2017-08-29  7:12 UTC (permalink / raw)
  To: Rodrigo Vivi; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Stop using long platform names on clock gating functions.
URL   : https://patchwork.freedesktop.org/series/29453/
State : warning

== Summary ==

Test kms_chv_cursor_fail:
        Subgroup pipe-C-128x128-bottom-edge:
                pass       -> SKIP       (shard-hsw)
Test kms_frontbuffer_tracking:
        Subgroup fbc-1p-offscren-pri-shrfb-draw-mmap-wc:
                pass       -> SKIP       (shard-hsw)
Test kms_flip:
        Subgroup plain-flip-ts-check:
                fail       -> PASS       (shard-hsw)
Test kms_setmode:
        Subgroup basic:
                pass       -> FAIL       (shard-hsw) fdo#99912

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-hsw        total:2230 pass:1228 dwarn:0   dfail:0   fail:18  skip:984 time:9621s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5515/shards.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915: Stop using long platform names on clock gating functions.
  2017-08-29  6:43 ` [PATCH] " Jani Nikula
@ 2017-08-31  4:42   ` Rodrigo Vivi
  0 siblings, 0 replies; 5+ messages in thread
From: Rodrigo Vivi @ 2017-08-31  4:42 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx, Dhinakaran Pandiyan, Rodrigo Vivi

On Tue, Aug 29, 2017 at 09:43:41AM +0300, Jani Nikula wrote:
> On Tue, 29 Aug 2017, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> > No functional changes.
> >
> > Our code was only a bit messy with mixed style there so
> > let's clean up a bit using the short codenames for the platforms.
> >
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> Acked-by: Jani Nikula <jani.nikula@intel.com>

thanks. merged to dinq.

> 
> 
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 44 ++++++++++++++++++++---------------------
> >  1 file changed, 22 insertions(+), 22 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index d5ff0b9f999f..4bdf1fb1df7e 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -7981,7 +7981,7 @@ static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
> >  	 */
> >  }
> >  
> > -static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv)
> > +static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
> >  {
> >  	uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
> >  
> > @@ -8264,7 +8264,7 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
> >  	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
> >  }
> >  
> > -static void cannonlake_init_clock_gating(struct drm_i915_private *dev_priv)
> > +static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
> >  {
> >  	/* This is not an Wa. Enable for better image quality */
> >  	I915_WRITE(_3D_CHICKEN3,
> > @@ -8285,7 +8285,7 @@ static void cannonlake_init_clock_gating(struct drm_i915_private *dev_priv)
> >  			   SARBUNIT_CLKGATE_DIS);
> >  }
> >  
> > -static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
> > +static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
> >  {
> >  	gen9_init_clock_gating(dev_priv);
> >  
> > @@ -8304,7 +8304,7 @@ static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
> >  		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
> >  }
> >  
> > -static void skylake_init_clock_gating(struct drm_i915_private *dev_priv)
> > +static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
> >  {
> >  	gen9_init_clock_gating(dev_priv);
> >  
> > @@ -8317,7 +8317,7 @@ static void skylake_init_clock_gating(struct drm_i915_private *dev_priv)
> >  		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
> >  }
> >  
> > -static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
> > +static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
> >  {
> >  	enum pipe pipe;
> >  
> > @@ -8375,7 +8375,7 @@ static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
> >  		   I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
> >  }
> >  
> > -static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
> > +static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
> >  {
> >  	ilk_init_lp_watermarks(dev_priv);
> >  
> > @@ -8429,7 +8429,7 @@ static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
> >  	lpt_init_clock_gating(dev_priv);
> >  }
> >  
> > -static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv)
> > +static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
> >  {
> >  	uint32_t snpcr;
> >  
> > @@ -8526,7 +8526,7 @@ static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv)
> >  	gen6_check_mch_setup(dev_priv);
> >  }
> >  
> > -static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv)
> > +static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
> >  {
> >  	/* WaDisableEarlyCull:vlv */
> >  	I915_WRITE(_3D_CHICKEN3,
> > @@ -8606,7 +8606,7 @@ static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv)
> >  	I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
> >  }
> >  
> > -static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv)
> > +static void chv_init_clock_gating(struct drm_i915_private *dev_priv)
> >  {
> >  	/* WaVSRefCountFullforceMissDisable:chv */
> >  	/* WaDSRefCountFullforceMissDisable:chv */
> > @@ -8666,7 +8666,7 @@ static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
> >  	g4x_disable_trickle_feed(dev_priv);
> >  }
> >  
> > -static void crestline_init_clock_gating(struct drm_i915_private *dev_priv)
> > +static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv)
> >  {
> >  	I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
> >  	I915_WRITE(RENCLK_GATE_D2, 0);
> > @@ -8680,7 +8680,7 @@ static void crestline_init_clock_gating(struct drm_i915_private *dev_priv)
> >  	I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
> >  }
> >  
> > -static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv)
> > +static void i965g_init_clock_gating(struct drm_i915_private *dev_priv)
> >  {
> >  	I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
> >  		   I965_RCC_CLOCK_GATE_DISABLE |
> > @@ -8766,35 +8766,35 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
> >  void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
> >  {
> >  	if (IS_CANNONLAKE(dev_priv))
> > -		dev_priv->display.init_clock_gating = cannonlake_init_clock_gating;
> > +		dev_priv->display.init_clock_gating = cnl_init_clock_gating;
> >  	else if (IS_SKYLAKE(dev_priv))
> > -		dev_priv->display.init_clock_gating = skylake_init_clock_gating;
> > +		dev_priv->display.init_clock_gating = skl_init_clock_gating;
> >  	else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
> > -		dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
> > +		dev_priv->display.init_clock_gating = kbl_init_clock_gating;
> >  	else if (IS_BROXTON(dev_priv))
> >  		dev_priv->display.init_clock_gating = bxt_init_clock_gating;
> >  	else if (IS_GEMINILAKE(dev_priv))
> >  		dev_priv->display.init_clock_gating = glk_init_clock_gating;
> >  	else if (IS_BROADWELL(dev_priv))
> > -		dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
> > +		dev_priv->display.init_clock_gating = bdw_init_clock_gating;
> >  	else if (IS_CHERRYVIEW(dev_priv))
> > -		dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
> > +		dev_priv->display.init_clock_gating = chv_init_clock_gating;
> >  	else if (IS_HASWELL(dev_priv))
> > -		dev_priv->display.init_clock_gating = haswell_init_clock_gating;
> > +		dev_priv->display.init_clock_gating = hsw_init_clock_gating;
> >  	else if (IS_IVYBRIDGE(dev_priv))
> > -		dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
> > +		dev_priv->display.init_clock_gating = ivb_init_clock_gating;
> >  	else if (IS_VALLEYVIEW(dev_priv))
> > -		dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
> > +		dev_priv->display.init_clock_gating = vlv_init_clock_gating;
> >  	else if (IS_GEN6(dev_priv))
> >  		dev_priv->display.init_clock_gating = gen6_init_clock_gating;
> >  	else if (IS_GEN5(dev_priv))
> > -		dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
> > +		dev_priv->display.init_clock_gating = ilk_init_clock_gating;
> >  	else if (IS_G4X(dev_priv))
> >  		dev_priv->display.init_clock_gating = g4x_init_clock_gating;
> >  	else if (IS_I965GM(dev_priv))
> > -		dev_priv->display.init_clock_gating = crestline_init_clock_gating;
> > +		dev_priv->display.init_clock_gating = i965gm_init_clock_gating;
> >  	else if (IS_I965G(dev_priv))
> > -		dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
> > +		dev_priv->display.init_clock_gating = i965g_init_clock_gating;
> >  	else if (IS_GEN3(dev_priv))
> >  		dev_priv->display.init_clock_gating = gen3_init_clock_gating;
> >  	else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2017-08-31  4:42 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-08-29  5:20 [PATCH] drm/i915: Stop using long platform names on clock gating functions Rodrigo Vivi
2017-08-29  5:45 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-08-29  6:43 ` [PATCH] " Jani Nikula
2017-08-31  4:42   ` Rodrigo Vivi
2017-08-29  7:12 ` ✗ Fi.CI.IGT: warning for " Patchwork

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