* [PATCH 2/4] drm/amd/amdgpu: Tidy up gmc_v9_0_gart_enable()
[not found] ` <20170901135711.3574-1-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
@ 2017-09-01 13:57 ` Tom St Denis
2017-09-01 13:57 ` [PATCH 3/4] drm/amd/amdgpu: Tidy up gmc_v9_0_hw_init() Tom St Denis
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Tom St Denis @ 2017-09-01 13:57 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tom St Denis
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 1cb7aa2af683..d7cfee807287 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -719,14 +719,11 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
if (r)
return r;
- tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL);
- tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK;
- WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp);
+ WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
-
if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
value = false;
else
@@ -734,7 +731,6 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
gfxhub_v1_0_set_fault_enable_default(adev, value);
mmhub_v1_0_set_fault_enable_default(adev, value);
-
gmc_v9_0_gart_flush_gpu_tlb(adev, 0);
DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
--
2.12.0
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^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 3/4] drm/amd/amdgpu: Tidy up gmc_v9_0_hw_init()
[not found] ` <20170901135711.3574-1-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
2017-09-01 13:57 ` [PATCH 2/4] drm/amd/amdgpu: Tidy up gmc_v9_0_gart_enable() Tom St Denis
@ 2017-09-01 13:57 ` Tom St Denis
2017-09-01 13:57 ` [PATCH 4/4] drm/amd/amdgpu: Cleanup gmc_v9_0_suspend() Tom St Denis
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Tom St Denis @ 2017-09-01 13:57 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tom St Denis
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 10 ++--------
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index d7cfee807287..0766dad1fafe 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -749,17 +749,11 @@ static int gmc_v9_0_hw_init(void *handle)
gmc_v9_0_init_golden_registers(adev);
if (adev->mode_info.num_crtc) {
- u32 tmp;
-
/* Lockout access through VGA aperture*/
- tmp = RREG32_SOC15(DCE, 0, mmVGA_HDP_CONTROL);
- tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
- WREG32_SOC15(DCE, 0, mmVGA_HDP_CONTROL, tmp);
+ WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
/* disable VGA render */
- tmp = RREG32_SOC15(DCE, 0, mmVGA_RENDER_CONTROL);
- tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
- WREG32_SOC15(DCE, 0, mmVGA_RENDER_CONTROL, tmp);
+ WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
}
r = gmc_v9_0_gart_enable(adev);
--
2.12.0
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^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 4/4] drm/amd/amdgpu: Cleanup gmc_v9_0_suspend()
[not found] ` <20170901135711.3574-1-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
2017-09-01 13:57 ` [PATCH 2/4] drm/amd/amdgpu: Tidy up gmc_v9_0_gart_enable() Tom St Denis
2017-09-01 13:57 ` [PATCH 3/4] drm/amd/amdgpu: Tidy up gmc_v9_0_hw_init() Tom St Denis
@ 2017-09-01 13:57 ` Tom St Denis
2017-09-01 14:44 ` [PATCH 1/4] drm/amd/amdgpu: Simplify gmc_v9_0_vm_fault_interrupt_state() Christian König
2017-09-01 14:55 ` Deucher, Alexander
4 siblings, 0 replies; 6+ messages in thread
From: Tom St Denis @ 2017-09-01 13:57 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tom St Denis
Even though fini returns 0 always it could theoretically
fail in the future. Might as well return it instead of 0.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 0766dad1fafe..7ca9cbec3004 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -795,9 +795,7 @@ static int gmc_v9_0_suspend(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- gmc_v9_0_hw_fini(adev);
-
- return 0;
+ return gmc_v9_0_hw_fini(adev);
}
static int gmc_v9_0_resume(void *handle)
--
2.12.0
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^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 1/4] drm/amd/amdgpu: Simplify gmc_v9_0_vm_fault_interrupt_state()
[not found] ` <20170901135711.3574-1-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2017-09-01 13:57 ` [PATCH 4/4] drm/amd/amdgpu: Cleanup gmc_v9_0_suspend() Tom St Denis
@ 2017-09-01 14:44 ` Christian König
2017-09-01 14:55 ` Deucher, Alexander
4 siblings, 0 replies; 6+ messages in thread
From: Christian König @ 2017-09-01 14:44 UTC (permalink / raw)
To: Tom St Denis, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Am 01.09.2017 um 15:57 schrieb Tom St Denis:
> Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com> for the entire
series.
> ---
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 51 ++++++++++++-----------------------
> 1 file changed, 17 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index d04d0b123212..1cb7aa2af683 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -77,7 +77,7 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
> enum amdgpu_interrupt_state state)
> {
> struct amdgpu_vmhub *hub;
> - u32 tmp, reg, bits, i;
> + u32 tmp, reg, bits, i, j;
>
> bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> @@ -89,43 +89,26 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
>
> switch (state) {
> case AMDGPU_IRQ_STATE_DISABLE:
> - /* MM HUB */
> - hub = &adev->vmhub[AMDGPU_MMHUB];
> - for (i = 0; i< 16; i++) {
> - reg = hub->vm_context0_cntl + i;
> - tmp = RREG32(reg);
> - tmp &= ~bits;
> - WREG32(reg, tmp);
> - }
> -
> - /* GFX HUB */
> - hub = &adev->vmhub[AMDGPU_GFXHUB];
> - for (i = 0; i < 16; i++) {
> - reg = hub->vm_context0_cntl + i;
> - tmp = RREG32(reg);
> - tmp &= ~bits;
> - WREG32(reg, tmp);
> + for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
> + hub = &adev->vmhub[j];
> + for (i = 0; i < 16; i++) {
> + reg = hub->vm_context0_cntl + i;
> + tmp = RREG32(reg);
> + tmp &= ~bits;
> + WREG32(reg, tmp);
> + }
> }
> break;
> case AMDGPU_IRQ_STATE_ENABLE:
> - /* MM HUB */
> - hub = &adev->vmhub[AMDGPU_MMHUB];
> - for (i = 0; i< 16; i++) {
> - reg = hub->vm_context0_cntl + i;
> - tmp = RREG32(reg);
> - tmp |= bits;
> - WREG32(reg, tmp);
> + for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
> + hub = &adev->vmhub[j];
> + for (i = 0; i < 16; i++) {
> + reg = hub->vm_context0_cntl + i;
> + tmp = RREG32(reg);
> + tmp |= bits;
> + WREG32(reg, tmp);
> + }
> }
> -
> - /* GFX HUB */
> - hub = &adev->vmhub[AMDGPU_GFXHUB];
> - for (i = 0; i < 16; i++) {
> - reg = hub->vm_context0_cntl + i;
> - tmp = RREG32(reg);
> - tmp |= bits;
> - WREG32(reg, tmp);
> - }
> - break;
> default:
> break;
> }
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^ permalink raw reply [flat|nested] 6+ messages in thread* RE: [PATCH 1/4] drm/amd/amdgpu: Simplify gmc_v9_0_vm_fault_interrupt_state()
[not found] ` <20170901135711.3574-1-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
` (3 preceding siblings ...)
2017-09-01 14:44 ` [PATCH 1/4] drm/amd/amdgpu: Simplify gmc_v9_0_vm_fault_interrupt_state() Christian König
@ 2017-09-01 14:55 ` Deucher, Alexander
4 siblings, 0 replies; 6+ messages in thread
From: Deucher, Alexander @ 2017-09-01 14:55 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: StDenis, Tom
> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Tom St Denis
> Sent: Friday, September 01, 2017 9:57 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: StDenis, Tom
> Subject: [PATCH 1/4] drm/amd/amdgpu: Simplify
> gmc_v9_0_vm_fault_interrupt_state()
>
> Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 51 ++++++++++++--------------
> ---------
> 1 file changed, 17 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index d04d0b123212..1cb7aa2af683 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -77,7 +77,7 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct
> amdgpu_device *adev,
> enum amdgpu_interrupt_state state)
> {
> struct amdgpu_vmhub *hub;
> - u32 tmp, reg, bits, i;
> + u32 tmp, reg, bits, i, j;
>
> bits =
> VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_
> MASK |
>
> VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENAB
> LE_INTERRUPT_MASK |
> @@ -89,43 +89,26 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct
> amdgpu_device *adev,
>
> switch (state) {
> case AMDGPU_IRQ_STATE_DISABLE:
> - /* MM HUB */
> - hub = &adev->vmhub[AMDGPU_MMHUB];
> - for (i = 0; i< 16; i++) {
> - reg = hub->vm_context0_cntl + i;
> - tmp = RREG32(reg);
> - tmp &= ~bits;
> - WREG32(reg, tmp);
> - }
> -
> - /* GFX HUB */
> - hub = &adev->vmhub[AMDGPU_GFXHUB];
> - for (i = 0; i < 16; i++) {
> - reg = hub->vm_context0_cntl + i;
> - tmp = RREG32(reg);
> - tmp &= ~bits;
> - WREG32(reg, tmp);
> + for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
> + hub = &adev->vmhub[j];
> + for (i = 0; i < 16; i++) {
> + reg = hub->vm_context0_cntl + i;
> + tmp = RREG32(reg);
> + tmp &= ~bits;
> + WREG32(reg, tmp);
> + }
> }
> break;
> case AMDGPU_IRQ_STATE_ENABLE:
> - /* MM HUB */
> - hub = &adev->vmhub[AMDGPU_MMHUB];
> - for (i = 0; i< 16; i++) {
> - reg = hub->vm_context0_cntl + i;
> - tmp = RREG32(reg);
> - tmp |= bits;
> - WREG32(reg, tmp);
> + for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
> + hub = &adev->vmhub[j];
> + for (i = 0; i < 16; i++) {
> + reg = hub->vm_context0_cntl + i;
> + tmp = RREG32(reg);
> + tmp |= bits;
> + WREG32(reg, tmp);
> + }
> }
> -
> - /* GFX HUB */
> - hub = &adev->vmhub[AMDGPU_GFXHUB];
> - for (i = 0; i < 16; i++) {
> - reg = hub->vm_context0_cntl + i;
> - tmp = RREG32(reg);
> - tmp |= bits;
> - WREG32(reg, tmp);
> - }
> - break;
> default:
> break;
> }
> --
> 2.12.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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^ permalink raw reply [flat|nested] 6+ messages in thread