[PATCH v2 0/4] rockchip: Add efuse support for RK3368 SoCs

[PATCH v2 0/4] rockchip: Add efuse support for RK3368 SoCs

[Romain Perier]

This set of patches exports the right clocks, add required functions
and data, and definition for enabling and supporting eFuse on RK3368
SoCs.

Note: On my geekbox rk3368, I was unable to flash a working upstream ATF
or upstream uboot (missing support for LPDDR3 init and timping). I cannot
test the driver without the secure mode for this efuse on my hardware.So
I am asking for testing. I think that it should work like on rk3288

Changes in v2:
- Removed ARM SMC calls for efuse, we need to do as upstream ATF and
  uboot mainline do, so no secure-regs for efuse

Romain Perier (4):
  clk: rockchip: add clock id for PCLK_EFUSE256 of RK3368 SoCs
  clk: rockchip: export clock pclk_efuse_256 for RK3368 SoCs
  nvmem: rockchip: add support for RK3368
  arm64: dts: rockchip: add efuse for RK3368 SoCs

 Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt |  1 +
 arch/arm64/boot/dts/rockchip/rk3368.dtsi                   | 14 ++++++++++++++
 drivers/clk/rockchip/clk-rk3368.c                          |  2 +-
 drivers/nvmem/rockchip-efuse.c                             |  4 ++++
 include/dt-bindings/clock/rk3368-cru.h                     |  1 +
 5 files changed, 21 insertions(+), 1 deletion(-)

-- 
2.11.0

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[PATCH v2 0/4] rockchip: Add efuse support for RK3368 SoCs

[Romain Perier]

This set of patches exports the right clocks, add required functions
and data, and definition for enabling and supporting eFuse on RK3368
SoCs.

Note: On my geekbox rk3368, I was unable to flash a working upstream ATF
or upstream uboot (missing support for LPDDR3 init and timping). I cannot
test the driver without the secure mode for this efuse on my hardware.So
I am asking for testing. I think that it should work like on rk3288

Changes in v2:
- Removed ARM SMC calls for efuse, we need to do as upstream ATF and
  uboot mainline do, so no secure-regs for efuse

Romain Perier (4):
  clk: rockchip: add clock id for PCLK_EFUSE256 of RK3368 SoCs
  clk: rockchip: export clock pclk_efuse_256 for RK3368 SoCs
  nvmem: rockchip: add support for RK3368
  arm64: dts: rockchip: add efuse for RK3368 SoCs

 Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt |  1 +
 arch/arm64/boot/dts/rockchip/rk3368.dtsi                   | 14 ++++++++++++++
 drivers/clk/rockchip/clk-rk3368.c                          |  2 +-
 drivers/nvmem/rockchip-efuse.c                             |  4 ++++
 include/dt-bindings/clock/rk3368-cru.h                     |  1 +
 5 files changed, 21 insertions(+), 1 deletion(-)

-- 
2.11.0

[PATCH v2 0/4] rockchip: Add efuse support for RK3368 SoCs

[Romain Perier]

This set of patches exports the right clocks, add required functions
and data, and definition for enabling and supporting eFuse on RK3368
SoCs.

Note: On my geekbox rk3368, I was unable to flash a working upstream ATF
or upstream uboot (missing support for LPDDR3 init and timping). I cannot
test the driver without the secure mode for this efuse on my hardware.So
I am asking for testing. I think that it should work like on rk3288

Changes in v2:
- Removed ARM SMC calls for efuse, we need to do as upstream ATF and
  uboot mainline do, so no secure-regs for efuse

Romain Perier (4):
  clk: rockchip: add clock id for PCLK_EFUSE256 of RK3368 SoCs
  clk: rockchip: export clock pclk_efuse_256 for RK3368 SoCs
  nvmem: rockchip: add support for RK3368
  arm64: dts: rockchip: add efuse for RK3368 SoCs

 Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt |  1 +
 arch/arm64/boot/dts/rockchip/rk3368.dtsi                   | 14 ++++++++++++++
 drivers/clk/rockchip/clk-rk3368.c                          |  2 +-
 drivers/nvmem/rockchip-efuse.c                             |  4 ++++
 include/dt-bindings/clock/rk3368-cru.h                     |  1 +
 5 files changed, 21 insertions(+), 1 deletion(-)

-- 
2.11.0

[PATCH v2 1/4] clk: rockchip: add clock id for PCLK_EFUSE256 of RK3368 SoCs

[Romain Perier]

Signed-off-by: Romain Perier <romain.perier@collabora.com>
---
 include/dt-bindings/clock/rk3368-cru.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h
index aeb83e581a11..a0063ed7284a 100644
--- a/include/dt-bindings/clock/rk3368-cru.h
+++ b/include/dt-bindings/clock/rk3368-cru.h
@@ -156,6 +156,7 @@
 #define PCLK_ISP		366
 #define PCLK_VIP		367
 #define PCLK_WDT		368
+#define PCLK_EFUSE256		369
 
 /* hclk gates */
 #define HCLK_SFC		448
-- 
2.11.0

[PATCH v2 1/4] clk: rockchip: add clock id for PCLK_EFUSE256 of RK3368 SoCs

[Romain Perier]

Signed-off-by: Romain Perier <romain.perier@collabora.com>
---
 include/dt-bindings/clock/rk3368-cru.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h
index aeb83e581a11..a0063ed7284a 100644
--- a/include/dt-bindings/clock/rk3368-cru.h
+++ b/include/dt-bindings/clock/rk3368-cru.h
@@ -156,6 +156,7 @@
 #define PCLK_ISP		366
 #define PCLK_VIP		367
 #define PCLK_WDT		368
+#define PCLK_EFUSE256		369
 
 /* hclk gates */
 #define HCLK_SFC		448
-- 
2.11.0

[PATCH v2 2/4] clk: rockchip: export clock pclk_efuse_256 for RK3368 SoCs

[Romain Perier]

This exports the clock for the pclk gate of the eFuse that is part of
the RK3368 SoCs. So we can use it from the dt-bindings.

Signed-off-by: Romain Perier <romain.perier@collabora.com>
---
 drivers/clk/rockchip/clk-rk3368.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index fc56565379dd..7c4d242f19c1 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -711,7 +711,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
 	GATE(PCLK_SIM, "pclk_sim", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 8, GFLAGS),
 	GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 6, GFLAGS),
 	GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 5, GFLAGS),
-	GATE(0, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS),
+	GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS),
 	GATE(0, "pclk_efuse_1024", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 0, GFLAGS),
 
 	/*
-- 
2.11.0

[PATCH v2 2/4] clk: rockchip: export clock pclk_efuse_256 for RK3368 SoCs

[Romain Perier]

This exports the clock for the pclk gate of the eFuse that is part of
the RK3368 SoCs. So we can use it from the dt-bindings.

Signed-off-by: Romain Perier <romain.perier@collabora.com>
---
 drivers/clk/rockchip/clk-rk3368.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index fc56565379dd..7c4d242f19c1 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -711,7 +711,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
 	GATE(PCLK_SIM, "pclk_sim", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 8, GFLAGS),
 	GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 6, GFLAGS),
 	GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 5, GFLAGS),
-	GATE(0, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS),
+	GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS),
 	GATE(0, "pclk_efuse_1024", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 0, GFLAGS),
 
 	/*
-- 
2.11.0

[PATCH v2 3/4] nvmem: rockchip: add support for RK3368

[Romain Perier]

This adds the necessary function for handling support on RK3368 SoCs

Signed-off-by: Romain Perier <romain.perier-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
 Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt | 1 +
 drivers/nvmem/rockchip-efuse.c                             | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt b/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt
index 1ff02afdc55a..60bec4782806 100644
--- a/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt
+++ b/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt
@@ -6,6 +6,7 @@ Required properties:
   - "rockchip,rk3188-efuse" - for RK3188 SoCs.
   - "rockchip,rk3228-efuse" - for RK3228 SoCs.
   - "rockchip,rk3288-efuse" - for RK3288 SoCs.
+  - "rockchip,rk3368-efuse" - for RK3368 SoCs.
   - "rockchip,rk3399-efuse" - for RK3399 SoCs.
 - reg: Should contain the registers location and exact eFuse size
 - clocks: Should be the clock id of eFuse
diff --git a/drivers/nvmem/rockchip-efuse.c b/drivers/nvmem/rockchip-efuse.c
index 63e3eb55f3ac..eb4c530c2564 100644
--- a/drivers/nvmem/rockchip-efuse.c
+++ b/drivers/nvmem/rockchip-efuse.c
@@ -178,6 +178,10 @@ static const struct of_device_id rockchip_efuse_match[] = {
 		.data = (void *)&rockchip_rk3288_efuse_read,
 	},
 	{
+		.compatible = "rockchip,rk3368-efuse",
+		.data = (void *)&rockchip_rk3288_efuse_read,
+	},
+	{
 		.compatible = "rockchip,rk3399-efuse",
 		.data = (void *)&rockchip_rk3399_efuse_read,
 	},
-- 
2.11.0

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[PATCH v2 3/4] nvmem: rockchip: add support for RK3368

[Romain Perier]

This adds the necessary function for handling support on RK3368 SoCs

Signed-off-by: Romain Perier <romain.perier@collabora.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt | 1 +
 drivers/nvmem/rockchip-efuse.c                             | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt b/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt
index 1ff02afdc55a..60bec4782806 100644
--- a/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt
+++ b/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt
@@ -6,6 +6,7 @@ Required properties:
   - "rockchip,rk3188-efuse" - for RK3188 SoCs.
   - "rockchip,rk3228-efuse" - for RK3228 SoCs.
   - "rockchip,rk3288-efuse" - for RK3288 SoCs.
+  - "rockchip,rk3368-efuse" - for RK3368 SoCs.
   - "rockchip,rk3399-efuse" - for RK3399 SoCs.
 - reg: Should contain the registers location and exact eFuse size
 - clocks: Should be the clock id of eFuse
diff --git a/drivers/nvmem/rockchip-efuse.c b/drivers/nvmem/rockchip-efuse.c
index 63e3eb55f3ac..eb4c530c2564 100644
--- a/drivers/nvmem/rockchip-efuse.c
+++ b/drivers/nvmem/rockchip-efuse.c
@@ -178,6 +178,10 @@ static const struct of_device_id rockchip_efuse_match[] = {
 		.data = (void *)&rockchip_rk3288_efuse_read,
 	},
 	{
+		.compatible = "rockchip,rk3368-efuse",
+		.data = (void *)&rockchip_rk3288_efuse_read,
+	},
+	{
 		.compatible = "rockchip,rk3399-efuse",
 		.data = (void *)&rockchip_rk3399_efuse_read,
 	},
-- 
2.11.0

[PATCH v2 3/4] nvmem: rockchip: add support for RK3368

[Romain Perier]

This adds the necessary function for handling support on RK3368 SoCs

Signed-off-by: Romain Perier <romain.perier@collabora.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt | 1 +
 drivers/nvmem/rockchip-efuse.c                             | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt b/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt
index 1ff02afdc55a..60bec4782806 100644
--- a/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt
+++ b/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt
@@ -6,6 +6,7 @@ Required properties:
   - "rockchip,rk3188-efuse" - for RK3188 SoCs.
   - "rockchip,rk3228-efuse" - for RK3228 SoCs.
   - "rockchip,rk3288-efuse" - for RK3288 SoCs.
+  - "rockchip,rk3368-efuse" - for RK3368 SoCs.
   - "rockchip,rk3399-efuse" - for RK3399 SoCs.
 - reg: Should contain the registers location and exact eFuse size
 - clocks: Should be the clock id of eFuse
diff --git a/drivers/nvmem/rockchip-efuse.c b/drivers/nvmem/rockchip-efuse.c
index 63e3eb55f3ac..eb4c530c2564 100644
--- a/drivers/nvmem/rockchip-efuse.c
+++ b/drivers/nvmem/rockchip-efuse.c
@@ -178,6 +178,10 @@ static const struct of_device_id rockchip_efuse_match[] = {
 		.data = (void *)&rockchip_rk3288_efuse_read,
 	},
 	{
+		.compatible = "rockchip,rk3368-efuse",
+		.data = (void *)&rockchip_rk3288_efuse_read,
+	},
+	{
 		.compatible = "rockchip,rk3399-efuse",
 		.data = (void *)&rockchip_rk3399_efuse_read,
 	},
-- 
2.11.0

[PATCH v2 4/4] arm64: dts: rockchip: add efuse for RK3368 SoCs

[Romain Perier]

This adds the definition for eFuse that is found on RK3368 SoCs with the
corresponding data cells.

Signed-off-by: Romain Perier <romain.perier-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
---
 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 3039c2da533e..cca2ce1705b3 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -569,6 +569,20 @@
 		};
 	};
 
+	efuse: efuse@ffb00000 {
+		compatible = "rockchip,rk3368-efuse";
+		reg = <0x0 0xffb00000 0x0 0x20>;
+		clocks = <&cru PCLK_EFUSE_256>;
+		clock-names = "pclk_efuse";
+
+		cpu_leakage: cpu-leakage@17 {
+			reg = <0x17 0x1>;
+		};
+		temp_adjust: temp-adjust@1f {
+			reg = <0x1f 0x1>;
+		};
+	};
+
 	tsadc: tsadc@ff280000 {
 		compatible = "rockchip,rk3368-tsadc";
 		reg = <0x0 0xff280000 0x0 0x100>;
-- 
2.11.0

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[PATCH v2 4/4] arm64: dts: rockchip: add efuse for RK3368 SoCs

[Romain Perier]

This adds the definition for eFuse that is found on RK3368 SoCs with the
corresponding data cells.

Signed-off-by: Romain Perier <romain.perier@collabora.com>
---
 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 3039c2da533e..cca2ce1705b3 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -569,6 +569,20 @@
 		};
 	};
 
+	efuse: efuse@ffb00000 {
+		compatible = "rockchip,rk3368-efuse";
+		reg = <0x0 0xffb00000 0x0 0x20>;
+		clocks = <&cru PCLK_EFUSE_256>;
+		clock-names = "pclk_efuse";
+
+		cpu_leakage: cpu-leakage@17 {
+			reg = <0x17 0x1>;
+		};
+		temp_adjust: temp-adjust@1f {
+			reg = <0x1f 0x1>;
+		};
+	};
+
 	tsadc: tsadc@ff280000 {
 		compatible = "rockchip,rk3368-tsadc";
 		reg = <0x0 0xff280000 0x0 0x100>;
-- 
2.11.0

[PATCH v2 4/4] arm64: dts: rockchip: add efuse for RK3368 SoCs

[Romain Perier]

This adds the definition for eFuse that is found on RK3368 SoCs with the
corresponding data cells.

Signed-off-by: Romain Perier <romain.perier@collabora.com>
---
 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 3039c2da533e..cca2ce1705b3 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -569,6 +569,20 @@
 		};
 	};
 
+	efuse: efuse at ffb00000 {
+		compatible = "rockchip,rk3368-efuse";
+		reg = <0x0 0xffb00000 0x0 0x20>;
+		clocks = <&cru PCLK_EFUSE_256>;
+		clock-names = "pclk_efuse";
+
+		cpu_leakage: cpu-leakage at 17 {
+			reg = <0x17 0x1>;
+		};
+		temp_adjust: temp-adjust at 1f {
+			reg = <0x1f 0x1>;
+		};
+	};
+
 	tsadc: tsadc at ff280000 {
 		compatible = "rockchip,rk3368-tsadc";
 		reg = <0x0 0xff280000 0x0 0x100>;
-- 
2.11.0

Re: [PATCH v2 1/4] clk: rockchip: add clock id for PCLK_EFUSE256 of RK3368 SoCs

[Heiko Stuebner]

Am Montag, 4. September 2017, 10:51:16 CEST schrieb Romain Perier:
> Signed-off-by: Romain Perier <romain.perier@collabora.com>

applied for 4.15

Thanks
Heiko

[PATCH v2 1/4] clk: rockchip: add clock id for PCLK_EFUSE256 of RK3368 SoCs

[Heiko Stuebner]

Am Montag, 4. September 2017, 10:51:16 CEST schrieb Romain Perier:
> Signed-off-by: Romain Perier <romain.perier@collabora.com>

applied for 4.15

Thanks
Heiko

Re: [PATCH v2 2/4] clk: rockchip: export clock pclk_efuse_256 for RK3368 SoCs

[Heiko Stuebner]

Am Montag, 4. September 2017, 10:51:17 CEST schrieb Romain Perier:
> This exports the clock for the pclk gate of the eFuse that is part of
> the RK3368 SoCs. So we can use it from the dt-bindings.
> 
> Signed-off-by: Romain Perier <romain.perier@collabora.com>

applied for 4.15


Thanks
Heiko

[PATCH v2 2/4] clk: rockchip: export clock pclk_efuse_256 for RK3368 SoCs

[Heiko Stuebner]

Am Montag, 4. September 2017, 10:51:17 CEST schrieb Romain Perier:
> This exports the clock for the pclk gate of the eFuse that is part of
> the RK3368 SoCs. So we can use it from the dt-bindings.
> 
> Signed-off-by: Romain Perier <romain.perier@collabora.com>

applied for 4.15


Thanks
Heiko

Re: [PATCH v2 3/4] nvmem: rockchip: add support for RK3368

[Heiko Stuebner]

Hi Srinivas,

Am Montag, 4. September 2017, 10:51:18 CEST schrieb Romain Perier:
> This adds the necessary function for handling support on RK3368 SoCs
> 
> Signed-off-by: Romain Perier <romain.perier-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>

Reviewed-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>

Srinivas, could you take a look at this patch and maybe pick it up?


Thanks
Heiko
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Re: [PATCH v2 3/4] nvmem: rockchip: add support for RK3368

[Heiko Stuebner]

Hi Srinivas,

Am Montag, 4. September 2017, 10:51:18 CEST schrieb Romain Perier:
> This adds the necessary function for handling support on RK3368 SoCs
> 
> Signed-off-by: Romain Perier <romain.perier@collabora.com>
> Acked-by: Rob Herring <robh@kernel.org>

Reviewed-by: Heiko Stuebner <heiko@sntech.de>

Srinivas, could you take a look at this patch and maybe pick it up?


Thanks
Heiko

[PATCH v2 3/4] nvmem: rockchip: add support for RK3368

[Heiko Stuebner]

Hi Srinivas,

Am Montag, 4. September 2017, 10:51:18 CEST schrieb Romain Perier:
> This adds the necessary function for handling support on RK3368 SoCs
> 
> Signed-off-by: Romain Perier <romain.perier@collabora.com>
> Acked-by: Rob Herring <robh@kernel.org>

Reviewed-by: Heiko Stuebner <heiko@sntech.de>

Srinivas, could you take a look at this patch and maybe pick it up?


Thanks
Heiko

Re: [PATCH v2 3/4] nvmem: rockchip: add support for RK3368

[Srinivas Kandagatla]

On 14/10/17 22:31, Heiko Stuebner wrote:
> Hi Srinivas,
> 
> Am Montag, 4. September 2017, 10:51:18 CEST schrieb Romain Perier:
>> This adds the necessary function for handling support on RK3368 SoCs
>>
>> Signed-off-by: Romain Perier <romain.perier@collabora.com>
>> Acked-by: Rob Herring <robh@kernel.org>
> 
> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> 
> Srinivas, could you take a look at this patch and maybe pick it up?
> 
Its already sent to Greg KH for inclusion in 4.15.

--srini
> 
> Thanks
> Heiko
> 

[PATCH v2 3/4] nvmem: rockchip: add support for RK3368

[Srinivas Kandagatla]

On 14/10/17 22:31, Heiko Stuebner wrote:
> Hi Srinivas,
> 
> Am Montag, 4. September 2017, 10:51:18 CEST schrieb Romain Perier:
>> This adds the necessary function for handling support on RK3368 SoCs
>>
>> Signed-off-by: Romain Perier <romain.perier@collabora.com>
>> Acked-by: Rob Herring <robh@kernel.org>
> 
> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> 
> Srinivas, could you take a look at this patch and maybe pick it up?
> 
Its already sent to Greg KH for inclusion in 4.15.

--srini
> 
> Thanks
> Heiko
> 

Re: [PATCH v2 4/4] arm64: dts: rockchip: add efuse for RK3368 SoCs

[Heiko Stuebner]

Am Montag, 4. September 2017, 10:51:19 CEST schrieb Romain Perier:
> This adds the definition for eFuse that is found on RK3368 SoCs with the
> corresponding data cells.
> 
> Signed-off-by: Romain Perier <romain.perier-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>

applied for 4.15 after the following changes
- moved efuse node to its correct position (determined by register address)
- use correct clock-id as added by patch1 (efuse256 without the underscore)
- added the #address- and #size-cells properties for the subnodes
  to make dtc happy

Please pay a bit more attention for future patches.


Thanks
Heiko
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Re: [PATCH v2 4/4] arm64: dts: rockchip: add efuse for RK3368 SoCs

[Heiko Stuebner]

Am Montag, 4. September 2017, 10:51:19 CEST schrieb Romain Perier:
> This adds the definition for eFuse that is found on RK3368 SoCs with the
> corresponding data cells.
> 
> Signed-off-by: Romain Perier <romain.perier@collabora.com>

applied for 4.15 after the following changes
- moved efuse node to its correct position (determined by register address)
- use correct clock-id as added by patch1 (efuse256 without the underscore)
- added the #address- and #size-cells properties for the subnodes
  to make dtc happy

Please pay a bit more attention for future patches.


Thanks
Heiko

[PATCH v2 4/4] arm64: dts: rockchip: add efuse for RK3368 SoCs

[Heiko Stuebner]

Am Montag, 4. September 2017, 10:51:19 CEST schrieb Romain Perier:
> This adds the definition for eFuse that is found on RK3368 SoCs with the
> corresponding data cells.
> 
> Signed-off-by: Romain Perier <romain.perier@collabora.com>

applied for 4.15 after the following changes
- moved efuse node to its correct position (determined by register address)
- use correct clock-id as added by patch1 (efuse256 without the underscore)
- added the #address- and #size-cells properties for the subnodes
  to make dtc happy

Please pay a bit more attention for future patches.


Thanks
Heiko