From: Christoffer Dall <cdall@linaro.org> To: kvmarm@lists.cs.columbia.edu, Eric Auger <eric.auger@redhat.com>, Marc Zyngier <marc.zyngier@arm.com> Cc: Andre Przywara <andre.przywara@arm.com>, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, Christoffer Dall <cdall@linaro.org> Subject: [PATCH v2 1/6] KVM: arm/arm64: Don't cache the timer IRQ level Date: Mon, 4 Sep 2017 12:24:51 +0200 [thread overview] Message-ID: <20170904102456.9025-2-cdall@linaro.org> (raw) In-Reply-To: <20170904102456.9025-1-cdall@linaro.org> The timer was modeled after a strict idea of modelling an interrupt line level in software, meaning that only transitions in the level needed to be reported to the VGIC. This works well for the timer, because the arch timer code is in complete control of the device and can track the transitions of the line. However, as we are about to support using the HW bit in the VGIC not just for the timer, but also for VFIO which cannot track transitions of the interrupt line, we have to decide on an interface for level triggered mapped interrupts to the GIC, which both the timer and VFIO can use. VFIO only sees an asserting transition of the physical interrupt line, and tells the VGIC when that happens. That means that part of the interrupt flow is offloaded to the hardware. To use the same interface for VFIO devices and the timer, we therefore have to change the timer (we cannot change VFIO because it doesn't know the details of the device it is assigning to a VM). Luckily, changing the timer is simple, we just need to stop 'caching' the line level, but instead let the VGIC know the state of the timer on every entry to the guest, and the VGIC can ignore notifications using its validate mechanism. Signed-off-by: Christoffer Dall <cdall@linaro.org> --- virt/kvm/arm/arch_timer.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c index 8e89d63..2a5f877 100644 --- a/virt/kvm/arm/arch_timer.c +++ b/virt/kvm/arm/arch_timer.c @@ -219,9 +219,10 @@ static void kvm_timer_update_irq(struct kvm_vcpu *vcpu, bool new_level, int ret; timer_ctx->active_cleared_last = false; + if (timer_ctx->irq.level != new_level) + trace_kvm_timer_update_irq(vcpu->vcpu_id, timer_ctx->irq.irq, + new_level); timer_ctx->irq.level = new_level; - trace_kvm_timer_update_irq(vcpu->vcpu_id, timer_ctx->irq.irq, - timer_ctx->irq.level); if (likely(irqchip_in_kernel(vcpu->kvm))) { ret = kvm_vgic_inject_irq(vcpu->kvm, vcpu->vcpu_id, @@ -241,6 +242,7 @@ static void kvm_timer_update_state(struct kvm_vcpu *vcpu) struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu; struct arch_timer_context *vtimer = vcpu_vtimer(vcpu); struct arch_timer_context *ptimer = vcpu_ptimer(vcpu); + bool level; /* * If userspace modified the timer registers via SET_ONE_REG before @@ -251,11 +253,11 @@ static void kvm_timer_update_state(struct kvm_vcpu *vcpu) if (unlikely(!timer->enabled)) return; - if (kvm_timer_should_fire(vtimer) != vtimer->irq.level) - kvm_timer_update_irq(vcpu, !vtimer->irq.level, vtimer); + level = kvm_timer_should_fire(vtimer); + kvm_timer_update_irq(vcpu, level, vtimer); - if (kvm_timer_should_fire(ptimer) != ptimer->irq.level) - kvm_timer_update_irq(vcpu, !ptimer->irq.level, ptimer); + level = kvm_timer_should_fire(ptimer); + kvm_timer_update_irq(vcpu, level, ptimer); } /* Schedule the background timer for the emulated timer. */ -- 2.9.0
WARNING: multiple messages have this Message-ID (diff)
From: cdall@linaro.org (Christoffer Dall) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 1/6] KVM: arm/arm64: Don't cache the timer IRQ level Date: Mon, 4 Sep 2017 12:24:51 +0200 [thread overview] Message-ID: <20170904102456.9025-2-cdall@linaro.org> (raw) In-Reply-To: <20170904102456.9025-1-cdall@linaro.org> The timer was modeled after a strict idea of modelling an interrupt line level in software, meaning that only transitions in the level needed to be reported to the VGIC. This works well for the timer, because the arch timer code is in complete control of the device and can track the transitions of the line. However, as we are about to support using the HW bit in the VGIC not just for the timer, but also for VFIO which cannot track transitions of the interrupt line, we have to decide on an interface for level triggered mapped interrupts to the GIC, which both the timer and VFIO can use. VFIO only sees an asserting transition of the physical interrupt line, and tells the VGIC when that happens. That means that part of the interrupt flow is offloaded to the hardware. To use the same interface for VFIO devices and the timer, we therefore have to change the timer (we cannot change VFIO because it doesn't know the details of the device it is assigning to a VM). Luckily, changing the timer is simple, we just need to stop 'caching' the line level, but instead let the VGIC know the state of the timer on every entry to the guest, and the VGIC can ignore notifications using its validate mechanism. Signed-off-by: Christoffer Dall <cdall@linaro.org> --- virt/kvm/arm/arch_timer.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c index 8e89d63..2a5f877 100644 --- a/virt/kvm/arm/arch_timer.c +++ b/virt/kvm/arm/arch_timer.c @@ -219,9 +219,10 @@ static void kvm_timer_update_irq(struct kvm_vcpu *vcpu, bool new_level, int ret; timer_ctx->active_cleared_last = false; + if (timer_ctx->irq.level != new_level) + trace_kvm_timer_update_irq(vcpu->vcpu_id, timer_ctx->irq.irq, + new_level); timer_ctx->irq.level = new_level; - trace_kvm_timer_update_irq(vcpu->vcpu_id, timer_ctx->irq.irq, - timer_ctx->irq.level); if (likely(irqchip_in_kernel(vcpu->kvm))) { ret = kvm_vgic_inject_irq(vcpu->kvm, vcpu->vcpu_id, @@ -241,6 +242,7 @@ static void kvm_timer_update_state(struct kvm_vcpu *vcpu) struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu; struct arch_timer_context *vtimer = vcpu_vtimer(vcpu); struct arch_timer_context *ptimer = vcpu_ptimer(vcpu); + bool level; /* * If userspace modified the timer registers via SET_ONE_REG before @@ -251,11 +253,11 @@ static void kvm_timer_update_state(struct kvm_vcpu *vcpu) if (unlikely(!timer->enabled)) return; - if (kvm_timer_should_fire(vtimer) != vtimer->irq.level) - kvm_timer_update_irq(vcpu, !vtimer->irq.level, vtimer); + level = kvm_timer_should_fire(vtimer); + kvm_timer_update_irq(vcpu, level, vtimer); - if (kvm_timer_should_fire(ptimer) != ptimer->irq.level) - kvm_timer_update_irq(vcpu, !ptimer->irq.level, ptimer); + level = kvm_timer_should_fire(ptimer); + kvm_timer_update_irq(vcpu, level, ptimer); } /* Schedule the background timer for the emulated timer. */ -- 2.9.0
next prev parent reply other threads:[~2017-09-04 10:25 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-09-04 10:24 [PATCH v2 0/6] Handle forwarded level-triggered interrupts Christoffer Dall 2017-09-04 10:24 ` Christoffer Dall 2017-09-04 10:24 ` Christoffer Dall [this message] 2017-09-04 10:24 ` [PATCH v2 1/6] KVM: arm/arm64: Don't cache the timer IRQ level Christoffer Dall 2017-09-04 10:24 ` [PATCH v2 2/6] KVM: arm/arm64: vgic: restructure kvm_vgic_(un)map_phys_irq Christoffer Dall 2017-09-04 10:24 ` Christoffer Dall 2017-09-04 10:24 ` [PATCH v2 3/6] KVM: arm/arm64: vgic: Support level-triggered mapped interrupts Christoffer Dall 2017-09-04 10:24 ` Christoffer Dall 2017-09-05 9:38 ` Auger Eric 2017-09-05 9:38 ` Auger Eric 2017-09-05 13:57 ` Christoffer Dall 2017-09-05 13:57 ` Christoffer Dall 2017-09-04 10:24 ` [PATCH v2 4/6] KVM: arm/arm64: Support VGIC dist pend/active changes for mapped IRQs Christoffer Dall 2017-09-04 10:24 ` Christoffer Dall 2017-09-04 10:24 ` [PATCH v2 5/6] KVM: arm/arm64: Rearrange kvm_vgic_[un]map_phys code in vgic.c Christoffer Dall 2017-09-04 10:24 ` Christoffer Dall 2017-09-05 10:26 ` Auger Eric 2017-09-05 10:26 ` Auger Eric 2017-09-05 14:00 ` Christoffer Dall 2017-09-05 14:00 ` Christoffer Dall 2017-09-05 14:49 ` Auger Eric 2017-09-05 14:49 ` Auger Eric 2017-09-04 10:24 ` [PATCH v2 6/6] KVM: arm/arm64: Provide a vgic interrupt line level sample function Christoffer Dall 2017-09-04 10:24 ` Christoffer Dall
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