* [Qemu-devel] [PULL 01/40] hw/ppc/spapr_drc.c: change spapr_drc_needed to use drc->dev
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 02/40] hw/ppc: clear pending_events on machine reset David Gibson
` (39 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
Daniel Henrique Barboza, David Gibson
From: Daniel Henrique Barboza <danielhb@linux.vnet.ibm.com>
This patch makes a small fix in 'spapr_drc_needed' to change how we detect
if a DRC has a device attached. Previously it used dr_entity_sense for this,
which works for physical DRCs.
However, for logical DRCs, it didn't cover the case where a logical DRC has
a drc->dev but the state is LOGICAL_UNUSABLE (e.g. a hotplugged CPU before
CAS). In this case, the dr_entity_sense of this DRC returns UNUSABLE and the
code was considering that there were no dev attached, making spapr_drc_needed
return 'false' when in fact we would like to migrate the DRC.
Changing it to check for drc->dev instead works for all DRC types.
Signed-off-by: Daniel Henrique Barboza <danielhb@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr_drc.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/ppc/spapr_drc.c b/hw/ppc/spapr_drc.c
index 605697d8bd..031ba7c387 100644
--- a/hw/ppc/spapr_drc.c
+++ b/hw/ppc/spapr_drc.c
@@ -464,10 +464,9 @@ static bool spapr_drc_needed(void *opaque)
{
sPAPRDRConnector *drc = (sPAPRDRConnector *)opaque;
sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
- sPAPRDREntitySense value = drck->dr_entity_sense(drc);
/* If no dev is plugged in there is no need to migrate the DRC state */
- if (value != SPAPR_DR_ENTITY_SENSE_PRESENT) {
+ if (!drc->dev) {
return false;
}
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 02/40] hw/ppc: clear pending_events on machine reset
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 01/40] hw/ppc/spapr_drc.c: change spapr_drc_needed to use drc->dev David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-12 17:28 ` Peter Maydell
2017-09-08 10:35 ` [Qemu-devel] [PULL 03/40] hw/ppc: CAS reset on early device hotplug David Gibson
` (38 subsequent siblings)
40 siblings, 1 reply; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
Daniel Henrique Barboza, David Gibson
From: Daniel Henrique Barboza <danielhb@linux.vnet.ibm.com>
The sPAPR machine isn't clearing up the pending events QTAILQ on
machine reboot. This allows for unprocessed hotplug/epow events
to persist in the queue after reset and, when reasserting the IRQs in
check_exception later on, these will be being processed by the OS.
This patch implements a new function called 'spapr_clear_pending_events'
that clears up the pending_events QTAILQ. This helper is then called
inside ppc_spapr_reset to clear up the events queue, preventing
old/deprecated events from persisting after a reset.
Signed-off-by: Daniel Henrique Barboza <danielhb@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr.c | 1 +
hw/ppc/spapr_events.c | 11 +++++++++++
include/hw/ppc/spapr.h | 1 +
3 files changed, 13 insertions(+)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index cec441cbf4..0e5f29d348 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1392,6 +1392,7 @@ static void ppc_spapr_reset(void)
}
qemu_devices_reset();
+ spapr_clear_pending_events(spapr);
/*
* We place the device tree and RTAS just below either the top of the RMA,
diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c
index f952b78237..66b8164f30 100644
--- a/hw/ppc/spapr_events.c
+++ b/hw/ppc/spapr_events.c
@@ -700,6 +700,17 @@ static void event_scan(PowerPCCPU *cpu, sPAPRMachineState *spapr,
rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND);
}
+void spapr_clear_pending_events(sPAPRMachineState *spapr)
+{
+ sPAPREventLogEntry *entry = NULL;
+
+ QTAILQ_FOREACH(entry, &spapr->pending_events, next) {
+ QTAILQ_REMOVE(&spapr->pending_events, entry, next);
+ g_free(entry->extended_log);
+ g_free(entry);
+ }
+}
+
void spapr_events_init(sPAPRMachineState *spapr)
{
QTAILQ_INIT(&spapr->pending_events);
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 2a303a705c..5d161ec580 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -662,6 +662,7 @@ void spapr_cpu_parse_features(sPAPRMachineState *spapr);
int spapr_hpt_shift_for_ramsize(uint64_t ramsize);
void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
Error **errp);
+void spapr_clear_pending_events(sPAPRMachineState *spapr);
/* CPU and LMB DRC release callbacks. */
void spapr_core_release(DeviceState *dev);
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [Qemu-devel] [PULL 02/40] hw/ppc: clear pending_events on machine reset
2017-09-08 10:35 ` [Qemu-devel] [PULL 02/40] hw/ppc: clear pending_events on machine reset David Gibson
@ 2017-09-12 17:28 ` Peter Maydell
2017-09-12 18:27 ` [Qemu-devel] [Qemu-ppc] " Greg Kurz
0 siblings, 1 reply; 44+ messages in thread
From: Peter Maydell @ 2017-09-12 17:28 UTC (permalink / raw)
To: David Gibson
Cc: Alexander Graf, Michael Roth, Alexey Kardashevskiy, Sam Bobroff,
Igor Mammedov, qemu-ppc, QEMU Developers,
Daniel Henrique Barboza
On 8 September 2017 at 11:35, David Gibson <david@gibson.dropbear.id.au> wrote:
> From: Daniel Henrique Barboza <danielhb@linux.vnet.ibm.com>
>
> The sPAPR machine isn't clearing up the pending events QTAILQ on
> machine reboot. This allows for unprocessed hotplug/epow events
> to persist in the queue after reset and, when reasserting the IRQs in
> check_exception later on, these will be being processed by the OS.
>
> This patch implements a new function called 'spapr_clear_pending_events'
> that clears up the pending_events QTAILQ. This helper is then called
> inside ppc_spapr_reset to clear up the events queue, preventing
> old/deprecated events from persisting after a reset.
>
> Signed-off-by: Daniel Henrique Barboza <danielhb@linux.vnet.ibm.com>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> +void spapr_clear_pending_events(sPAPRMachineState *spapr)
> +{
> + sPAPREventLogEntry *entry = NULL;
> +
> + QTAILQ_FOREACH(entry, &spapr->pending_events, next) {
> + QTAILQ_REMOVE(&spapr->pending_events, entry, next);
> + g_free(entry->extended_log);
> + g_free(entry);
> + }
> +}
Coverity points out that this is a use-after-free error,
because QTAILQ_FOREACH will access the list pointers of
entry after the loop body has freed it. You want
QTAILQ_FOREACH_SAFE, I think. (CID 1381017)
thanks
-- PMM
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [Qemu-devel] [Qemu-ppc] [PULL 02/40] hw/ppc: clear pending_events on machine reset
2017-09-12 17:28 ` Peter Maydell
@ 2017-09-12 18:27 ` Greg Kurz
0 siblings, 0 replies; 44+ messages in thread
From: Greg Kurz @ 2017-09-12 18:27 UTC (permalink / raw)
To: Peter Maydell
Cc: David Gibson, QEMU Developers, Michael Roth, qemu-ppc,
Igor Mammedov, Daniel Henrique Barboza, Sam Bobroff
[-- Attachment #1: Type: text/plain, Size: 1675 bytes --]
On Tue, 12 Sep 2017 18:28:04 +0100
Peter Maydell <peter.maydell@linaro.org> wrote:
> On 8 September 2017 at 11:35, David Gibson <david@gibson.dropbear.id.au> wrote:
> > From: Daniel Henrique Barboza <danielhb@linux.vnet.ibm.com>
> >
> > The sPAPR machine isn't clearing up the pending events QTAILQ on
> > machine reboot. This allows for unprocessed hotplug/epow events
> > to persist in the queue after reset and, when reasserting the IRQs in
> > check_exception later on, these will be being processed by the OS.
> >
> > This patch implements a new function called 'spapr_clear_pending_events'
> > that clears up the pending_events QTAILQ. This helper is then called
> > inside ppc_spapr_reset to clear up the events queue, preventing
> > old/deprecated events from persisting after a reset.
> >
> > Signed-off-by: Daniel Henrique Barboza <danielhb@linux.vnet.ibm.com>
> > Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
>
> > +void spapr_clear_pending_events(sPAPRMachineState *spapr)
> > +{
> > + sPAPREventLogEntry *entry = NULL;
> > +
> > + QTAILQ_FOREACH(entry, &spapr->pending_events, next) {
> > + QTAILQ_REMOVE(&spapr->pending_events, entry, next);
> > + g_free(entry->extended_log);
> > + g_free(entry);
> > + }
> > +}
>
> Coverity points out that this is a use-after-free error,
> because QTAILQ_FOREACH will access the list pointers of
> entry after the loop body has freed it. You want
> QTAILQ_FOREACH_SAFE, I think. (CID 1381017)
>
Yes indeed, QTAILQ_FOREACH_SAFE() is needed when removing
the current element from the list. I'll send a patch.
> thanks
> -- PMM
>
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 44+ messages in thread
* [Qemu-devel] [PULL 03/40] hw/ppc: CAS reset on early device hotplug
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 01/40] hw/ppc/spapr_drc.c: change spapr_drc_needed to use drc->dev David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 02/40] hw/ppc: clear pending_events on machine reset David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 04/40] spapr_pci: use memory_region_add_subregion() with DMA windows David Gibson
` (37 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
Daniel Henrique Barboza, David Gibson
From: Daniel Henrique Barboza <danielhb@linux.vnet.ibm.com>
This patch is a follow up on the discussions made in patch
"hw/ppc: disable hotplug before CAS is completed" that can be
found at [1].
At this moment, we do not support CPU/memory hotplug in early
boot stages, before CAS. When a hotplug occurs, the event is logged
in an internal RTAS event log queue and an IRQ pulse is fired. In
regular conditions, the guest handles the interrupt by executing
check_exception, fetching the generated hotplug event and enabling
the device for use.
In early boot, this IRQ isn't caught (SLOF does not handle hotplug
events), leaving the event in the rtas event log queue. If the guest
executes check_exception due to another hotplug event, the re-assertion
of the IRQ ends up de-queuing the first hotplug event as well. In short,
a device hotplugged before CAS is considered coldplugged by SLOF.
This leads to device misbehavior and, in some cases, guest kernel
Ooops when trying to unplug the device.
A proper fix would be to turn every device hotplugged before CAS
as a colplugged device. This is not trivial to do with the current
code base though - the FDT is written in the guest memory at
ppc_spapr_reset and can't be retrieved without adding extra state
(fdt_size for example) that will need to managed and migrated. Adding
the hotplugged DT in the middle of CAS negotiation via the updated DT
tree works with CPU devs, but panics the guest kernel at boot. Additional
analysis would be necessary for LMBs and PCI devices. There are
questions to be made in QEMU/SLOF/kernel level about how we can make
this change in a sustainable way.
With Linux guests, a fix would be the kernel executing check_exception
at boot time, de-queueing the events that happened in early boot and
processing them. However, even if/when the newer kernels start
fetching these events at boot time, we need to take care of older
kernels that won't be doing that.
This patch works around the situation by issuing a CAS reset if a hotplugged
device is detected during CAS:
- the DRC conditions that warrant a CAS reset is the same as those that
triggers a DRC migration - the DRC must have a device attached and
the DRC state is not equal to its ready_state. With that in mind, this
patch makes use of 'spapr_drc_needed' to determine if a CAS reset
is needed.
- In the middle of CAS negotiations, the function
'spapr_hotplugged_dev_before_cas' goes through all the DRCs to see
if there are any DRC that requires a reset, using spapr_drc_needed. If
that happens, returns '1' in 'spapr_h_cas_compose_response' which will set
spapr->cas_reboot to true, causing the machine to reboot.
No changes are made for coldplug devices.
[1] http://lists.nongnu.org/archive/html/qemu-devel/2017-08/msg02855.html
Signed-off-by: Daniel Henrique Barboza <danielhb@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr.c | 26 +++++++++++++++++++++++++-
hw/ppc/spapr_drc.c | 2 +-
include/hw/ppc/spapr_drc.h | 1 +
3 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 0e5f29d348..954fd1a747 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -790,6 +790,26 @@ out:
return ret;
}
+static bool spapr_hotplugged_dev_before_cas(void)
+{
+ Object *drc_container, *obj;
+ ObjectProperty *prop;
+ ObjectPropertyIterator iter;
+
+ drc_container = container_get(object_get_root(), "/dr-connector");
+ object_property_iter_init(&iter, drc_container);
+ while ((prop = object_property_iter_next(&iter))) {
+ if (!strstart(prop->type, "link<", NULL)) {
+ continue;
+ }
+ obj = object_property_get_link(drc_container, prop->name, NULL);
+ if (spapr_drc_needed(obj)) {
+ return true;
+ }
+ }
+ return false;
+}
+
int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
target_ulong addr, target_ulong size,
sPAPROptionVector *ov5_updates)
@@ -797,9 +817,13 @@ int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
void *fdt, *fdt_skel;
sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
+ if (spapr_hotplugged_dev_before_cas()) {
+ return 1;
+ }
+
size -= sizeof(hdr);
- /* Create sceleton */
+ /* Create skeleton */
fdt_skel = g_malloc0(size);
_FDT((fdt_create(fdt_skel, size)));
_FDT((fdt_begin_node(fdt_skel, "")));
diff --git a/hw/ppc/spapr_drc.c b/hw/ppc/spapr_drc.c
index 031ba7c387..85c999d9cb 100644
--- a/hw/ppc/spapr_drc.c
+++ b/hw/ppc/spapr_drc.c
@@ -460,7 +460,7 @@ static void drc_reset(void *opaque)
spapr_drc_reset(SPAPR_DR_CONNECTOR(opaque));
}
-static bool spapr_drc_needed(void *opaque)
+bool spapr_drc_needed(void *opaque)
{
sPAPRDRConnector *drc = (sPAPRDRConnector *)opaque;
sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
diff --git a/include/hw/ppc/spapr_drc.h b/include/hw/ppc/spapr_drc.h
index a7958d0a8d..f8d9f5b231 100644
--- a/include/hw/ppc/spapr_drc.h
+++ b/include/hw/ppc/spapr_drc.h
@@ -257,6 +257,7 @@ int spapr_drc_populate_dt(void *fdt, int fdt_offset, Object *owner,
void spapr_drc_attach(sPAPRDRConnector *drc, DeviceState *d, void *fdt,
int fdt_start_offset, Error **errp);
void spapr_drc_detach(sPAPRDRConnector *drc);
+bool spapr_drc_needed(void *opaque);
static inline bool spapr_drc_unplug_requested(sPAPRDRConnector *drc)
{
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 04/40] spapr_pci: use memory_region_add_subregion() with DMA windows
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (2 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 03/40] hw/ppc: CAS reset on early device hotplug David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 05/40] spapr_iommu: use g_strdup_printf() instead of snprintf() David Gibson
` (36 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
Greg Kurz, David Gibson
From: Greg Kurz <groug@kaod.org>
Passing a null priority to memory_region_add_subregion_overlap() is
strictly equivalent to calling memory_region_add_subregion().
Signed-off-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr_pci.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index d84abf1070..d258bc08d5 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -1752,8 +1752,8 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp)
i, sphb->dtbusname);
return;
}
- memory_region_add_subregion_overlap(&sphb->iommu_root, 0,
- spapr_tce_get_iommu(tcet), 0);
+ memory_region_add_subregion(&sphb->iommu_root, 0,
+ spapr_tce_get_iommu(tcet));
}
sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free);
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 05/40] spapr_iommu: use g_strdup_printf() instead of snprintf()
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (3 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 04/40] spapr_pci: use memory_region_add_subregion() with DMA windows David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 06/40] spapr_drc: " David Gibson
` (35 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
Greg Kurz, David Gibson
From: Greg Kurz <groug@kaod.org>
Passing a stack allocated buffer of arbitrary length to snprintf()
without checking the return value can cause the resultant strings
to be silently truncated.
Signed-off-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr_iommu.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/hw/ppc/spapr_iommu.c b/hw/ppc/spapr_iommu.c
index ed2d53559a..ed4388bd75 100644
--- a/hw/ppc/spapr_iommu.c
+++ b/hw/ppc/spapr_iommu.c
@@ -252,17 +252,19 @@ static int spapr_tce_table_realize(DeviceState *dev)
{
sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev);
Object *tcetobj = OBJECT(tcet);
- char tmp[32];
+ gchar *tmp;
tcet->fd = -1;
tcet->need_vfio = false;
- snprintf(tmp, sizeof(tmp), "tce-root-%x", tcet->liobn);
+ tmp = g_strdup_printf("tce-root-%x", tcet->liobn);
memory_region_init(&tcet->root, tcetobj, tmp, UINT64_MAX);
+ g_free(tmp);
- snprintf(tmp, sizeof(tmp), "tce-iommu-%x", tcet->liobn);
+ tmp = g_strdup_printf("tce-iommu-%x", tcet->liobn);
memory_region_init_iommu(&tcet->iommu, sizeof(tcet->iommu),
TYPE_SPAPR_IOMMU_MEMORY_REGION,
tcetobj, tmp, 0);
+ g_free(tmp);
QLIST_INSERT_HEAD(&spapr_tce_tables, tcet, list);
@@ -307,7 +309,7 @@ void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio)
sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn)
{
sPAPRTCETable *tcet;
- char tmp[32];
+ gchar *tmp;
if (spapr_tce_find_by_liobn(liobn)) {
error_report("Attempted to create TCE table with duplicate"
@@ -318,8 +320,9 @@ sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn)
tcet = SPAPR_TCE_TABLE(object_new(TYPE_SPAPR_TCE_TABLE));
tcet->liobn = liobn;
- snprintf(tmp, sizeof(tmp), "tce-table-%x", liobn);
+ tmp = g_strdup_printf("tce-table-%x", liobn);
object_property_add_child(OBJECT(owner), tmp, OBJECT(tcet), NULL);
+ g_free(tmp);
object_property_set_bool(OBJECT(tcet), true, "realized", NULL);
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 06/40] spapr_drc: use g_strdup_printf() instead of snprintf()
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (4 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 05/40] spapr_iommu: use g_strdup_printf() instead of snprintf() David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 07/40] spapr_iommu: convert TCE table object to realize() David Gibson
` (34 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
Greg Kurz, David Gibson
From: Greg Kurz <groug@kaod.org>
Passing a stack allocated buffer of arbitrary length to snprintf()
without checking the return value can cause the resultant strings
to be silently truncated.
Signed-off-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr_drc.c | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/hw/ppc/spapr_drc.c b/hw/ppc/spapr_drc.c
index 85c999d9cb..644a6fffaf 100644
--- a/hw/ppc/spapr_drc.c
+++ b/hw/ppc/spapr_drc.c
@@ -492,7 +492,7 @@ static void realize(DeviceState *d, Error **errp)
{
sPAPRDRConnector *drc = SPAPR_DR_CONNECTOR(d);
Object *root_container;
- char link_name[256];
+ gchar *link_name;
gchar *child_name;
Error *err = NULL;
@@ -505,12 +505,13 @@ static void realize(DeviceState *d, Error **errp)
* existing in the composition tree
*/
root_container = container_get(object_get_root(), DRC_CONTAINER_PATH);
- snprintf(link_name, sizeof(link_name), "%x", spapr_drc_index(drc));
+ link_name = g_strdup_printf("%x", spapr_drc_index(drc));
child_name = object_get_canonical_path_component(OBJECT(drc));
trace_spapr_drc_realize_child(spapr_drc_index(drc), child_name);
object_property_add_alias(root_container, link_name,
drc->owner, child_name, &err);
g_free(child_name);
+ g_free(link_name);
if (err) {
error_propagate(errp, err);
return;
@@ -525,14 +526,15 @@ static void unrealize(DeviceState *d, Error **errp)
{
sPAPRDRConnector *drc = SPAPR_DR_CONNECTOR(d);
Object *root_container;
- char name[256];
+ gchar *name;
trace_spapr_drc_unrealize(spapr_drc_index(drc));
qemu_unregister_reset(drc_reset, drc);
vmstate_unregister(DEVICE(drc), &vmstate_spapr_drc, drc);
root_container = container_get(object_get_root(), DRC_CONTAINER_PATH);
- snprintf(name, sizeof(name), "%x", spapr_drc_index(drc));
+ name = g_strdup_printf("%x", spapr_drc_index(drc));
object_property_del(root_container, name, errp);
+ g_free(name);
}
sPAPRDRConnector *spapr_dr_connector_new(Object *owner, const char *type,
@@ -730,10 +732,11 @@ static const TypeInfo spapr_drc_lmb_info = {
sPAPRDRConnector *spapr_drc_by_index(uint32_t index)
{
Object *obj;
- char name[256];
+ gchar *name;
- snprintf(name, sizeof(name), "%s/%x", DRC_CONTAINER_PATH, index);
+ name = g_strdup_printf("%s/%x", DRC_CONTAINER_PATH, index);
obj = object_resolve_path(name, NULL);
+ g_free(name);
return !obj ? NULL : SPAPR_DR_CONNECTOR(obj);
}
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 07/40] spapr_iommu: convert TCE table object to realize()
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (5 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 06/40] spapr_drc: " David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 08/40] spapr_pci: parent the MSI memory region to the PHB David Gibson
` (33 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
Greg Kurz, David Gibson
From: Greg Kurz <groug@kaod.org>
Signed-off-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr_iommu.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/spapr_iommu.c b/hw/ppc/spapr_iommu.c
index ed4388bd75..84d03df5ef 100644
--- a/hw/ppc/spapr_iommu.c
+++ b/hw/ppc/spapr_iommu.c
@@ -248,7 +248,7 @@ static const VMStateDescription vmstate_spapr_tce_table = {
}
};
-static int spapr_tce_table_realize(DeviceState *dev)
+static void spapr_tce_table_realize(DeviceState *dev, Error **errp)
{
sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev);
Object *tcetobj = OBJECT(tcet);
@@ -270,8 +270,6 @@ static int spapr_tce_table_realize(DeviceState *dev)
vmstate_register(DEVICE(tcet), tcet->liobn, &vmstate_spapr_tce_table,
tcet);
-
- return 0;
}
void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio)
@@ -618,7 +616,7 @@ int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
static void spapr_tce_table_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->init = spapr_tce_table_realize;
+ dc->realize = spapr_tce_table_realize;
dc->reset = spapr_tce_reset;
dc->unrealize = spapr_tce_table_unrealize;
/* Reason: This is just an internal device for handling the hypercalls */
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 08/40] spapr_pci: parent the MSI memory region to the PHB
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (6 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 07/40] spapr_iommu: convert TCE table object to realize() David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 09/40] spapr_drc: add unrealize method to physical DRC class David Gibson
` (32 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
Greg Kurz, David Gibson
From: Greg Kurz <groug@kaod.org>
This memory region should be owned by the PHB. This ensures the PHB
cannot be finalized as long as the the region is guest visible, or
used by a CPU or a device.
Signed-off-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr_pci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index d258bc08d5..d7880f257a 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -1703,7 +1703,7 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp)
}
#endif
- memory_region_init_io(&sphb->msiwindow, NULL, &spapr_msi_ops, spapr,
+ memory_region_init_io(&sphb->msiwindow, OBJECT(sphb), &spapr_msi_ops, spapr,
"msi", msi_window_size);
memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW,
&sphb->msiwindow);
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 09/40] spapr_drc: add unrealize method to physical DRC class
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (7 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 08/40] spapr_pci: parent the MSI memory region to the PHB David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 10/40] spapr_drc: pass object ownership to parent/owner David Gibson
` (31 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
Greg Kurz, David Gibson
From: Greg Kurz <groug@kaod.org>
When hot-unplugging a PHB, all its PCI DRC connectors get unrealized. This
patch adds an unrealize method to the physical DRC class, in order to undo
registrations performed in realize_physical().
Signed-off-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr_drc.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/hw/ppc/spapr_drc.c b/hw/ppc/spapr_drc.c
index 644a6fffaf..b10f849d37 100644
--- a/hw/ppc/spapr_drc.c
+++ b/hw/ppc/spapr_drc.c
@@ -630,12 +630,28 @@ static void realize_physical(DeviceState *d, Error **errp)
qemu_register_reset(drc_physical_reset, drcp);
}
+static void unrealize_physical(DeviceState *d, Error **errp)
+{
+ sPAPRDRCPhysical *drcp = SPAPR_DRC_PHYSICAL(d);
+ Error *local_err = NULL;
+
+ unrealize(d, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ vmstate_unregister(DEVICE(drcp), &vmstate_spapr_drc_physical, drcp);
+ qemu_unregister_reset(drc_physical_reset, drcp);
+}
+
static void spapr_drc_physical_class_init(ObjectClass *k, void *data)
{
DeviceClass *dk = DEVICE_CLASS(k);
sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_CLASS(k);
dk->realize = realize_physical;
+ dk->unrealize = unrealize_physical;
drck->dr_entity_sense = physical_entity_sense;
drck->isolate = drc_isolate_physical;
drck->unisolate = drc_unisolate_physical;
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 10/40] spapr_drc: pass object ownership to parent/owner
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (8 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 09/40] spapr_drc: add unrealize method to physical DRC class David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 11/40] spapr_iommu: " David Gibson
` (30 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
Greg Kurz, David Gibson
From: Michael Roth <mdroth@linux.vnet.ibm.com>
DRC objects attach themselves to an owner as a child
property. unref afterward to allow them to be finalized
when their owner is finalized.
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr_drc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/ppc/spapr_drc.c b/hw/ppc/spapr_drc.c
index b10f849d37..915e9b51c4 100644
--- a/hw/ppc/spapr_drc.c
+++ b/hw/ppc/spapr_drc.c
@@ -548,6 +548,7 @@ sPAPRDRConnector *spapr_dr_connector_new(Object *owner, const char *type,
prop_name = g_strdup_printf("dr-connector[%"PRIu32"]",
spapr_drc_index(drc));
object_property_add_child(owner, prop_name, OBJECT(drc), &error_abort);
+ object_unref(OBJECT(drc));
object_property_set_bool(OBJECT(drc), true, "realized", NULL);
g_free(prop_name);
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 11/40] spapr_iommu: pass object ownership to parent/owner
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (9 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 10/40] spapr_drc: pass object ownership to parent/owner David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 12/40] spapr_iommu: unregister vmstate at unrealize time David Gibson
` (29 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
Greg Kurz, David Gibson
From: Michael Roth <mdroth@linux.vnet.ibm.com>
TCE table objects attach themselves to an owner as a child
property. unref afterward to allow them to be finalized
when their owner is finalized.
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr_iommu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/ppc/spapr_iommu.c b/hw/ppc/spapr_iommu.c
index 84d03df5ef..25c5f6d795 100644
--- a/hw/ppc/spapr_iommu.c
+++ b/hw/ppc/spapr_iommu.c
@@ -321,6 +321,7 @@ sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn)
tmp = g_strdup_printf("tce-table-%x", liobn);
object_property_add_child(OBJECT(owner), tmp, OBJECT(tcet), NULL);
g_free(tmp);
+ object_unref(OBJECT(tcet));
object_property_set_bool(OBJECT(tcet), true, "realized", NULL);
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 12/40] spapr_iommu: unregister vmstate at unrealize time
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (10 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 11/40] spapr_iommu: " David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 13/40] spapr: add pseries-2.11 machine type David Gibson
` (28 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
Greg Kurz, David Gibson
From: Greg Kurz <groug@kaod.org>
Signed-off-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr_iommu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/ppc/spapr_iommu.c b/hw/ppc/spapr_iommu.c
index 25c5f6d795..a75584c947 100644
--- a/hw/ppc/spapr_iommu.c
+++ b/hw/ppc/spapr_iommu.c
@@ -374,6 +374,8 @@ static void spapr_tce_table_unrealize(DeviceState *dev, Error **errp)
{
sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev);
+ vmstate_unregister(DEVICE(tcet), &vmstate_spapr_tce_table, tcet);
+
QLIST_REMOVE(tcet, list);
spapr_tce_table_disable(tcet);
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 13/40] spapr: add pseries-2.11 machine type
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (11 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 12/40] spapr_iommu: unregister vmstate at unrealize time David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 14/40] e500: Use cpu_index instead of vcpu_dt_id David Gibson
` (27 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
Greg Kurz, David Gibson
From: Greg Kurz <groug@kaod.org>
Signed-off-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr.c | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 954fd1a747..a0c5923776 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -3563,18 +3563,36 @@ static const TypeInfo spapr_machine_info = {
type_init(spapr_machine_register_##suffix)
/*
+ * pseries-2.11
+ */
+static void spapr_machine_2_11_instance_options(MachineState *machine)
+{
+}
+
+static void spapr_machine_2_11_class_options(MachineClass *mc)
+{
+ /* Defaults for the latest behaviour inherited from the base class */
+}
+
+DEFINE_SPAPR_MACHINE(2_11, "2.11", true);
+
+/*
* pseries-2.10
*/
+#define SPAPR_COMPAT_2_10 \
+ HW_COMPAT_2_10 \
+
static void spapr_machine_2_10_instance_options(MachineState *machine)
{
}
static void spapr_machine_2_10_class_options(MachineClass *mc)
{
- /* Defaults for the latest behaviour inherited from the base class */
+ spapr_machine_2_11_class_options(mc);
+ SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_10);
}
-DEFINE_SPAPR_MACHINE(2_10, "2.10", true);
+DEFINE_SPAPR_MACHINE(2_10, "2.10", false);
/*
* pseries-2.9
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 14/40] e500: Use cpu_index instead of vcpu_dt_id
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (12 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 13/40] spapr: add pseries-2.11 machine type David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 15/40] ppc: spapr: Rename cpu_dt_id to vcpu_id David Gibson
` (26 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
David Gibson
From: Sam Bobroff <sam.bobroff@au1.ibm.com>
The e500 platform code uses the function ppc_get_vcpu_dt_id() to get
an id to put in its device tree. Which seems like it makes sense, but
ppc_get_vcpu_dt_id() is actually badly named - it only differs from
cpu_index in cases where you're running on KVM HV and the host's
number of threads differs from the guests. Since KVM HV only supports
PAPR, not e500, it doesn't make sense to use it here.
Simply use the cpu_index instead (which is 'i' in this context
because qemu_get_cpu(i) returns the cpu with cpu_index == i).
Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
[dwg: Rewrote commit message]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/e500.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index f0596f34ff..55cad780f4 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -382,7 +382,6 @@ static int ppce500_load_device_tree(MachineState *machine,
the first node as boot node and be happy */
for (i = smp_cpus - 1; i >= 0; i--) {
CPUState *cpu;
- PowerPCCPU *pcpu;
char cpu_name[128];
uint64_t cpu_release_addr = params->spin_base + (i * 0x20);
@@ -391,16 +390,13 @@ static int ppce500_load_device_tree(MachineState *machine,
continue;
}
env = cpu->env_ptr;
- pcpu = POWERPC_CPU(cpu);
- snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x",
- ppc_get_vcpu_dt_id(pcpu));
+ snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", i);
qemu_fdt_add_subnode(fdt, cpu_name);
qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
- qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
- ppc_get_vcpu_dt_id(pcpu));
+ qemu_fdt_setprop_cell(fdt, cpu_name, "reg", i);
qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size",
env->dcache_line_size);
qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size",
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 15/40] ppc: spapr: Rename cpu_dt_id to vcpu_id
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (13 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 14/40] e500: Use cpu_index instead of vcpu_dt_id David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 16/40] ppc: spapr: Make VCPU ID handling private to SPAPR David Gibson
` (25 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
David Gibson
From: Sam Bobroff <sam.bobroff@au1.ibm.com>
This field actually records the VCPU ID used by KVM and, although the
value is also used in the device tree it is primarily the VCPU ID so
rename it as such.
Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com>
[dwg: Updated comment missed in cpu.h]
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/ppc.c | 8 ++++----
hw/ppc/spapr.c | 16 ++++++++--------
hw/ppc/spapr_hcall.c | 4 ++--
hw/ppc/spapr_rtas.c | 4 ++--
target/ppc/cpu.h | 16 ++++++++--------
target/ppc/kvm.c | 2 +-
target/ppc/translate_init.c | 8 ++++----
7 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index 224184d66d..4477d4ad89 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -1359,19 +1359,19 @@ void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
}
/* CPU device-tree ID helpers */
-int ppc_get_vcpu_dt_id(PowerPCCPU *cpu)
+int ppc_get_vcpu_id(PowerPCCPU *cpu)
{
- return cpu->cpu_dt_id;
+ return cpu->vcpu_id;
}
-PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id)
+PowerPCCPU *ppc_get_cpu_by_vcpu_id(int vcpu_id)
{
CPUState *cs;
CPU_FOREACH(cs) {
PowerPCCPU *cpu = POWERPC_CPU(cs);
- if (cpu->cpu_dt_id == cpu_dt_id) {
+ if (cpu->vcpu_id == vcpu_id) {
return cpu;
}
}
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index a0c5923776..f7a4c73e08 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -208,7 +208,7 @@ static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
int i, ret = 0;
uint32_t servers_prop[smt_threads];
uint32_t gservers_prop[smt_threads * 2];
- int index = ppc_get_vcpu_dt_id(cpu);
+ int index = ppc_get_vcpu_id(cpu);
if (cpu->compat_pvr) {
ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
@@ -237,7 +237,7 @@ static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu)
{
- int index = ppc_get_vcpu_dt_id(cpu);
+ int index = ppc_get_vcpu_id(cpu);
uint32_t associativity[] = {cpu_to_be32(0x5),
cpu_to_be32(0x0),
cpu_to_be32(0x0),
@@ -341,7 +341,7 @@ static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = &cpu->env;
DeviceClass *dc = DEVICE_GET_CLASS(cs);
- int index = ppc_get_vcpu_dt_id(cpu);
+ int index = ppc_get_vcpu_id(cpu);
int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu));
if ((index % smt) != 0) {
@@ -493,7 +493,7 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = &cpu->env;
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
- int index = ppc_get_vcpu_dt_id(cpu);
+ int index = ppc_get_vcpu_id(cpu);
uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
0xffffffff, 0xffffffff};
uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
@@ -626,7 +626,7 @@ static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
*/
CPU_FOREACH_REVERSE(cs) {
PowerPCCPU *cpu = POWERPC_CPU(cs);
- int index = ppc_get_vcpu_dt_id(cpu);
+ int index = ppc_get_vcpu_id(cpu);
DeviceClass *dc = DEVICE_GET_CLASS(cs);
int offset;
@@ -3025,7 +3025,7 @@ static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
DeviceClass *dc = DEVICE_GET_CLASS(cs);
- int id = ppc_get_vcpu_dt_id(cpu);
+ int id = ppc_get_vcpu_id(cpu);
void *fdt;
int offset, fdt_size;
char *nodename;
@@ -3433,9 +3433,9 @@ static void spapr_ics_resend(XICSFabric *dev)
ics_resend(spapr->ics);
}
-static ICPState *spapr_icp_get(XICSFabric *xi, int cpu_dt_id)
+static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id)
{
- PowerPCCPU *cpu = ppc_get_vcpu_by_dt_id(cpu_dt_id);
+ PowerPCCPU *cpu = ppc_get_cpu_by_vcpu_id(vcpu_id);
return cpu ? ICP(cpu->intc) : NULL;
}
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 07b3da8dc4..4ca233854a 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -999,7 +999,7 @@ static target_ulong h_register_vpa(PowerPCCPU *cpu, sPAPRMachineState *spapr,
CPUPPCState *tenv;
PowerPCCPU *tcpu;
- tcpu = ppc_get_vcpu_by_dt_id(procno);
+ tcpu = ppc_get_cpu_by_vcpu_id(procno);
if (!tcpu) {
return H_PARAMETER;
}
@@ -1431,7 +1431,7 @@ static target_ulong h_signal_sys_reset(PowerPCCPU *cpu,
} else {
/* Unicast */
- cs = CPU(ppc_get_vcpu_by_dt_id(target));
+ cs = CPU(ppc_get_cpu_by_vcpu_id(target));
if (cs) {
run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
return H_SUCCESS;
diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
index 94a2799b99..626c06b375 100644
--- a/hw/ppc/spapr_rtas.c
+++ b/hw/ppc/spapr_rtas.c
@@ -104,7 +104,7 @@ static void rtas_query_cpu_stopped_state(PowerPCCPU *cpu_,
}
id = rtas_ld(args, 0);
- cpu = ppc_get_vcpu_by_dt_id(id);
+ cpu = ppc_get_cpu_by_vcpu_id(id);
if (cpu != NULL) {
if (CPU(cpu)->halted) {
rtas_st(rets, 1, 0);
@@ -158,7 +158,7 @@ static void rtas_start_cpu(PowerPCCPU *cpu_, sPAPRMachineState *spapr,
start = rtas_ld(args, 1);
r3 = rtas_ld(args, 2);
- cpu = ppc_get_vcpu_by_dt_id(id);
+ cpu = ppc_get_cpu_by_vcpu_id(id);
if (cpu != NULL) {
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 12f09492fb..687e66acde 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1188,7 +1188,7 @@ typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
/**
* PowerPCCPU:
* @env: #CPUPPCState
- * @cpu_dt_id: CPU index used in the device tree. KVM uses this index too
+ * @vcpu_id: vCPU identifier given to KVM
* @compat_pvr: Current logical PVR, zero if in "raw" mode
*
* A PowerPC CPU.
@@ -1199,7 +1199,7 @@ struct PowerPCCPU {
/*< public >*/
CPUPPCState env;
- int cpu_dt_id;
+ int vcpu_id;
uint32_t compat_pvr;
PPCVirtualHypervisor *vhyp;
Object *intc;
@@ -2515,22 +2515,22 @@ static inline bool lsw_reg_in_range(int start, int nregs, int rx)
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
/**
- * ppc_get_vcpu_dt_id:
+ * ppc_get_vcpu_id:
* @cs: a PowerPCCPU struct.
*
* Returns a device-tree ID for a CPU.
*/
-int ppc_get_vcpu_dt_id(PowerPCCPU *cpu);
+int ppc_get_vcpu_id(PowerPCCPU *cpu);
/**
- * ppc_get_vcpu_by_dt_id:
- * @cpu_dt_id: a device tree id
+ * ppc_get_cpu_by_vcpu_id:
+ * @vcpu_id: a VCPU ID
*
- * Searches for a CPU by @cpu_dt_id.
+ * Searches for a CPU by @vcpu_id.
*
* Returns: a PowerPCCPU struct
*/
-PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id);
+PowerPCCPU *ppc_get_cpu_by_vcpu_id(int vcpu_id);
void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
#endif /* PPC_CPU_H */
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index f31c67e1b1..1142d5c970 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -520,7 +520,7 @@ bool kvmppc_is_mem_backend_page_size_ok(const char *obj_path)
unsigned long kvm_arch_vcpu_id(CPUState *cpu)
{
- return ppc_get_vcpu_dt_id(POWERPC_CPU(cpu));
+ return ppc_get_vcpu_id(POWERPC_CPU(cpu));
}
/* e500 supports 2 h/w breakpoint and 2 watchpoint.
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 43be9a8331..1586e28055 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -9838,14 +9838,14 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
}
#if !defined(CONFIG_USER_ONLY)
- cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * max_smt
+ cpu->vcpu_id = (cs->cpu_index / smp_threads) * max_smt
+ (cs->cpu_index % smp_threads);
- if (kvm_enabled() && !kvm_vcpu_id_is_valid(cpu->cpu_dt_id)) {
- error_setg(errp, "Can't create CPU with id %d in KVM", cpu->cpu_dt_id);
+ if (kvm_enabled() && !kvm_vcpu_id_is_valid(cpu->vcpu_id)) {
+ error_setg(errp, "Can't create CPU with id %d in KVM", cpu->vcpu_id);
error_append_hint(errp, "Adjust the number of cpus to %d "
"or try to raise the number of threads per core\n",
- cpu->cpu_dt_id * smp_threads / max_smt);
+ cpu->vcpu_id * smp_threads / max_smt);
goto unrealize;
}
#endif
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 16/40] ppc: spapr: Make VCPU ID handling private to SPAPR
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (14 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 15/40] ppc: spapr: Rename cpu_dt_id to vcpu_id David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 17/40] booke206: fix booke206_tlbnps for mav 2.0 David Gibson
` (24 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
David Gibson
From: Sam Bobroff <sam.bobroff@au1.ibm.com>
The concept of a VCPU ID that differs from the CPU's index
(cpu->cpu_index) exists only within SPAPR machines so, move the
functions ppc_get_vcpu_id() and ppc_get_cpu_by_vcpu_id() into spapr.c
and rename them appropriately.
Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/ppc.c | 21 ---------------------
hw/ppc/spapr.c | 40 +++++++++++++++++++++++++++++++++-------
hw/ppc/spapr_hcall.c | 4 ++--
hw/ppc/spapr_rtas.c | 4 ++--
include/hw/ppc/spapr.h | 3 +++
target/ppc/cpu.h | 18 ------------------
target/ppc/kvm.c | 2 +-
7 files changed, 41 insertions(+), 51 deletions(-)
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index 4477d4ad89..f76886f4d3 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -1358,27 +1358,6 @@ void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
}
}
-/* CPU device-tree ID helpers */
-int ppc_get_vcpu_id(PowerPCCPU *cpu)
-{
- return cpu->vcpu_id;
-}
-
-PowerPCCPU *ppc_get_cpu_by_vcpu_id(int vcpu_id)
-{
- CPUState *cs;
-
- CPU_FOREACH(cs) {
- PowerPCCPU *cpu = POWERPC_CPU(cs);
-
- if (cpu->vcpu_id == vcpu_id) {
- return cpu;
- }
- }
-
- return NULL;
-}
-
void ppc_cpu_parse_features(const char *cpu_model)
{
CPUClass *cc;
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index f7a4c73e08..067f571416 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -208,7 +208,7 @@ static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
int i, ret = 0;
uint32_t servers_prop[smt_threads];
uint32_t gservers_prop[smt_threads * 2];
- int index = ppc_get_vcpu_id(cpu);
+ int index = spapr_vcpu_id(cpu);
if (cpu->compat_pvr) {
ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
@@ -237,7 +237,7 @@ static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu)
{
- int index = ppc_get_vcpu_id(cpu);
+ int index = spapr_vcpu_id(cpu);
uint32_t associativity[] = {cpu_to_be32(0x5),
cpu_to_be32(0x0),
cpu_to_be32(0x0),
@@ -341,7 +341,7 @@ static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = &cpu->env;
DeviceClass *dc = DEVICE_GET_CLASS(cs);
- int index = ppc_get_vcpu_id(cpu);
+ int index = spapr_vcpu_id(cpu);
int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu));
if ((index % smt) != 0) {
@@ -493,7 +493,7 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = &cpu->env;
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
- int index = ppc_get_vcpu_id(cpu);
+ int index = spapr_vcpu_id(cpu);
uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
0xffffffff, 0xffffffff};
uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
@@ -626,7 +626,7 @@ static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
*/
CPU_FOREACH_REVERSE(cs) {
PowerPCCPU *cpu = POWERPC_CPU(cs);
- int index = ppc_get_vcpu_id(cpu);
+ int index = spapr_vcpu_id(cpu);
DeviceClass *dc = DEVICE_GET_CLASS(cs);
int offset;
@@ -3025,7 +3025,7 @@ static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
DeviceClass *dc = DEVICE_GET_CLASS(cs);
- int id = ppc_get_vcpu_id(cpu);
+ int id = spapr_vcpu_id(cpu);
void *fdt;
int offset, fdt_size;
char *nodename;
@@ -3435,7 +3435,7 @@ static void spapr_ics_resend(XICSFabric *dev)
static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id)
{
- PowerPCCPU *cpu = ppc_get_cpu_by_vcpu_id(vcpu_id);
+ PowerPCCPU *cpu = spapr_find_cpu(vcpu_id);
return cpu ? ICP(cpu->intc) : NULL;
}
@@ -3455,6 +3455,32 @@ static void spapr_pic_print_info(InterruptStatsProvider *obj,
ics_pic_print_info(spapr->ics, mon);
}
+int spapr_vcpu_id(PowerPCCPU *cpu)
+{
+ CPUState *cs = CPU(cpu);
+
+ if (kvm_enabled()) {
+ return kvm_arch_vcpu_id(cs);
+ } else {
+ return cs->cpu_index;
+ }
+}
+
+PowerPCCPU *spapr_find_cpu(int vcpu_id)
+{
+ CPUState *cs;
+
+ CPU_FOREACH(cs) {
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+
+ if (spapr_vcpu_id(cpu) == vcpu_id) {
+ return cpu;
+ }
+ }
+
+ return NULL;
+}
+
static void spapr_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 4ca233854a..7cf0993800 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -999,7 +999,7 @@ static target_ulong h_register_vpa(PowerPCCPU *cpu, sPAPRMachineState *spapr,
CPUPPCState *tenv;
PowerPCCPU *tcpu;
- tcpu = ppc_get_cpu_by_vcpu_id(procno);
+ tcpu = spapr_find_cpu(procno);
if (!tcpu) {
return H_PARAMETER;
}
@@ -1431,7 +1431,7 @@ static target_ulong h_signal_sys_reset(PowerPCCPU *cpu,
} else {
/* Unicast */
- cs = CPU(ppc_get_cpu_by_vcpu_id(target));
+ cs = CPU(spapr_find_cpu(target));
if (cs) {
run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
return H_SUCCESS;
diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
index 626c06b375..cdf0b607a0 100644
--- a/hw/ppc/spapr_rtas.c
+++ b/hw/ppc/spapr_rtas.c
@@ -104,7 +104,7 @@ static void rtas_query_cpu_stopped_state(PowerPCCPU *cpu_,
}
id = rtas_ld(args, 0);
- cpu = ppc_get_cpu_by_vcpu_id(id);
+ cpu = spapr_find_cpu(id);
if (cpu != NULL) {
if (CPU(cpu)->halted) {
rtas_st(rets, 1, 0);
@@ -158,7 +158,7 @@ static void rtas_start_cpu(PowerPCCPU *cpu_, sPAPRMachineState *spapr,
start = rtas_ld(args, 1);
r3 = rtas_ld(args, 2);
- cpu = ppc_get_cpu_by_vcpu_id(id);
+ cpu = spapr_find_cpu(id);
if (cpu != NULL) {
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 5d161ec580..91617e3277 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -705,4 +705,7 @@ void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg);
#define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
+int spapr_vcpu_id(PowerPCCPU *cpu);
+PowerPCCPU *spapr_find_cpu(int vcpu_id);
+
#endif /* HW_SPAPR_H */
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 687e66acde..cf4ded7b8e 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2514,23 +2514,5 @@ static inline bool lsw_reg_in_range(int start, int nregs, int rx)
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
-/**
- * ppc_get_vcpu_id:
- * @cs: a PowerPCCPU struct.
- *
- * Returns a device-tree ID for a CPU.
- */
-int ppc_get_vcpu_id(PowerPCCPU *cpu);
-
-/**
- * ppc_get_cpu_by_vcpu_id:
- * @vcpu_id: a VCPU ID
- *
- * Searches for a CPU by @vcpu_id.
- *
- * Returns: a PowerPCCPU struct
- */
-PowerPCCPU *ppc_get_cpu_by_vcpu_id(int vcpu_id);
-
void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
#endif /* PPC_CPU_H */
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 1142d5c970..f1d54106ac 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -520,7 +520,7 @@ bool kvmppc_is_mem_backend_page_size_ok(const char *obj_path)
unsigned long kvm_arch_vcpu_id(CPUState *cpu)
{
- return ppc_get_vcpu_id(POWERPC_CPU(cpu));
+ return POWERPC_CPU(cpu)->vcpu_id;
}
/* e500 supports 2 h/w breakpoint and 2 watchpoint.
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 17/40] booke206: fix booke206_tlbnps for mav 2.0
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (15 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 16/40] ppc: spapr: Make VCPU ID handling private to SPAPR David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 18/40] booke206: fix tlbnps for fixed size TLB David Gibson
` (23 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
KONRAD Frederic, David Gibson
From: KONRAD Frederic <frederic.konrad@adacore.com>
This fixes booke206_tlbnps for MAV 2.0 by checking the MMUCFG register and
return directly the right tlbnps instead of computing it from non existing
field.
Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index cf4ded7b8e..21f0ddd056 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2473,10 +2473,10 @@ static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
/* returns bitmap of supported page sizes for a given TLB */
static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
{
- bool mav2 = false;
uint32_t ret = 0;
- if (mav2) {
+ if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
+ /* MAV2 */
ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
} else {
uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 18/40] booke206: fix tlbnps for fixed size TLB
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (16 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 17/40] booke206: fix booke206_tlbnps for mav 2.0 David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 19/40] booke206: allow to specify an mmucfg value at the init David Gibson
` (22 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
KONRAD Frederic, David Gibson
From: KONRAD Frederic <frederic.konrad@adacore.com>
Some OS don't populate the TSIZE field when using a fixed size TLB which result
in a 1KB TLB. When the TLB is a fixed size TLB the TSIZE field should be
ignored.
Fix this wrong behavior with MAV 2.0.
Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu.h | 22 ++++++++++++++++++++++
target/ppc/mmu_helper.c | 16 ++++++++++------
2 files changed, 32 insertions(+), 6 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 21f0ddd056..042372c5ad 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2491,6 +2491,28 @@ static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
return ret;
}
+static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn,
+ ppcmas_tlb_t *tlb)
+{
+ uint8_t i;
+ int32_t tsize = -1;
+
+ for (i = 0; i < 32; i++) {
+ if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) {
+ if (tsize == -1) {
+ tsize = i;
+ } else {
+ return;
+ }
+ }
+ }
+
+ /* TLBnPS unimplemented? Odd.. */
+ assert(tsize != -1);
+ tlb->mas1 &= ~MAS1_TSIZE_MASK;
+ tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT;
+}
+
#endif
static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index f06b9382b4..2a1f9902c9 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -2632,12 +2632,16 @@ void helper_booke206_tlbwe(CPUPPCState *env)
env->spr[SPR_BOOKE_MAS3];
tlb->mas1 = env->spr[SPR_BOOKE_MAS1];
- /* MAV 1.0 only */
- if (!(tlbncfg & TLBnCFG_AVAIL)) {
- /* force !AVAIL TLB entries to correct page size */
- tlb->mas1 &= ~MAS1_TSIZE_MASK;
- /* XXX can be configured in MMUCSR0 */
- tlb->mas1 |= (tlbncfg & TLBnCFG_MINSIZE) >> 12;
+ if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
+ /* For TLB which has a fixed size TSIZE is ignored with MAV2 */
+ booke206_fixed_size_tlbn(env, tlbn, tlb);
+ } else {
+ if (!(tlbncfg & TLBnCFG_AVAIL)) {
+ /* force !AVAIL TLB entries to correct page size */
+ tlb->mas1 &= ~MAS1_TSIZE_MASK;
+ /* XXX can be configured in MMUCSR0 */
+ tlb->mas1 |= (tlbncfg & TLBnCFG_MINSIZE) >> 12;
+ }
}
/* Make a mask from TLB size to discard invalid bits in EPN field */
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 19/40] booke206: allow to specify an mmucfg value at the init
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (17 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 18/40] booke206: fix tlbnps for fixed size TLB David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 20/40] ppc64: introduce e6500 David Gibson
` (21 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
KONRAD Frederic, David Gibson
From: KONRAD Frederic <frederic.konrad@adacore.com>
This allows to init the MMUCFG SPR with a non NULL value.
Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate_init.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 1586e28055..4104629df7 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -1842,7 +1842,7 @@ static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
/* BookE 2.06 storage control registers */
static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
- uint32_t *tlbncfg)
+ uint32_t *tlbncfg, uint32_t mmucfg)
{
#if !defined(CONFIG_USER_ONLY)
const char *mas_names[8] = {
@@ -1886,7 +1886,7 @@ static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
spr_register(env, SPR_MMUCFG, "MMUCFG",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
- 0x00000000); /* TOFIX */
+ mmucfg);
switch (env->nb_ways) {
case 4:
spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
@@ -4615,7 +4615,7 @@ static void init_proc_e200(CPUPPCState *env)
&spr_read_spefscr, &spr_write_spefscr,
0x00000000);
/* Memory management */
- gen_spr_BookE206(env, 0x0000005D, NULL);
+ gen_spr_BookE206(env, 0x0000005D, NULL, 0);
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
@@ -4900,6 +4900,7 @@ static void init_proc_e500(CPUPPCState *env, int version)
| 0x0020; /* 32 kb */
uint32_t l1cfg1 = 0x3800 /* 8 ways */
| 0x0020; /* 32 kb */
+ uint32_t mmucfg = 0;
#if !defined(CONFIG_USER_ONLY)
int i;
#endif
@@ -4974,7 +4975,7 @@ static void init_proc_e500(CPUPPCState *env, int version)
default:
cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
}
- gen_spr_BookE206(env, 0x000000DF, tlbncfg);
+ gen_spr_BookE206(env, 0x000000DF, tlbncfg, mmucfg);
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 20/40] ppc64: introduce e6500
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (18 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 19/40] booke206: allow to specify an mmucfg value at the init David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 21/40] spapr_iommu: Realloc guest visible TCE table when hot(un)plugging vfio-pci David Gibson
` (20 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
KONRAD Frederic, David Gibson
From: KONRAD Frederic <frederic.konrad@adacore.com>
This introduces e6500 core.
Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu-models.c | 2 +
target/ppc/cpu-models.h | 1 +
target/ppc/translate_init.c | 91 ++++++++++++++++++++++++++++++++++++++++++++-
3 files changed, 93 insertions(+), 1 deletion(-)
diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c
index 4d3e6354cf..e0d9faf848 100644
--- a/target/ppc/cpu-models.c
+++ b/target/ppc/cpu-models.c
@@ -693,6 +693,8 @@
#ifdef TARGET_PPC64
POWERPC_DEF_SVR("e5500", "e5500",
CPU_POWERPC_e5500, POWERPC_SVR_E500, e5500)
+ POWERPC_DEF_SVR("e6500", "e6500",
+ CPU_POWERPC_e6500, POWERPC_SVR_E500, e6500)
#endif
/* PowerPC e500 microcontrollers */
POWERPC_DEF_SVR("MPC8533_v10", "MPC8533 v1.0",
diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h
index b563c45b68..eaa6849a42 100644
--- a/target/ppc/cpu-models.h
+++ b/target/ppc/cpu-models.h
@@ -346,6 +346,7 @@ enum {
CPU_POWERPC_e500v2_v30 = 0x80210030,
CPU_POWERPC_e500mc = 0x80230020,
CPU_POWERPC_e5500 = 0x80240020,
+ CPU_POWERPC_e6500 = 0x80400020,
/* MPC85xx microcontrollers */
#define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
#define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 4104629df7..08ef74f064 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -4888,6 +4888,7 @@ enum fsl_e500_version {
fsl_e500v2,
fsl_e500mc,
fsl_e5500,
+ fsl_e6500,
};
static void init_proc_e500(CPUPPCState *env, int version)
@@ -4922,6 +4923,9 @@ static void init_proc_e500(CPUPPCState *env, int version)
case fsl_e5500:
ivor_mask = 0x000003FE0000FFFFULL;
break;
+ case fsl_e6500:
+ ivor_mask = 0x000003FF0000FFFFULL;
+ break;
}
gen_spr_BookE(env, ivor_mask);
gen_spr_usprg3(env);
@@ -4954,6 +4958,12 @@ static void init_proc_e500(CPUPPCState *env, int version)
tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
break;
+ case fsl_e6500:
+ mmucfg = 0x6510B45;
+ env->nb_pids = 1;
+ tlbncfg[0] = 0x08052400;
+ tlbncfg[1] = 0x40028040;
+ break;
default:
cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
}
@@ -4972,6 +4982,12 @@ static void init_proc_e500(CPUPPCState *env, int version)
l1cfg0 |= 0x1000000; /* 64 byte cache block size */
l1cfg1 |= 0x1000000; /* 64 byte cache block size */
break;
+ case fsl_e6500:
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ l1cfg0 |= 0x0F83820;
+ l1cfg1 |= 0x0B83820;
+ break;
default:
cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
}
@@ -5050,7 +5066,7 @@ static void init_proc_e500(CPUPPCState *env, int version)
&spr_read_generic, SPR_NOACCESS,
0x00000000);
/* XXX better abstract into Emb.xxx features */
- if (version == fsl_e5500) {
+ if ((version == fsl_e5500) || (version == fsl_e6500)) {
spr_register(env, SPR_BOOKE_EPCR, "EPCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -5062,6 +5078,30 @@ static void init_proc_e500(CPUPPCState *env, int version)
ivpr_mask = (target_ulong)~0xFFFFULL;
}
+ if (version == fsl_e6500) {
+ spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Thread identification */
+ spr_register(env, SPR_TIR, "TIR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000004);
+ spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x7FFFFFFC);
+ }
+
#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 0;
env->tlb_type = TLB_MAS;
@@ -5254,6 +5294,55 @@ POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
}
+
+static void init_proc_e6500(CPUPPCState *env)
+{
+ init_proc_e500(env, fsl_e6500);
+}
+
+POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "e6500 core";
+ pcc->init_proc = init_proc_e6500;
+ pcc->check_pow = check_pow_none;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
+ PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
+ PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_FLOAT | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
+ PPC_FLOAT_STFIWX | PPC_WAIT |
+ PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
+ PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;
+ pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | \
+ PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;
+ pcc->msr_mask = (1ull << MSR_CM) |
+ (1ull << MSR_GS) |
+ (1ull << MSR_UCLE) |
+ (1ull << MSR_CE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_IS) |
+ (1ull << MSR_DS) |
+ (1ull << MSR_PX) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_VR);
+ pcc->mmu_model = POWERPC_MMU_BOOKE206;
+ pcc->excp_model = POWERPC_EXCP_BOOKE;
+ pcc->bus_model = PPC_FLAGS_INPUT_BookE;
+ pcc->bfd_mach = bfd_mach_ppc_e500;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;
+}
+
#endif
/* Non-embedded PowerPC */
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 21/40] spapr_iommu: Realloc guest visible TCE table when hot(un)plugging vfio-pci
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (19 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 20/40] ppc64: introduce e6500 David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 22/40] ppc4xx: Move MAL from ppc405_uc to ppc4xx_devs David Gibson
` (19 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
David Gibson
From: Alexey Kardashevskiy <aik@ozlabs.ru>
This replaces g_malloc() with spapr_tce_alloc_table() as this is
the standard way of allocating tables and this allows moving the table
back to KVM when unplugging a VFIO PCI device and VFIO TCE acceleration
support is not present in the KVM.
Although spapr_tce_alloc_table() is expected to fail with EBUSY
if called when previous fd is not closed yet, in practice we will not
see it because cap_spapr_vfio is false at the moment.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr_iommu.c | 35 ++++++++++++++---------------------
1 file changed, 14 insertions(+), 21 deletions(-)
diff --git a/hw/ppc/spapr_iommu.c b/hw/ppc/spapr_iommu.c
index a75584c947..fa8b969840 100644
--- a/hw/ppc/spapr_iommu.c
+++ b/hw/ppc/spapr_iommu.c
@@ -275,33 +275,26 @@ static void spapr_tce_table_realize(DeviceState *dev, Error **errp)
void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio)
{
size_t table_size = tcet->nb_table * sizeof(uint64_t);
- void *newtable;
+ uint64_t *oldtable;
+ int newfd = -1;
- if (need_vfio == tcet->need_vfio) {
- /* Nothing to do */
- return;
- }
-
- if (!need_vfio) {
- /* FIXME: We don't support transition back to KVM accelerated
- * TCEs yet */
- return;
- }
+ g_assert(need_vfio != tcet->need_vfio);
- tcet->need_vfio = true;
+ tcet->need_vfio = need_vfio;
- if (tcet->fd < 0) {
- /* Table is already in userspace, nothing to be do */
- return;
- }
+ oldtable = tcet->table;
- newtable = g_malloc(table_size);
- memcpy(newtable, tcet->table, table_size);
+ tcet->table = spapr_tce_alloc_table(tcet->liobn,
+ tcet->page_shift,
+ tcet->bus_offset,
+ tcet->nb_table,
+ &newfd,
+ need_vfio);
+ memcpy(tcet->table, oldtable, table_size);
- kvmppc_remove_spapr_tce(tcet->table, tcet->fd, tcet->nb_table);
+ spapr_tce_free_table(oldtable, tcet->fd, tcet->nb_table);
- tcet->fd = -1;
- tcet->table = newtable;
+ tcet->fd = newfd;
}
sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn)
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 22/40] ppc4xx: Move MAL from ppc405_uc to ppc4xx_devs
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (20 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 21/40] spapr_iommu: Realloc guest visible TCE table when hot(un)plugging vfio-pci David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 23/40] ppc4xx: Make MAL emulation more generic David Gibson
` (18 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
BALATON Zoltan, David Gibson
From: BALATON Zoltan <balaton@eik.bme.hu>
This device appears in other SoCs as well not just in 405 ones
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/ppc405_uc.c | 263 -----------------------------------------------
hw/ppc/ppc4xx_devs.c | 264 ++++++++++++++++++++++++++++++++++++++++++++++++
include/hw/ppc/ppc4xx.h | 2 +
3 files changed, 266 insertions(+), 263 deletions(-)
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index f6fe3e6f5e..3c744021d6 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -42,7 +42,6 @@
//#define DEBUG_OCM
//#define DEBUG_I2C
//#define DEBUG_GPT
-//#define DEBUG_MAL
//#define DEBUG_CLOCKS
//#define DEBUG_CLOCKS_LL
@@ -1513,268 +1512,6 @@ static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5])
}
/*****************************************************************************/
-/* MAL */
-enum {
- MAL0_CFG = 0x180,
- MAL0_ESR = 0x181,
- MAL0_IER = 0x182,
- MAL0_TXCASR = 0x184,
- MAL0_TXCARR = 0x185,
- MAL0_TXEOBISR = 0x186,
- MAL0_TXDEIR = 0x187,
- MAL0_RXCASR = 0x190,
- MAL0_RXCARR = 0x191,
- MAL0_RXEOBISR = 0x192,
- MAL0_RXDEIR = 0x193,
- MAL0_TXCTP0R = 0x1A0,
- MAL0_TXCTP1R = 0x1A1,
- MAL0_TXCTP2R = 0x1A2,
- MAL0_TXCTP3R = 0x1A3,
- MAL0_RXCTP0R = 0x1C0,
- MAL0_RXCTP1R = 0x1C1,
- MAL0_RCBS0 = 0x1E0,
- MAL0_RCBS1 = 0x1E1,
-};
-
-typedef struct ppc40x_mal_t ppc40x_mal_t;
-struct ppc40x_mal_t {
- qemu_irq irqs[4];
- uint32_t cfg;
- uint32_t esr;
- uint32_t ier;
- uint32_t txcasr;
- uint32_t txcarr;
- uint32_t txeobisr;
- uint32_t txdeir;
- uint32_t rxcasr;
- uint32_t rxcarr;
- uint32_t rxeobisr;
- uint32_t rxdeir;
- uint32_t txctpr[4];
- uint32_t rxctpr[2];
- uint32_t rcbs[2];
-};
-
-static void ppc40x_mal_reset (void *opaque);
-
-static uint32_t dcr_read_mal (void *opaque, int dcrn)
-{
- ppc40x_mal_t *mal;
- uint32_t ret;
-
- mal = opaque;
- switch (dcrn) {
- case MAL0_CFG:
- ret = mal->cfg;
- break;
- case MAL0_ESR:
- ret = mal->esr;
- break;
- case MAL0_IER:
- ret = mal->ier;
- break;
- case MAL0_TXCASR:
- ret = mal->txcasr;
- break;
- case MAL0_TXCARR:
- ret = mal->txcarr;
- break;
- case MAL0_TXEOBISR:
- ret = mal->txeobisr;
- break;
- case MAL0_TXDEIR:
- ret = mal->txdeir;
- break;
- case MAL0_RXCASR:
- ret = mal->rxcasr;
- break;
- case MAL0_RXCARR:
- ret = mal->rxcarr;
- break;
- case MAL0_RXEOBISR:
- ret = mal->rxeobisr;
- break;
- case MAL0_RXDEIR:
- ret = mal->rxdeir;
- break;
- case MAL0_TXCTP0R:
- ret = mal->txctpr[0];
- break;
- case MAL0_TXCTP1R:
- ret = mal->txctpr[1];
- break;
- case MAL0_TXCTP2R:
- ret = mal->txctpr[2];
- break;
- case MAL0_TXCTP3R:
- ret = mal->txctpr[3];
- break;
- case MAL0_RXCTP0R:
- ret = mal->rxctpr[0];
- break;
- case MAL0_RXCTP1R:
- ret = mal->rxctpr[1];
- break;
- case MAL0_RCBS0:
- ret = mal->rcbs[0];
- break;
- case MAL0_RCBS1:
- ret = mal->rcbs[1];
- break;
- default:
- ret = 0;
- break;
- }
-
- return ret;
-}
-
-static void dcr_write_mal (void *opaque, int dcrn, uint32_t val)
-{
- ppc40x_mal_t *mal;
- int idx;
-
- mal = opaque;
- switch (dcrn) {
- case MAL0_CFG:
- if (val & 0x80000000)
- ppc40x_mal_reset(mal);
- mal->cfg = val & 0x00FFC087;
- break;
- case MAL0_ESR:
- /* Read/clear */
- mal->esr &= ~val;
- break;
- case MAL0_IER:
- mal->ier = val & 0x0000001F;
- break;
- case MAL0_TXCASR:
- mal->txcasr = val & 0xF0000000;
- break;
- case MAL0_TXCARR:
- mal->txcarr = val & 0xF0000000;
- break;
- case MAL0_TXEOBISR:
- /* Read/clear */
- mal->txeobisr &= ~val;
- break;
- case MAL0_TXDEIR:
- /* Read/clear */
- mal->txdeir &= ~val;
- break;
- case MAL0_RXCASR:
- mal->rxcasr = val & 0xC0000000;
- break;
- case MAL0_RXCARR:
- mal->rxcarr = val & 0xC0000000;
- break;
- case MAL0_RXEOBISR:
- /* Read/clear */
- mal->rxeobisr &= ~val;
- break;
- case MAL0_RXDEIR:
- /* Read/clear */
- mal->rxdeir &= ~val;
- break;
- case MAL0_TXCTP0R:
- idx = 0;
- goto update_tx_ptr;
- case MAL0_TXCTP1R:
- idx = 1;
- goto update_tx_ptr;
- case MAL0_TXCTP2R:
- idx = 2;
- goto update_tx_ptr;
- case MAL0_TXCTP3R:
- idx = 3;
- update_tx_ptr:
- mal->txctpr[idx] = val;
- break;
- case MAL0_RXCTP0R:
- idx = 0;
- goto update_rx_ptr;
- case MAL0_RXCTP1R:
- idx = 1;
- update_rx_ptr:
- mal->rxctpr[idx] = val;
- break;
- case MAL0_RCBS0:
- idx = 0;
- goto update_rx_size;
- case MAL0_RCBS1:
- idx = 1;
- update_rx_size:
- mal->rcbs[idx] = val & 0x000000FF;
- break;
- }
-}
-
-static void ppc40x_mal_reset (void *opaque)
-{
- ppc40x_mal_t *mal;
-
- mal = opaque;
- mal->cfg = 0x0007C000;
- mal->esr = 0x00000000;
- mal->ier = 0x00000000;
- mal->rxcasr = 0x00000000;
- mal->rxdeir = 0x00000000;
- mal->rxeobisr = 0x00000000;
- mal->txcasr = 0x00000000;
- mal->txdeir = 0x00000000;
- mal->txeobisr = 0x00000000;
-}
-
-static void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4])
-{
- ppc40x_mal_t *mal;
- int i;
-
- mal = g_malloc0(sizeof(ppc40x_mal_t));
- for (i = 0; i < 4; i++)
- mal->irqs[i] = irqs[i];
- qemu_register_reset(&ppc40x_mal_reset, mal);
- ppc_dcr_register(env, MAL0_CFG,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_ESR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_IER,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_TXCASR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_TXCARR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_TXEOBISR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_TXDEIR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_RXCASR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_RXCARR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_RXEOBISR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_RXDEIR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_TXCTP0R,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_TXCTP1R,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_TXCTP2R,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_TXCTP3R,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_RXCTP0R,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_RXCTP1R,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_RCBS0,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_RCBS1,
- mal, &dcr_read_mal, &dcr_write_mal);
-}
-
-/*****************************************************************************/
/* SPR */
void ppc40x_core_reset(PowerPCCPU *cpu)
{
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 6b38ed7bc7..b296ea66c2 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -734,3 +734,267 @@ ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
return ram_size;
}
+
+/*****************************************************************************/
+/* MAL */
+enum {
+ MAL0_CFG = 0x180,
+ MAL0_ESR = 0x181,
+ MAL0_IER = 0x182,
+ MAL0_TXCASR = 0x184,
+ MAL0_TXCARR = 0x185,
+ MAL0_TXEOBISR = 0x186,
+ MAL0_TXDEIR = 0x187,
+ MAL0_RXCASR = 0x190,
+ MAL0_RXCARR = 0x191,
+ MAL0_RXEOBISR = 0x192,
+ MAL0_RXDEIR = 0x193,
+ MAL0_TXCTP0R = 0x1A0,
+ MAL0_TXCTP1R = 0x1A1,
+ MAL0_TXCTP2R = 0x1A2,
+ MAL0_TXCTP3R = 0x1A3,
+ MAL0_RXCTP0R = 0x1C0,
+ MAL0_RXCTP1R = 0x1C1,
+ MAL0_RCBS0 = 0x1E0,
+ MAL0_RCBS1 = 0x1E1,
+};
+
+typedef struct ppc40x_mal_t ppc40x_mal_t;
+struct ppc40x_mal_t {
+ qemu_irq irqs[4];
+ uint32_t cfg;
+ uint32_t esr;
+ uint32_t ier;
+ uint32_t txcasr;
+ uint32_t txcarr;
+ uint32_t txeobisr;
+ uint32_t txdeir;
+ uint32_t rxcasr;
+ uint32_t rxcarr;
+ uint32_t rxeobisr;
+ uint32_t rxdeir;
+ uint32_t txctpr[4];
+ uint32_t rxctpr[2];
+ uint32_t rcbs[2];
+};
+
+static void ppc40x_mal_reset(void *opaque);
+
+static uint32_t dcr_read_mal(void *opaque, int dcrn)
+{
+ ppc40x_mal_t *mal;
+ uint32_t ret;
+
+ mal = opaque;
+ switch (dcrn) {
+ case MAL0_CFG:
+ ret = mal->cfg;
+ break;
+ case MAL0_ESR:
+ ret = mal->esr;
+ break;
+ case MAL0_IER:
+ ret = mal->ier;
+ break;
+ case MAL0_TXCASR:
+ ret = mal->txcasr;
+ break;
+ case MAL0_TXCARR:
+ ret = mal->txcarr;
+ break;
+ case MAL0_TXEOBISR:
+ ret = mal->txeobisr;
+ break;
+ case MAL0_TXDEIR:
+ ret = mal->txdeir;
+ break;
+ case MAL0_RXCASR:
+ ret = mal->rxcasr;
+ break;
+ case MAL0_RXCARR:
+ ret = mal->rxcarr;
+ break;
+ case MAL0_RXEOBISR:
+ ret = mal->rxeobisr;
+ break;
+ case MAL0_RXDEIR:
+ ret = mal->rxdeir;
+ break;
+ case MAL0_TXCTP0R:
+ ret = mal->txctpr[0];
+ break;
+ case MAL0_TXCTP1R:
+ ret = mal->txctpr[1];
+ break;
+ case MAL0_TXCTP2R:
+ ret = mal->txctpr[2];
+ break;
+ case MAL0_TXCTP3R:
+ ret = mal->txctpr[3];
+ break;
+ case MAL0_RXCTP0R:
+ ret = mal->rxctpr[0];
+ break;
+ case MAL0_RXCTP1R:
+ ret = mal->rxctpr[1];
+ break;
+ case MAL0_RCBS0:
+ ret = mal->rcbs[0];
+ break;
+ case MAL0_RCBS1:
+ ret = mal->rcbs[1];
+ break;
+ default:
+ ret = 0;
+ break;
+ }
+
+ return ret;
+}
+
+static void dcr_write_mal(void *opaque, int dcrn, uint32_t val)
+{
+ ppc40x_mal_t *mal;
+ int idx;
+
+ mal = opaque;
+ switch (dcrn) {
+ case MAL0_CFG:
+ if (val & 0x80000000) {
+ ppc40x_mal_reset(mal);
+ }
+ mal->cfg = val & 0x00FFC087;
+ break;
+ case MAL0_ESR:
+ /* Read/clear */
+ mal->esr &= ~val;
+ break;
+ case MAL0_IER:
+ mal->ier = val & 0x0000001F;
+ break;
+ case MAL0_TXCASR:
+ mal->txcasr = val & 0xF0000000;
+ break;
+ case MAL0_TXCARR:
+ mal->txcarr = val & 0xF0000000;
+ break;
+ case MAL0_TXEOBISR:
+ /* Read/clear */
+ mal->txeobisr &= ~val;
+ break;
+ case MAL0_TXDEIR:
+ /* Read/clear */
+ mal->txdeir &= ~val;
+ break;
+ case MAL0_RXCASR:
+ mal->rxcasr = val & 0xC0000000;
+ break;
+ case MAL0_RXCARR:
+ mal->rxcarr = val & 0xC0000000;
+ break;
+ case MAL0_RXEOBISR:
+ /* Read/clear */
+ mal->rxeobisr &= ~val;
+ break;
+ case MAL0_RXDEIR:
+ /* Read/clear */
+ mal->rxdeir &= ~val;
+ break;
+ case MAL0_TXCTP0R:
+ idx = 0;
+ goto update_tx_ptr;
+ case MAL0_TXCTP1R:
+ idx = 1;
+ goto update_tx_ptr;
+ case MAL0_TXCTP2R:
+ idx = 2;
+ goto update_tx_ptr;
+ case MAL0_TXCTP3R:
+ idx = 3;
+ update_tx_ptr:
+ mal->txctpr[idx] = val;
+ break;
+ case MAL0_RXCTP0R:
+ idx = 0;
+ goto update_rx_ptr;
+ case MAL0_RXCTP1R:
+ idx = 1;
+ update_rx_ptr:
+ mal->rxctpr[idx] = val;
+ break;
+ case MAL0_RCBS0:
+ idx = 0;
+ goto update_rx_size;
+ case MAL0_RCBS1:
+ idx = 1;
+ update_rx_size:
+ mal->rcbs[idx] = val & 0x000000FF;
+ break;
+ }
+}
+
+static void ppc40x_mal_reset(void *opaque)
+{
+ ppc40x_mal_t *mal;
+
+ mal = opaque;
+ mal->cfg = 0x0007C000;
+ mal->esr = 0x00000000;
+ mal->ier = 0x00000000;
+ mal->rxcasr = 0x00000000;
+ mal->rxdeir = 0x00000000;
+ mal->rxeobisr = 0x00000000;
+ mal->txcasr = 0x00000000;
+ mal->txdeir = 0x00000000;
+ mal->txeobisr = 0x00000000;
+}
+
+void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4])
+{
+ ppc40x_mal_t *mal;
+ int i;
+
+ mal = g_malloc0(sizeof(ppc40x_mal_t));
+ for (i = 0; i < 4; i++) {
+ mal->irqs[i] = irqs[i];
+ }
+ qemu_register_reset(&ppc40x_mal_reset, mal);
+ ppc_dcr_register(env, MAL0_CFG,
+ mal, &dcr_read_mal, &dcr_write_mal);
+ ppc_dcr_register(env, MAL0_ESR,
+ mal, &dcr_read_mal, &dcr_write_mal);
+ ppc_dcr_register(env, MAL0_IER,
+ mal, &dcr_read_mal, &dcr_write_mal);
+ ppc_dcr_register(env, MAL0_TXCASR,
+ mal, &dcr_read_mal, &dcr_write_mal);
+ ppc_dcr_register(env, MAL0_TXCARR,
+ mal, &dcr_read_mal, &dcr_write_mal);
+ ppc_dcr_register(env, MAL0_TXEOBISR,
+ mal, &dcr_read_mal, &dcr_write_mal);
+ ppc_dcr_register(env, MAL0_TXDEIR,
+ mal, &dcr_read_mal, &dcr_write_mal);
+ ppc_dcr_register(env, MAL0_RXCASR,
+ mal, &dcr_read_mal, &dcr_write_mal);
+ ppc_dcr_register(env, MAL0_RXCARR,
+ mal, &dcr_read_mal, &dcr_write_mal);
+ ppc_dcr_register(env, MAL0_RXEOBISR,
+ mal, &dcr_read_mal, &dcr_write_mal);
+ ppc_dcr_register(env, MAL0_RXDEIR,
+ mal, &dcr_read_mal, &dcr_write_mal);
+ ppc_dcr_register(env, MAL0_TXCTP0R,
+ mal, &dcr_read_mal, &dcr_write_mal);
+ ppc_dcr_register(env, MAL0_TXCTP1R,
+ mal, &dcr_read_mal, &dcr_write_mal);
+ ppc_dcr_register(env, MAL0_TXCTP2R,
+ mal, &dcr_read_mal, &dcr_write_mal);
+ ppc_dcr_register(env, MAL0_TXCTP3R,
+ mal, &dcr_read_mal, &dcr_write_mal);
+ ppc_dcr_register(env, MAL0_RXCTP0R,
+ mal, &dcr_read_mal, &dcr_write_mal);
+ ppc_dcr_register(env, MAL0_RXCTP1R,
+ mal, &dcr_read_mal, &dcr_write_mal);
+ ppc_dcr_register(env, MAL0_RCBS0,
+ mal, &dcr_read_mal, &dcr_write_mal);
+ ppc_dcr_register(env, MAL0_RCBS1,
+ mal, &dcr_read_mal, &dcr_write_mal);
+}
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index 66e57a5194..db50cfac02 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -53,6 +53,8 @@ void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
hwaddr *ram_sizes,
int do_init);
+void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4]);
+
#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
#endif /* PPC4XX_H */
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 23/40] ppc4xx: Make MAL emulation more generic
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (21 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 22/40] ppc4xx: Move MAL from ppc405_uc to ppc4xx_devs David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 24/40] ppc4xx: Split off 4xx I2C emulation from ppc405_uc to its own file David Gibson
` (17 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
BALATON Zoltan, David Gibson
From: BALATON Zoltan <balaton@eik.bme.hu>
Allow MAL with more RX and TX channels as found in newer versions.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/ppc405_uc.c | 2 +-
hw/ppc/ppc4xx_devs.c | 171 +++++++++++++++++++-----------------------------
include/hw/ppc/ppc4xx.h | 3 +-
3 files changed, 70 insertions(+), 106 deletions(-)
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 3c744021d6..03856d573f 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -2281,7 +2281,7 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
mal_irqs[1] = pic[12];
mal_irqs[2] = pic[13];
mal_irqs[3] = pic[14];
- ppc405_mal_init(env, mal_irqs);
+ ppc4xx_mal_init(env, 4, 2, mal_irqs);
/* Ethernet */
/* Uses pic[9], pic[15], pic[17] */
/* CPU control */
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index b296ea66c2..ec90f13295 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -737,6 +737,7 @@ ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
/*****************************************************************************/
/* MAL */
+
enum {
MAL0_CFG = 0x180,
MAL0_ESR = 0x181,
@@ -750,17 +751,13 @@ enum {
MAL0_RXEOBISR = 0x192,
MAL0_RXDEIR = 0x193,
MAL0_TXCTP0R = 0x1A0,
- MAL0_TXCTP1R = 0x1A1,
- MAL0_TXCTP2R = 0x1A2,
- MAL0_TXCTP3R = 0x1A3,
MAL0_RXCTP0R = 0x1C0,
- MAL0_RXCTP1R = 0x1C1,
MAL0_RCBS0 = 0x1E0,
MAL0_RCBS1 = 0x1E1,
};
-typedef struct ppc40x_mal_t ppc40x_mal_t;
-struct ppc40x_mal_t {
+typedef struct ppc4xx_mal_t ppc4xx_mal_t;
+struct ppc4xx_mal_t {
qemu_irq irqs[4];
uint32_t cfg;
uint32_t esr;
@@ -773,16 +770,32 @@ struct ppc40x_mal_t {
uint32_t rxcarr;
uint32_t rxeobisr;
uint32_t rxdeir;
- uint32_t txctpr[4];
- uint32_t rxctpr[2];
- uint32_t rcbs[2];
+ uint32_t *txctpr;
+ uint32_t *rxctpr;
+ uint32_t *rcbs;
+ uint8_t txcnum;
+ uint8_t rxcnum;
};
-static void ppc40x_mal_reset(void *opaque);
+static void ppc4xx_mal_reset(void *opaque)
+{
+ ppc4xx_mal_t *mal;
+
+ mal = opaque;
+ mal->cfg = 0x0007C000;
+ mal->esr = 0x00000000;
+ mal->ier = 0x00000000;
+ mal->rxcasr = 0x00000000;
+ mal->rxdeir = 0x00000000;
+ mal->rxeobisr = 0x00000000;
+ mal->txcasr = 0x00000000;
+ mal->txdeir = 0x00000000;
+ mal->txeobisr = 0x00000000;
+}
static uint32_t dcr_read_mal(void *opaque, int dcrn)
{
- ppc40x_mal_t *mal;
+ ppc4xx_mal_t *mal;
uint32_t ret;
mal = opaque;
@@ -820,48 +833,32 @@ static uint32_t dcr_read_mal(void *opaque, int dcrn)
case MAL0_RXDEIR:
ret = mal->rxdeir;
break;
- case MAL0_TXCTP0R:
- ret = mal->txctpr[0];
- break;
- case MAL0_TXCTP1R:
- ret = mal->txctpr[1];
- break;
- case MAL0_TXCTP2R:
- ret = mal->txctpr[2];
- break;
- case MAL0_TXCTP3R:
- ret = mal->txctpr[3];
- break;
- case MAL0_RXCTP0R:
- ret = mal->rxctpr[0];
- break;
- case MAL0_RXCTP1R:
- ret = mal->rxctpr[1];
- break;
- case MAL0_RCBS0:
- ret = mal->rcbs[0];
- break;
- case MAL0_RCBS1:
- ret = mal->rcbs[1];
- break;
default:
ret = 0;
break;
}
+ if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) {
+ ret = mal->txctpr[dcrn - MAL0_TXCTP0R];
+ }
+ if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) {
+ ret = mal->rxctpr[dcrn - MAL0_RXCTP0R];
+ }
+ if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) {
+ ret = mal->rcbs[dcrn - MAL0_RCBS0];
+ }
return ret;
}
static void dcr_write_mal(void *opaque, int dcrn, uint32_t val)
{
- ppc40x_mal_t *mal;
- int idx;
+ ppc4xx_mal_t *mal;
mal = opaque;
switch (dcrn) {
case MAL0_CFG:
if (val & 0x80000000) {
- ppc40x_mal_reset(mal);
+ ppc4xx_mal_reset(mal);
}
mal->cfg = val & 0x00FFC087;
break;
@@ -900,65 +897,35 @@ static void dcr_write_mal(void *opaque, int dcrn, uint32_t val)
/* Read/clear */
mal->rxdeir &= ~val;
break;
- case MAL0_TXCTP0R:
- idx = 0;
- goto update_tx_ptr;
- case MAL0_TXCTP1R:
- idx = 1;
- goto update_tx_ptr;
- case MAL0_TXCTP2R:
- idx = 2;
- goto update_tx_ptr;
- case MAL0_TXCTP3R:
- idx = 3;
- update_tx_ptr:
- mal->txctpr[idx] = val;
- break;
- case MAL0_RXCTP0R:
- idx = 0;
- goto update_rx_ptr;
- case MAL0_RXCTP1R:
- idx = 1;
- update_rx_ptr:
- mal->rxctpr[idx] = val;
- break;
- case MAL0_RCBS0:
- idx = 0;
- goto update_rx_size;
- case MAL0_RCBS1:
- idx = 1;
- update_rx_size:
- mal->rcbs[idx] = val & 0x000000FF;
- break;
+ }
+ if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) {
+ mal->txctpr[dcrn - MAL0_TXCTP0R] = val;
+ }
+ if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) {
+ mal->rxctpr[dcrn - MAL0_RXCTP0R] = val;
+ }
+ if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) {
+ mal->rcbs[dcrn - MAL0_RCBS0] = val & 0x000000FF;
}
}
-static void ppc40x_mal_reset(void *opaque)
-{
- ppc40x_mal_t *mal;
-
- mal = opaque;
- mal->cfg = 0x0007C000;
- mal->esr = 0x00000000;
- mal->ier = 0x00000000;
- mal->rxcasr = 0x00000000;
- mal->rxdeir = 0x00000000;
- mal->rxeobisr = 0x00000000;
- mal->txcasr = 0x00000000;
- mal->txdeir = 0x00000000;
- mal->txeobisr = 0x00000000;
-}
-
-void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4])
+void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
+ qemu_irq irqs[4])
{
- ppc40x_mal_t *mal;
+ ppc4xx_mal_t *mal;
int i;
- mal = g_malloc0(sizeof(ppc40x_mal_t));
+ assert(txcnum <= 32 && rxcnum <= 32);
+ mal = g_malloc0(sizeof(*mal));
+ mal->txcnum = txcnum;
+ mal->rxcnum = rxcnum;
+ mal->txctpr = g_new0(uint32_t, txcnum);
+ mal->rxctpr = g_new0(uint32_t, rxcnum);
+ mal->rcbs = g_new0(uint32_t, rxcnum);
for (i = 0; i < 4; i++) {
mal->irqs[i] = irqs[i];
}
- qemu_register_reset(&ppc40x_mal_reset, mal);
+ qemu_register_reset(&ppc4xx_mal_reset, mal);
ppc_dcr_register(env, MAL0_CFG,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_ESR,
@@ -981,20 +948,16 @@ void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4])
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RXDEIR,
mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_TXCTP0R,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_TXCTP1R,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_TXCTP2R,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_TXCTP3R,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_RXCTP0R,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_RXCTP1R,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_RCBS0,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_RCBS1,
- mal, &dcr_read_mal, &dcr_write_mal);
+ for (i = 0; i < txcnum; i++) {
+ ppc_dcr_register(env, MAL0_TXCTP0R + i,
+ mal, &dcr_read_mal, &dcr_write_mal);
+ }
+ for (i = 0; i < rxcnum; i++) {
+ ppc_dcr_register(env, MAL0_RXCTP0R + i,
+ mal, &dcr_read_mal, &dcr_write_mal);
+ }
+ for (i = 0; i < rxcnum; i++) {
+ ppc_dcr_register(env, MAL0_RCBS0 + i,
+ mal, &dcr_read_mal, &dcr_write_mal);
+ }
}
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index db50cfac02..cb0bb55cec 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -53,7 +53,8 @@ void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
hwaddr *ram_sizes,
int do_init);
-void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4]);
+void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
+ qemu_irq irqs[4]);
#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 24/40] ppc4xx: Split off 4xx I2C emulation from ppc405_uc to its own file
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (22 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 23/40] ppc4xx: Make MAL emulation more generic David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 25/40] ppc4xx_i2c: QOMify David Gibson
` (16 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
BALATON Zoltan, David Gibson
From: BALATON Zoltan <balaton@eik.bme.hu>
This device appears in other SoCs as well not just in 405 ones and
subsequent patches will modify it, so move it out of ppc405_uc.c in
preparation
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/Makefile.objs | 2 +-
hw/ppc/ppc405.h | 2 +
hw/ppc/ppc405_uc.c | 241 ---------------------------------------------
hw/ppc/ppc4xx_i2c.c | 272 +++++++++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 275 insertions(+), 242 deletions(-)
create mode 100644 hw/ppc/ppc4xx_i2c.c
diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs
index 7efc686748..207721647a 100644
--- a/hw/ppc/Makefile.objs
+++ b/hw/ppc/Makefile.objs
@@ -13,7 +13,7 @@ endif
obj-$(CONFIG_PSERIES) += spapr_rtas_ddw.o
# PowerPC 4xx boards
obj-y += ppc405_boards.o ppc4xx_devs.o ppc405_uc.o ppc440_bamboo.o
-obj-y += ppc4xx_pci.o
+obj-y += ppc4xx_pci.o ppc4xx_i2c.o
# PReP
obj-$(CONFIG_PREP) += prep.o
obj-$(CONFIG_PREP) += prep_systemio.o
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index a9ffc87f19..61ec739ebf 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -59,6 +59,8 @@ struct ppc4xx_bd_info_t {
ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
uint32_t flags);
+void ppc405_i2c_init(hwaddr base, qemu_irq irq);
+
CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[4],
hwaddr ram_bases[4],
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 03856d573f..3925e4c60b 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -40,7 +40,6 @@
//#define DEBUG_GPIO
//#define DEBUG_SERIAL
//#define DEBUG_OCM
-//#define DEBUG_I2C
//#define DEBUG_GPT
//#define DEBUG_CLOCKS
//#define DEBUG_CLOCKS_LL
@@ -993,246 +992,6 @@ static void ppc405_ocm_init(CPUPPCState *env)
}
/*****************************************************************************/
-/* I2C controller */
-typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
-struct ppc4xx_i2c_t {
- qemu_irq irq;
- MemoryRegion iomem;
- uint8_t mdata;
- uint8_t lmadr;
- uint8_t hmadr;
- uint8_t cntl;
- uint8_t mdcntl;
- uint8_t sts;
- uint8_t extsts;
- uint8_t sdata;
- uint8_t lsadr;
- uint8_t hsadr;
- uint8_t clkdiv;
- uint8_t intrmsk;
- uint8_t xfrcnt;
- uint8_t xtcntlss;
- uint8_t directcntl;
-};
-
-static uint32_t ppc4xx_i2c_readb (void *opaque, hwaddr addr)
-{
- ppc4xx_i2c_t *i2c;
- uint32_t ret;
-
-#ifdef DEBUG_I2C
- printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
-#endif
- i2c = opaque;
- switch (addr) {
- case 0x00:
- // i2c_readbyte(&i2c->mdata);
- ret = i2c->mdata;
- break;
- case 0x02:
- ret = i2c->sdata;
- break;
- case 0x04:
- ret = i2c->lmadr;
- break;
- case 0x05:
- ret = i2c->hmadr;
- break;
- case 0x06:
- ret = i2c->cntl;
- break;
- case 0x07:
- ret = i2c->mdcntl;
- break;
- case 0x08:
- ret = i2c->sts;
- break;
- case 0x09:
- ret = i2c->extsts;
- break;
- case 0x0A:
- ret = i2c->lsadr;
- break;
- case 0x0B:
- ret = i2c->hsadr;
- break;
- case 0x0C:
- ret = i2c->clkdiv;
- break;
- case 0x0D:
- ret = i2c->intrmsk;
- break;
- case 0x0E:
- ret = i2c->xfrcnt;
- break;
- case 0x0F:
- ret = i2c->xtcntlss;
- break;
- case 0x10:
- ret = i2c->directcntl;
- break;
- default:
- ret = 0x00;
- break;
- }
-#ifdef DEBUG_I2C
- printf("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, addr, ret);
-#endif
-
- return ret;
-}
-
-static void ppc4xx_i2c_writeb (void *opaque,
- hwaddr addr, uint32_t value)
-{
- ppc4xx_i2c_t *i2c;
-
-#ifdef DEBUG_I2C
- printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
- value);
-#endif
- i2c = opaque;
- switch (addr) {
- case 0x00:
- i2c->mdata = value;
- // i2c_sendbyte(&i2c->mdata);
- break;
- case 0x02:
- i2c->sdata = value;
- break;
- case 0x04:
- i2c->lmadr = value;
- break;
- case 0x05:
- i2c->hmadr = value;
- break;
- case 0x06:
- i2c->cntl = value;
- break;
- case 0x07:
- i2c->mdcntl = value & 0xDF;
- break;
- case 0x08:
- i2c->sts &= ~(value & 0x0A);
- break;
- case 0x09:
- i2c->extsts &= ~(value & 0x8F);
- break;
- case 0x0A:
- i2c->lsadr = value;
- break;
- case 0x0B:
- i2c->hsadr = value;
- break;
- case 0x0C:
- i2c->clkdiv = value;
- break;
- case 0x0D:
- i2c->intrmsk = value;
- break;
- case 0x0E:
- i2c->xfrcnt = value & 0x77;
- break;
- case 0x0F:
- i2c->xtcntlss = value;
- break;
- case 0x10:
- i2c->directcntl = value & 0x7;
- break;
- }
-}
-
-static uint32_t ppc4xx_i2c_readw (void *opaque, hwaddr addr)
-{
- uint32_t ret;
-
-#ifdef DEBUG_I2C
- printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
-#endif
- ret = ppc4xx_i2c_readb(opaque, addr) << 8;
- ret |= ppc4xx_i2c_readb(opaque, addr + 1);
-
- return ret;
-}
-
-static void ppc4xx_i2c_writew (void *opaque,
- hwaddr addr, uint32_t value)
-{
-#ifdef DEBUG_I2C
- printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
- value);
-#endif
- ppc4xx_i2c_writeb(opaque, addr, value >> 8);
- ppc4xx_i2c_writeb(opaque, addr + 1, value);
-}
-
-static uint32_t ppc4xx_i2c_readl (void *opaque, hwaddr addr)
-{
- uint32_t ret;
-
-#ifdef DEBUG_I2C
- printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
-#endif
- ret = ppc4xx_i2c_readb(opaque, addr) << 24;
- ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
- ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8;
- ret |= ppc4xx_i2c_readb(opaque, addr + 3);
-
- return ret;
-}
-
-static void ppc4xx_i2c_writel (void *opaque,
- hwaddr addr, uint32_t value)
-{
-#ifdef DEBUG_I2C
- printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
- value);
-#endif
- ppc4xx_i2c_writeb(opaque, addr, value >> 24);
- ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
- ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8);
- ppc4xx_i2c_writeb(opaque, addr + 3, value);
-}
-
-static const MemoryRegionOps i2c_ops = {
- .old_mmio = {
- .read = { ppc4xx_i2c_readb, ppc4xx_i2c_readw, ppc4xx_i2c_readl, },
- .write = { ppc4xx_i2c_writeb, ppc4xx_i2c_writew, ppc4xx_i2c_writel, },
- },
- .endianness = DEVICE_NATIVE_ENDIAN,
-};
-
-static void ppc4xx_i2c_reset (void *opaque)
-{
- ppc4xx_i2c_t *i2c;
-
- i2c = opaque;
- i2c->mdata = 0x00;
- i2c->sdata = 0x00;
- i2c->cntl = 0x00;
- i2c->mdcntl = 0x00;
- i2c->sts = 0x00;
- i2c->extsts = 0x00;
- i2c->clkdiv = 0x00;
- i2c->xfrcnt = 0x00;
- i2c->directcntl = 0x0F;
-}
-
-static void ppc405_i2c_init(hwaddr base, qemu_irq irq)
-{
- ppc4xx_i2c_t *i2c;
-
- i2c = g_malloc0(sizeof(ppc4xx_i2c_t));
- i2c->irq = irq;
-#ifdef DEBUG_I2C
- printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
-#endif
- memory_region_init_io(&i2c->iomem, NULL, &i2c_ops, i2c, "i2c", 0x011);
- memory_region_add_subregion(get_system_memory(), base, &i2c->iomem);
- qemu_register_reset(ppc4xx_i2c_reset, i2c);
-}
-
-/*****************************************************************************/
/* General purpose timers */
typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
struct ppc4xx_gpt_t {
diff --git a/hw/ppc/ppc4xx_i2c.c b/hw/ppc/ppc4xx_i2c.c
new file mode 100644
index 0000000000..15f2dea69e
--- /dev/null
+++ b/hw/ppc/ppc4xx_i2c.c
@@ -0,0 +1,272 @@
+/*
+ * PPC4xx I2C controller emulation
+ *
+ * Copyright (c) 2007 Jocelyn Mayer
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu-common.h"
+#include "cpu.h"
+#include "hw/hw.h"
+#include "exec/address-spaces.h"
+#include "hw/ppc/ppc.h"
+#include "ppc405.h"
+
+/*#define DEBUG_I2C*/
+
+typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
+struct ppc4xx_i2c_t {
+ qemu_irq irq;
+ MemoryRegion iomem;
+ uint8_t mdata;
+ uint8_t lmadr;
+ uint8_t hmadr;
+ uint8_t cntl;
+ uint8_t mdcntl;
+ uint8_t sts;
+ uint8_t extsts;
+ uint8_t sdata;
+ uint8_t lsadr;
+ uint8_t hsadr;
+ uint8_t clkdiv;
+ uint8_t intrmsk;
+ uint8_t xfrcnt;
+ uint8_t xtcntlss;
+ uint8_t directcntl;
+};
+
+static uint32_t ppc4xx_i2c_readb(void *opaque, hwaddr addr)
+{
+ ppc4xx_i2c_t *i2c;
+ uint32_t ret;
+
+#ifdef DEBUG_I2C
+ printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
+#endif
+ i2c = opaque;
+ switch (addr) {
+ case 0x00:
+ /*i2c_readbyte(&i2c->mdata);*/
+ ret = i2c->mdata;
+ break;
+ case 0x02:
+ ret = i2c->sdata;
+ break;
+ case 0x04:
+ ret = i2c->lmadr;
+ break;
+ case 0x05:
+ ret = i2c->hmadr;
+ break;
+ case 0x06:
+ ret = i2c->cntl;
+ break;
+ case 0x07:
+ ret = i2c->mdcntl;
+ break;
+ case 0x08:
+ ret = i2c->sts;
+ break;
+ case 0x09:
+ ret = i2c->extsts;
+ break;
+ case 0x0A:
+ ret = i2c->lsadr;
+ break;
+ case 0x0B:
+ ret = i2c->hsadr;
+ break;
+ case 0x0C:
+ ret = i2c->clkdiv;
+ break;
+ case 0x0D:
+ ret = i2c->intrmsk;
+ break;
+ case 0x0E:
+ ret = i2c->xfrcnt;
+ break;
+ case 0x0F:
+ ret = i2c->xtcntlss;
+ break;
+ case 0x10:
+ ret = i2c->directcntl;
+ break;
+ default:
+ ret = 0x00;
+ break;
+ }
+#ifdef DEBUG_I2C
+ printf("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, addr, ret);
+#endif
+
+ return ret;
+}
+
+static void ppc4xx_i2c_writeb(void *opaque,
+ hwaddr addr, uint32_t value)
+{
+ ppc4xx_i2c_t *i2c;
+
+#ifdef DEBUG_I2C
+ printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
+ value);
+#endif
+ i2c = opaque;
+ switch (addr) {
+ case 0x00:
+ i2c->mdata = value;
+ /*i2c_sendbyte(&i2c->mdata);*/
+ break;
+ case 0x02:
+ i2c->sdata = value;
+ break;
+ case 0x04:
+ i2c->lmadr = value;
+ break;
+ case 0x05:
+ i2c->hmadr = value;
+ break;
+ case 0x06:
+ i2c->cntl = value;
+ break;
+ case 0x07:
+ i2c->mdcntl = value & 0xDF;
+ break;
+ case 0x08:
+ i2c->sts &= ~(value & 0x0A);
+ break;
+ case 0x09:
+ i2c->extsts &= ~(value & 0x8F);
+ break;
+ case 0x0A:
+ i2c->lsadr = value;
+ break;
+ case 0x0B:
+ i2c->hsadr = value;
+ break;
+ case 0x0C:
+ i2c->clkdiv = value;
+ break;
+ case 0x0D:
+ i2c->intrmsk = value;
+ break;
+ case 0x0E:
+ i2c->xfrcnt = value & 0x77;
+ break;
+ case 0x0F:
+ i2c->xtcntlss = value;
+ break;
+ case 0x10:
+ i2c->directcntl = value & 0x7;
+ break;
+ }
+}
+
+static uint32_t ppc4xx_i2c_readw(void *opaque, hwaddr addr)
+{
+ uint32_t ret;
+
+#ifdef DEBUG_I2C
+ printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
+#endif
+ ret = ppc4xx_i2c_readb(opaque, addr) << 8;
+ ret |= ppc4xx_i2c_readb(opaque, addr + 1);
+
+ return ret;
+}
+
+static void ppc4xx_i2c_writew(void *opaque,
+ hwaddr addr, uint32_t value)
+{
+#ifdef DEBUG_I2C
+ printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
+ value);
+#endif
+ ppc4xx_i2c_writeb(opaque, addr, value >> 8);
+ ppc4xx_i2c_writeb(opaque, addr + 1, value);
+}
+
+static uint32_t ppc4xx_i2c_readl(void *opaque, hwaddr addr)
+{
+ uint32_t ret;
+
+#ifdef DEBUG_I2C
+ printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
+#endif
+ ret = ppc4xx_i2c_readb(opaque, addr) << 24;
+ ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
+ ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8;
+ ret |= ppc4xx_i2c_readb(opaque, addr + 3);
+
+ return ret;
+}
+
+static void ppc4xx_i2c_writel(void *opaque,
+ hwaddr addr, uint32_t value)
+{
+#ifdef DEBUG_I2C
+ printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
+ value);
+#endif
+ ppc4xx_i2c_writeb(opaque, addr, value >> 24);
+ ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
+ ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8);
+ ppc4xx_i2c_writeb(opaque, addr + 3, value);
+}
+
+static const MemoryRegionOps i2c_ops = {
+ .old_mmio = {
+ .read = { ppc4xx_i2c_readb, ppc4xx_i2c_readw, ppc4xx_i2c_readl, },
+ .write = { ppc4xx_i2c_writeb, ppc4xx_i2c_writew, ppc4xx_i2c_writel, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void ppc4xx_i2c_reset(void *opaque)
+{
+ ppc4xx_i2c_t *i2c;
+
+ i2c = opaque;
+ i2c->mdata = 0x00;
+ i2c->sdata = 0x00;
+ i2c->cntl = 0x00;
+ i2c->mdcntl = 0x00;
+ i2c->sts = 0x00;
+ i2c->extsts = 0x00;
+ i2c->clkdiv = 0x00;
+ i2c->xfrcnt = 0x00;
+ i2c->directcntl = 0x0F;
+}
+
+void ppc405_i2c_init(hwaddr base, qemu_irq irq)
+{
+ ppc4xx_i2c_t *i2c;
+
+ i2c = g_malloc0(sizeof(ppc4xx_i2c_t));
+ i2c->irq = irq;
+#ifdef DEBUG_I2C
+ printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
+#endif
+ memory_region_init_io(&i2c->iomem, NULL, &i2c_ops, i2c, "i2c", 0x011);
+ memory_region_add_subregion(get_system_memory(), base, &i2c->iomem);
+ qemu_register_reset(ppc4xx_i2c_reset, i2c);
+}
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 25/40] ppc4xx_i2c: QOMify
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (23 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 24/40] ppc4xx: Split off 4xx I2C emulation from ppc405_uc to its own file David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 26/40] ppc4xx_i2c: Move to hw/i2c David Gibson
` (15 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
BALATON Zoltan, David Gibson
From: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/ppc405.h | 2 -
hw/ppc/ppc405_uc.c | 5 +-
hw/ppc/ppc4xx_i2c.c | 154 ++++++++++++++------------------------------
include/hw/i2c/ppc4xx_i2c.h | 61 ++++++++++++++++++
4 files changed, 113 insertions(+), 109 deletions(-)
create mode 100644 include/hw/i2c/ppc4xx_i2c.h
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 61ec739ebf..a9ffc87f19 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -59,8 +59,6 @@ struct ppc4xx_bd_info_t {
ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
uint32_t flags);
-void ppc405_i2c_init(hwaddr base, qemu_irq irq);
-
CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[4],
hwaddr ram_bases[4],
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 3925e4c60b..8f44cb46d0 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -28,6 +28,7 @@
#include "hw/hw.h"
#include "hw/ppc/ppc.h"
#include "hw/boards.h"
+#include "hw/i2c/ppc4xx_i2c.h"
#include "ppc405.h"
#include "hw/char/serial.h"
#include "qemu/timer.h"
@@ -1663,7 +1664,7 @@ CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
DEVICE_BIG_ENDIAN);
}
/* IIC controller */
- ppc405_i2c_init(0xef600500, pic[2]);
+ sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]);
/* GPIO */
ppc405_gpio_init(0xef600700);
/* CPU control */
@@ -2010,7 +2011,7 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
dma_irqs[3] = pic[8];
ppc405_dma_init(env, dma_irqs);
/* IIC controller */
- ppc405_i2c_init(0xef600500, pic[2]);
+ sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]);
/* GPIO */
ppc405_gpio_init(0xef600700);
/* Serial ports */
diff --git a/hw/ppc/ppc4xx_i2c.c b/hw/ppc/ppc4xx_i2c.c
index 15f2dea69e..5a6bde951e 100644
--- a/hw/ppc/ppc4xx_i2c.c
+++ b/hw/ppc/ppc4xx_i2c.c
@@ -27,42 +27,20 @@
#include "qemu-common.h"
#include "cpu.h"
#include "hw/hw.h"
-#include "exec/address-spaces.h"
-#include "hw/ppc/ppc.h"
-#include "ppc405.h"
+#include "hw/i2c/ppc4xx_i2c.h"
/*#define DEBUG_I2C*/
-typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
-struct ppc4xx_i2c_t {
- qemu_irq irq;
- MemoryRegion iomem;
- uint8_t mdata;
- uint8_t lmadr;
- uint8_t hmadr;
- uint8_t cntl;
- uint8_t mdcntl;
- uint8_t sts;
- uint8_t extsts;
- uint8_t sdata;
- uint8_t lsadr;
- uint8_t hsadr;
- uint8_t clkdiv;
- uint8_t intrmsk;
- uint8_t xfrcnt;
- uint8_t xtcntlss;
- uint8_t directcntl;
-};
+#define PPC4xx_I2C_MEM_SIZE 0x11
-static uint32_t ppc4xx_i2c_readb(void *opaque, hwaddr addr)
+static uint64_t ppc4xx_i2c_readb(void *opaque, hwaddr addr, unsigned int size)
{
- ppc4xx_i2c_t *i2c;
- uint32_t ret;
+ PPC4xxI2CState *i2c = PPC4xx_I2C(opaque);
+ uint64_t ret;
#ifdef DEBUG_I2C
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
- i2c = opaque;
switch (addr) {
case 0x00:
/*i2c_readbyte(&i2c->mdata);*/
@@ -115,22 +93,20 @@ static uint32_t ppc4xx_i2c_readb(void *opaque, hwaddr addr)
break;
}
#ifdef DEBUG_I2C
- printf("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, addr, ret);
+ printf("%s: addr " TARGET_FMT_plx " %02" PRIx64 "\n", __func__, addr, ret);
#endif
return ret;
}
-static void ppc4xx_i2c_writeb(void *opaque,
- hwaddr addr, uint32_t value)
+static void ppc4xx_i2c_writeb(void *opaque, hwaddr addr, uint64_t value,
+ unsigned int size)
{
- ppc4xx_i2c_t *i2c;
-
+ PPC4xxI2CState *i2c = opaque;
#ifdef DEBUG_I2C
- printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
- value);
+ printf("%s: addr " TARGET_FMT_plx " val %08" PRIx64 "\n",
+ __func__, addr, value);
#endif
- i2c = opaque;
switch (addr) {
case 0x00:
i2c->mdata = value;
@@ -181,71 +157,20 @@ static void ppc4xx_i2c_writeb(void *opaque,
}
}
-static uint32_t ppc4xx_i2c_readw(void *opaque, hwaddr addr)
-{
- uint32_t ret;
-
-#ifdef DEBUG_I2C
- printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
-#endif
- ret = ppc4xx_i2c_readb(opaque, addr) << 8;
- ret |= ppc4xx_i2c_readb(opaque, addr + 1);
-
- return ret;
-}
-
-static void ppc4xx_i2c_writew(void *opaque,
- hwaddr addr, uint32_t value)
-{
-#ifdef DEBUG_I2C
- printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
- value);
-#endif
- ppc4xx_i2c_writeb(opaque, addr, value >> 8);
- ppc4xx_i2c_writeb(opaque, addr + 1, value);
-}
-
-static uint32_t ppc4xx_i2c_readl(void *opaque, hwaddr addr)
-{
- uint32_t ret;
-
-#ifdef DEBUG_I2C
- printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
-#endif
- ret = ppc4xx_i2c_readb(opaque, addr) << 24;
- ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
- ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8;
- ret |= ppc4xx_i2c_readb(opaque, addr + 3);
-
- return ret;
-}
-
-static void ppc4xx_i2c_writel(void *opaque,
- hwaddr addr, uint32_t value)
-{
-#ifdef DEBUG_I2C
- printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
- value);
-#endif
- ppc4xx_i2c_writeb(opaque, addr, value >> 24);
- ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
- ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8);
- ppc4xx_i2c_writeb(opaque, addr + 3, value);
-}
-
-static const MemoryRegionOps i2c_ops = {
- .old_mmio = {
- .read = { ppc4xx_i2c_readb, ppc4xx_i2c_readw, ppc4xx_i2c_readl, },
- .write = { ppc4xx_i2c_writeb, ppc4xx_i2c_writew, ppc4xx_i2c_writel, },
- },
+static const MemoryRegionOps ppc4xx_i2c_ops = {
+ .read = ppc4xx_i2c_readb,
+ .write = ppc4xx_i2c_writeb,
+ .valid.min_access_size = 1,
+ .valid.max_access_size = 4,
+ .impl.min_access_size = 1,
+ .impl.max_access_size = 1,
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void ppc4xx_i2c_reset(void *opaque)
+static void ppc4xx_i2c_reset(DeviceState *s)
{
- ppc4xx_i2c_t *i2c;
+ PPC4xxI2CState *i2c = PPC4xx_I2C(s);
- i2c = opaque;
i2c->mdata = 0x00;
i2c->sdata = 0x00;
i2c->cntl = 0x00;
@@ -257,16 +182,35 @@ static void ppc4xx_i2c_reset(void *opaque)
i2c->directcntl = 0x0F;
}
-void ppc405_i2c_init(hwaddr base, qemu_irq irq)
+static void ppc4xx_i2c_init(Object *o)
{
- ppc4xx_i2c_t *i2c;
+ PPC4xxI2CState *s = PPC4xx_I2C(o);
- i2c = g_malloc0(sizeof(ppc4xx_i2c_t));
- i2c->irq = irq;
-#ifdef DEBUG_I2C
- printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
-#endif
- memory_region_init_io(&i2c->iomem, NULL, &i2c_ops, i2c, "i2c", 0x011);
- memory_region_add_subregion(get_system_memory(), base, &i2c->iomem);
- qemu_register_reset(ppc4xx_i2c_reset, i2c);
+ memory_region_init_io(&s->iomem, OBJECT(s), &ppc4xx_i2c_ops, s,
+ TYPE_PPC4xx_I2C, PPC4xx_I2C_MEM_SIZE);
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
+ sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
+ s->bus = i2c_init_bus(DEVICE(s), "i2c");
}
+
+static void ppc4xx_i2c_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = ppc4xx_i2c_reset;
+}
+
+static const TypeInfo ppc4xx_i2c_type_info = {
+ .name = TYPE_PPC4xx_I2C,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(PPC4xxI2CState),
+ .instance_init = ppc4xx_i2c_init,
+ .class_init = ppc4xx_i2c_class_init,
+};
+
+static void ppc4xx_i2c_register_types(void)
+{
+ type_register_static(&ppc4xx_i2c_type_info);
+}
+
+type_init(ppc4xx_i2c_register_types)
diff --git a/include/hw/i2c/ppc4xx_i2c.h b/include/hw/i2c/ppc4xx_i2c.h
new file mode 100644
index 0000000000..e53042f6d4
--- /dev/null
+++ b/include/hw/i2c/ppc4xx_i2c.h
@@ -0,0 +1,61 @@
+/*
+ * PPC4xx I2C controller emulation
+ *
+ * Copyright (c) 2007 Jocelyn Mayer
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef PPC4XX_I2C_H
+#define PPC4XX_I2C_H
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "hw/sysbus.h"
+#include "hw/i2c/i2c.h"
+
+#define TYPE_PPC4xx_I2C "ppc4xx-i2c"
+#define PPC4xx_I2C(obj) OBJECT_CHECK(PPC4xxI2CState, (obj), TYPE_PPC4xx_I2C)
+
+typedef struct PPC4xxI2CState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ I2CBus *bus;
+ qemu_irq irq;
+ MemoryRegion iomem;
+ uint8_t mdata;
+ uint8_t lmadr;
+ uint8_t hmadr;
+ uint8_t cntl;
+ uint8_t mdcntl;
+ uint8_t sts;
+ uint8_t extsts;
+ uint8_t sdata;
+ uint8_t lsadr;
+ uint8_t hsadr;
+ uint8_t clkdiv;
+ uint8_t intrmsk;
+ uint8_t xfrcnt;
+ uint8_t xtcntlss;
+ uint8_t directcntl;
+} PPC4xxI2CState;
+
+#endif /* PPC4XX_I2C_H */
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 26/40] ppc4xx_i2c: Move to hw/i2c
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (24 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 25/40] ppc4xx_i2c: QOMify David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 27/40] ppc4xx: Export ECB and PLB emulation David Gibson
` (14 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
BALATON Zoltan, David Gibson
From: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
default-configs/ppc-softmmu.mak | 1 +
default-configs/ppc64-softmmu.mak | 1 +
default-configs/ppcemb-softmmu.mak | 1 +
hw/i2c/Makefile.objs | 1 +
hw/{ppc => i2c}/ppc4xx_i2c.c | 0
hw/ppc/Makefile.objs | 2 +-
6 files changed, 5 insertions(+), 1 deletion(-)
rename hw/{ppc => i2c}/ppc4xx_i2c.c (100%)
diff --git a/default-configs/ppc-softmmu.mak b/default-configs/ppc-softmmu.mak
index 1f1cd85b12..d4d44eb66b 100644
--- a/default-configs/ppc-softmmu.mak
+++ b/default-configs/ppc-softmmu.mak
@@ -3,6 +3,7 @@
include pci.mak
include sound.mak
include usb.mak
+CONFIG_PPC4XX=y
CONFIG_ESCC=y
CONFIG_M48T59=y
CONFIG_SERIAL=y
diff --git a/default-configs/ppc64-softmmu.mak b/default-configs/ppc64-softmmu.mak
index 46c9599321..af32589b38 100644
--- a/default-configs/ppc64-softmmu.mak
+++ b/default-configs/ppc64-softmmu.mak
@@ -3,6 +3,7 @@
include pci.mak
include sound.mak
include usb.mak
+CONFIG_PPC4XX=y
CONFIG_VIRTIO_VGA=y
CONFIG_ESCC=y
CONFIG_M48T59=y
diff --git a/default-configs/ppcemb-softmmu.mak b/default-configs/ppcemb-softmmu.mak
index 94340de356..635923a166 100644
--- a/default-configs/ppcemb-softmmu.mak
+++ b/default-configs/ppcemb-softmmu.mak
@@ -3,6 +3,7 @@
include pci.mak
include sound.mak
include usb.mak
+CONFIG_PPC4XX=y
CONFIG_M48T59=y
CONFIG_SERIAL=y
CONFIG_SERIAL_ISA=y
diff --git a/hw/i2c/Makefile.objs b/hw/i2c/Makefile.objs
index a081b8ef2c..0594dea3ae 100644
--- a/hw/i2c/Makefile.objs
+++ b/hw/i2c/Makefile.objs
@@ -8,3 +8,4 @@ common-obj-$(CONFIG_EXYNOS4) += exynos4210_i2c.o
common-obj-$(CONFIG_IMX_I2C) += imx_i2c.o
common-obj-$(CONFIG_ASPEED_SOC) += aspeed_i2c.o
obj-$(CONFIG_OMAP) += omap_i2c.o
+obj-$(CONFIG_PPC4XX) += ppc4xx_i2c.o
diff --git a/hw/ppc/ppc4xx_i2c.c b/hw/i2c/ppc4xx_i2c.c
similarity index 100%
rename from hw/ppc/ppc4xx_i2c.c
rename to hw/i2c/ppc4xx_i2c.c
diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs
index 207721647a..7efc686748 100644
--- a/hw/ppc/Makefile.objs
+++ b/hw/ppc/Makefile.objs
@@ -13,7 +13,7 @@ endif
obj-$(CONFIG_PSERIES) += spapr_rtas_ddw.o
# PowerPC 4xx boards
obj-y += ppc405_boards.o ppc4xx_devs.o ppc405_uc.o ppc440_bamboo.o
-obj-y += ppc4xx_pci.o ppc4xx_i2c.o
+obj-y += ppc4xx_pci.o
# PReP
obj-$(CONFIG_PREP) += prep.o
obj-$(CONFIG_PREP) += prep_systemio.o
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 27/40] ppc4xx: Export ECB and PLB emulation
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (25 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 26/40] ppc4xx_i2c: Move to hw/i2c David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 28/40] hw/ppc/spapr_cpu_core: Add a proper check for spapr machine David Gibson
` (13 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
BALATON Zoltan, David Gibson
From: BALATON Zoltan <balaton@eik.bme.hu>
Make these device models available outside ppc405_uc.c for reuse in
460EX emulation. They are left in their current place for now because
they are used mostly unchanged and I'm not sure these correctly model
the components in 440 SoCs (but they seem to be good enough). These
functions could be moved in a subsequent clean up series when this is
confirmed.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/ppc405.h | 3 +++
hw/ppc/ppc405_uc.c | 4 ++--
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index a9ffc87f19..7ed25cfa1b 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -59,6 +59,9 @@ struct ppc4xx_bd_info_t {
ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
uint32_t flags);
+void ppc4xx_plb_init(CPUPPCState *env);
+void ppc405_ebc_init(CPUPPCState *env);
+
CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[4],
hwaddr ram_bases[4],
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 8f44cb46d0..e621d0aec5 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -174,7 +174,7 @@ static void ppc4xx_plb_reset (void *opaque)
plb->besr = 0x00000000;
}
-static void ppc4xx_plb_init(CPUPPCState *env)
+void ppc4xx_plb_init(CPUPPCState *env)
{
ppc4xx_plb_t *plb;
@@ -585,7 +585,7 @@ static void ebc_reset (void *opaque)
ebc->cfg = 0x80400000;
}
-static void ppc405_ebc_init(CPUPPCState *env)
+void ppc405_ebc_init(CPUPPCState *env)
{
ppc4xx_ebc_t *ebc;
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 28/40] hw/ppc/spapr_cpu_core: Add a proper check for spapr machine
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (26 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 27/40] ppc4xx: Export ECB and PLB emulation David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 29/40] hw/nvram/spapr_nvram: Device can not be created by the users David Gibson
` (12 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
Thomas Huth, David Gibson
From: Thomas Huth <thuth@redhat.com>
QEMU currently crashes when the user tries to add a spapr-cpu-core
on a non-pseries machine:
$ qemu-system-ppc64 -S -machine ppce500,accel=tcg \
-device POWER5+_v2.1-spapr-cpu-core
hw/ppc/spapr_cpu_core.c:178:spapr_cpu_core_realize_child:
Object 0x55cee1f55160 is not an instance of type spapr-machine
Aborted (core dumped)
So let's add a proper check for the correct machine time with
a more friendly error message here.
Reported-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr_cpu_core.c | 5 +++++
scripts/device-crash-test | 3 +++
2 files changed, 8 insertions(+)
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index ea278ce2a7..dd9232620d 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -220,6 +220,11 @@ static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
void *obj;
int i, j;
+ if (!object_dynamic_cast(qdev_get_machine(), TYPE_SPAPR_MACHINE)) {
+ error_setg(errp, "spapr-cpu-core needs a pseries machine");
+ return;
+ }
+
sc->threads = g_malloc0(size * cc->nr_threads);
for (i = 0; i < cc->nr_threads; i++) {
char id[32];
diff --git a/scripts/device-crash-test b/scripts/device-crash-test
index 81d65b9617..043b24a4aa 100755
--- a/scripts/device-crash-test
+++ b/scripts/device-crash-test
@@ -160,6 +160,9 @@ ERROR_WHITELIST = [
{'machine':'q35|pc.*', 'device':'kvm-ioapic', 'expected':True}, # Only 1 ioapics allowed
{'machine':'q35|pc.*', 'device':'ioapic', 'expected':True}, # Only 1 ioapics allowed
+ # "spapr-cpu-core needs a pseries machine"
+ {'machine':'(?!pseries).*', 'device':'.*-spapr-cpu-core', 'expected':True},
+
# KVM-specific devices shouldn't be tried without accel=kvm:
{'accel':'(?!kvm).*', 'device':'kvmclock', 'expected':True},
{'accel':'(?!kvm).*', 'device':'kvm-pci-assign', 'expected':True},
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 29/40] hw/nvram/spapr_nvram: Device can not be created by the users
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (27 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 28/40] hw/ppc/spapr_cpu_core: Add a proper check for spapr machine David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 30/40] spapr: fallback to raw mode if best compat mode cannot be set during CAS David Gibson
` (11 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
Thomas Huth, David Gibson
From: Thomas Huth <thuth@redhat.com>
Trying to add a spapr-nvram device currently aborts QEMU like this:
$ ppc64-softmmu/qemu-system-ppc64 -device spapr-nvram
qemu-system-ppc64: hw/ppc/spapr_rtas.c:407: spapr_rtas_register:
Assertion `!rtas_table[token].name' failed.
Aborted (core dumped)
This NVRAM device registers RTAS calls during its realize function
and thus can only be used once - and that's internally from spapr.c.
So let's mark the device with user_creatable = false to avoid that
the users can crash their QEMU this way.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/nvram/spapr_nvram.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/nvram/spapr_nvram.c b/hw/nvram/spapr_nvram.c
index bc355a4348..4a0aec8e1d 100644
--- a/hw/nvram/spapr_nvram.c
+++ b/hw/nvram/spapr_nvram.c
@@ -264,6 +264,8 @@ static void spapr_nvram_class_init(ObjectClass *klass, void *data)
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
dc->props = spapr_nvram_properties;
dc->vmsd = &vmstate_spapr_nvram;
+ /* Reason: Internal device only, uses spapr_rtas_register() in realize() */
+ dc->user_creatable = false;
}
static const TypeInfo spapr_nvram_type_info = {
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 30/40] spapr: fallback to raw mode if best compat mode cannot be set during CAS
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (28 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 29/40] hw/nvram/spapr_nvram: Device can not be created by the users David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 31/40] PPC: KVM: Support machine option to set VSMT mode David Gibson
` (10 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
Greg Kurz, David Gibson
From: Greg Kurz <groug@kaod.org>
KVM PR doesn't allow to set a compat mode. This causes ppc_set_compat_all()
to fail and we return H_HARDWARE to the guest right away.
This is excessive: even if we favor compat mode since commit 152ef803ceb19,
we should at least fallback to raw mode if the guest supports it.
This patch modifies cas_check_pvr() so that it also reports that the real
PVR was found in the table supplied by the guest. Note that this is only
makes sense if raw mode isn't explicitely disabled (ie, the user didn't
set the machine "max-cpu-compat" property). If this is the case, we can
simply ignore ppc_set_compat_all() failures, and let the guest run in raw
mode.
Signed-off-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr_hcall.c | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 7cf0993800..8b3c0e17e7 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -1441,7 +1441,8 @@ static target_ulong h_signal_sys_reset(PowerPCCPU *cpu,
}
static uint32_t cas_check_pvr(sPAPRMachineState *spapr, PowerPCCPU *cpu,
- target_ulong *addr, Error **errp)
+ target_ulong *addr, bool *raw_mode_supported,
+ Error **errp)
{
bool explicit_match = false; /* Matched the CPU's real PVR */
uint32_t max_compat = spapr->max_compat_pvr;
@@ -1481,6 +1482,8 @@ static uint32_t cas_check_pvr(sPAPRMachineState *spapr, PowerPCCPU *cpu,
return 0;
}
+ *raw_mode_supported = explicit_match;
+
/* Parsing finished */
trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat);
@@ -1499,8 +1502,9 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
sPAPROptionVector *ov1_guest, *ov5_guest, *ov5_cas_old, *ov5_updates;
bool guest_radix;
Error *local_err = NULL;
+ bool raw_mode_supported = false;
- cas_pvr = cas_check_pvr(spapr, cpu, &addr, &local_err);
+ cas_pvr = cas_check_pvr(spapr, cpu, &addr, &raw_mode_supported, &local_err);
if (local_err) {
error_report_err(local_err);
return H_HARDWARE;
@@ -1510,8 +1514,14 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
if (cpu->compat_pvr != cas_pvr) {
ppc_set_compat_all(cas_pvr, &local_err);
if (local_err) {
- error_report_err(local_err);
- return H_HARDWARE;
+ /* We fail to set compat mode (likely because running with KVM PR),
+ * but maybe we can fallback to raw mode if the guest supports it.
+ */
+ if (!raw_mode_supported) {
+ error_report_err(local_err);
+ return H_HARDWARE;
+ }
+ local_err = NULL;
}
}
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 31/40] PPC: KVM: Support machine option to set VSMT mode
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (29 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 30/40] spapr: fallback to raw mode if best compat mode cannot be set during CAS David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 32/40] target/ppc: Remove old STATUS file David Gibson
` (9 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
David Gibson
From: Sam Bobroff <sam.bobroff@au1.ibm.com>
KVM now allows writing to KVM_CAP_PPC_SMT which has previously been
read only. Doing so causes KVM to act, for that VM, as if the host's
SMT mode was the given value. This is particularly important on Power
9 systems because their default value is 1, but they are able to
support values up to 8.
This patch introduces a way to control this capability via a new
machine property called VSMT ("Virtual SMT"). If the value is not set
on the command line a default is chosen that is, when possible,
compatible with legacy systems.
Note that the intialization of KVM_CAP_PPC_SMT has changed slightly
because it has changed (in KVM) from a global capability to a
VM-specific one. This won't cause a problem on older KVMs because VM
capabilities fall back to global ones.
Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr.c | 75 +++++++++++++++++++++++++++++++++++++++++++++
include/hw/ppc/spapr.h | 1 +
target/ppc/kvm.c | 39 ++++++++++++++++++++++-
target/ppc/kvm_ppc.h | 12 ++++++++
target/ppc/translate_init.c | 14 ---------
5 files changed, 126 insertions(+), 15 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 067f571416..caffa12763 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -26,6 +26,7 @@
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
+#include "qapi/visitor.h"
#include "sysemu/sysemu.h"
#include "sysemu/numa.h"
#include "hw/hw.h"
@@ -2165,6 +2166,61 @@ static void spapr_init_cpus(sPAPRMachineState *spapr)
g_free(type);
}
+static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp)
+{
+ Error *local_err = NULL;
+ bool vsmt_user = !!spapr->vsmt;
+ int kvm_smt = kvmppc_smt_threads();
+ int ret;
+
+ if (!kvm_enabled() && (smp_threads > 1)) {
+ error_setg(&local_err, "TCG cannot support more than 1 thread/core "
+ "on a pseries machine");
+ goto out;
+ }
+ if (!is_power_of_2(smp_threads)) {
+ error_setg(&local_err, "Cannot support %d threads/core on a pseries "
+ "machine because it must be a power of 2", smp_threads);
+ goto out;
+ }
+
+ /* Detemine the VSMT mode to use: */
+ if (vsmt_user) {
+ if (spapr->vsmt < smp_threads) {
+ error_setg(&local_err, "Cannot support VSMT mode %d"
+ " because it must be >= threads/core (%d)",
+ spapr->vsmt, smp_threads);
+ goto out;
+ }
+ /* In this case, spapr->vsmt has been set by the command line */
+ } else {
+ /* Choose a VSMT mode that may be higher than necessary but is
+ * likely to be compatible with hosts that don't have VSMT. */
+ spapr->vsmt = MAX(kvm_smt, smp_threads);
+ }
+
+ /* KVM: If necessary, set the SMT mode: */
+ if (kvm_enabled() && (spapr->vsmt != kvm_smt)) {
+ ret = kvmppc_set_smt_threads(spapr->vsmt);
+ if (ret) {
+ error_setg(&local_err,
+ "Failed to set KVM's VSMT mode to %d (errno %d)",
+ spapr->vsmt, ret);
+ if (!vsmt_user) {
+ error_append_hint(&local_err, "On PPC, a VM with %d threads/"
+ "core on a host with %d threads/core requires "
+ " the use of VSMT mode %d.\n",
+ smp_threads, kvm_smt, spapr->vsmt);
+ }
+ kvmppc_hint_smt_possible(&local_err);
+ goto out;
+ }
+ }
+ /* else TCG: nothing to do currently */
+out:
+ error_propagate(errp, local_err);
+}
+
/* pSeries LPAR / sPAPR hardware init */
static void ppc_spapr_init(MachineState *machine)
{
@@ -2297,6 +2353,8 @@ static void ppc_spapr_init(MachineState *machine)
spapr_cpu_parse_features(spapr);
+ spapr_set_vsmt_mode(spapr, &error_fatal);
+
spapr_init_cpus(spapr);
if (kvm_enabled()) {
@@ -2681,6 +2739,18 @@ static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp)
}
}
+static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ visit_type_uint32(v, name, (uint32_t *)opaque, errp);
+}
+
+static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ visit_type_uint32(v, name, (uint32_t *)opaque, errp);
+}
+
static void spapr_machine_initfn(Object *obj)
{
sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
@@ -2711,6 +2781,11 @@ static void spapr_machine_initfn(Object *obj)
object_property_set_description(obj, "resize-hpt",
"Resizing of the Hash Page Table (enabled, disabled, required)",
NULL);
+ object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt,
+ spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort);
+ object_property_set_description(obj, "vsmt",
+ "Virtual SMT: KVM behaves as if this were"
+ " the host's SMT mode", &error_abort);
}
static void spapr_machine_finalizefn(Object *obj)
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 91617e3277..c1b365f564 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -99,6 +99,7 @@ struct sPAPRMachineState {
uint64_t rtc_offset; /* Now used only during incoming migration */
struct PPCTimebase tb;
bool has_graphics;
+ uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */
Notifier epow_notifier;
QTAILQ_HEAD(, sPAPREventLogEntry) pending_events;
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index f1d54106ac..b6bd0fa7a6 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -74,6 +74,7 @@ static int cap_interrupt_level = false;
static int cap_segstate;
static int cap_booke_sregs;
static int cap_ppc_smt;
+static int cap_ppc_smt_possible;
static int cap_ppc_rma;
static int cap_spapr_tce;
static int cap_spapr_tce_64;
@@ -130,7 +131,7 @@ int kvm_arch_init(MachineState *ms, KVMState *s)
cap_interrupt_level = kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL);
cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE);
cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS);
- cap_ppc_smt = kvm_check_extension(s, KVM_CAP_PPC_SMT);
+ cap_ppc_smt_possible = kvm_check_extension(s, KVM_CAP_PPC_SMT_POSSIBLE);
cap_ppc_rma = kvm_check_extension(s, KVM_CAP_PPC_RMA);
cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE);
cap_spapr_tce_64 = kvm_check_extension(s, KVM_CAP_SPAPR_TCE_64);
@@ -144,6 +145,7 @@ int kvm_arch_init(MachineState *ms, KVMState *s)
* only activated after this by kvmppc_set_papr() */
cap_htab_fd = kvm_check_extension(s, KVM_CAP_PPC_HTAB_FD);
cap_fixup_hcalls = kvm_check_extension(s, KVM_CAP_PPC_FIXUP_HCALL);
+ cap_ppc_smt = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT);
cap_htm = kvm_vm_check_extension(s, KVM_CAP_PPC_HTM);
cap_mmu_radix = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_RADIX);
cap_mmu_hash_v3 = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_HASH_V3);
@@ -2134,6 +2136,41 @@ int kvmppc_smt_threads(void)
return cap_ppc_smt ? cap_ppc_smt : 1;
}
+int kvmppc_set_smt_threads(int smt)
+{
+ int ret;
+
+ ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_SMT, 0, smt, 0);
+ if (!ret) {
+ cap_ppc_smt = smt;
+ }
+ return ret;
+}
+
+void kvmppc_hint_smt_possible(Error **errp)
+{
+ int i;
+ GString *g;
+ char *s;
+
+ assert(kvm_enabled());
+ if (cap_ppc_smt_possible) {
+ g = g_string_new("Available VSMT modes:");
+ for (i = 63; i >= 0; i--) {
+ if ((1UL << i) & cap_ppc_smt_possible) {
+ g_string_append_printf(g, " %lu", (1UL << i));
+ }
+ }
+ s = g_string_free(g, false);
+ error_append_hint(errp, "%s.\n", s);
+ g_free(s);
+ } else {
+ error_append_hint(errp,
+ "This KVM seems to be too old to support VSMT.\n");
+ }
+}
+
+
#ifdef TARGET_PPC64
off_t kvmppc_alloc_rma(void **rma)
{
diff --git a/target/ppc/kvm_ppc.h b/target/ppc/kvm_ppc.h
index 381afe6240..e6711fc2b7 100644
--- a/target/ppc/kvm_ppc.h
+++ b/target/ppc/kvm_ppc.h
@@ -29,6 +29,8 @@ void kvmppc_set_papr(PowerPCCPU *cpu);
int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr);
void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy);
int kvmppc_smt_threads(void);
+void kvmppc_hint_smt_possible(Error **errp);
+int kvmppc_set_smt_threads(int smt);
int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits);
int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits);
int kvmppc_set_tcr(PowerPCCPU *cpu);
@@ -148,6 +150,16 @@ static inline int kvmppc_smt_threads(void)
return 1;
}
+static inline void kvmppc_hint_smt_possible(Error **errp)
+{
+ return;
+}
+
+static inline int kvmppc_set_smt_threads(int smt)
+{
+ return 0;
+}
+
static inline int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
{
return 0;
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 08ef74f064..703ea12f2a 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -9907,20 +9907,6 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
int max_smt = kvmppc_smt_threads();
#endif
-#if !defined(CONFIG_USER_ONLY)
- if (smp_threads > max_smt) {
- error_setg(errp, "Cannot support more than %d threads on PPC with %s",
- max_smt, kvm_enabled() ? "KVM" : "TCG");
- return;
- }
- if (!is_power_of_2(smp_threads)) {
- error_setg(errp, "Cannot support %d threads on PPC with %s, "
- "threads count must be a power of 2.",
- smp_threads, kvm_enabled() ? "KVM" : "TCG");
- return;
- }
-#endif
-
cpu_exec_realizefn(cs, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 32/40] target/ppc: Remove old STATUS file
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (30 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 31/40] PPC: KVM: Support machine option to set VSMT mode David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 33/40] ppc: use macros to make cpu type name from string literal David Gibson
` (8 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
Thomas Huth, David Gibson
From: Thomas Huth <thuth@redhat.com>
The target/ppc/STATUS file has seen its last real update 10 years
ago - so the information in there is not up to date anymore. Since
nobody seems to care about this file, let's simply remove it.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/STATUS | 550 ------------------------------------------------------
1 file changed, 550 deletions(-)
delete mode 100644 target/ppc/STATUS
diff --git a/target/ppc/STATUS b/target/ppc/STATUS
deleted file mode 100644
index a4d48a7ca2..0000000000
--- a/target/ppc/STATUS
+++ /dev/null
@@ -1,550 +0,0 @@
-PowerPC emulation status.
-The goal of this file is to provide a reference status to avoid regressions.
-
-===============================================================================
-PowerPC core emulation status
-
-INSN: instruction set.
- OK => all instructions are emulated
- KO => some insns are missing or some should be removed
- ? => unchecked
-SPR: special purpose registers set
- OK => all SPR registered (but some may be fake)
- KO => some SPR are missing or should be removed
- ? => unchecked
-MSR: MSR bits definitions
- OK => all MSR bits properly defined
- KO => MSR definition is incorrect
- ? => unchecked
-IRQ: input signals definitions (mostly interrupts)
- OK => input signals are properly defined
- KO => input signals are not implemented (system emulation does not work)
- ? => input signals definitions may be incorrect
-MMU: MMU model implementation
- OK => MMU model is implemented and Linux is able to boot
- KO => MMU model not implemented or bugged
- ? => MMU model not tested
-EXCP: exceptions model implementation
- OK => exception model is implemented and Linux is able to boot
- KO => exception model not implemented or known to be buggy
- ? => exception model may be incorrect or is untested
-
-Embedded PowerPC cores
-***
-PowerPC 401:
-INSN OK
-SPR OK 401A1
-MSR OK
-IRQ KO partially implemented
-MMU OK
-EXCP ?
-
-PowerPC 401x2:
-INSN OK
-SPR OK 401B2 401C2 401D2 401E2 401F2
-MSR OK
-IRQ KO partially implemented
-MMU OK
-EXCP ?
-
-PowerPC IOP480:
-INSN OK
-SPR OK IOP480
-MSR OK
-IRQ KO partially implemented
-MMU OK
-EXCP ?
-
-To be checked: 401G2 401B3 Cobra
-
-***
-PowerPC 403:
-INSN OK
-SPR OK 403GA 403GB
-MMU OK
-MSR OK
-IRQ KO not implemented
-EXCP ?
-
-PowerPC 403GCX:
-INSN OK
-SPR OK 403GCX
-MMU OK
-MSR OK
-IRQ KO not implemented
-EXCP ?
-
-To be checked: 403GC
-
-***
-PowerPC 405:
-Checked: 405CRa 405CRb 405CRc 405EP 405GPa 405GPb 405GPc 405GPd 405GPe 405GPR
- Npe405H Npe405H2 Npe405L
-INSN OK
-SPR OK
-MSR OK
-IRQ OK
-MMU OK
-EXCP OK
-Remarks: Linux 2.4 boots (at least 1 proprietary firmware).
- uboot seems to freeze at boot time.
-To be checked: 405D2 405D4 405EZ 405LP Npe4GS3 STB03 STB04 STB25
- x2vp4 x2vp7 x2vp20 x2vp50
-
-XXX: find what is IBM e407b4
-
-***
-PowerPC 440:
-Checked: 440EPa 440EPb 440GXa 440GXb 440GXc 440GXf 440SP 440SP2
-INSN OK
-SPR OK
-MSR OK
-IRQ KO not implemented
-MMU ?
-EXCP ?
-
-PowerPC 440GP:
-Checked: 440GPb 440GPc
-INSN OK
-SPR OK
-MSR OK
-IRQ KO not implemented
-MMU ?
-EXCP ?
-
-PowerPC 440x4:
-Checked: 440A4 440B4 440G4 440H4
-INSN OK
-SPR OK
-MSR OK
-IRQ KO not implemented
-MMU ?
-EXCP ?
-
-PowerPC 440x5:
-Checked: 440A5 440F5 440G5 440H6 440GRa
-INSN OK
-SPR OK
-MSR OK
-IRQ KO not implemented
-MMU ?
-EXCP ?
-
-To be checked: 440EPx 440GRx 440SPE
-
-***
-PowerPC 460: (disabled: lack of detailed specifications)
-INSN KO
-SPR KO
-MSR KO
-IRQ KO
-MMU KO
-EXCP KO
-
-PowerPC 460F: (disabled: lack of detailed specifications)
-INSN KO
-SPR KO
-MSR KO
-IRQ KO
-MMU KO
-EXCP KO
-
-***
-PowerPC e200: (not implemented)
-INSN KO
-SPR KO
-MSR KO
-IRQ KO
-MMU KO
-EXCP KO
-
-***
-PowerPC e300: (not implemented)
-INSN KO
-SPR KO
-MSR KO
-IRQ KO
-MMU KO
-EXCP KO
-
-***
-PowerPC e500: (not implemented)
-INSN KO
-SPR KO
-MSR KO
-IRQ KO
-MMU KO
-EXCP KO
-
-***
-PowerPC e600: (not implemented)
-INSN KO
-SPR KO
-MSR KO
-IRQ KO
-MMU KO
-EXCP KO
-
-***
-32 bits PowerPC
-PowerPC 601: (601 601v2)
-INSN OK
-SPR OK is HID15 only on 601v2 ?
-MSR OK
-IRQ KO not implemented
-MMU ?
-EXCP ?
-Remarks: some instructions should have a specific behavior (not implemented)
-
-PowerPC 602: 602
-INSN OK
-SPR OK
-MSR OK
-IRQ OK
-MMU ?
-EXCP ? at least timer and external interrupt are OK
-Remarks: Linux 2.4 crashes when entering user-mode.
- Linux 2.6.22 boots on this CPU but does not recognize it.
-
-PowerPC 603: (603)
-INSN OK
-SPR OK
-MSR OK
-IRQ OK
-MMU OK
-EXCP OK
-Remarks: Linux 2.4 boots and properly recognizes the CPU
- Linux 2.6.22 idem.
-
-PowerPC 603e: (603e11)
-INSN OK
-SPR OK
-MSR OK
-IRQ OK
-MMU OK
-EXCP OK
-Remarks: Linux 2.4 boots and properly recognizes the CPU
- Linux 2.6.22 idem.
-
-PowerPC G2:
-INSN OK
-SPR OK
-MSR OK
-IRQ OK
-MMU OK
-EXCP OK
-Remarks: Linux 2.4 boots, recognizes the CPU as a 82xx.
- Linux 2.6.22 idem.
-
-PowerPC G2le:
-INSN OK
-SPR OK
-MSR OK
-IRQ OK
-MMU OK
-EXCP OK
-Remarks: Linux 2.4 does not boots. Same symptoms as 602.
- Linux 2.6.22 boots and properly recognizes the CPU.
-
-PowerPC 604:
-INSN OK
-SPR OK
-MSR OK
-IRQ OK
-MMU OK
-EXCP OK
-Remarks: Linux 2.4 boots and properly recognizes the CPU.
- Linux 2.6.22 idem.
-
-PowerPC 7x0:
-INSN OK
-SPR OK
-MSR OK
-IRQ OK
-MMU OK
-EXCP OK
-Remarks: Linux 2.4 boots and properly recognizes the CPU.
- Linux 2.6.22 idem.
-
-PowerPC 750fx:
-INSN OK
-SPR OK
-MSR OK
-IRQ OK
-MMU OK
-EXCP OK
-Remarks: Linux 2.4 boots but does not properly recognizes the CPU.
- Linux 2.6.22 boots and properly recognizes the CPU.
-
-PowerPC 7x5:
-INSN ?
-SPR ?
-MSR ?
-IRQ OK
-MMU ?
-EXCP OK
-Remarks: Linux 2.4 does not boot.
- Linux 2.6.22 idem.
-
-PowerPC 7400:
-INSN KO Altivec missing
-SPR OK
-MSR OK
-IRQ OK
-MMU OK
-EXCP ? Altivec, ...
-Remarks: Linux 2.4 boots and properly recognize the CPU.
- Linux 2.6.22 idem.
-
-PowerPC 7410:
-INSN KO Altivec missing
-SPR OK
-MSR OK
-IRQ OK
-MMU OK
-EXCP ? Altivec, ...
-Remarks: Linux 2.4 boots and properly recognize the CPU.
- Linux 2.6.22 idem.
- Note that UM says tlbld & tlbli are implemented but this may be a mistake
- as TLB loads are managed by the hardware and the CPU does not implement the
- needed registers.
-
-PowerPC 7441:
-INSN KO Altivec missing
-SPR OK
-MSR OK
-IRQ OK
-MMU OK
-EXCP ? Altivec, ...
-Remarks: Linux does not have the code to handle TLB miss on this CPU
- Linux 2.6.22 idem.
-
-PowerPC 7450/7451:
-INSN KO Altivec missing
-SPR OK
-MSR OK
-IRQ OK
-MMU OK
-EXCP ? Altivec, ...
-Remarks: Linux does not have the code to handle TLB miss on this CPU
- Linux 2.6.22 idem.
-
-PowerPC 7445/7447:
-INSN KO Altivec missing
-SPR OK
-MSR OK
-IRQ OK
-MMU OK
-EXCP ? Altivec, ...
-Remarks: Linux does not have the code to handle TLB miss on this CPU
- Linux 2.6.22 idem.
-
-PowerPC 7455/7457:
-INSN KO Altivec missing
-SPR OK
-MSR OK
-IRQ OK
-MMU OK
-EXCP ? Altivec, ...
-Remarks: Linux does not have the code to handle TLB miss on this CPU
- Linux 2.6.22 idem.
-
-64 bits PowerPC
-PowerPC 620: (disabled)
-INSN KO
-SPR KO
-MSR ?
-IRQ KO
-MMU KO
-EXCP KO
-Remarks: not much documentation for this implementation...
-
-PowerPC 970:
-INSN KO Altivec missing and more
-SPR KO
-MSR ?
-IRQ OK
-MMU OK
-EXCP KO partially implemented
-Remarks: Should be able to boot but there is no hw platform currently emulated.
-
-PowerPC 970FX:
-INSN KO Altivec missing and more
-SPR KO
-MSR ?
-IRQ OK
-MMU OK
-EXCP KO partially implemented
-Remarks: Should be able to boot but there is no hw platform currently emulated.
-
-PowerPC Cell:
-INSN KO Altivec missing and more
-SPR KO
-MSR ?
-IRQ ?
-MMU ?
-EXCP ? partially implemented
-Remarks: As the core is mostly a 970, should be able to boot.
- SPE are not implemented.
-
-PowerPC 630: (disabled: lack of detailed specifications)
-INSN KO
-SPR KO
-MSR KO
-IRQ KO
-MMU KO
-EXCP KO
-
-PowerPC 631: (disabled: lack of detailed specifications)
-INSN KO
-SPR KO
-MSR KO
-IRQ KO
-MMU KO
-EXCP KO
-
-POWER4: (disabled: lack of detailed specifications)
-INSN KO
-SPR KO
-MSR KO
-IRQ KO
-MMU KO
-EXCP KO
-
-POWER4+: (disabled: lack of detailed specifications)
-INSN KO
-SPR KO
-MSR KO
-IRQ KO
-MMU KO
-EXCP KO
-
-POWER5: (disabled: lack of detailed specifications)
-INSN KO
-SPR KO
-MSR KO
-IRQ KO
-MMU KO
-EXCP KO
-
-POWER5+: (disabled: lack of detailed specifications)
-INSN KO
-SPR KO
-MSR KO
-IRQ KO
-MMU KO
-EXCP KO
-
-POWER6: (disabled: lack of detailed specifications)
-INSN KO
-SPR KO
-MSR KO
-IRQ KO
-MMU KO
-EXCP KO
-
-RS64: (disabled: lack of detailed specifications)
-INSN KO
-SPR KO
-MSR KO
-IRQ KO
-MMU KO
-EXCP KO
-
-RS64-II: (disabled: lack of detailed specifications)
-INSN KO
-SPR KO
-MSR KO
-IRQ KO
-MMU KO
-EXCP KO
-
-RS64-III: (disabled: lack of detailed specifications)
-INSN KO
-SPR KO
-MSR KO
-IRQ KO
-MMU KO
-EXCP KO
-
-RS64-IV: (disabled: lack of detailed specifications)
-INSN KO
-SPR KO
-MSR KO
-IRQ KO
-MMU KO
-EXCP KO
-
-Original POWER
-POWER: (disabled: lack of detailed specifications)
-INSN KO
-SPR KO
-MSR KO
-IRQ KO
-MMU KO
-EXCP KO
-
-POWER2: (disabled: lack of detailed specifications)
-INSN KO
-SPR KO
-MSR KO
-IRQ KO
-MMU KO
-EXCP KO
-
-===============================================================================
-PowerPC microcontrollers emulation status
-
-Implemementation should be sufficient to boot Linux:
-(there seem to be problems with uboot freezing at some point)
-- PowerPC 405CR
-- PowerPC 405EP
-
-TODO:
-- PowerPC 401 microcontrollers emulation
-- PowerPC 403 microcontrollers emulation
-- more PowerPC 405 microcontrollers emulation
-- Fixes / more features for implemented PowerPC 405 microcontrollers emulation
-- PowerPC 440 microcontrollers emulation
-- e200 microcontrollers emulation
-- e300 microcontrollers emulation
-- e500 microcontrollers emulation
-- e600 microcontrollers emulation
-
-===============================================================================
-PowerPC based platforms emulation status
-
-* PREP platform (RS/6000 7043...) - TO BE CHECKED (broken)
-- Gentoo Linux live CDROM 1.4
-- Debian Linux 3.0
-- Mandrake Linux 9
-
-* heathrow PowerMac platform (beige PowerMac) - TO BE CHECKED (broken)
-- Gentoo Linux live CDROM 1.4
-- Debian Linux 3.0
-- Mandrake Linux 9
-
-* mac99 platform (white and blue PowerMac, ...)
-- Gentoo Linux live CDROM 1.4 - boots, compiles linux kernel
-- Debian Linux woody - boots from CDROM and HDD
-- Mandrake Linux 9 - boots from CDROM, freezes during install
-- Knoppix 2003-07-13_4 boots from CDROM, pb with X configuration
- distribution bug: X runs with a properly hand-coded configuration.
-- rock Linux 2.0 runs from CDROM
-
-* Linux 2.6 support seems deadly broken (used to boot...).
-
-* PowerPC 405EP reference boards:
-- can boot Linux 2.4 & 2.6.
- Need to provide a flash image ready to boot for reproductible tests.
-
-TODO:
-- URGENT: fix PreP and heathrow platforms
-- PowerPC 64 reference platform
-- MCA based RS/6000 emulation
-- CHRP emulation (not PowerMac)
-- PPAR emulation
-- ePPAR emulation
-- misc PowerPC reference boards emulation
-
-===============================================================================
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 33/40] ppc: use macros to make cpu type name from string literal
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (31 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 32/40] target/ppc: Remove old STATUS file David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 34/40] ppc: make cpu_model translation to type consistent David Gibson
` (7 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
David Gibson
From: Igor Mammedov <imammedo@redhat.com>
Replace
"-" TYPE_POWERPC_CPU
when composing cpu type name from cpu model string literal
and the same pattern in format strings with
POWERPC_CPU_TYPE_SUFFIX and POWERPC_CPU_TYPE_NAME(model)
macroses like we do in x86.
Later POWERPC_CPU_TYPE_NAME() will be used to define default
cpu type per machine type and as bonus it will be consistent
and easy grep-able pattern across all other targets that I'm
plannig to treat the same way.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu-models.c | 2 +-
target/ppc/cpu.h | 3 +++
target/ppc/kvm.c | 2 +-
target/ppc/kvm_ppc.h | 2 +-
target/ppc/translate_init.c | 6 +++---
5 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c
index e0d9faf848..782977425b 100644
--- a/target/ppc/cpu-models.c
+++ b/target/ppc/cpu-models.c
@@ -51,7 +51,7 @@
\
static const TypeInfo \
glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_type_info) = { \
- .name = _name "-" TYPE_POWERPC_CPU, \
+ .name = POWERPC_CPU_TYPE_NAME(_name), \
.parent = stringify(_type) "-family-" TYPE_POWERPC_CPU, \
.class_init = \
glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_class_init), \
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 042372c5ad..c9d3ffa89b 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1354,6 +1354,9 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
#define cpu_init(cpu_model) cpu_generic_init(TYPE_POWERPC_CPU, cpu_model)
+#define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU
+#define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX
+
#define cpu_signal_handler cpu_ppc_signal_handler
#define cpu_list ppc_cpu_list
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index b6bd0fa7a6..abcfe13b8a 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -2529,7 +2529,7 @@ static int kvm_ppc_register_host_cpu_type(void)
char *suffix;
ppc_cpu_aliases[i].model = g_strdup(object_class_get_name(oc));
- suffix = strstr(ppc_cpu_aliases[i].model, "-"TYPE_POWERPC_CPU);
+ suffix = strstr(ppc_cpu_aliases[i].model, POWERPC_CPU_TYPE_SUFFIX);
if (suffix) {
*suffix = 0;
}
diff --git a/target/ppc/kvm_ppc.h b/target/ppc/kvm_ppc.h
index e6711fc2b7..f780e6ec7b 100644
--- a/target/ppc/kvm_ppc.h
+++ b/target/ppc/kvm_ppc.h
@@ -9,7 +9,7 @@
#ifndef KVM_PPC_H
#define KVM_PPC_H
-#define TYPE_HOST_POWERPC_CPU "host-" TYPE_POWERPC_CPU
+#define TYPE_HOST_POWERPC_CPU POWERPC_CPU_TYPE_NAME("host")
#ifdef CONFIG_KVM
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 703ea12f2a..ee42c56288 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -10261,7 +10261,7 @@ static gint ppc_cpu_compare_class_name(gconstpointer a, gconstpointer b)
if (strncasecmp(name, object_class_get_name(oc), strlen(name)) == 0 &&
ppc_cpu_is_valid(pcc) &&
strcmp(object_class_get_name(oc) + strlen(name),
- "-" TYPE_POWERPC_CPU) == 0) {
+ POWERPC_CPU_TYPE_SUFFIX) == 0) {
return 0;
}
return -1;
@@ -10403,7 +10403,7 @@ static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
}
name = g_strndup(typename,
- strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
+ strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
(*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
name, pcc->pvr);
for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
@@ -10464,7 +10464,7 @@ static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
typename = object_class_get_name(oc);
info = g_malloc0(sizeof(*info));
info->name = g_strndup(typename,
- strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
+ strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
entry = g_malloc0(sizeof(*entry));
entry->value = info;
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 34/40] ppc: make cpu_model translation to type consistent
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (32 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 33/40] ppc: use macros to make cpu type name from string literal David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 35/40] ppc: make cpu alias point only to real cpu models David Gibson
` (6 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
David Gibson
From: Igor Mammedov <imammedo@redhat.com>
PPC handles -cpu FOO rather incosistently,
i.e. it does case-insensitive matching of FOO to
a CPU type (see: ppc_cpu_compare_class_name) but
handles alias names as case-sensitive, as result:
# qemu-system-ppc64 -M mac99 -cpu g3
qemu-system-ppc64: unable to find CPU model ' kN�U'
# qemu-system-ppc64 -cpu 970MP_V1.1
qemu-system-ppc64: Unable to find sPAPR CPU Core definition
while
# qemu-system-ppc64 -M mac99 -cpu G3
# qemu-system-ppc64 -cpu 970MP_v1.1
start up just fine.
Considering we can't take case-insensitive matching away,
make it case-insensitive for all alias/type/core_type
lookups.
As side effect it allows to remove duplicate core types
which are the same except of using different cased letters in name.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr_cpu_core.c | 24 +-
target/ppc/cpu-models.c | 752 ++++++++++++++++++++++----------------------
target/ppc/kvm.c | 2 +-
target/ppc/translate_init.c | 2 +-
4 files changed, 390 insertions(+), 390 deletions(-)
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index dd9232620d..92bec033b3 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -130,8 +130,10 @@ char *spapr_get_cpu_core_type(const char *model)
{
char *core_type;
gchar **model_pieces = g_strsplit(model, ",", 2);
+ gchar *cpu_model = g_ascii_strdown(model_pieces[0], -1);
+ g_strfreev(model_pieces);
- core_type = g_strdup_printf("%s-%s", model_pieces[0], TYPE_SPAPR_CPU_CORE);
+ core_type = g_strdup_printf("%s-" TYPE_SPAPR_CPU_CORE, cpu_model);
/* Check whether it exists or whether we have to look up an alias name */
if (!object_class_by_name(core_type)) {
@@ -139,13 +141,13 @@ char *spapr_get_cpu_core_type(const char *model)
g_free(core_type);
core_type = NULL;
- realmodel = ppc_cpu_lookup_alias(model_pieces[0]);
+ realmodel = ppc_cpu_lookup_alias(cpu_model);
if (realmodel) {
core_type = spapr_get_cpu_core_type(realmodel);
}
}
+ g_free(cpu_model);
- g_strfreev(model_pieces);
return core_type;
}
@@ -273,31 +275,29 @@ static const char *spapr_core_models[] = {
"970_v2.2",
/* 970MP variants */
- "970MP_v1.0",
"970mp_v1.0",
- "970MP_v1.1",
"970mp_v1.1",
/* POWER5+ */
- "POWER5+_v2.1",
+ "power5+_v2.1",
/* POWER7 */
- "POWER7_v2.3",
+ "power7_v2.3",
/* POWER7+ */
- "POWER7+_v2.1",
+ "power7+_v2.1",
/* POWER8 */
- "POWER8_v2.0",
+ "power8_v2.0",
/* POWER8E */
- "POWER8E_v2.1",
+ "power8e_v2.1",
/* POWER8NVL */
- "POWER8NVL_v1.0",
+ "power8nvl_v1.0",
/* POWER9 */
- "POWER9_v1.0",
+ "power9_v1.0",
};
static Property spapr_cpu_core_properties[] = {
diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c
index 782977425b..07a48ca548 100644
--- a/target/ppc/cpu-models.c
+++ b/target/ppc/cpu-models.c
@@ -75,206 +75,206 @@
POWERPC_DEF("401", CPU_POWERPC_401, 401,
"Generic PowerPC 401")
/* PowerPC 401 cores */
- POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401,
+ POWERPC_DEF("401a1", CPU_POWERPC_401A1, 401,
"PowerPC 401A1")
- POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2,
+ POWERPC_DEF("401b2", CPU_POWERPC_401B2, 401x2,
"PowerPC 401B2")
#if defined(TODO)
- POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3,
+ POWERPC_DEF("401b3", CPU_POWERPC_401B3, 401x3,
"PowerPC 401B3")
#endif
- POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2,
+ POWERPC_DEF("401c2", CPU_POWERPC_401C2, 401x2,
"PowerPC 401C2")
- POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2,
+ POWERPC_DEF("401d2", CPU_POWERPC_401D2, 401x2,
"PowerPC 401D2")
- POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2,
+ POWERPC_DEF("401e2", CPU_POWERPC_401E2, 401x2,
"PowerPC 401E2")
- POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2,
+ POWERPC_DEF("401f2", CPU_POWERPC_401F2, 401x2,
"PowerPC 401F2")
/* XXX: to be checked */
- POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2,
+ POWERPC_DEF("401g2", CPU_POWERPC_401G2, 401x2,
"PowerPC 401G2")
/* PowerPC 401 microcontrollers */
#if defined(TODO)
- POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401,
+ POWERPC_DEF("401gf", CPU_POWERPC_401GF, 401,
"PowerPC 401GF")
#endif
- POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480,
+ POWERPC_DEF("iop480", CPU_POWERPC_IOP480, IOP480,
"IOP480 (401 microcontroller)")
- POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401,
+ POWERPC_DEF("cobra", CPU_POWERPC_COBRA, 401,
"IBM Processor for Network Resources")
#if defined(TODO)
- POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401,
+ POWERPC_DEF("xipchip", CPU_POWERPC_XIPCHIP, 401,
NULL)
#endif
/* PowerPC 403 family */
/* PowerPC 403 microcontrollers */
- POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403,
+ POWERPC_DEF("403ga", CPU_POWERPC_403GA, 403,
"PowerPC 403 GA")
- POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403,
+ POWERPC_DEF("403gb", CPU_POWERPC_403GB, 403,
"PowerPC 403 GB")
- POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403,
+ POWERPC_DEF("403gc", CPU_POWERPC_403GC, 403,
"PowerPC 403 GC")
- POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX,
+ POWERPC_DEF("403gcx", CPU_POWERPC_403GCX, 403GCX,
"PowerPC 403 GCX")
#if defined(TODO)
- POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403,
+ POWERPC_DEF("403gp", CPU_POWERPC_403GP, 403,
"PowerPC 403 GP")
#endif
/* PowerPC 405 family */
/* PowerPC 405 cores */
#if defined(TODO)
- POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405,
+ POWERPC_DEF("405a3", CPU_POWERPC_405A3, 405,
"PowerPC 405 A3")
#endif
#if defined(TODO)
- POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405,
+ POWERPC_DEF("405a4", CPU_POWERPC_405A4, 405,
"PowerPC 405 A4")
#endif
#if defined(TODO)
- POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405,
+ POWERPC_DEF("405b3", CPU_POWERPC_405B3, 405,
"PowerPC 405 B3")
#endif
#if defined(TODO)
- POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405,
+ POWERPC_DEF("405b4", CPU_POWERPC_405B4, 405,
"PowerPC 405 B4")
#endif
#if defined(TODO)
- POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405,
+ POWERPC_DEF("405c3", CPU_POWERPC_405C3, 405,
"PowerPC 405 C3")
#endif
#if defined(TODO)
- POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405,
+ POWERPC_DEF("405c4", CPU_POWERPC_405C4, 405,
"PowerPC 405 C4")
#endif
- POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405,
+ POWERPC_DEF("405d2", CPU_POWERPC_405D2, 405,
"PowerPC 405 D2")
#if defined(TODO)
- POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405,
+ POWERPC_DEF("405d3", CPU_POWERPC_405D3, 405,
"PowerPC 405 D3")
#endif
- POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405,
+ POWERPC_DEF("405d4", CPU_POWERPC_405D4, 405,
"PowerPC 405 D4")
#if defined(TODO)
- POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405,
+ POWERPC_DEF("405d5", CPU_POWERPC_405D5, 405,
"PowerPC 405 D5")
#endif
#if defined(TODO)
- POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405,
+ POWERPC_DEF("405e4", CPU_POWERPC_405E4, 405,
"PowerPC 405 E4")
#endif
#if defined(TODO)
- POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405,
+ POWERPC_DEF("405f4", CPU_POWERPC_405F4, 405,
"PowerPC 405 F4")
#endif
#if defined(TODO)
- POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405,
+ POWERPC_DEF("405f5", CPU_POWERPC_405F5, 405,
"PowerPC 405 F5")
#endif
#if defined(TODO)
- POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405,
+ POWERPC_DEF("405f6", CPU_POWERPC_405F6, 405,
"PowerPC 405 F6")
#endif
/* PowerPC 405 microcontrollers */
- POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405,
+ POWERPC_DEF("405cra", CPU_POWERPC_405CRa, 405,
"PowerPC 405 CRa")
- POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405,
+ POWERPC_DEF("405crb", CPU_POWERPC_405CRb, 405,
"PowerPC 405 CRb")
- POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405,
+ POWERPC_DEF("405crc", CPU_POWERPC_405CRc, 405,
"PowerPC 405 CRc")
- POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405,
+ POWERPC_DEF("405ep", CPU_POWERPC_405EP, 405,
"PowerPC 405 EP")
#if defined(TODO)
- POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405,
+ POWERPC_DEF("405exr", CPU_POWERPC_405EXr, 405,
"PowerPC 405 EXr")
#endif
- POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405,
+ POWERPC_DEF("405ez", CPU_POWERPC_405EZ, 405,
"PowerPC 405 EZ")
#if defined(TODO)
- POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405,
+ POWERPC_DEF("405fx", CPU_POWERPC_405FX, 405,
"PowerPC 405 FX")
#endif
- POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405,
+ POWERPC_DEF("405gpa", CPU_POWERPC_405GPa, 405,
"PowerPC 405 GPa")
- POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405,
+ POWERPC_DEF("405gpb", CPU_POWERPC_405GPb, 405,
"PowerPC 405 GPb")
- POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405,
+ POWERPC_DEF("405gpc", CPU_POWERPC_405GPc, 405,
"PowerPC 405 GPc")
- POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405,
+ POWERPC_DEF("405gpd", CPU_POWERPC_405GPd, 405,
"PowerPC 405 GPd")
- POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405,
+ POWERPC_DEF("405gpr", CPU_POWERPC_405GPR, 405,
"PowerPC 405 GPR")
#if defined(TODO)
- POWERPC_DEF("405H", CPU_POWERPC_405H, 405,
+ POWERPC_DEF("405h", CPU_POWERPC_405H, 405,
"PowerPC 405 H")
#endif
#if defined(TODO)
- POWERPC_DEF("405L", CPU_POWERPC_405L, 405,
+ POWERPC_DEF("405l", CPU_POWERPC_405L, 405,
"PowerPC 405 L")
#endif
- POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405,
+ POWERPC_DEF("405lp", CPU_POWERPC_405LP, 405,
"PowerPC 405 LP")
#if defined(TODO)
- POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405,
+ POWERPC_DEF("405pm", CPU_POWERPC_405PM, 405,
"PowerPC 405 PM")
#endif
#if defined(TODO)
- POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405,
+ POWERPC_DEF("405ps", CPU_POWERPC_405PS, 405,
"PowerPC 405 PS")
#endif
#if defined(TODO)
- POWERPC_DEF("405S", CPU_POWERPC_405S, 405,
+ POWERPC_DEF("405s", CPU_POWERPC_405S, 405,
"PowerPC 405 S")
#endif
- POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405,
+ POWERPC_DEF("npe405h", CPU_POWERPC_NPE405H, 405,
"Npe405 H")
- POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405,
+ POWERPC_DEF("npe405h2", CPU_POWERPC_NPE405H2, 405,
"Npe405 H2")
- POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405,
+ POWERPC_DEF("npe405l", CPU_POWERPC_NPE405L, 405,
"Npe405 L")
- POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405,
+ POWERPC_DEF("npe4gs3", CPU_POWERPC_NPE4GS3, 405,
"Npe4GS3")
#if defined(TODO)
- POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405,
+ POWERPC_DEF("npcxx1", CPU_POWERPC_NPCxx1, 405,
NULL)
#endif
#if defined(TODO)
- POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405,
+ POWERPC_DEF("npr161", CPU_POWERPC_NPR161, 405,
NULL)
#endif
#if defined(TODO)
- POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405,
+ POWERPC_DEF("lc77700", CPU_POWERPC_LC77700, 405,
"PowerPC LC77700 (Sanyo)")
#endif
/* PowerPC 401/403/405 based set-top-box microcontrollers */
#if defined(TODO)
- POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2,
+ POWERPC_DEF("stb01000", CPU_POWERPC_STB01000, 401x2,
"STB010000")
#endif
#if defined(TODO)
- POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2,
+ POWERPC_DEF("stb01010", CPU_POWERPC_STB01010, 401x2,
"STB01010")
#endif
#if defined(TODO)
- POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3,
+ POWERPC_DEF("stb0210", CPU_POWERPC_STB0210, 401x3,
"STB0210")
#endif
- POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405,
+ POWERPC_DEF("stb03", CPU_POWERPC_STB03, 405,
"STB03xx")
#if defined(TODO)
- POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405,
+ POWERPC_DEF("stb043", CPU_POWERPC_STB043, 405,
"STB043x")
#endif
#if defined(TODO)
- POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405,
+ POWERPC_DEF("stb045", CPU_POWERPC_STB045, 405,
"STB045x")
#endif
- POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405,
+ POWERPC_DEF("stb04", CPU_POWERPC_STB04, 405,
"STB04xx")
- POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405,
+ POWERPC_DEF("stb25", CPU_POWERPC_STB25, 405,
"STB25xx")
#if defined(TODO)
- POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405,
+ POWERPC_DEF("stb130", CPU_POWERPC_STB130, 405,
"STB130")
#endif
/* Xilinx PowerPC 405 cores */
@@ -305,95 +305,95 @@
#endif
/* PowerPC 440 cores */
#if defined(TODO)
- POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4,
+ POWERPC_DEF("440a4", CPU_POWERPC_440A4, 440x4,
"PowerPC 440 A4")
#endif
- POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX, 440x5,
+ POWERPC_DEF("440-xilinx", CPU_POWERPC_440_XILINX, 440x5,
"PowerPC 440 Xilinx 5")
- POWERPC_DEF("440-Xilinx-w-dfpu", CPU_POWERPC_440_XILINX, 440x5wDFPU,
+ POWERPC_DEF("440-xilinx-w-dfpu", CPU_POWERPC_440_XILINX, 440x5wDFPU,
"PowerPC 440 Xilinx 5 With a Double Prec. FPU")
#if defined(TODO)
- POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5,
+ POWERPC_DEF("440a5", CPU_POWERPC_440A5, 440x5,
"PowerPC 440 A5")
#endif
#if defined(TODO)
- POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4,
+ POWERPC_DEF("440b4", CPU_POWERPC_440B4, 440x4,
"PowerPC 440 B4")
#endif
#if defined(TODO)
- POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4,
+ POWERPC_DEF("440g4", CPU_POWERPC_440G4, 440x4,
"PowerPC 440 G4")
#endif
#if defined(TODO)
- POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5,
+ POWERPC_DEF("440f5", CPU_POWERPC_440F5, 440x5,
"PowerPC 440 F5")
#endif
#if defined(TODO)
- POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5,
+ POWERPC_DEF("440g5", CPU_POWERPC_440G5, 440x5,
"PowerPC 440 G5")
#endif
#if defined(TODO)
- POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4,
+ POWERPC_DEF("440h4", CPU_POWERPC_440H4, 440x4,
"PowerPC 440H4")
#endif
#if defined(TODO)
- POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5,
+ POWERPC_DEF("440h6", CPU_POWERPC_440H6, 440Gx5,
"PowerPC 440H6")
#endif
/* PowerPC 440 microcontrollers */
- POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP,
+ POWERPC_DEF("440epa", CPU_POWERPC_440EPa, 440EP,
"PowerPC 440 EPa")
- POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP,
+ POWERPC_DEF("440epb", CPU_POWERPC_440EPb, 440EP,
"PowerPC 440 EPb")
- POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP,
+ POWERPC_DEF("440epx", CPU_POWERPC_440EPX, 440EP,
"PowerPC 440 EPX")
#if defined(TODO_USER_ONLY)
- POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP,
+ POWERPC_DEF("440gpb", CPU_POWERPC_440GPb, 440GP,
"PowerPC 440 GPb")
#endif
#if defined(TODO_USER_ONLY)
- POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP,
+ POWERPC_DEF("440gpc", CPU_POWERPC_440GPc, 440GP,
"PowerPC 440 GPc")
#endif
#if defined(TODO_USER_ONLY)
- POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5,
+ POWERPC_DEF("440gra", CPU_POWERPC_440GRa, 440x5,
"PowerPC 440 GRa")
#endif
#if defined(TODO_USER_ONLY)
- POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5,
+ POWERPC_DEF("440grx", CPU_POWERPC_440GRX, 440x5,
"PowerPC 440 GRX")
#endif
#if defined(TODO_USER_ONLY)
- POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP,
+ POWERPC_DEF("440gxa", CPU_POWERPC_440GXa, 440EP,
"PowerPC 440 GXa")
#endif
#if defined(TODO_USER_ONLY)
- POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP,
+ POWERPC_DEF("440gxb", CPU_POWERPC_440GXb, 440EP,
"PowerPC 440 GXb")
#endif
#if defined(TODO_USER_ONLY)
- POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP,
+ POWERPC_DEF("440gxc", CPU_POWERPC_440GXc, 440EP,
"PowerPC 440 GXc")
#endif
#if defined(TODO_USER_ONLY)
- POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP,
+ POWERPC_DEF("440gxf", CPU_POWERPC_440GXf, 440EP,
"PowerPC 440 GXf")
#endif
#if defined(TODO)
- POWERPC_DEF("440S", CPU_POWERPC_440S, 440,
+ POWERPC_DEF("440s", CPU_POWERPC_440S, 440,
"PowerPC 440 S")
#endif
#if defined(TODO_USER_ONLY)
- POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP,
+ POWERPC_DEF("440sp", CPU_POWERPC_440SP, 440EP,
"PowerPC 440 SP")
#endif
#if defined(TODO_USER_ONLY)
- POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP,
+ POWERPC_DEF("440sp2", CPU_POWERPC_440SP2, 440EP,
"PowerPC 440 SP2")
#endif
#if defined(TODO_USER_ONLY)
- POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP,
+ POWERPC_DEF("440spe", CPU_POWERPC_440SPE, 440EP,
"PowerPC 440 SPE")
#endif
/* PowerPC 460 family */
@@ -403,67 +403,67 @@
#endif
/* PowerPC 464 microcontrollers */
#if defined(TODO)
- POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460,
+ POWERPC_DEF("464h90", CPU_POWERPC_464H90, 460,
"PowerPC 464H90")
#endif
#if defined(TODO)
- POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F,
+ POWERPC_DEF("464h90f", CPU_POWERPC_464H90F, 460F,
"PowerPC 464H90F")
#endif
/* Freescale embedded PowerPC cores */
/* MPC5xx family (aka RCPU) */
#if defined(TODO_USER_ONLY)
- POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx,
+ POWERPC_DEF("mpc5xx", CPU_POWERPC_MPC5xx, MPC5xx,
"Generic MPC5xx core")
#endif
/* MPC8xx family (aka PowerQUICC) */
#if defined(TODO_USER_ONLY)
- POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx,
+ POWERPC_DEF("mpc8xx", CPU_POWERPC_MPC8xx, MPC8xx,
"Generic MPC8xx core")
#endif
/* MPC82xx family (aka PowerQUICC-II) */
- POWERPC_DEF("G2", CPU_POWERPC_G2, G2,
+ POWERPC_DEF("g2", CPU_POWERPC_G2, G2,
"PowerPC G2 core")
- POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2,
+ POWERPC_DEF("g2h4", CPU_POWERPC_G2H4, G2,
"PowerPC G2 H4 core")
- POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2,
+ POWERPC_DEF("g2gp", CPU_POWERPC_G2gp, G2,
"PowerPC G2 GP core")
- POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2,
+ POWERPC_DEF("g2ls", CPU_POWERPC_G2ls, G2,
"PowerPC G2 LS core")
- POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2,
+ POWERPC_DEF("g2hip3", CPU_POWERPC_G2_HIP3, G2,
"PowerPC G2 HiP3 core")
- POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2,
+ POWERPC_DEF("g2hip4", CPU_POWERPC_G2_HIP4, G2,
"PowerPC G2 HiP4 core")
- POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E,
+ POWERPC_DEF("mpc603", CPU_POWERPC_MPC603, 603E,
"PowerPC MPC603 core")
- POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE,
+ POWERPC_DEF("g2le", CPU_POWERPC_G2LE, G2LE,
"PowerPC G2le core (same as G2 plus little-endian mode support)")
- POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE,
+ POWERPC_DEF("g2legp", CPU_POWERPC_G2LEgp, G2LE,
"PowerPC G2LE GP core")
- POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE,
+ POWERPC_DEF("g2lels", CPU_POWERPC_G2LEls, G2LE,
"PowerPC G2LE LS core")
- POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE,
+ POWERPC_DEF("g2legp1", CPU_POWERPC_G2LEgp1, G2LE,
"PowerPC G2LE GP1 core")
- POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp3, G2LE,
+ POWERPC_DEF("g2legp3", CPU_POWERPC_G2LEgp3, G2LE,
"PowerPC G2LE GP3 core")
/* PowerPC G2 microcontrollers */
#if defined(TODO)
- POWERPC_DEF_SVR("MPC5121", "MPC5121",
+ POWERPC_DEF_SVR("mpc5121", "MPC5121",
CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE)
#endif
- POWERPC_DEF_SVR("MPC5200_v10", "MPC5200 v1.0",
+ POWERPC_DEF_SVR("mpc5200_v10", "MPC5200 v1.0",
CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE)
- POWERPC_DEF_SVR("MPC5200_v11", "MPC5200 v1.1",
+ POWERPC_DEF_SVR("mpc5200_v11", "MPC5200 v1.1",
CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE)
- POWERPC_DEF_SVR("MPC5200_v12", "MPC5200 v1.2",
+ POWERPC_DEF_SVR("mpc5200_v12", "MPC5200 v1.2",
CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE)
- POWERPC_DEF_SVR("MPC5200B_v20", "MPC5200B v2.0",
+ POWERPC_DEF_SVR("mpc5200b_v20", "MPC5200B v2.0",
CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE)
- POWERPC_DEF_SVR("MPC5200B_v21", "MPC5200B v2.1",
+ POWERPC_DEF_SVR("mpc5200b_v21", "MPC5200B v2.1",
CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE)
/* e200 family */
#if defined(TODO)
- POWERPC_DEF_SVR("MPC55xx", "Generic MPC55xx core",
+ POWERPC_DEF_SVR("mpc55xx", "Generic MPC55xx core",
CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200)
#endif
#if defined(TODO)
@@ -484,91 +484,91 @@
"PowerPC e200z6 core")
/* PowerPC e200 microcontrollers */
#if defined(TODO)
- POWERPC_DEF_SVR("MPC5514E", "MPC5514E",
+ POWERPC_DEF_SVR("mpc5514e", "MPC5514E",
CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200)
#endif
#if defined(TODO)
- POWERPC_DEF_SVR("MPC5514E_v0", "MPC5514E v0",
+ POWERPC_DEF_SVR("mpc5514e_v0", "MPC5514E v0",
CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200)
#endif
#if defined(TODO)
- POWERPC_DEF_SVR("MPC5514E_v1", "MPC5514E v1",
+ POWERPC_DEF_SVR("mpc5514e_v1", "MPC5514E v1",
CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200)
#endif
#if defined(TODO)
- POWERPC_DEF_SVR("MPC5514G", "MPC5514G",
+ POWERPC_DEF_SVR("mpc5514g", "MPC5514G",
CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200)
#endif
#if defined(TODO)
- POWERPC_DEF_SVR("MPC5514G_v0", "MPC5514G v0",
+ POWERPC_DEF_SVR("mpc5514g_v0", "MPC5514G v0",
CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200)
#endif
#if defined(TODO)
- POWERPC_DEF_SVR("MPC5514G_v1", "MPC5514G v1",
+ POWERPC_DEF_SVR("mpc5514g_v1", "MPC5514G v1",
CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200)
#endif
#if defined(TODO)
- POWERPC_DEF_SVR("MPC5515S", "MPC5515S",
+ POWERPC_DEF_SVR("mpc5515s", "MPC5515S",
CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200)
#endif
#if defined(TODO)
- POWERPC_DEF_SVR("MPC5516E", "MPC5516E",
+ POWERPC_DEF_SVR("mpc5516e", "MPC5516E",
CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200)
#endif
#if defined(TODO)
- POWERPC_DEF_SVR("MPC5516E_v0", "MPC5516E v0",
+ POWERPC_DEF_SVR("mpc5516e_v0", "MPC5516E v0",
CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200)
#endif
#if defined(TODO)
- POWERPC_DEF_SVR("MPC5516E_v1", "MPC5516E v1",
+ POWERPC_DEF_SVR("mpc5516e_v1", "MPC5516E v1",
CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200)
#endif
#if defined(TODO)
- POWERPC_DEF_SVR("MPC5516G", "MPC5516G",
+ POWERPC_DEF_SVR("mpc5516g", "MPC5516G",
CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200)
#endif
#if defined(TODO)
- POWERPC_DEF_SVR("MPC5516G_v0", "MPC5516G v0",
+ POWERPC_DEF_SVR("mpc5516g_v0", "MPC5516G v0",
CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200)
#endif
#if defined(TODO)
- POWERPC_DEF_SVR("MPC5516G_v1", "MPC5516G v1",
+ POWERPC_DEF_SVR("mpc5516g_v1", "MPC5516G v1",
CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200)
#endif
#if defined(TODO)
- POWERPC_DEF_SVR("MPC5516S", "MPC5516S",
+ POWERPC_DEF_SVR("mpc5516s", "MPC5516S",
CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200)
#endif
#if defined(TODO)
- POWERPC_DEF_SVR("MPC5533", "MPC5533",
+ POWERPC_DEF_SVR("mpc5533", "MPC5533",
CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200)
#endif
#if defined(TODO)
- POWERPC_DEF_SVR("MPC5534", "MPC5534",
+ POWERPC_DEF_SVR("mpc5534", "MPC5534",
CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200)
#endif
#if defined(TODO)
- POWERPC_DEF_SVR("MPC5553", "MPC5553",
+ POWERPC_DEF_SVR("mpc5553", "MPC5553",
CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200)
#endif
#if defined(TODO)
- POWERPC_DEF_SVR("MPC5554", "MPC5554",
+ POWERPC_DEF_SVR("mpc5554", "MPC5554",
CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200)
#endif
#if defined(TODO)
- POWERPC_DEF_SVR("MPC5561", "MPC5561",
+ POWERPC_DEF_SVR("mpc5561", "MPC5561",
CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200)
#endif
#if defined(TODO)
- POWERPC_DEF_SVR("MPC5565", "MPC5565",
+ POWERPC_DEF_SVR("mpc5565", "MPC5565",
CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200)
#endif
#if defined(TODO)
- POWERPC_DEF_SVR("MPC5566", "MPC5566",
+ POWERPC_DEF_SVR("mpc5566", "MPC5566",
CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200)
#endif
#if defined(TODO)
- POWERPC_DEF_SVR("MPC5567", "MPC5567",
+ POWERPC_DEF_SVR("mpc5567", "MPC5567",
CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200)
#endif
/* e300 family */
@@ -582,96 +582,96 @@
"PowerPC e300c4 core")
/* PowerPC e300 microcontrollers */
#if defined(TODO)
- POWERPC_DEF_SVR("MPC8313", "MPC8313",
+ POWERPC_DEF_SVR("mpc8313", "MPC8313",
CPU_POWERPC_MPC831x, POWERPC_SVR_8313, e300)
#endif
#if defined(TODO)
- POWERPC_DEF_SVR("MPC8313E", "MPC8313E",
+ POWERPC_DEF_SVR("mpc8313e", "MPC8313E",
CPU_POWERPC_MPC831x, POWERPC_SVR_8313E, e300)
#endif
#if defined(TODO)
- POWERPC_DEF_SVR("MPC8314", "MPC8314",
+ POWERPC_DEF_SVR("mpc8314", "MPC8314",
CPU_POWERPC_MPC831x, POWERPC_SVR_8314, e300)
#endif
#if defined(TODO)
- POWERPC_DEF_SVR("MPC8314E", "MPC8314E",
+ POWERPC_DEF_SVR("mpc8314e", "MPC8314E",
CPU_POWERPC_MPC831x, POWERPC_SVR_8314E, e300)
#endif
#if defined(TODO)
- POWERPC_DEF_SVR("MPC8315", "MPC8315",
+ POWERPC_DEF_SVR("mpc8315", "MPC8315",
CPU_POWERPC_MPC831x, POWERPC_SVR_8315, e300)
#endif
#if defined(TODO)
- POWERPC_DEF_SVR("MPC8315E", "MPC8315E",
+ POWERPC_DEF_SVR("mpc8315e", "MPC8315E",
CPU_POWERPC_MPC831x, POWERPC_SVR_8315E, e300)
#endif
#if defined(TODO)
- POWERPC_DEF_SVR("MPC8321", "MPC8321",
+ POWERPC_DEF_SVR("mpc8321", "MPC8321",
CPU_POWERPC_MPC832x, POWERPC_SVR_8321, e300)
#endif
#if defined(TODO)
- POWERPC_DEF_SVR("MPC8321E", "MPC8321E",
+ POWERPC_DEF_SVR("mpc8321e", "MPC8321E",
CPU_POWERPC_MPC832x, POWERPC_SVR_8321E, e300)
#endif
#if defined(TODO)
- POWERPC_DEF_SVR("MPC8323", "MPC8323",
+ POWERPC_DEF_SVR("mpc8323", "MPC8323",
CPU_POWERPC_MPC832x, POWERPC_SVR_8323, e300)
#endif
#if defined(TODO)
- POWERPC_DEF_SVR("MPC8323E", "MPC8323E",
+ POWERPC_DEF_SVR("mpc8323e", "MPC8323E",
CPU_POWERPC_MPC832x, POWERPC_SVR_8323E, e300)
#endif
- POWERPC_DEF_SVR("MPC8343", "MPC8343",
+ POWERPC_DEF_SVR("mpc8343", "MPC8343",
CPU_POWERPC_MPC834x, POWERPC_SVR_8343, e300)
- POWERPC_DEF_SVR("MPC8343A", "MPC8343A",
+ POWERPC_DEF_SVR("mpc8343a", "MPC8343A",
CPU_POWERPC_MPC834x, POWERPC_SVR_8343A, e300)
- POWERPC_DEF_SVR("MPC8343E", "MPC8343E",
+ POWERPC_DEF_SVR("mpc8343e", "MPC8343E",
CPU_POWERPC_MPC834x, POWERPC_SVR_8343E, e300)
- POWERPC_DEF_SVR("MPC8343EA", "MPC8343EA",
+ POWERPC_DEF_SVR("mpc8343ea", "MPC8343EA",
CPU_POWERPC_MPC834x, POWERPC_SVR_8343EA, e300)
- POWERPC_DEF_SVR("MPC8347T", "MPC8347T",
+ POWERPC_DEF_SVR("mpc8347t", "MPC8347T",
CPU_POWERPC_MPC834x, POWERPC_SVR_8347T, e300)
- POWERPC_DEF_SVR("MPC8347P", "MPC8347P",
+ POWERPC_DEF_SVR("mpc8347p", "MPC8347P",
CPU_POWERPC_MPC834x, POWERPC_SVR_8347P, e300)
- POWERPC_DEF_SVR("MPC8347AT", "MPC8347AT",
+ POWERPC_DEF_SVR("mpc8347at", "MPC8347AT",
CPU_POWERPC_MPC834x, POWERPC_SVR_8347AT, e300)
- POWERPC_DEF_SVR("MPC8347AP", "MPC8347AP",
+ POWERPC_DEF_SVR("mpc8347ap", "MPC8347AP",
CPU_POWERPC_MPC834x, POWERPC_SVR_8347AP, e300)
- POWERPC_DEF_SVR("MPC8347ET", "MPC8347ET",
+ POWERPC_DEF_SVR("mpc8347et", "MPC8347ET",
CPU_POWERPC_MPC834x, POWERPC_SVR_8347ET, e300)
- POWERPC_DEF_SVR("MPC8347EP", "MPC8343EP",
+ POWERPC_DEF_SVR("mpc8347ep", "MPC8343EP",
CPU_POWERPC_MPC834x, POWERPC_SVR_8347EP, e300)
- POWERPC_DEF_SVR("MPC8347EAT", "MPC8347EAT",
+ POWERPC_DEF_SVR("mpc8347eat", "MPC8347EAT",
CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAT, e300)
- POWERPC_DEF_SVR("MPC8347EAP", "MPC8343EAP",
+ POWERPC_DEF_SVR("mpc8347eap", "MPC8343EAP",
CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAP, e300)
- POWERPC_DEF_SVR("MPC8349", "MPC8349",
+ POWERPC_DEF_SVR("mpc8349", "MPC8349",
CPU_POWERPC_MPC834x, POWERPC_SVR_8349, e300)
- POWERPC_DEF_SVR("MPC8349A", "MPC8349A",
+ POWERPC_DEF_SVR("mpc8349a", "MPC8349A",
CPU_POWERPC_MPC834x, POWERPC_SVR_8349A, e300)
- POWERPC_DEF_SVR("MPC8349E", "MPC8349E",
+ POWERPC_DEF_SVR("mpc8349e", "MPC8349E",
CPU_POWERPC_MPC834x, POWERPC_SVR_8349E, e300)
- POWERPC_DEF_SVR("MPC8349EA", "MPC8349EA",
+ POWERPC_DEF_SVR("mpc8349ea", "MPC8349EA",
CPU_POWERPC_MPC834x, POWERPC_SVR_8349EA, e300)
#if defined(TODO)
- POWERPC_DEF_SVR("MPC8358E", "MPC8358E",
+ POWERPC_DEF_SVR("mpc8358e", "MPC8358E",
CPU_POWERPC_MPC835x, POWERPC_SVR_8358E, e300)
#endif
#if defined(TODO)
- POWERPC_DEF_SVR("MPC8360E", "MPC8360E",
+ POWERPC_DEF_SVR("mpc8360e", "MPC8360E",
CPU_POWERPC_MPC836x, POWERPC_SVR_8360E, e300)
#endif
- POWERPC_DEF_SVR("MPC8377", "MPC8377",
+ POWERPC_DEF_SVR("mpc8377", "MPC8377",
CPU_POWERPC_MPC837x, POWERPC_SVR_8377, e300)
- POWERPC_DEF_SVR("MPC8377E", "MPC8377E",
+ POWERPC_DEF_SVR("mpc8377e", "MPC8377E",
CPU_POWERPC_MPC837x, POWERPC_SVR_8377E, e300)
- POWERPC_DEF_SVR("MPC8378", "MPC8378",
+ POWERPC_DEF_SVR("mpc8378", "MPC8378",
CPU_POWERPC_MPC837x, POWERPC_SVR_8378, e300)
- POWERPC_DEF_SVR("MPC8378E", "MPC8378E",
+ POWERPC_DEF_SVR("mpc8378e", "MPC8378E",
CPU_POWERPC_MPC837x, POWERPC_SVR_8378E, e300)
- POWERPC_DEF_SVR("MPC8379", "MPC8379",
+ POWERPC_DEF_SVR("mpc8379", "MPC8379",
CPU_POWERPC_MPC837x, POWERPC_SVR_8379, e300)
- POWERPC_DEF_SVR("MPC8379E", "MPC8379E",
+ POWERPC_DEF_SVR("mpc8379e", "MPC8379E",
CPU_POWERPC_MPC837x, POWERPC_SVR_8379E, e300)
/* e500 family */
POWERPC_DEF_SVR("e500_v10", "PowerPC e500 v1.0 core",
@@ -697,115 +697,115 @@
CPU_POWERPC_e6500, POWERPC_SVR_E500, e6500)
#endif
/* PowerPC e500 microcontrollers */
- POWERPC_DEF_SVR("MPC8533_v10", "MPC8533 v1.0",
+ POWERPC_DEF_SVR("mpc8533_v10", "MPC8533 v1.0",
CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2)
- POWERPC_DEF_SVR("MPC8533_v11", "MPC8533 v1.1",
+ POWERPC_DEF_SVR("mpc8533_v11", "MPC8533 v1.1",
CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2)
- POWERPC_DEF_SVR("MPC8533E_v10", "MPC8533E v1.0",
+ POWERPC_DEF_SVR("mpc8533e_v10", "MPC8533E v1.0",
CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2)
- POWERPC_DEF_SVR("MPC8533E_v11", "MPC8533E v1.1",
+ POWERPC_DEF_SVR("mpc8533e_v11", "MPC8533E v1.1",
CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2)
- POWERPC_DEF_SVR("MPC8540_v10", "MPC8540 v1.0",
+ POWERPC_DEF_SVR("mpc8540_v10", "MPC8540 v1.0",
CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500v1)
- POWERPC_DEF_SVR("MPC8540_v20", "MPC8540 v2.0",
+ POWERPC_DEF_SVR("mpc8540_v20", "MPC8540 v2.0",
CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500v1)
- POWERPC_DEF_SVR("MPC8540_v21", "MPC8540 v2.1",
+ POWERPC_DEF_SVR("mpc8540_v21", "MPC8540 v2.1",
CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500v1)
- POWERPC_DEF_SVR("MPC8541_v10", "MPC8541 v1.0",
+ POWERPC_DEF_SVR("mpc8541_v10", "MPC8541 v1.0",
CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500v1)
- POWERPC_DEF_SVR("MPC8541_v11", "MPC8541 v1.1",
+ POWERPC_DEF_SVR("mpc8541_v11", "MPC8541 v1.1",
CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500v1)
- POWERPC_DEF_SVR("MPC8541E_v10", "MPC8541E v1.0",
+ POWERPC_DEF_SVR("mpc8541e_v10", "MPC8541E v1.0",
CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1)
- POWERPC_DEF_SVR("MPC8541E_v11", "MPC8541E v1.1",
+ POWERPC_DEF_SVR("mpc8541e_v11", "MPC8541E v1.1",
CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1)
- POWERPC_DEF_SVR("MPC8543_v10", "MPC8543 v1.0",
+ POWERPC_DEF_SVR("mpc8543_v10", "MPC8543 v1.0",
CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2)
- POWERPC_DEF_SVR("MPC8543_v11", "MPC8543 v1.1",
+ POWERPC_DEF_SVR("mpc8543_v11", "MPC8543 v1.1",
CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500v2)
- POWERPC_DEF_SVR("MPC8543_v20", "MPC8543 v2.0",
+ POWERPC_DEF_SVR("mpc8543_v20", "MPC8543 v2.0",
CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500v2)
- POWERPC_DEF_SVR("MPC8543_v21", "MPC8543 v2.1",
+ POWERPC_DEF_SVR("mpc8543_v21", "MPC8543 v2.1",
CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500v2)
- POWERPC_DEF_SVR("MPC8543E_v10", "MPC8543E v1.0",
+ POWERPC_DEF_SVR("mpc8543e_v10", "MPC8543E v1.0",
CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2)
- POWERPC_DEF_SVR("MPC8543E_v11", "MPC8543E v1.1",
+ POWERPC_DEF_SVR("mpc8543e_v11", "MPC8543E v1.1",
CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2)
- POWERPC_DEF_SVR("MPC8543E_v20", "MPC8543E v2.0",
+ POWERPC_DEF_SVR("mpc8543e_v20", "MPC8543E v2.0",
CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2)
- POWERPC_DEF_SVR("MPC8543E_v21", "MPC8543E v2.1",
+ POWERPC_DEF_SVR("mpc8543e_v21", "MPC8543E v2.1",
CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2)
- POWERPC_DEF_SVR("MPC8544_v10", "MPC8544 v1.0",
+ POWERPC_DEF_SVR("mpc8544_v10", "MPC8544 v1.0",
CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500v2)
- POWERPC_DEF_SVR("MPC8544_v11", "MPC8544 v1.1",
+ POWERPC_DEF_SVR("mpc8544_v11", "MPC8544 v1.1",
CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500v2)
- POWERPC_DEF_SVR("MPC8544E_v10", "MPC8544E v1.0",
+ POWERPC_DEF_SVR("mpc8544e_v10", "MPC8544E v1.0",
CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2)
- POWERPC_DEF_SVR("MPC8544E_v11", "MPC8544E v1.1",
+ POWERPC_DEF_SVR("mpc8544e_v11", "MPC8544E v1.1",
CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2)
- POWERPC_DEF_SVR("MPC8545_v20", "MPC8545 v2.0",
+ POWERPC_DEF_SVR("mpc8545_v20", "MPC8545 v2.0",
CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500v2)
- POWERPC_DEF_SVR("MPC8545_v21", "MPC8545 v2.1",
+ POWERPC_DEF_SVR("mpc8545_v21", "MPC8545 v2.1",
CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500v2)
- POWERPC_DEF_SVR("MPC8545E_v20", "MPC8545E v2.0",
+ POWERPC_DEF_SVR("mpc8545e_v20", "MPC8545E v2.0",
CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2)
- POWERPC_DEF_SVR("MPC8545E_v21", "MPC8545E v2.1",
+ POWERPC_DEF_SVR("mpc8545e_v21", "MPC8545E v2.1",
CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2)
- POWERPC_DEF_SVR("MPC8547E_v20", "MPC8547E v2.0",
+ POWERPC_DEF_SVR("mpc8547e_v20", "MPC8547E v2.0",
CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2)
- POWERPC_DEF_SVR("MPC8547E_v21", "MPC8547E v2.1",
+ POWERPC_DEF_SVR("mpc8547e_v21", "MPC8547E v2.1",
CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2)
- POWERPC_DEF_SVR("MPC8548_v10", "MPC8548 v1.0",
+ POWERPC_DEF_SVR("mpc8548_v10", "MPC8548 v1.0",
CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500v2)
- POWERPC_DEF_SVR("MPC8548_v11", "MPC8548 v1.1",
+ POWERPC_DEF_SVR("mpc8548_v11", "MPC8548 v1.1",
CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500v2)
- POWERPC_DEF_SVR("MPC8548_v20", "MPC8548 v2.0",
+ POWERPC_DEF_SVR("mpc8548_v20", "MPC8548 v2.0",
CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500v2)
- POWERPC_DEF_SVR("MPC8548_v21", "MPC8548 v2.1",
+ POWERPC_DEF_SVR("mpc8548_v21", "MPC8548 v2.1",
CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500v2)
- POWERPC_DEF_SVR("MPC8548E_v10", "MPC8548E v1.0",
+ POWERPC_DEF_SVR("mpc8548e_v10", "MPC8548E v1.0",
CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2)
- POWERPC_DEF_SVR("MPC8548E_v11", "MPC8548E v1.1",
+ POWERPC_DEF_SVR("mpc8548e_v11", "MPC8548E v1.1",
CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2)
- POWERPC_DEF_SVR("MPC8548E_v20", "MPC8548E v2.0",
+ POWERPC_DEF_SVR("mpc8548e_v20", "MPC8548E v2.0",
CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2)
- POWERPC_DEF_SVR("MPC8548E_v21", "MPC8548E v2.1",
+ POWERPC_DEF_SVR("mpc8548e_v21", "MPC8548E v2.1",
CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2)
- POWERPC_DEF_SVR("MPC8555_v10", "MPC8555 v1.0",
+ POWERPC_DEF_SVR("mpc8555_v10", "MPC8555 v1.0",
CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500v2)
- POWERPC_DEF_SVR("MPC8555_v11", "MPC8555 v1.1",
+ POWERPC_DEF_SVR("mpc8555_v11", "MPC8555 v1.1",
CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500v2)
- POWERPC_DEF_SVR("MPC8555E_v10", "MPC8555E v1.0",
+ POWERPC_DEF_SVR("mpc8555e_v10", "MPC8555E v1.0",
CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2)
- POWERPC_DEF_SVR("MPC8555E_v11", "MPC8555E v1.1",
+ POWERPC_DEF_SVR("mpc8555e_v11", "MPC8555E v1.1",
CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2)
- POWERPC_DEF_SVR("MPC8560_v10", "MPC8560 v1.0",
+ POWERPC_DEF_SVR("mpc8560_v10", "MPC8560 v1.0",
CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500v2)
- POWERPC_DEF_SVR("MPC8560_v20", "MPC8560 v2.0",
+ POWERPC_DEF_SVR("mpc8560_v20", "MPC8560 v2.0",
CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500v2)
- POWERPC_DEF_SVR("MPC8560_v21", "MPC8560 v2.1",
+ POWERPC_DEF_SVR("mpc8560_v21", "MPC8560 v2.1",
CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500v2)
- POWERPC_DEF_SVR("MPC8567", "MPC8567",
+ POWERPC_DEF_SVR("mpc8567", "MPC8567",
CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500v2)
- POWERPC_DEF_SVR("MPC8567E", "MPC8567E",
+ POWERPC_DEF_SVR("mpc8567e", "MPC8567E",
CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500v2)
- POWERPC_DEF_SVR("MPC8568", "MPC8568",
+ POWERPC_DEF_SVR("mpc8568", "MPC8568",
CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500v2)
- POWERPC_DEF_SVR("MPC8568E", "MPC8568E",
+ POWERPC_DEF_SVR("mpc8568e", "MPC8568E",
CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500v2)
- POWERPC_DEF_SVR("MPC8572", "MPC8572",
+ POWERPC_DEF_SVR("mpc8572", "MPC8572",
CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500v2)
- POWERPC_DEF_SVR("MPC8572E", "MPC8572E",
+ POWERPC_DEF_SVR("mpc8572e", "MPC8572E",
CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2)
/* e600 family */
POWERPC_DEF("e600", CPU_POWERPC_e600, e600,
"PowerPC e600 core")
/* PowerPC e600 microcontrollers */
- POWERPC_DEF_SVR("MPC8610", "MPC8610",
+ POWERPC_DEF_SVR("mpc8610", "MPC8610",
CPU_POWERPC_MPC8610, POWERPC_SVR_8610, e600)
- POWERPC_DEF_SVR("MPC8641", "MPC8641",
+ POWERPC_DEF_SVR("mpc8641", "MPC8641",
CPU_POWERPC_MPC8641, POWERPC_SVR_8641, e600)
- POWERPC_DEF_SVR("MPC8641D", "MPC8641D",
+ POWERPC_DEF_SVR("mpc8641d", "MPC8641D",
CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, e600)
/* 32 bits "classic" PowerPC */
/* PowerPC 6xx family */
@@ -1091,17 +1091,17 @@
"PowerPC 7457 v1.1 (G4)")
POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455,
"PowerPC 7457 v1.2 (G4)")
- POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445,
+ POWERPC_DEF("7447a_v1.0", CPU_POWERPC_74x7A_v10, 7445,
"PowerPC 7447A v1.0 (G4)")
- POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455,
+ POWERPC_DEF("7457a_v1.0", CPU_POWERPC_74x7A_v10, 7455,
"PowerPC 7457A v1.0 (G4)")
- POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445,
+ POWERPC_DEF("7447a_v1.1", CPU_POWERPC_74x7A_v11, 7445,
"PowerPC 7447A v1.1 (G4)")
- POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455,
+ POWERPC_DEF("7457a_v1.1", CPU_POWERPC_74x7A_v11, 7455,
"PowerPC 7457A v1.1 (G4)")
- POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445,
+ POWERPC_DEF("7447a_v1.2", CPU_POWERPC_74x7A_v12, 7445,
"PowerPC 7447A v1.2 (G4)")
- POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455,
+ POWERPC_DEF("7457a_v1.2", CPU_POWERPC_74x7A_v12, 7455,
"PowerPC 7457A v1.2 (G4)")
/* 64 bits PowerPC */
#if defined (TARGET_PPC64)
@@ -1116,37 +1116,37 @@
"PowerPC 631 (Power 3+)")
#endif
#if defined(TODO)
- POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4,
+ POWERPC_DEF("power4", CPU_POWERPC_POWER4, POWER4,
"POWER4")
#endif
#if defined(TODO)
- POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P,
+ POWERPC_DEF("power4+", CPU_POWERPC_POWER4P, POWER4P,
"POWER4p")
#endif
#if defined(TODO)
- POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5,
+ POWERPC_DEF("power5", CPU_POWERPC_POWER5, POWER5,
"POWER5")
#endif
- POWERPC_DEF("POWER5+_v2.1", CPU_POWERPC_POWER5P_v21, POWER5P,
+ POWERPC_DEF("power5+_v2.1", CPU_POWERPC_POWER5P_v21, POWER5P,
"POWER5+ v2.1")
#if defined(TODO)
- POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6,
+ POWERPC_DEF("power6", CPU_POWERPC_POWER6, POWER6,
"POWER6")
#endif
- POWERPC_DEF("POWER7_v2.3", CPU_POWERPC_POWER7_v23, POWER7,
+ POWERPC_DEF("power7_v2.3", CPU_POWERPC_POWER7_v23, POWER7,
"POWER7 v2.3")
- POWERPC_DEF("POWER7+_v2.1", CPU_POWERPC_POWER7P_v21, POWER7,
+ POWERPC_DEF("power7+_v2.1", CPU_POWERPC_POWER7P_v21, POWER7,
"POWER7+ v2.1")
- POWERPC_DEF("POWER8E_v2.1", CPU_POWERPC_POWER8E_v21, POWER8,
+ POWERPC_DEF("power8e_v2.1", CPU_POWERPC_POWER8E_v21, POWER8,
"POWER8E v2.1")
- POWERPC_DEF("POWER8_v2.0", CPU_POWERPC_POWER8_v20, POWER8,
+ POWERPC_DEF("power8_v2.0", CPU_POWERPC_POWER8_v20, POWER8,
"POWER8 v2.0")
- POWERPC_DEF("POWER8NVL_v1.0",CPU_POWERPC_POWER8NVL_v10, POWER8,
+ POWERPC_DEF("power8nvl_v1.0", CPU_POWERPC_POWER8NVL_v10, POWER8,
"POWER8NVL v1.0")
POWERPC_DEF("970_v2.2", CPU_POWERPC_970_v22, 970,
"PowerPC 970 v2.2")
- POWERPC_DEF("POWER9_v1.0", CPU_POWERPC_POWER9_BASE, POWER9,
+ POWERPC_DEF("power9_v1.0", CPU_POWERPC_POWER9_BASE, POWER9,
"POWER9 v1.0")
POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970,
@@ -1164,27 +1164,27 @@
POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970,
"PowerPC 970MP v1.1")
#if defined(TODO)
- POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970,
+ POWERPC_DEF("cell", CPU_POWERPC_CELL, 970,
"PowerPC Cell")
#endif
#if defined(TODO)
- POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970,
+ POWERPC_DEF("cell_v1.0", CPU_POWERPC_CELL_v10, 970,
"PowerPC Cell v1.0")
#endif
#if defined(TODO)
- POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970,
+ POWERPC_DEF("cell_v2.0", CPU_POWERPC_CELL_v20, 970,
"PowerPC Cell v2.0")
#endif
#if defined(TODO)
- POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970,
+ POWERPC_DEF("cell_v3.0", CPU_POWERPC_CELL_v30, 970,
"PowerPC Cell v3.0")
#endif
#if defined(TODO)
- POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970,
+ POWERPC_DEF("cell_v3.1", CPU_POWERPC_CELL_v31, 970,
"PowerPC Cell v3.1")
#endif
#if defined(TODO)
- POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970,
+ POWERPC_DEF("cell_v3.2", CPU_POWERPC_CELL_v32, 970,
"PowerPC Cell v3.2")
#endif
#if defined(TODO)
@@ -1192,34 +1192,34 @@
* and the PowerPC 64 one.
*/
/* What about A10 & A30 ? */
- POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64,
+ POWERPC_DEF("rs64", CPU_POWERPC_RS64, RS64,
"RS64 (Apache/A35)")
#endif
#if defined(TODO)
- POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64,
+ POWERPC_DEF("rs64-ii", CPU_POWERPC_RS64II, RS64,
"RS64-II (NorthStar/A50)")
#endif
#if defined(TODO)
- POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64,
+ POWERPC_DEF("rs64-iii", CPU_POWERPC_RS64III, RS64,
"RS64-III (Pulsar)")
#endif
#if defined(TODO)
- POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64,
+ POWERPC_DEF("rs64-iv", CPU_POWERPC_RS64IV, RS64,
"RS64-IV (IceStar/IStar/SStar)")
#endif
#endif /* defined (TARGET_PPC64) */
/* POWER */
#if defined(TODO)
- POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER,
+ POWERPC_DEF("power", CPU_POWERPC_POWER, POWER,
"Original POWER")
#endif
#if defined(TODO)
- POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER,
+ POWERPC_DEF("power2", CPU_POWERPC_POWER2, POWER,
"POWER2")
#endif
/* PA semi cores */
#if defined(TODO)
- POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T,
+ POWERPC_DEF("pa6t", CPU_POWERPC_PA6T, PA6T,
"PA PA6T")
#endif
@@ -1228,172 +1228,172 @@
/* PowerPC CPU aliases */
PowerPCCPUAlias ppc_cpu_aliases[] = {
- { "403", "403GC" },
- { "405", "405D4" },
- { "405CR", "405CRc" },
- { "405GP", "405GPd" },
- { "405GPe", "405CRc" },
+ { "403", "403gc" },
+ { "405", "405d4" },
+ { "405cr", "405crc" },
+ { "405gp", "405gpd" },
+ { "405gpe", "405crc" },
{ "x2vp7", "x2vp4" },
{ "x2vp50", "x2vp20" },
- { "440EP", "440EPb" },
- { "440GP", "440GPc" },
- { "440GR", "440GRa" },
- { "440GX", "440GXf" },
+ { "440ep", "440epb" },
+ { "440gp", "440gpc" },
+ { "440gr", "440gra" },
+ { "440gx", "440gxf" },
- { "RCPU", "MPC5xx" },
+ { "rcpu", "mpc5xx" },
/* MPC5xx microcontrollers */
- { "MGT560", "MPC5xx" },
- { "MPC509", "MPC5xx" },
- { "MPC533", "MPC5xx" },
- { "MPC534", "MPC5xx" },
- { "MPC555", "MPC5xx" },
- { "MPC556", "MPC5xx" },
- { "MPC560", "MPC5xx" },
- { "MPC561", "MPC5xx" },
- { "MPC562", "MPC5xx" },
- { "MPC563", "MPC5xx" },
- { "MPC564", "MPC5xx" },
- { "MPC565", "MPC5xx" },
- { "MPC566", "MPC5xx" },
+ { "mgt560", "mpc5xx" },
+ { "mpc509", "mpc5xx" },
+ { "mpc533", "mpc5xx" },
+ { "mpc534", "mpc5xx" },
+ { "mpc555", "mpc5xx" },
+ { "mpc556", "mpc5xx" },
+ { "mpc560", "mpc5xx" },
+ { "mpc561", "mpc5xx" },
+ { "mpc562", "mpc5xx" },
+ { "mpc563", "mpc5xx" },
+ { "mpc564", "mpc5xx" },
+ { "mpc565", "mpc5xx" },
+ { "mpc566", "mpc5xx" },
- { "PowerQUICC", "MPC8xx" },
+ { "powerquicc", "mpc8xx" },
/* MPC8xx microcontrollers */
- { "MGT823", "MPC8xx" },
- { "MPC821", "MPC8xx" },
- { "MPC823", "MPC8xx" },
- { "MPC850", "MPC8xx" },
- { "MPC852T", "MPC8xx" },
- { "MPC855T", "MPC8xx" },
- { "MPC857", "MPC8xx" },
- { "MPC859", "MPC8xx" },
- { "MPC860", "MPC8xx" },
- { "MPC862", "MPC8xx" },
- { "MPC866", "MPC8xx" },
- { "MPC870", "MPC8xx" },
- { "MPC875", "MPC8xx" },
- { "MPC880", "MPC8xx" },
- { "MPC885", "MPC8xx" },
+ { "mgt823", "mpc8xx" },
+ { "mpc821", "mpc8xx" },
+ { "mpc823", "mpc8xx" },
+ { "mpc850", "mpc8xx" },
+ { "mpc852t", "mpc8xx" },
+ { "mpc855t", "mpc8xx" },
+ { "mpc857", "mpc8xx" },
+ { "mpc859", "mpc8xx" },
+ { "mpc860", "mpc8xx" },
+ { "mpc862", "mpc8xx" },
+ { "mpc866", "mpc8xx" },
+ { "mpc870", "mpc8xx" },
+ { "mpc875", "mpc8xx" },
+ { "mpc880", "mpc8xx" },
+ { "mpc885", "mpc8xx" },
/* PowerPC MPC603 microcontrollers */
- { "MPC8240", "603" },
+ { "mpc8240", "603" },
- { "MPC52xx", "MPC5200" },
- { "MPC5200", "MPC5200_v12" },
- { "MPC5200B", "MPC5200B_v21" },
+ { "mpc52xx", "mpc5200" },
+ { "mpc5200", "mpc5200_v12" },
+ { "mpc5200b", "mpc5200b_v21" },
- { "MPC82xx", "MPC8280" },
- { "PowerQUICC-II", "MPC82xx" },
- { "MPC8241", "G2HiP4" },
- { "MPC8245", "G2HiP4" },
- { "MPC8247", "G2leGP3" },
- { "MPC8248", "G2leGP3" },
- { "MPC8250", "MPC8250_HiP4" },
- { "MPC8250_HiP3", "G2HiP3" },
- { "MPC8250_HiP4", "G2HiP4" },
- { "MPC8255", "MPC8255_HiP4" },
- { "MPC8255_HiP3", "G2HiP3" },
- { "MPC8255_HiP4", "G2HiP4" },
- { "MPC8260", "MPC8260_HiP4" },
- { "MPC8260_HiP3", "G2HiP3" },
- { "MPC8260_HiP4", "G2HiP4" },
- { "MPC8264", "MPC8264_HiP4" },
- { "MPC8264_HiP3", "G2HiP3" },
- { "MPC8264_HiP4", "G2HiP4" },
- { "MPC8265", "MPC8265_HiP4" },
- { "MPC8265_HiP3", "G2HiP3" },
- { "MPC8265_HiP4", "G2HiP4" },
- { "MPC8266", "MPC8266_HiP4" },
- { "MPC8266_HiP3", "G2HiP3" },
- { "MPC8266_HiP4", "G2HiP4" },
- { "MPC8270", "G2leGP3" },
- { "MPC8271", "G2leGP3" },
- { "MPC8272", "G2leGP3" },
- { "MPC8275", "G2leGP3" },
- { "MPC8280", "G2leGP3" },
+ { "mpc82xx", "mpc8280" },
+ { "powerquicc-ii", "mpc82xx" },
+ { "mpc8241", "g2hip4" },
+ { "mpc8245", "g2hip4" },
+ { "mpc8247", "g2legp3" },
+ { "mpc8248", "g2legp3" },
+ { "mpc8250", "mpc8250_hip4" },
+ { "mpc8250_hip3", "g2hip3" },
+ { "mpc8250_hip4", "g2hip4" },
+ { "mpc8255", "mpc8255_hip4" },
+ { "mpc8255_hip3", "g2hip3" },
+ { "mpc8255_hip4", "g2hip4" },
+ { "mpc8260", "mpc8260_hip4" },
+ { "mpc8260_hip3", "g2hip3" },
+ { "mpc8260_hip4", "g2hip4" },
+ { "mpc8264", "mpc8264_hip4" },
+ { "mpc8264_hip3", "g2hip3" },
+ { "mpc8264_hip4", "g2hip4" },
+ { "mpc8265", "mpc8265_hip4" },
+ { "mpc8265_hip3", "g2hip3" },
+ { "mpc8265_hip4", "g2hip4" },
+ { "mpc8266", "mpc8266_hip4" },
+ { "mpc8266_hip3", "g2hip3" },
+ { "mpc8266_hip4", "g2hip4" },
+ { "mpc8270", "g2legp3" },
+ { "mpc8271", "g2legp3" },
+ { "mpc8272", "g2legp3" },
+ { "mpc8275", "g2legp3" },
+ { "mpc8280", "g2legp3" },
{ "e200", "e200z6" },
{ "e300", "e300c3" },
- { "MPC8347", "MPC8347T" },
- { "MPC8347A", "MPC8347AT" },
- { "MPC8347E", "MPC8347ET" },
- { "MPC8347EA", "MPC8347EAT" },
+ { "mpc8347", "mpc8347t" },
+ { "mpc8347a", "mpc8347at" },
+ { "mpc8347e", "mpc8347et" },
+ { "mpc8347ea", "mpc8347eat" },
{ "e500", "e500v2_v22" },
{ "e500v1", "e500_v20" },
{ "e500v2", "e500v2_v22" },
- { "MPC8533", "MPC8533_v11" },
- { "MPC8533E", "MPC8533E_v11" },
- { "MPC8540", "MPC8540_v21" },
- { "MPC8541", "MPC8541_v11" },
- { "MPC8541E", "MPC8541E_v11" },
- { "MPC8543", "MPC8543_v21" },
- { "MPC8543E", "MPC8543E_v21" },
- { "MPC8544", "MPC8544_v11" },
- { "MPC8544E", "MPC8544E_v11" },
- { "MPC8545", "MPC8545_v21" },
- { "MPC8545E", "MPC8545E_v21" },
- { "MPC8547E", "MPC8547E_v21" },
- { "MPC8548", "MPC8548_v21" },
- { "MPC8548E", "MPC8548E_v21" },
- { "MPC8555", "MPC8555_v11" },
- { "MPC8555E", "MPC8555E_v11" },
- { "MPC8560", "MPC8560_v21" },
+ { "mpc8533", "mpc8533_v11" },
+ { "mpc8533e", "mpc8533e_v11" },
+ { "mpc8540", "mpc8540_v21" },
+ { "mpc8541", "mpc8541_v11" },
+ { "mpc8541e", "mpc8541e_v11" },
+ { "mpc8543", "mpc8543_v21" },
+ { "mpc8543e", "mpc8543e_v21" },
+ { "mpc8544", "mpc8544_v11" },
+ { "mpc8544e", "mpc8544e_v11" },
+ { "mpc8545", "mpc8545_v21" },
+ { "mpc8545e", "mpc8545e_v21" },
+ { "mpc8547e", "mpc8547e_v21" },
+ { "mpc8548", "mpc8548_v21" },
+ { "mpc8548e", "mpc8548e_v21" },
+ { "mpc8555", "mpc8555_v11" },
+ { "mpc8555e", "mpc8555e_v11" },
+ { "mpc8560", "mpc8560_v21" },
{ "601", "601_v2" },
{ "601v", "601_v2" },
- { "Vanilla", "603" },
+ { "vanilla", "603" },
{ "603e", "603e_v4.1" },
- { "Stretch", "603e" },
- { "Vaillant", "603e7v" },
+ { "stretch", "603e" },
+ { "vaillant", "603e7v" },
{ "603r", "603e7t" },
- { "Goldeneye", "603r" },
+ { "goldeneye", "603r" },
{ "604e", "604e_v2.4" },
- { "Sirocco", "604e" },
- { "Mach5", "604r" },
+ { "sirocco", "604e" },
+ { "mach5", "604r" },
{ "740", "740_v3.1" },
- { "Arthur", "740" },
+ { "arthur", "740" },
{ "750", "750_v3.1" },
- { "Typhoon", "750" },
- { "G3", "750" },
- { "Conan/Doyle", "750p" },
+ { "typhoon", "750" },
+ { "g3", "750" },
+ { "conan/doyle", "750p" },
{ "750cl", "750cl_v2.0" },
{ "750cx", "750cx_v2.2" },
{ "750cxe", "750cxe_v3.1b" },
{ "750fx", "750fx_v2.3" },
{ "750gx", "750gx_v1.2" },
{ "750l", "750l_v3.2" },
- { "LoneStar", "750l" },
+ { "lonestar", "750l" },
{ "745", "745_v2.8" },
{ "755", "755_v2.8" },
- { "Goldfinger", "755" },
+ { "goldfinger", "755" },
{ "7400", "7400_v2.9" },
- { "Max", "7400" },
- { "G4", "7400" },
+ { "max", "7400" },
+ { "g4", "7400" },
{ "7410", "7410_v1.4" },
- { "Nitro", "7410" },
+ { "nitro", "7410" },
{ "7448", "7448_v2.1" },
{ "7450", "7450_v2.1" },
- { "Vger", "7450" },
+ { "vger", "7450" },
{ "7441", "7441_v2.3" },
{ "7451", "7451_v2.3" },
{ "7445", "7445_v3.2" },
{ "7455", "7455_v3.2" },
- { "Apollo6", "7455" },
+ { "apollo6", "7455" },
{ "7447", "7447_v1.1" },
{ "7457", "7457_v1.2" },
- { "Apollo7", "7457" },
- { "7447A", "7447A_v1.2" },
- { "7457A", "7457A_v1.2" },
- { "Apollo7PM", "7457A_v1.0" },
+ { "apollo7", "7457" },
+ { "7447a", "7447a_v1.2" },
+ { "7457a", "7457a_v1.2" },
+ { "apollo7pm", "7457a_v1.0" },
#if defined(TARGET_PPC64)
- { "POWER3", "630" },
- { "POWER3+", "631" },
- { "POWER5+", "POWER5+_v2.1" },
- { "POWER5gs", "POWER5+_v2.1" },
- { "POWER7", "POWER7_v2.3" },
- { "POWER7+", "POWER7+_v2.1" },
- { "POWER8E", "POWER8E_v2.1" },
- { "POWER8", "POWER8_v2.0" },
- { "POWER8NVL", "POWER8NVL_v1.0" },
- { "POWER9", "POWER9_v1.0" },
+ { "power3", "630" },
+ { "power3+", "631" },
+ { "power5+", "power5+_v2.1" },
+ { "power5gs", "power5+_v2.1" },
+ { "power7", "power7_v2.3" },
+ { "power7+", "power7+_v2.1" },
+ { "power8e", "power8e_v2.1" },
+ { "power8", "power8_v2.0" },
+ { "power8nvl", "power8nvl_v1.0" },
+ { "power9", "power9_v1.0" },
{ "970", "970_v2.2" },
{ "970fx", "970fx_v3.1" },
{ "970mp", "970mp_v1.1" },
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index abcfe13b8a..6861f2f585 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -2525,7 +2525,7 @@ static int kvm_ppc_register_host_cpu_type(void)
*/
dc = DEVICE_CLASS(ppc_cpu_get_family_class(pvr_pcc));
for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
- if (strcmp(ppc_cpu_aliases[i].alias, dc->desc) == 0) {
+ if (strcasecmp(ppc_cpu_aliases[i].alias, dc->desc) == 0) {
char *suffix;
ppc_cpu_aliases[i].model = g_strdup(object_class_get_name(oc));
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index ee42c56288..f392fa6ea9 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -10326,7 +10326,7 @@ static ObjectClass *ppc_cpu_class_by_name(const char *name)
}
for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
- if (strcmp(ppc_cpu_aliases[i].alias, name) == 0) {
+ if (strcasecmp(ppc_cpu_aliases[i].alias, name) == 0) {
return ppc_cpu_class_by_alias(&ppc_cpu_aliases[i]);
}
}
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 35/40] ppc: make cpu alias point only to real cpu models
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (33 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 34/40] ppc: make cpu_model translation to type consistent David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 36/40] ppc: replace inter-function cyclic dependency/recurssion with 2 simple lookups David Gibson
` (5 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
David Gibson
From: Igor Mammedov <imammedo@redhat.com>
alias pointing to another alias forces lookup code to
do recurrsive translation till real cpu model is reached.
Drop this nonsence and make each alias point to cpu model
that has corresponding CPU type. It will allow to drop
recurrsion in cpu model translation code and actually
make ppc_cpu_aliases[] content use PowerPCCPUAlias
fields properly
(i.e. alias goes into .alias and model goes into .model)
While at it add TODO defines around aliases that point to
cpu models excluded by the same TODO defines.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu-models.c | 56 ++++++++++++++++++++++++++-----------------------
target/ppc/cpu-models.h | 2 +-
2 files changed, 31 insertions(+), 27 deletions(-)
diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c
index 07a48ca548..64629fc39f 100644
--- a/target/ppc/cpu-models.c
+++ b/target/ppc/cpu-models.c
@@ -1237,6 +1237,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "x2vp50", "x2vp20" },
{ "440ep", "440epb" },
+#if defined(TODO_USER_ONLY)
{ "440gp", "440gpc" },
{ "440gr", "440gra" },
{ "440gx", "440gxf" },
@@ -1274,36 +1275,37 @@ PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "mpc875", "mpc8xx" },
{ "mpc880", "mpc8xx" },
{ "mpc885", "mpc8xx" },
+#endif
/* PowerPC MPC603 microcontrollers */
{ "mpc8240", "603" },
- { "mpc52xx", "mpc5200" },
+ { "mpc52xx", "mpc5200_v12" },
{ "mpc5200", "mpc5200_v12" },
{ "mpc5200b", "mpc5200b_v21" },
- { "mpc82xx", "mpc8280" },
- { "powerquicc-ii", "mpc82xx" },
+ { "mpc82xx", "g2legp3" },
+ { "powerquicc-ii", "g2legp3" },
{ "mpc8241", "g2hip4" },
{ "mpc8245", "g2hip4" },
{ "mpc8247", "g2legp3" },
{ "mpc8248", "g2legp3" },
- { "mpc8250", "mpc8250_hip4" },
+ { "mpc8250", "g2hip4" },
{ "mpc8250_hip3", "g2hip3" },
{ "mpc8250_hip4", "g2hip4" },
- { "mpc8255", "mpc8255_hip4" },
+ { "mpc8255", "g2hip4" },
{ "mpc8255_hip3", "g2hip3" },
{ "mpc8255_hip4", "g2hip4" },
- { "mpc8260", "mpc8260_hip4" },
+ { "mpc8260", "g2hip4" },
{ "mpc8260_hip3", "g2hip3" },
{ "mpc8260_hip4", "g2hip4" },
- { "mpc8264", "mpc8264_hip4" },
+ { "mpc8264", "g2hip4" },
{ "mpc8264_hip3", "g2hip3" },
{ "mpc8264_hip4", "g2hip4" },
- { "mpc8265", "mpc8265_hip4" },
+ { "mpc8265", "g2hip4" },
{ "mpc8265_hip3", "g2hip3" },
{ "mpc8265_hip4", "g2hip4" },
- { "mpc8266", "mpc8266_hip4" },
+ { "mpc8266", "g2hip4" },
{ "mpc8266_hip3", "g2hip3" },
{ "mpc8266_hip4", "g2hip4" },
{ "mpc8270", "g2legp3" },
@@ -1341,18 +1343,18 @@ PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "601v", "601_v2" },
{ "vanilla", "603" },
{ "603e", "603e_v4.1" },
- { "stretch", "603e" },
+ { "stretch", "603e_v4.1" },
{ "vaillant", "603e7v" },
{ "603r", "603e7t" },
- { "goldeneye", "603r" },
+ { "goldeneye", "603e7t" },
{ "604e", "604e_v2.4" },
- { "sirocco", "604e" },
+ { "sirocco", "604e_v2.4" },
{ "mach5", "604r" },
{ "740", "740_v3.1" },
- { "arthur", "740" },
+ { "arthur", "740_v3.1" },
{ "750", "750_v3.1" },
- { "typhoon", "750" },
- { "g3", "750" },
+ { "typhoon", "750_v3.1" },
+ { "g3", "750_v3.1" },
{ "conan/doyle", "750p" },
{ "750cl", "750cl_v2.0" },
{ "750cx", "750cx_v2.2" },
@@ -1360,32 +1362,34 @@ PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "750fx", "750fx_v2.3" },
{ "750gx", "750gx_v1.2" },
{ "750l", "750l_v3.2" },
- { "lonestar", "750l" },
+ { "lonestar", "750l_v3.2" },
{ "745", "745_v2.8" },
{ "755", "755_v2.8" },
- { "goldfinger", "755" },
+ { "goldfinger", "755_v2.8" },
{ "7400", "7400_v2.9" },
- { "max", "7400" },
- { "g4", "7400" },
+ { "max", "7400_v2.9" },
+ { "g4", "7400_v2.9" },
{ "7410", "7410_v1.4" },
- { "nitro", "7410" },
+ { "nitro", "7410_v1.4" },
{ "7448", "7448_v2.1" },
{ "7450", "7450_v2.1" },
- { "vger", "7450" },
+ { "vger", "7450_v2.1" },
{ "7441", "7441_v2.3" },
{ "7451", "7451_v2.3" },
{ "7445", "7445_v3.2" },
{ "7455", "7455_v3.2" },
- { "apollo6", "7455" },
+ { "apollo6", "7455_v3.2" },
{ "7447", "7447_v1.1" },
{ "7457", "7457_v1.2" },
- { "apollo7", "7457" },
+ { "apollo7", "7457_v1.2" },
{ "7447a", "7447a_v1.2" },
{ "7457a", "7457a_v1.2" },
{ "apollo7pm", "7457a_v1.0" },
#if defined(TARGET_PPC64)
+#if defined(TODO)
{ "power3", "630" },
{ "power3+", "631" },
+#endif
{ "power5+", "power5+_v2.1" },
{ "power5gs", "power5+_v2.1" },
{ "power7", "power7_v2.3" },
@@ -1401,10 +1405,10 @@ PowerPCCPUAlias ppc_cpu_aliases[] = {
/* Generic PowerPCs */
#if defined(TARGET_PPC64)
- { "ppc64", "970fx" },
+ { "ppc64", "970fx_v3.1" },
#endif
{ "ppc32", "604" },
- { "ppc", "ppc32" },
- { "default", "ppc" },
+ { "ppc", "604" },
+ { "default", "604" },
{ NULL, NULL }
};
diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h
index eaa6849a42..629f112337 100644
--- a/target/ppc/cpu-models.h
+++ b/target/ppc/cpu-models.h
@@ -24,7 +24,7 @@
/**
* PowerPCCPUAlias:
* @alias: The alias name.
- * @model: The CPU model @alias refers to.
+ * @model: The CPU model @alias refers to, that directly resolves into CPU type
*
* A mapping entry from CPU @alias to CPU @model.
*/
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 36/40] ppc: replace inter-function cyclic dependency/recurssion with 2 simple lookups
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (34 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 35/40] ppc: make cpu alias point only to real cpu models David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 37/40] ppc: simplify cpu model lookup by PVR David Gibson
` (4 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
David Gibson
From: Igor Mammedov <imammedo@redhat.com>
previous patches cleaned up cpu model/alias naming which
allows to simplify cpu model/alias to cpu type lookup a bit
byt removing recurssion and dependency of ppc_cpu_class_by_name() /
ppc_cpu_class_by_alias() on each other.
Besides of simplifying code it reduces it by ~15LOC.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate_init.c | 43 +++++++++++++------------------------------
1 file changed, 13 insertions(+), 30 deletions(-)
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index f392fa6ea9..4092310c83 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -10252,22 +10252,6 @@ PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
return pcc;
}
-static gint ppc_cpu_compare_class_name(gconstpointer a, gconstpointer b)
-{
- ObjectClass *oc = (ObjectClass *)a;
- const char *name = b;
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- if (strncasecmp(name, object_class_get_name(oc), strlen(name)) == 0 &&
- ppc_cpu_is_valid(pcc) &&
- strcmp(object_class_get_name(oc) + strlen(name),
- POWERPC_CPU_TYPE_SUFFIX) == 0) {
- return 0;
- }
- return -1;
-}
-
-
static ObjectClass *ppc_cpu_class_by_name(const char *name);
static ObjectClass *ppc_cpu_class_by_alias(PowerPCCPUAlias *alias)
@@ -10292,8 +10276,8 @@ static ObjectClass *ppc_cpu_class_by_alias(PowerPCCPUAlias *alias)
static ObjectClass *ppc_cpu_class_by_name(const char *name)
{
- GSList *list, *item;
- ObjectClass *ret = NULL;
+ char *cpu_model, *typename;
+ ObjectClass *oc;
const char *p;
int i, len;
@@ -10314,21 +10298,20 @@ static ObjectClass *ppc_cpu_class_by_name(const char *name)
}
}
- list = object_class_get_list(TYPE_POWERPC_CPU, false);
- item = g_slist_find_custom(list, name, ppc_cpu_compare_class_name);
- if (item != NULL) {
- ret = OBJECT_CLASS(item->data);
+ cpu_model = g_ascii_strdown(name, -1);
+ p = ppc_cpu_lookup_alias(cpu_model);
+ if (p) {
+ g_free(cpu_model);
+ cpu_model = g_strdup(p);
}
- g_slist_free(list);
- if (ret) {
- return ret;
- }
+ typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model);
+ oc = object_class_by_name(typename);
+ g_free(typename);
+ g_free(cpu_model);
- for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
- if (strcasecmp(ppc_cpu_aliases[i].alias, name) == 0) {
- return ppc_cpu_class_by_alias(&ppc_cpu_aliases[i]);
- }
+ if (oc && ppc_cpu_is_valid(POWERPC_CPU_CLASS(oc))) {
+ return oc;
}
return NULL;
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 37/40] ppc: simplify cpu model lookup by PVR
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (35 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 36/40] ppc: replace inter-function cyclic dependency/recurssion with 2 simple lookups David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 38/40] ppc: drop caching ObjectClass from PowerPCCPUAlias David Gibson
` (3 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
David Gibson
From: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate_init.c | 27 +++++++++++----------------
1 file changed, 11 insertions(+), 16 deletions(-)
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 4092310c83..7c1d83b489 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -34,6 +34,7 @@
#include "hw/ppc/ppc.h"
#include "mmu-book3s-v3.h"
#include "sysemu/qtest.h"
+#include "qemu/cutils.h"
//#define PPC_DUMP_CPU
//#define PPC_DEBUG_SPR
@@ -10279,22 +10280,16 @@ static ObjectClass *ppc_cpu_class_by_name(const char *name)
char *cpu_model, *typename;
ObjectClass *oc;
const char *p;
- int i, len;
-
- /* Check if the given name is a PVR */
- len = strlen(name);
- if (len == 10 && name[0] == '0' && name[1] == 'x') {
- p = name + 2;
- goto check_pvr;
- } else if (len == 8) {
- p = name;
- check_pvr:
- for (i = 0; i < 8; i++) {
- if (!qemu_isxdigit(*p++))
- break;
- }
- if (i == 8) {
- return OBJECT_CLASS(ppc_cpu_class_by_pvr(strtoul(name, NULL, 16)));
+ unsigned long pvr;
+
+ /* Lookup by PVR if cpu_model is valid 8 digit hex number
+ * (excl: 0x prefix if present)
+ */
+ if (!qemu_strtoul(name, &p, 16, &pvr)) {
+ int len = p - name;
+ len = (len == 10) && (name[1] == 'x') ? len - 2 : len;
+ if ((len == 8) && (*p == '\0')) {
+ return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr));
}
}
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 38/40] ppc: drop caching ObjectClass from PowerPCCPUAlias
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (36 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 37/40] ppc: simplify cpu model lookup by PVR David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 39/40] ppc: remove non implemented cpu models David Gibson
` (2 subsequent siblings)
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
David Gibson
From: Igor Mammedov <imammedo@redhat.com>
Caching there practically doesn't give any benefits
and that at slow path druring querying supported CPU list.
But it introduces non conventional path of where from
comes used CPU type name (kvm_ppc_register_host_cpu_type).
Taking in account that kvm_ppc_register_host_cpu_type()
fixes up models the aliases point to, it's sufficient to
make ppc_cpu_class_by_name() translate cpu alias to
correct cpu type name.
So drop PowerPCCPUAlias::oc field + ppc_cpu_class_by_alias()
and let ppc_cpu_class_by_name() do conversion to cpu type name,
which simplifies code a little bit saving ~20LOC and trouble
wondering why ppc_cpu_class_by_alias() is necessary.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu-models.h | 1 -
target/ppc/kvm.c | 1 -
target/ppc/translate_init.c | 26 ++------------------------
3 files changed, 2 insertions(+), 26 deletions(-)
diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h
index 629f112337..df31d7f492 100644
--- a/target/ppc/cpu-models.h
+++ b/target/ppc/cpu-models.h
@@ -31,7 +31,6 @@
typedef struct PowerPCCPUAlias {
const char *alias;
const char *model;
- ObjectClass *oc;
} PowerPCCPUAlias;
extern PowerPCCPUAlias ppc_cpu_aliases[];
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 6861f2f585..6442dfcb95 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -2533,7 +2533,6 @@ static int kvm_ppc_register_host_cpu_type(void)
if (suffix) {
*suffix = 0;
}
- ppc_cpu_aliases[i].oc = oc;
break;
}
}
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 7c1d83b489..3e24cddb86 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -10253,28 +10253,6 @@ PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
return pcc;
}
-static ObjectClass *ppc_cpu_class_by_name(const char *name);
-
-static ObjectClass *ppc_cpu_class_by_alias(PowerPCCPUAlias *alias)
-{
- ObjectClass *invalid_class = (void*)ppc_cpu_class_by_alias;
-
- /* Cache target class lookups in the alias table */
- if (!alias->oc) {
- alias->oc = ppc_cpu_class_by_name(alias->model);
- if (!alias->oc) {
- /* Fast check for non-existing aliases */
- alias->oc = invalid_class;
- }
- }
-
- if (alias->oc == invalid_class) {
- return NULL;
- } else {
- return alias->oc;
- }
-}
-
static ObjectClass *ppc_cpu_class_by_name(const char *name)
{
char *cpu_model, *typename;
@@ -10386,7 +10364,7 @@ static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
name, pcc->pvr);
for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
- ObjectClass *alias_oc = ppc_cpu_class_by_alias(alias);
+ ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
if (alias_oc != oc) {
continue;
@@ -10466,7 +10444,7 @@ CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
CpuDefinitionInfoList *entry;
CpuDefinitionInfo *info;
- oc = ppc_cpu_class_by_alias(alias);
+ oc = ppc_cpu_class_by_name(alias->model);
if (oc == NULL) {
continue;
}
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 39/40] ppc: remove non implemented cpu models
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (37 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 38/40] ppc: drop caching ObjectClass from PowerPCCPUAlias David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 10:35 ` [Qemu-devel] [PULL 40/40] ppc: spapr: Move VCPU ID calculation into sPAPR David Gibson
2017-09-08 15:04 ` [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 Peter Maydell
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
David Gibson
From: Igor Mammedov <imammedo@redhat.com>
Remove cpu models that aren't implemented and are not
compiled/tested since they are under TODO ifdef
which isn't defined in sources.
If someone really needs a removed model he/she should add
as regular one with corresponding implementation.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu-models.c | 455 ------------------------------------------------
1 file changed, 455 deletions(-)
diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c
index 64629fc39f..9626d6b7c4 100644
--- a/target/ppc/cpu-models.c
+++ b/target/ppc/cpu-models.c
@@ -19,11 +19,6 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
-/* A lot of PowerPC definition have been included here.
- * Most of them are not usable for now but have been kept
- * inside "#if defined(TODO) ... #endif" statements to make tests easier.
- */
-
#include "qemu/osdep.h"
#include "cpu.h"
#include "cpu-models.h"
@@ -79,10 +74,6 @@
"PowerPC 401A1")
POWERPC_DEF("401b2", CPU_POWERPC_401B2, 401x2,
"PowerPC 401B2")
-#if defined(TODO)
- POWERPC_DEF("401b3", CPU_POWERPC_401B3, 401x3,
- "PowerPC 401B3")
-#endif
POWERPC_DEF("401c2", CPU_POWERPC_401C2, 401x2,
"PowerPC 401C2")
POWERPC_DEF("401d2", CPU_POWERPC_401D2, 401x2,
@@ -95,18 +86,10 @@
POWERPC_DEF("401g2", CPU_POWERPC_401G2, 401x2,
"PowerPC 401G2")
/* PowerPC 401 microcontrollers */
-#if defined(TODO)
- POWERPC_DEF("401gf", CPU_POWERPC_401GF, 401,
- "PowerPC 401GF")
-#endif
POWERPC_DEF("iop480", CPU_POWERPC_IOP480, IOP480,
"IOP480 (401 microcontroller)")
POWERPC_DEF("cobra", CPU_POWERPC_COBRA, 401,
"IBM Processor for Network Resources")
-#if defined(TODO)
- POWERPC_DEF("xipchip", CPU_POWERPC_XIPCHIP, 401,
- NULL)
-#endif
/* PowerPC 403 family */
/* PowerPC 403 microcontrollers */
POWERPC_DEF("403ga", CPU_POWERPC_403GA, 403,
@@ -117,64 +100,12 @@
"PowerPC 403 GC")
POWERPC_DEF("403gcx", CPU_POWERPC_403GCX, 403GCX,
"PowerPC 403 GCX")
-#if defined(TODO)
- POWERPC_DEF("403gp", CPU_POWERPC_403GP, 403,
- "PowerPC 403 GP")
-#endif
/* PowerPC 405 family */
/* PowerPC 405 cores */
-#if defined(TODO)
- POWERPC_DEF("405a3", CPU_POWERPC_405A3, 405,
- "PowerPC 405 A3")
-#endif
-#if defined(TODO)
- POWERPC_DEF("405a4", CPU_POWERPC_405A4, 405,
- "PowerPC 405 A4")
-#endif
-#if defined(TODO)
- POWERPC_DEF("405b3", CPU_POWERPC_405B3, 405,
- "PowerPC 405 B3")
-#endif
-#if defined(TODO)
- POWERPC_DEF("405b4", CPU_POWERPC_405B4, 405,
- "PowerPC 405 B4")
-#endif
-#if defined(TODO)
- POWERPC_DEF("405c3", CPU_POWERPC_405C3, 405,
- "PowerPC 405 C3")
-#endif
-#if defined(TODO)
- POWERPC_DEF("405c4", CPU_POWERPC_405C4, 405,
- "PowerPC 405 C4")
-#endif
POWERPC_DEF("405d2", CPU_POWERPC_405D2, 405,
"PowerPC 405 D2")
-#if defined(TODO)
- POWERPC_DEF("405d3", CPU_POWERPC_405D3, 405,
- "PowerPC 405 D3")
-#endif
POWERPC_DEF("405d4", CPU_POWERPC_405D4, 405,
"PowerPC 405 D4")
-#if defined(TODO)
- POWERPC_DEF("405d5", CPU_POWERPC_405D5, 405,
- "PowerPC 405 D5")
-#endif
-#if defined(TODO)
- POWERPC_DEF("405e4", CPU_POWERPC_405E4, 405,
- "PowerPC 405 E4")
-#endif
-#if defined(TODO)
- POWERPC_DEF("405f4", CPU_POWERPC_405F4, 405,
- "PowerPC 405 F4")
-#endif
-#if defined(TODO)
- POWERPC_DEF("405f5", CPU_POWERPC_405F5, 405,
- "PowerPC 405 F5")
-#endif
-#if defined(TODO)
- POWERPC_DEF("405f6", CPU_POWERPC_405F6, 405,
- "PowerPC 405 F6")
-#endif
/* PowerPC 405 microcontrollers */
POWERPC_DEF("405cra", CPU_POWERPC_405CRa, 405,
"PowerPC 405 CRa")
@@ -184,16 +115,8 @@
"PowerPC 405 CRc")
POWERPC_DEF("405ep", CPU_POWERPC_405EP, 405,
"PowerPC 405 EP")
-#if defined(TODO)
- POWERPC_DEF("405exr", CPU_POWERPC_405EXr, 405,
- "PowerPC 405 EXr")
-#endif
POWERPC_DEF("405ez", CPU_POWERPC_405EZ, 405,
"PowerPC 405 EZ")
-#if defined(TODO)
- POWERPC_DEF("405fx", CPU_POWERPC_405FX, 405,
- "PowerPC 405 FX")
-#endif
POWERPC_DEF("405gpa", CPU_POWERPC_405GPa, 405,
"PowerPC 405 GPa")
POWERPC_DEF("405gpb", CPU_POWERPC_405GPb, 405,
@@ -204,28 +127,8 @@
"PowerPC 405 GPd")
POWERPC_DEF("405gpr", CPU_POWERPC_405GPR, 405,
"PowerPC 405 GPR")
-#if defined(TODO)
- POWERPC_DEF("405h", CPU_POWERPC_405H, 405,
- "PowerPC 405 H")
-#endif
-#if defined(TODO)
- POWERPC_DEF("405l", CPU_POWERPC_405L, 405,
- "PowerPC 405 L")
-#endif
POWERPC_DEF("405lp", CPU_POWERPC_405LP, 405,
"PowerPC 405 LP")
-#if defined(TODO)
- POWERPC_DEF("405pm", CPU_POWERPC_405PM, 405,
- "PowerPC 405 PM")
-#endif
-#if defined(TODO)
- POWERPC_DEF("405ps", CPU_POWERPC_405PS, 405,
- "PowerPC 405 PS")
-#endif
-#if defined(TODO)
- POWERPC_DEF("405s", CPU_POWERPC_405S, 405,
- "PowerPC 405 S")
-#endif
POWERPC_DEF("npe405h", CPU_POWERPC_NPE405H, 405,
"Npe405 H")
POWERPC_DEF("npe405h2", CPU_POWERPC_NPE405H2, 405,
@@ -234,113 +137,29 @@
"Npe405 L")
POWERPC_DEF("npe4gs3", CPU_POWERPC_NPE4GS3, 405,
"Npe4GS3")
-#if defined(TODO)
- POWERPC_DEF("npcxx1", CPU_POWERPC_NPCxx1, 405,
- NULL)
-#endif
-#if defined(TODO)
- POWERPC_DEF("npr161", CPU_POWERPC_NPR161, 405,
- NULL)
-#endif
-#if defined(TODO)
- POWERPC_DEF("lc77700", CPU_POWERPC_LC77700, 405,
- "PowerPC LC77700 (Sanyo)")
-#endif
/* PowerPC 401/403/405 based set-top-box microcontrollers */
-#if defined(TODO)
- POWERPC_DEF("stb01000", CPU_POWERPC_STB01000, 401x2,
- "STB010000")
-#endif
-#if defined(TODO)
- POWERPC_DEF("stb01010", CPU_POWERPC_STB01010, 401x2,
- "STB01010")
-#endif
-#if defined(TODO)
- POWERPC_DEF("stb0210", CPU_POWERPC_STB0210, 401x3,
- "STB0210")
-#endif
POWERPC_DEF("stb03", CPU_POWERPC_STB03, 405,
"STB03xx")
-#if defined(TODO)
- POWERPC_DEF("stb043", CPU_POWERPC_STB043, 405,
- "STB043x")
-#endif
-#if defined(TODO)
- POWERPC_DEF("stb045", CPU_POWERPC_STB045, 405,
- "STB045x")
-#endif
POWERPC_DEF("stb04", CPU_POWERPC_STB04, 405,
"STB04xx")
POWERPC_DEF("stb25", CPU_POWERPC_STB25, 405,
"STB25xx")
-#if defined(TODO)
- POWERPC_DEF("stb130", CPU_POWERPC_STB130, 405,
- "STB130")
-#endif
/* Xilinx PowerPC 405 cores */
POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405,
NULL)
POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405,
NULL)
-#if defined(TODO)
- POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405,
- "Zarlink ZL10310")
-#endif
-#if defined(TODO)
- POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405,
- "Zarlink ZL10311")
-#endif
-#if defined(TODO)
- POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405,
- "Zarlink ZL10320")
-#endif
-#if defined(TODO)
- POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405,
- "Zarlink ZL10321")
-#endif
/* PowerPC 440 family */
#if defined(TODO_USER_ONLY)
POWERPC_DEF("440", CPU_POWERPC_440, 440GP,
"Generic PowerPC 440")
#endif
/* PowerPC 440 cores */
-#if defined(TODO)
- POWERPC_DEF("440a4", CPU_POWERPC_440A4, 440x4,
- "PowerPC 440 A4")
-#endif
POWERPC_DEF("440-xilinx", CPU_POWERPC_440_XILINX, 440x5,
"PowerPC 440 Xilinx 5")
POWERPC_DEF("440-xilinx-w-dfpu", CPU_POWERPC_440_XILINX, 440x5wDFPU,
"PowerPC 440 Xilinx 5 With a Double Prec. FPU")
-#if defined(TODO)
- POWERPC_DEF("440a5", CPU_POWERPC_440A5, 440x5,
- "PowerPC 440 A5")
-#endif
-#if defined(TODO)
- POWERPC_DEF("440b4", CPU_POWERPC_440B4, 440x4,
- "PowerPC 440 B4")
-#endif
-#if defined(TODO)
- POWERPC_DEF("440g4", CPU_POWERPC_440G4, 440x4,
- "PowerPC 440 G4")
-#endif
-#if defined(TODO)
- POWERPC_DEF("440f5", CPU_POWERPC_440F5, 440x5,
- "PowerPC 440 F5")
-#endif
-#if defined(TODO)
- POWERPC_DEF("440g5", CPU_POWERPC_440G5, 440x5,
- "PowerPC 440 G5")
-#endif
-#if defined(TODO)
- POWERPC_DEF("440h4", CPU_POWERPC_440H4, 440x4,
- "PowerPC 440H4")
-#endif
-#if defined(TODO)
- POWERPC_DEF("440h6", CPU_POWERPC_440H6, 440Gx5,
- "PowerPC 440H6")
-#endif
/* PowerPC 440 microcontrollers */
POWERPC_DEF("440epa", CPU_POWERPC_440EPa, 440EP,
"PowerPC 440 EPa")
@@ -380,10 +199,6 @@
POWERPC_DEF("440gxf", CPU_POWERPC_440GXf, 440EP,
"PowerPC 440 GXf")
#endif
-#if defined(TODO)
- POWERPC_DEF("440s", CPU_POWERPC_440S, 440,
- "PowerPC 440 S")
-#endif
#if defined(TODO_USER_ONLY)
POWERPC_DEF("440sp", CPU_POWERPC_440SP, 440EP,
"PowerPC 440 SP")
@@ -396,20 +211,6 @@
POWERPC_DEF("440spe", CPU_POWERPC_440SPE, 440EP,
"PowerPC 440 SPE")
#endif
- /* PowerPC 460 family */
-#if defined(TODO)
- POWERPC_DEF("464", CPU_POWERPC_464, 460,
- "Generic PowerPC 464")
-#endif
- /* PowerPC 464 microcontrollers */
-#if defined(TODO)
- POWERPC_DEF("464h90", CPU_POWERPC_464H90, 460,
- "PowerPC 464H90")
-#endif
-#if defined(TODO)
- POWERPC_DEF("464h90f", CPU_POWERPC_464H90F, 460F,
- "PowerPC 464H90F")
-#endif
/* Freescale embedded PowerPC cores */
/* MPC5xx family (aka RCPU) */
#if defined(TODO_USER_ONLY)
@@ -447,10 +248,6 @@
POWERPC_DEF("g2legp3", CPU_POWERPC_G2LEgp3, G2LE,
"PowerPC G2LE GP3 core")
/* PowerPC G2 microcontrollers */
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc5121", "MPC5121",
- CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE)
-#endif
POWERPC_DEF_SVR("mpc5200_v10", "MPC5200 v1.0",
CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE)
POWERPC_DEF_SVR("mpc5200_v11", "MPC5200 v1.1",
@@ -462,115 +259,10 @@
POWERPC_DEF_SVR("mpc5200b_v21", "MPC5200B v2.1",
CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE)
/* e200 family */
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc55xx", "Generic MPC55xx core",
- CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200,
- "PowerPC e200z0 core")
-#endif
-#if defined(TODO)
- POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200,
- "PowerPC e200z1 core")
-#endif
-#if defined(TODO)
- POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200,
- "PowerPC e200z3 core")
-#endif
POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200,
"PowerPC e200z5 core")
POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200,
"PowerPC e200z6 core")
- /* PowerPC e200 microcontrollers */
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc5514e", "MPC5514E",
- CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc5514e_v0", "MPC5514E v0",
- CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc5514e_v1", "MPC5514E v1",
- CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc5514g", "MPC5514G",
- CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc5514g_v0", "MPC5514G v0",
- CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc5514g_v1", "MPC5514G v1",
- CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc5515s", "MPC5515S",
- CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc5516e", "MPC5516E",
- CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc5516e_v0", "MPC5516E v0",
- CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc5516e_v1", "MPC5516E v1",
- CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc5516g", "MPC5516G",
- CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc5516g_v0", "MPC5516G v0",
- CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc5516g_v1", "MPC5516G v1",
- CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc5516s", "MPC5516S",
- CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc5533", "MPC5533",
- CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc5534", "MPC5534",
- CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc5553", "MPC5553",
- CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc5554", "MPC5554",
- CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc5561", "MPC5561",
- CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc5565", "MPC5565",
- CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc5566", "MPC5566",
- CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc5567", "MPC5567",
- CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200)
-#endif
/* e300 family */
POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300,
"PowerPC e300c1 core")
@@ -581,46 +273,6 @@
POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300,
"PowerPC e300c4 core")
/* PowerPC e300 microcontrollers */
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc8313", "MPC8313",
- CPU_POWERPC_MPC831x, POWERPC_SVR_8313, e300)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc8313e", "MPC8313E",
- CPU_POWERPC_MPC831x, POWERPC_SVR_8313E, e300)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc8314", "MPC8314",
- CPU_POWERPC_MPC831x, POWERPC_SVR_8314, e300)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc8314e", "MPC8314E",
- CPU_POWERPC_MPC831x, POWERPC_SVR_8314E, e300)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc8315", "MPC8315",
- CPU_POWERPC_MPC831x, POWERPC_SVR_8315, e300)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc8315e", "MPC8315E",
- CPU_POWERPC_MPC831x, POWERPC_SVR_8315E, e300)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc8321", "MPC8321",
- CPU_POWERPC_MPC832x, POWERPC_SVR_8321, e300)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc8321e", "MPC8321E",
- CPU_POWERPC_MPC832x, POWERPC_SVR_8321E, e300)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc8323", "MPC8323",
- CPU_POWERPC_MPC832x, POWERPC_SVR_8323, e300)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc8323e", "MPC8323E",
- CPU_POWERPC_MPC832x, POWERPC_SVR_8323E, e300)
-#endif
POWERPC_DEF_SVR("mpc8343", "MPC8343",
CPU_POWERPC_MPC834x, POWERPC_SVR_8343, e300)
POWERPC_DEF_SVR("mpc8343a", "MPC8343A",
@@ -653,14 +305,6 @@
CPU_POWERPC_MPC834x, POWERPC_SVR_8349E, e300)
POWERPC_DEF_SVR("mpc8349ea", "MPC8349EA",
CPU_POWERPC_MPC834x, POWERPC_SVR_8349EA, e300)
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc8358e", "MPC8358E",
- CPU_POWERPC_MPC835x, POWERPC_SVR_8358E, e300)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("mpc8360e", "MPC8360E",
- CPU_POWERPC_MPC836x, POWERPC_SVR_8360E, e300)
-#endif
POWERPC_DEF_SVR("mpc8377", "MPC8377",
CPU_POWERPC_MPC837x, POWERPC_SVR_8377, e300)
POWERPC_DEF_SVR("mpc8377e", "MPC8377E",
@@ -857,10 +501,6 @@
"PowerPC 604e v2.4")
POWERPC_DEF("604r", CPU_POWERPC_604R, 604E,
"PowerPC 604r (aka PIDA)")
-#if defined(TODO)
- POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E,
- "PowerPC 604ev")
-#endif
/* PowerPC 7xx family */
POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740,
"PowerPC 740 v1.0 (G3)")
@@ -998,12 +638,6 @@
"PowerPC 745 v2.8")
POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755,
"PowerPC 755 v2.8")
-#if defined(TODO)
- POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745,
- "PowerPC 745P (G3)")
- POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755,
- "PowerPC 755P (G3)")
-#endif
/* PowerPC 74xx family */
POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400,
"PowerPC 7400 v1.0 (G4)")
@@ -1105,34 +739,8 @@
"PowerPC 7457A v1.2 (G4)")
/* 64 bits PowerPC */
#if defined (TARGET_PPC64)
-#if defined(TODO)
- POWERPC_DEF("620", CPU_POWERPC_620, 620,
- "PowerPC 620")
- POWERPC_DEF("630", CPU_POWERPC_630, 630,
- "PowerPC 630 (POWER3)")
-#endif
-#if defined(TODO)
- POWERPC_DEF("631", CPU_POWERPC_631, 631,
- "PowerPC 631 (Power 3+)")
-#endif
-#if defined(TODO)
- POWERPC_DEF("power4", CPU_POWERPC_POWER4, POWER4,
- "POWER4")
-#endif
-#if defined(TODO)
- POWERPC_DEF("power4+", CPU_POWERPC_POWER4P, POWER4P,
- "POWER4p")
-#endif
-#if defined(TODO)
- POWERPC_DEF("power5", CPU_POWERPC_POWER5, POWER5,
- "POWER5")
-#endif
POWERPC_DEF("power5+_v2.1", CPU_POWERPC_POWER5P_v21, POWER5P,
"POWER5+ v2.1")
-#if defined(TODO)
- POWERPC_DEF("power6", CPU_POWERPC_POWER6, POWER6,
- "POWER6")
-#endif
POWERPC_DEF("power7_v2.3", CPU_POWERPC_POWER7_v23, POWER7,
"POWER7 v2.3")
POWERPC_DEF("power7+_v2.1", CPU_POWERPC_POWER7P_v21, POWER7,
@@ -1163,66 +771,7 @@
"PowerPC 970MP v1.0")
POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970,
"PowerPC 970MP v1.1")
-#if defined(TODO)
- POWERPC_DEF("cell", CPU_POWERPC_CELL, 970,
- "PowerPC Cell")
-#endif
-#if defined(TODO)
- POWERPC_DEF("cell_v1.0", CPU_POWERPC_CELL_v10, 970,
- "PowerPC Cell v1.0")
-#endif
-#if defined(TODO)
- POWERPC_DEF("cell_v2.0", CPU_POWERPC_CELL_v20, 970,
- "PowerPC Cell v2.0")
-#endif
-#if defined(TODO)
- POWERPC_DEF("cell_v3.0", CPU_POWERPC_CELL_v30, 970,
- "PowerPC Cell v3.0")
-#endif
-#if defined(TODO)
- POWERPC_DEF("cell_v3.1", CPU_POWERPC_CELL_v31, 970,
- "PowerPC Cell v3.1")
-#endif
-#if defined(TODO)
- POWERPC_DEF("cell_v3.2", CPU_POWERPC_CELL_v32, 970,
- "PowerPC Cell v3.2")
-#endif
-#if defined(TODO)
- /* This one seems to support the whole POWER2 instruction set
- * and the PowerPC 64 one.
- */
- /* What about A10 & A30 ? */
- POWERPC_DEF("rs64", CPU_POWERPC_RS64, RS64,
- "RS64 (Apache/A35)")
-#endif
-#if defined(TODO)
- POWERPC_DEF("rs64-ii", CPU_POWERPC_RS64II, RS64,
- "RS64-II (NorthStar/A50)")
-#endif
-#if defined(TODO)
- POWERPC_DEF("rs64-iii", CPU_POWERPC_RS64III, RS64,
- "RS64-III (Pulsar)")
-#endif
-#if defined(TODO)
- POWERPC_DEF("rs64-iv", CPU_POWERPC_RS64IV, RS64,
- "RS64-IV (IceStar/IStar/SStar)")
-#endif
#endif /* defined (TARGET_PPC64) */
- /* POWER */
-#if defined(TODO)
- POWERPC_DEF("power", CPU_POWERPC_POWER, POWER,
- "Original POWER")
-#endif
-#if defined(TODO)
- POWERPC_DEF("power2", CPU_POWERPC_POWER2, POWER,
- "POWER2")
-#endif
- /* PA semi cores */
-#if defined(TODO)
- POWERPC_DEF("pa6t", CPU_POWERPC_PA6T, PA6T,
- "PA PA6T")
-#endif
-
/***************************************************************************/
/* PowerPC CPU aliases */
@@ -1386,10 +935,6 @@ PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "7457a", "7457a_v1.2" },
{ "apollo7pm", "7457a_v1.0" },
#if defined(TARGET_PPC64)
-#if defined(TODO)
- { "power3", "630" },
- { "power3+", "631" },
-#endif
{ "power5+", "power5+_v2.1" },
{ "power5gs", "power5+_v2.1" },
{ "power7", "power7_v2.3" },
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Qemu-devel] [PULL 40/40] ppc: spapr: Move VCPU ID calculation into sPAPR
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (38 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 39/40] ppc: remove non implemented cpu models David Gibson
@ 2017-09-08 10:35 ` David Gibson
2017-09-08 15:04 ` [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 Peter Maydell
40 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2017-09-08 10:35 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, mdroth, aik, sam.bobroff, imammedo, qemu-ppc, qemu-devel,
David Gibson
From: Sam Bobroff <sam.bobroff@au1.ibm.com>
Move the calculation of a CPU's VCPU ID out of the generic PPC code
(ppc_cpu_realizefn()) and into sPAPR specific code
(spapr_cpu_core_realize()) where it belongs.
Unfortunately, due to the way things are ordered, we still need to
default the VCPU ID in ppc_cpu_realizfn() but at least doing that
doesn't require any interaction with sPAPR.
Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr_cpu_core.c | 11 +++++++++++
target/ppc/translate_init.c | 18 +++---------------
2 files changed, 14 insertions(+), 15 deletions(-)
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index 92bec033b3..85037ef71e 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -213,6 +213,7 @@ error:
static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
{
+ sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev));
CPUCore *cc = CPU_CORE(OBJECT(dev));
@@ -239,6 +240,16 @@ static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
cs = CPU(obj);
cpu = POWERPC_CPU(cs);
cs->cpu_index = cc->core_id + i;
+ cpu->vcpu_id = (cc->core_id * spapr->vsmt / smp_threads) + i;
+ if (kvm_enabled() && !kvm_vcpu_id_is_valid(cpu->vcpu_id)) {
+ error_setg(&local_err, "Can't create CPU with id %d in KVM",
+ cpu->vcpu_id);
+ error_append_hint(&local_err, "Adjust the number of cpus to %d "
+ "or try to raise the number of threads per core\n",
+ cpu->vcpu_id * smp_threads / spapr->vsmt);
+ goto err;
+ }
+
/* Set NUMA node for the threads belonged to core */
cpu->node_id = sc->node_id;
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 3e24cddb86..c827d1e388 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -9904,28 +9904,15 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
PowerPCCPU *cpu = POWERPC_CPU(dev);
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
Error *local_err = NULL;
-#if !defined(CONFIG_USER_ONLY)
- int max_smt = kvmppc_smt_threads();
-#endif
cpu_exec_realizefn(cs, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
return;
}
-
-#if !defined(CONFIG_USER_ONLY)
- cpu->vcpu_id = (cs->cpu_index / smp_threads) * max_smt
- + (cs->cpu_index % smp_threads);
-
- if (kvm_enabled() && !kvm_vcpu_id_is_valid(cpu->vcpu_id)) {
- error_setg(errp, "Can't create CPU with id %d in KVM", cpu->vcpu_id);
- error_append_hint(errp, "Adjust the number of cpus to %d "
- "or try to raise the number of threads per core\n",
- cpu->vcpu_id * smp_threads / max_smt);
- goto unrealize;
+ if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) {
+ cpu->vcpu_id = cs->cpu_index;
}
-#endif
if (tcg_enabled()) {
if (ppc_fixup_cpu(cpu) != 0) {
@@ -10576,6 +10563,7 @@ static void ppc_cpu_initfn(Object *obj)
CPUPPCState *env = &cpu->env;
cs->env_ptr = env;
+ cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
env->msr_mask = pcc->msr_mask;
env->mmu_model = pcc->mmu_model;
--
2.13.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908
2017-09-08 10:35 [Qemu-devel] [PULL 00/40] ppc-for-2.11 queue 20170908 David Gibson
` (39 preceding siblings ...)
2017-09-08 10:35 ` [Qemu-devel] [PULL 40/40] ppc: spapr: Move VCPU ID calculation into sPAPR David Gibson
@ 2017-09-08 15:04 ` Peter Maydell
40 siblings, 0 replies; 44+ messages in thread
From: Peter Maydell @ 2017-09-08 15:04 UTC (permalink / raw)
To: David Gibson
Cc: Alexander Graf, Michael Roth, Alexey Kardashevskiy, Sam Bobroff,
Igor Mammedov, qemu-ppc, QEMU Developers
On 8 September 2017 at 11:35, David Gibson <david@gibson.dropbear.id.au> wrote:
> The following changes since commit cda4a338c4243fa3bff4498b935340ac7121cc76:
>
> tcg/tci: Add TCG_TARGET_DEFAULT_MO (2017-09-07 18:57:34 +0100)
>
> are available in the git repository at:
>
> git://github.com/dgibson/qemu.git tags/ppc-for-2.11-20170908
>
> for you to fetch changes up to 7cca3e466eb0baa36d1cc29d5aeb5da74a260711:
>
> ppc: spapr: Move VCPU ID calculation into sPAPR (2017-09-08 09:30:55 +1000)
>
> ----------------------------------------------------------------
> ppc patch queue 2017-09-08
>
> This is the first batch of ppc related patches for qemu-2.11, and it's
> accumulated quite a few things. Includes:
>
> * A cleanup to handling of ppc cpu models from Igor
> * First parts of fixes to handling of guest vs. host SMT modes from
> Sam Bobroff
> * Preliminary patches towards supporting the Sam460 board from
> Balaton Zoltan
> * Several fixes for hotplug logic
> * Assorted other fixes and cleanups
>
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 44+ messages in thread