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* [PATCH v2 1/2] dt-bindings: clock: add R8A77970 CPG core clock definitions
@ 2017-09-08 21:34 ` Sergei Shtylyov
  0 siblings, 0 replies; 5+ messages in thread
From: Sergei Shtylyov @ 2017-09-08 21:34 UTC (permalink / raw)
  To: Michael Turquette, Rob Herring, Mark Rutland, devicetree,
	Geert Uytterhoeven, Stephen Boyd, linux-clk
  Cc: linux-renesas-soc, Simon Horman, Vladimir Barinov, Sergei Shtylyov

[-- Attachment #1: dt-bindings-clock-add-R8A77970-CPG-core-clock-definitions-v2.patch --]
[-- Type: text/plain, Size: 2673 bytes --]

Add macros usable by the device tree sources to reference the R8A77970
CPG core clocks by index. The data come from the table 8.2c of R-Car
Series, 3rd Generation User's Manual: Hardware (Rev. 0.55, Jun. 30, 2017).

Based on the original (and large) patch by Daisuke Matsushita
<daisuke.matsushita.ns@hitachi.com>.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

---
Changed in version 2:
- changed R8A7797 to R8A77970 everywhere;
- removed the CSIREF clock (renumbering the clocks that followed it);
- added the R-Car gen3 manual reference to the patch description;
- added Geert's tag;
- added Cogent Embedded's copyright;
- renamed the patch.

 include/dt-bindings/clock/r8a77970-cpg-mssr.h |   48 ++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

Index: linux/include/dt-bindings/clock/r8a77970-cpg-mssr.h
===================================================================
--- /dev/null
+++ linux/include/dt-bindings/clock/r8a77970-cpg-mssr.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77970 CPG Core Clocks */
+#define R8A77970_CLK_Z2			0
+#define R8A77970_CLK_ZR			1
+#define R8A77970_CLK_ZTR		2
+#define R8A77970_CLK_ZTRD2		3
+#define R8A77970_CLK_ZT			4
+#define R8A77970_CLK_ZX			5
+#define R8A77970_CLK_S1D1		6
+#define R8A77970_CLK_S1D2		7
+#define R8A77970_CLK_S1D4		8
+#define R8A77970_CLK_S2D1		9
+#define R8A77970_CLK_S2D2		10
+#define R8A77970_CLK_S2D4		11
+#define R8A77970_CLK_LB			12
+#define R8A77970_CLK_CL			13
+#define R8A77970_CLK_ZB3		14
+#define R8A77970_CLK_ZB3D2		15
+#define R8A77970_CLK_DDR		16
+#define R8A77970_CLK_CR			17
+#define R8A77970_CLK_CRD2		18
+#define R8A77970_CLK_SD0H		19
+#define R8A77970_CLK_SD0		20
+#define R8A77970_CLK_RPC		21
+#define R8A77970_CLK_RPCD2		22
+#define R8A77970_CLK_MSO		23
+#define R8A77970_CLK_CANFD		24
+#define R8A77970_CLK_CSI0		25
+#define R8A77970_CLK_FRAY		26
+#define R8A77970_CLK_CP			27
+#define R8A77970_CLK_CPEX		28
+#define R8A77970_CLK_R			29
+#define R8A77970_CLK_OSC		30
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */

^ permalink raw reply	[flat|nested] 5+ messages in thread
* [PATCH v2 1/2] dt-bindings: clock: add R8A77970 CPG core clock definitions
@ 2017-09-08 21:34 ` Sergei Shtylyov
  0 siblings, 0 replies; 5+ messages in thread
From: Sergei Shtylyov @ 2017-09-08 21:34 UTC (permalink / raw)
  To: Michael Turquette, Rob Herring, Mark Rutland, devicetree,
	Geert Uytterhoeven, Stephen Boyd, linux-clk
  Cc: linux-renesas-soc, Simon Horman, Vladimir Barinov, Sergei Shtylyov

[-- Attachment #1: dt-bindings-clock-add-R8A77970-CPG-core-clock-definitions-v2.patch --]
[-- Type: text/plain, Size: 2673 bytes --]

Add macros usable by the device tree sources to reference the R8A77970
CPG core clocks by index. The data come from the table 8.2c of R-Car
Series, 3rd Generation User's Manual: Hardware (Rev. 0.55, Jun. 30, 2017).

Based on the original (and large) patch by Daisuke Matsushita
<daisuke.matsushita.ns@hitachi.com>.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

---
Changed in version 2:
- changed R8A7797 to R8A77970 everywhere;
- removed the CSIREF clock (renumbering the clocks that followed it);
- added the R-Car gen3 manual reference to the patch description;
- added Geert's tag;
- added Cogent Embedded's copyright;
- renamed the patch.

 include/dt-bindings/clock/r8a77970-cpg-mssr.h |   48 ++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

Index: linux/include/dt-bindings/clock/r8a77970-cpg-mssr.h
===================================================================
--- /dev/null
+++ linux/include/dt-bindings/clock/r8a77970-cpg-mssr.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77970 CPG Core Clocks */
+#define R8A77970_CLK_Z2			0
+#define R8A77970_CLK_ZR			1
+#define R8A77970_CLK_ZTR		2
+#define R8A77970_CLK_ZTRD2		3
+#define R8A77970_CLK_ZT			4
+#define R8A77970_CLK_ZX			5
+#define R8A77970_CLK_S1D1		6
+#define R8A77970_CLK_S1D2		7
+#define R8A77970_CLK_S1D4		8
+#define R8A77970_CLK_S2D1		9
+#define R8A77970_CLK_S2D2		10
+#define R8A77970_CLK_S2D4		11
+#define R8A77970_CLK_LB			12
+#define R8A77970_CLK_CL			13
+#define R8A77970_CLK_ZB3		14
+#define R8A77970_CLK_ZB3D2		15
+#define R8A77970_CLK_DDR		16
+#define R8A77970_CLK_CR			17
+#define R8A77970_CLK_CRD2		18
+#define R8A77970_CLK_SD0H		19
+#define R8A77970_CLK_SD0		20
+#define R8A77970_CLK_RPC		21
+#define R8A77970_CLK_RPCD2		22
+#define R8A77970_CLK_MSO		23
+#define R8A77970_CLK_CANFD		24
+#define R8A77970_CLK_CSI0		25
+#define R8A77970_CLK_FRAY		26
+#define R8A77970_CLK_CP			27
+#define R8A77970_CLK_CPEX		28
+#define R8A77970_CLK_R			29
+#define R8A77970_CLK_OSC		30
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/2] dt-bindings: clock: add R8A77970 CPG core clock definitions
  2017-09-08 21:34 ` Sergei Shtylyov
  (?)
@ 2017-09-11 14:03 ` Geert Uytterhoeven
  -1 siblings, 0 replies; 5+ messages in thread
From: Geert Uytterhoeven @ 2017-09-11 14:03 UTC (permalink / raw)
  To: Sergei Shtylyov
  Cc: Michael Turquette, Rob Herring, Mark Rutland, devicetree,
	Geert Uytterhoeven, Stephen Boyd, linux-clk, Linux-Renesas,
	Simon Horman, Vladimir Barinov

On Fri, Sep 8, 2017 at 11:34 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Add macros usable by the device tree sources to reference the R8A77970
> CPG core clocks by index. The data come from the table 8.2c of R-Car
> Series, 3rd Generation User's Manual: Hardware (Rev. 0.55, Jun. 30, 2017).
>
> Based on the original (and large) patch by Daisuke Matsushita
> <daisuke.matsushita.ns@hitachi.com>.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Thank you, will queue in clk-renesas-for-v4.15.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 5+ messages in thread
* [PATCH v2 1/2] dt-bindings: clock: add R8A77970 CPG core clock definitions
@ 2017-09-08 21:34 Sergei Shtylyov
  0 siblings, 0 replies; 5+ messages in thread
From: Sergei Shtylyov @ 2017-09-08 21:34 UTC (permalink / raw)
  To: Michael Turquette, Rob Herring, Mark Rutland, devicetree,
	Geert Uytterhoeven, Stephen Boyd, linux-clk
  Cc: linux-renesas-soc, Simon Horman, Vladimir Barinov, Sergei Shtylyov

[-- Attachment #1: dt-bindings-clock-add-R8A77970-CPG-core-clock-definitions-v2.patch --]
[-- Type: text/plain, Size: 2674 bytes --]

Add macros usable by the device tree sources to reference the R8A77970
CPG core clocks by index. The data come from the table 8.2c of R-Car
Series, 3rd Generation User's Manual: Hardware (Rev. 0.55, Jun. 30, 2017).

Based on the original (and large) patch by Daisuke Matsushita
<daisuke.matsushita.ns@hitachi.com>.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

---
Changed in version 2:
- changed R8A7797 to R8A77970 everywhere;
- removed the CSIREF clock (renumbering the clocks that followed it);
- added the R-Car gen3 manual reference to the patch description;
- added Geert's tag;
- added Cogent Embedded's copyright;
- renamed the patch.

 include/dt-bindings/clock/r8a77970-cpg-mssr.h |   48 ++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

Index: linux/include/dt-bindings/clock/r8a77970-cpg-mssr.h
===================================================================
--- /dev/null
+++ linux/include/dt-bindings/clock/r8a77970-cpg-mssr.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77970 CPG Core Clocks */
+#define R8A77970_CLK_Z2			0
+#define R8A77970_CLK_ZR			1
+#define R8A77970_CLK_ZTR		2
+#define R8A77970_CLK_ZTRD2		3
+#define R8A77970_CLK_ZT			4
+#define R8A77970_CLK_ZX			5
+#define R8A77970_CLK_S1D1		6
+#define R8A77970_CLK_S1D2		7
+#define R8A77970_CLK_S1D4		8
+#define R8A77970_CLK_S2D1		9
+#define R8A77970_CLK_S2D2		10
+#define R8A77970_CLK_S2D4		11
+#define R8A77970_CLK_LB			12
+#define R8A77970_CLK_CL			13
+#define R8A77970_CLK_ZB3		14
+#define R8A77970_CLK_ZB3D2		15
+#define R8A77970_CLK_DDR		16
+#define R8A77970_CLK_CR			17
+#define R8A77970_CLK_CRD2		18
+#define R8A77970_CLK_SD0H		19
+#define R8A77970_CLK_SD0		20
+#define R8A77970_CLK_RPC		21
+#define R8A77970_CLK_RPCD2		22
+#define R8A77970_CLK_MSO		23
+#define R8A77970_CLK_CANFD		24
+#define R8A77970_CLK_CSI0		25
+#define R8A77970_CLK_FRAY		26
+#define R8A77970_CLK_CP			27
+#define R8A77970_CLK_CPEX		28
+#define R8A77970_CLK_R			29
+#define R8A77970_CLK_OSC		30
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */


^ permalink raw reply	[flat|nested] 5+ messages in thread
* [PATCH v2 1/2] dt-bindings: clock: add R8A77970 CPG core clock definitions
@ 2017-09-08 21:34 Sergei Shtylyov
  0 siblings, 0 replies; 5+ messages in thread
From: Sergei Shtylyov @ 2017-09-08 21:34 UTC (permalink / raw)
  To: Michael Turquette, Rob Herring, Mark Rutland,
	devicetree-u79uwXL29TY76Z2rM5mHXA, Geert Uytterhoeven,
	Stephen Boyd, linux-clk-u79uwXL29TY76Z2rM5mHXA
  Cc: linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, Simon Horman,
	Vladimir Barinov, Sergei Shtylyov

[-- Attachment #1: dt-bindings-clock-add-R8A77970-CPG-core-clock-definitions-v2.patch --]
[-- Type: text/plain, Size: 3012 bytes --]

Add macros usable by the device tree sources to reference the R8A77970
CPG core clocks by index. The data come from the table 8.2c of R-Car
Series, 3rd Generation User's Manual: Hardware (Rev. 0.55, Jun. 30, 2017).

Based on the original (and large) patch by Daisuke Matsushita
<daisuke.matsushita.ns-FCd8Q96Dh0JBDgjK7y7TUQ@public.gmane.org>.

Signed-off-by: Vladimir Barinov <vladimir.barinov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>

---
Changed in version 2:
- changed R8A7797 to R8A77970 everywhere;
- removed the CSIREF clock (renumbering the clocks that followed it);
- added the R-Car gen3 manual reference to the patch description;
- added Geert's tag;
- added Cogent Embedded's copyright;
- renamed the patch.

 include/dt-bindings/clock/r8a77970-cpg-mssr.h |   48 ++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

Index: linux/include/dt-bindings/clock/r8a77970-cpg-mssr.h
===================================================================
--- /dev/null
+++ linux/include/dt-bindings/clock/r8a77970-cpg-mssr.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77970 CPG Core Clocks */
+#define R8A77970_CLK_Z2			0
+#define R8A77970_CLK_ZR			1
+#define R8A77970_CLK_ZTR		2
+#define R8A77970_CLK_ZTRD2		3
+#define R8A77970_CLK_ZT			4
+#define R8A77970_CLK_ZX			5
+#define R8A77970_CLK_S1D1		6
+#define R8A77970_CLK_S1D2		7
+#define R8A77970_CLK_S1D4		8
+#define R8A77970_CLK_S2D1		9
+#define R8A77970_CLK_S2D2		10
+#define R8A77970_CLK_S2D4		11
+#define R8A77970_CLK_LB			12
+#define R8A77970_CLK_CL			13
+#define R8A77970_CLK_ZB3		14
+#define R8A77970_CLK_ZB3D2		15
+#define R8A77970_CLK_DDR		16
+#define R8A77970_CLK_CR			17
+#define R8A77970_CLK_CRD2		18
+#define R8A77970_CLK_SD0H		19
+#define R8A77970_CLK_SD0		20
+#define R8A77970_CLK_RPC		21
+#define R8A77970_CLK_RPCD2		22
+#define R8A77970_CLK_MSO		23
+#define R8A77970_CLK_CANFD		24
+#define R8A77970_CLK_CSI0		25
+#define R8A77970_CLK_FRAY		26
+#define R8A77970_CLK_CP			27
+#define R8A77970_CLK_CPEX		28
+#define R8A77970_CLK_R			29
+#define R8A77970_CLK_OSC		30
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */

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^ permalink raw reply	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2017-09-11 14:03 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-09-08 21:34 [PATCH v2 1/2] dt-bindings: clock: add R8A77970 CPG core clock definitions Sergei Shtylyov
2017-09-08 21:34 ` Sergei Shtylyov
2017-09-11 14:03 ` Geert Uytterhoeven
2017-09-08 21:34 Sergei Shtylyov
2017-09-08 21:34 Sergei Shtylyov

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