* [PATCH 1/4] drm/amdgpu: fixed raven psp cmd prepare and submit
@ 2017-09-11 1:22 Evan Quan
[not found] ` <1505092926-9029-1-git-send-email-evan.quan-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 9+ messages in thread
From: Evan Quan @ 2017-09-11 1:22 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Evan Quan
Change-Id: I9b7ebc99b7c75c03fb46d16c4c49348dd551325e
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 16 +++++++++-------
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index 5283113..702d68d 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
@@ -137,15 +137,13 @@ int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cm
{
int ret;
uint64_t fw_mem_mc_addr = ucode->mc_addr;
- struct common_firmware_header *header;
memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
- header = (struct common_firmware_header *)ucode->fw;
cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
- cmd->cmd.cmd_load_ip_fw.fw_size = le32_to_cpu(header->ucode_size_bytes);
+ cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
ret = psp_v10_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
if (ret)
@@ -246,15 +244,20 @@ int psp_v10_0_cmd_submit(struct psp_context *psp,
struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
struct psp_ring *ring = &psp->km_ring;
struct amdgpu_device *adev = psp->adev;
+ uint32_t ring_size_dw = ring->ring_size / 4;
+ uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
/* KM (GPCOM) prepare write pointer */
psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
/* Update KM RB frame pointer to new frame */
- if ((psp_write_ptr_reg % ring->ring_size) == 0)
+ if ((psp_write_ptr_reg % ring_size_dw) == 0)
write_frame = ring->ring_mem;
else
- write_frame = ring->ring_mem + (psp_write_ptr_reg / (sizeof(struct psp_gfx_rb_frame) / 4));
+ write_frame = ring->ring_mem + (psp_write_ptr_reg / rb_frame_size_dw);
+
+ /* Initialize KM RB frame */
+ memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
/* Update KM RB frame */
write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
@@ -264,8 +267,7 @@ int psp_v10_0_cmd_submit(struct psp_context *psp,
write_frame->fence_value = index;
/* Update the write Pointer in DWORDs */
- psp_write_ptr_reg += sizeof(struct psp_gfx_rb_frame) / 4;
- psp_write_ptr_reg = (psp_write_ptr_reg >= ring->ring_size) ? 0 : psp_write_ptr_reg;
+ psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
return 0;
--
2.7.4
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/4] drm/amdgpu: added api for stopping psp ring
[not found] ` <1505092926-9029-1-git-send-email-evan.quan-5C7GfCeVMHo@public.gmane.org>
@ 2017-09-11 1:22 ` Evan Quan
[not found] ` <1505092926-9029-2-git-send-email-evan.quan-5C7GfCeVMHo@public.gmane.org>
2017-09-11 1:22 ` [PATCH 3/4] drm/amdgpu: stop psp ring on suspend Evan Quan
` (3 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Evan Quan @ 2017-09-11 1:22 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Evan Quan
Change-Id: I53bcacd531d8df801a49acd0409c3f27b49fb1be
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 ++
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 23 +++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/psp_v10_0.h | 2 ++
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 23 +++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/psp_v3_1.h | 2 ++
6 files changed, 54 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 4c429f4..1ea879d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -57,6 +57,7 @@ static int psp_sw_init(void *handle)
psp->prep_cmd_buf = psp_v3_1_prep_cmd_buf;
psp->ring_init = psp_v3_1_ring_init;
psp->ring_create = psp_v3_1_ring_create;
+ psp->ring_stop = psp_v3_1_ring_stop;
psp->ring_destroy = psp_v3_1_ring_destroy;
psp->cmd_submit = psp_v3_1_cmd_submit;
psp->compare_sram_data = psp_v3_1_compare_sram_data;
@@ -69,6 +70,7 @@ static int psp_sw_init(void *handle)
psp->prep_cmd_buf = psp_v10_0_prep_cmd_buf;
psp->ring_init = psp_v10_0_ring_init;
psp->ring_create = psp_v10_0_ring_create;
+ psp->ring_stop = psp_v10_0_ring_stop;
psp->ring_destroy = psp_v10_0_ring_destroy;
psp->cmd_submit = psp_v10_0_cmd_submit;
psp->compare_sram_data = psp_v10_0_compare_sram_data;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 538fa9d..e79795b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -66,6 +66,8 @@ struct psp_context
struct psp_gfx_cmd_resp *cmd);
int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
int (*ring_create)(struct psp_context *psp, enum psp_ring_type ring_type);
+ int (*ring_stop)(struct psp_context *psp,
+ enum psp_ring_type ring_type);
int (*ring_destroy)(struct psp_context *psp,
enum psp_ring_type ring_type);
int (*cmd_submit)(struct psp_context *psp, struct amdgpu_firmware_info *ucode,
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index 702d68d..5826a83 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
@@ -208,6 +208,29 @@ int psp_v10_0_ring_create(struct psp_context *psp, enum psp_ring_type ring_type)
return ret;
}
+int psp_v10_0_ring_stop(struct psp_context *psp, enum psp_ring_type ring_type)
+{
+ int ret = 0;
+ struct psp_ring *ring;
+ unsigned int psp_ring_reg = 0;
+ struct amdgpu_device *adev = psp->adev;
+
+ ring = &psp->km_ring;
+
+ /* Write the ring destroy command to C2PMSG_64 */
+ psp_ring_reg = 3 << 16;
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
+
+ /* There might be handshake issue with hardware which needs delay */
+ mdelay(20);
+
+ /* Wait for response flag (bit 31) in C2PMSG_64 */
+ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
+ 0x80000000, 0x80000000, false);
+
+ return ret;
+}
+
int psp_v10_0_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type)
{
int ret = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
index e76cde2..3af3ad1 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
@@ -34,6 +34,8 @@ extern int psp_v10_0_ring_init(struct psp_context *psp,
enum psp_ring_type ring_type);
extern int psp_v10_0_ring_create(struct psp_context *psp,
enum psp_ring_type ring_type);
+extern int psp_v10_0_ring_stop(struct psp_context *psp,
+ enum psp_ring_type ring_type);
extern int psp_v10_0_ring_destroy(struct psp_context *psp,
enum psp_ring_type ring_type);
extern int psp_v10_0_cmd_submit(struct psp_context *psp,
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index 23106e3..80c4f97 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -319,6 +319,29 @@ int psp_v3_1_ring_create(struct psp_context *psp, enum psp_ring_type ring_type)
return ret;
}
+int psp_v3_1_ring_stop(struct psp_context *psp, enum psp_ring_type ring_type)
+{
+ int ret = 0;
+ struct psp_ring *ring;
+ unsigned int psp_ring_reg = 0;
+ struct amdgpu_device *adev = psp->adev;
+
+ ring = &psp->km_ring;
+
+ /* Write the ring destroy command to C2PMSG_64 */
+ psp_ring_reg = 3 << 16;
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
+
+ /* there might be handshake issue with hardware which needs delay */
+ mdelay(20);
+
+ /* Wait for response flag (bit 31) in C2PMSG_64 */
+ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
+ 0x80000000, 0x80000000, false);
+
+ return ret;
+}
+
int psp_v3_1_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type)
{
int ret = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h
index 9dcd0b2..5af2231 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h
@@ -41,6 +41,8 @@ extern int psp_v3_1_ring_init(struct psp_context *psp,
enum psp_ring_type ring_type);
extern int psp_v3_1_ring_create(struct psp_context *psp,
enum psp_ring_type ring_type);
+extern int psp_v3_1_ring_stop(struct psp_context *psp,
+ enum psp_ring_type ring_type);
extern int psp_v3_1_ring_destroy(struct psp_context *psp,
enum psp_ring_type ring_type);
extern int psp_v3_1_cmd_submit(struct psp_context *psp,
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/4] drm/amdgpu: stop psp ring on suspend
[not found] ` <1505092926-9029-1-git-send-email-evan.quan-5C7GfCeVMHo@public.gmane.org>
2017-09-11 1:22 ` [PATCH 2/4] drm/amdgpu: added api for stopping psp ring Evan Quan
@ 2017-09-11 1:22 ` Evan Quan
2017-09-11 1:22 ` [PATCH 4/4] drm/amdgpu: enable raven to load firmwares by psp at default Evan Quan
` (2 subsequent siblings)
4 siblings, 0 replies; 9+ messages in thread
From: Evan Quan @ 2017-09-11 1:22 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Evan Quan
Otherwise, the ring will fail to create on next resume.
Change-Id: Ia25aded6c838ab8022ebf9f42adc9045133343ca
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 10 ++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 +
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 1ea879d..1157eb4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -455,6 +455,16 @@ static int psp_hw_fini(void *handle)
static int psp_suspend(void *handle)
{
+ int ret;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct psp_context *psp = &adev->psp;
+
+ ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
+ if (ret) {
+ DRM_ERROR("PSP ring stop failed\n");
+ return ret;
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index e79795b..1b7d12d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -125,6 +125,7 @@ struct amdgpu_psp_funcs {
#define psp_prep_cmd_buf(ucode, type) (psp)->prep_cmd_buf((ucode), (type))
#define psp_ring_init(psp, type) (psp)->ring_init((psp), (type))
#define psp_ring_create(psp, type) (psp)->ring_create((psp), (type))
+#define psp_ring_stop(psp, type) (psp)->ring_stop((psp), (type))
#define psp_ring_destroy(psp, type) ((psp)->ring_destroy((psp), (type)))
#define psp_cmd_submit(psp, ucode, cmd_mc, fence_mc, index) \
(psp)->cmd_submit((psp), (ucode), (cmd_mc), (fence_mc), (index))
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 4/4] drm/amdgpu: enable raven to load firmwares by psp at default
[not found] ` <1505092926-9029-1-git-send-email-evan.quan-5C7GfCeVMHo@public.gmane.org>
2017-09-11 1:22 ` [PATCH 2/4] drm/amdgpu: added api for stopping psp ring Evan Quan
2017-09-11 1:22 ` [PATCH 3/4] drm/amdgpu: stop psp ring on suspend Evan Quan
@ 2017-09-11 1:22 ` Evan Quan
[not found] ` <1505092926-9029-4-git-send-email-evan.quan-5C7GfCeVMHo@public.gmane.org>
2017-09-11 1:42 ` [PATCH 1/4] drm/amdgpu: fixed raven psp cmd prepare and submit Zhang, Jerry (Junwei)
2017-09-11 8:58 ` Huang Rui
4 siblings, 1 reply; 9+ messages in thread
From: Evan Quan @ 2017-09-11 1:22 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Evan Quan
Change-Id: I7a0427555b34111e4e7600aa1e8b9cae31b44af7
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 --
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 +-
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 1157eb4..8a1ee97 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -64,9 +64,7 @@ static int psp_sw_init(void *handle)
psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk;
break;
case CHIP_RAVEN:
-#if 0
psp->init_microcode = psp_v10_0_init_microcode;
-#endif
psp->prep_cmd_buf = psp_v10_0_prep_cmd_buf;
psp->ring_init = psp_v10_0_ring_init;
psp->ring_create = psp_v10_0_ring_create;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 36c7633..4073e08 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -275,7 +275,7 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
else
return AMDGPU_FW_LOAD_PSP;
case CHIP_RAVEN:
- if (load_type != 2)
+ if (!load_type)
return AMDGPU_FW_LOAD_DIRECT;
else
return AMDGPU_FW_LOAD_PSP;
--
2.7.4
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/4] drm/amdgpu: fixed raven psp cmd prepare and submit
[not found] ` <1505092926-9029-1-git-send-email-evan.quan-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2017-09-11 1:22 ` [PATCH 4/4] drm/amdgpu: enable raven to load firmwares by psp at default Evan Quan
@ 2017-09-11 1:42 ` Zhang, Jerry (Junwei)
[not found] ` <59B5E9F9.2000803-5C7GfCeVMHo@public.gmane.org>
2017-09-11 8:58 ` Huang Rui
4 siblings, 1 reply; 9+ messages in thread
From: Zhang, Jerry (Junwei) @ 2017-09-11 1:42 UTC (permalink / raw)
To: Evan Quan, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
On 09/11/2017 09:22 AM, Evan Quan wrote:
> Change-Id: I9b7ebc99b7c75c03fb46d16c4c49348dd551325e
> Signed-off-by: Evan Quan <evan.quan@amd.com>
The series patches is
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 16 +++++++++-------
> 1 file changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> index 5283113..702d68d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> @@ -137,15 +137,13 @@ int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cm
> {
> int ret;
> uint64_t fw_mem_mc_addr = ucode->mc_addr;
> - struct common_firmware_header *header;
>
> memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
> - header = (struct common_firmware_header *)ucode->fw;
>
> cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
> cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
> cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
> - cmd->cmd.cmd_load_ip_fw.fw_size = le32_to_cpu(header->ucode_size_bytes);
> + cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
>
> ret = psp_v10_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
> if (ret)
> @@ -246,15 +244,20 @@ int psp_v10_0_cmd_submit(struct psp_context *psp,
> struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
> struct psp_ring *ring = &psp->km_ring;
> struct amdgpu_device *adev = psp->adev;
> + uint32_t ring_size_dw = ring->ring_size / 4;
> + uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
>
> /* KM (GPCOM) prepare write pointer */
> psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
>
> /* Update KM RB frame pointer to new frame */
> - if ((psp_write_ptr_reg % ring->ring_size) == 0)
> + if ((psp_write_ptr_reg % ring_size_dw) == 0)
> write_frame = ring->ring_mem;
> else
> - write_frame = ring->ring_mem + (psp_write_ptr_reg / (sizeof(struct psp_gfx_rb_frame) / 4));
> + write_frame = ring->ring_mem + (psp_write_ptr_reg / rb_frame_size_dw);
> +
> + /* Initialize KM RB frame */
> + memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
>
> /* Update KM RB frame */
> write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
> @@ -264,8 +267,7 @@ int psp_v10_0_cmd_submit(struct psp_context *psp,
> write_frame->fence_value = index;
>
> /* Update the write Pointer in DWORDs */
> - psp_write_ptr_reg += sizeof(struct psp_gfx_rb_frame) / 4;
> - psp_write_ptr_reg = (psp_write_ptr_reg >= ring->ring_size) ? 0 : psp_write_ptr_reg;
> + psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
> WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
>
> return 0;
>
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/4] drm/amdgpu: fixed raven psp cmd prepare and submit
[not found] ` <59B5E9F9.2000803-5C7GfCeVMHo@public.gmane.org>
@ 2017-09-11 7:51 ` Christian König
0 siblings, 0 replies; 9+ messages in thread
From: Christian König @ 2017-09-11 7:51 UTC (permalink / raw)
To: Zhang, Jerry (Junwei),
Evan Quan, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Am 11.09.2017 um 03:42 schrieb Zhang, Jerry (Junwei):
> On 09/11/2017 09:22 AM, Evan Quan wrote:
>> Change-Id: I9b7ebc99b7c75c03fb46d16c4c49348dd551325e
>> Signed-off-by: Evan Quan <evan.quan@amd.com>
>
> The series patches is
> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
A bit more commit message would be rather nice to have.
With that fixed the series is Acked-by: Christian König
<christian.koenig@amd.com> as well.
Regards,
Christian.
>
>> ---
>> drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 16 +++++++++-------
>> 1 file changed, 9 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
>> b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
>> index 5283113..702d68d 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
>> @@ -137,15 +137,13 @@ int psp_v10_0_prep_cmd_buf(struct
>> amdgpu_firmware_info *ucode, struct psp_gfx_cm
>> {
>> int ret;
>> uint64_t fw_mem_mc_addr = ucode->mc_addr;
>> - struct common_firmware_header *header;
>>
>> memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
>> - header = (struct common_firmware_header *)ucode->fw;
>>
>> cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
>> cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo =
>> lower_32_bits(fw_mem_mc_addr);
>> cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi =
>> upper_32_bits(fw_mem_mc_addr);
>> - cmd->cmd.cmd_load_ip_fw.fw_size =
>> le32_to_cpu(header->ucode_size_bytes);
>> + cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
>>
>> ret = psp_v10_0_get_fw_type(ucode,
>> &cmd->cmd.cmd_load_ip_fw.fw_type);
>> if (ret)
>> @@ -246,15 +244,20 @@ int psp_v10_0_cmd_submit(struct psp_context *psp,
>> struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
>> struct psp_ring *ring = &psp->km_ring;
>> struct amdgpu_device *adev = psp->adev;
>> + uint32_t ring_size_dw = ring->ring_size / 4;
>> + uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
>>
>> /* KM (GPCOM) prepare write pointer */
>> psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
>>
>> /* Update KM RB frame pointer to new frame */
>> - if ((psp_write_ptr_reg % ring->ring_size) == 0)
>> + if ((psp_write_ptr_reg % ring_size_dw) == 0)
>> write_frame = ring->ring_mem;
>> else
>> - write_frame = ring->ring_mem + (psp_write_ptr_reg /
>> (sizeof(struct psp_gfx_rb_frame) / 4));
>> + write_frame = ring->ring_mem + (psp_write_ptr_reg /
>> rb_frame_size_dw);
>> +
>> + /* Initialize KM RB frame */
>> + memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
>>
>> /* Update KM RB frame */
>> write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
>> @@ -264,8 +267,7 @@ int psp_v10_0_cmd_submit(struct psp_context *psp,
>> write_frame->fence_value = index;
>>
>> /* Update the write Pointer in DWORDs */
>> - psp_write_ptr_reg += sizeof(struct psp_gfx_rb_frame) / 4;
>> - psp_write_ptr_reg = (psp_write_ptr_reg >= ring->ring_size) ? 0 :
>> psp_write_ptr_reg;
>> + psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) %
>> ring_size_dw;
>> WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
>>
>> return 0;
>>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/4] drm/amdgpu: added api for stopping psp ring
[not found] ` <1505092926-9029-2-git-send-email-evan.quan-5C7GfCeVMHo@public.gmane.org>
@ 2017-09-11 8:51 ` Huang Rui
0 siblings, 0 replies; 9+ messages in thread
From: Huang Rui @ 2017-09-11 8:51 UTC (permalink / raw)
To: Evan Quan; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
On Mon, Sep 11, 2017 at 09:22:03AM +0800, Evan Quan wrote:
> Change-Id: I53bcacd531d8df801a49acd0409c3f27b49fb1be
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 ++
> drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 23 +++++++++++++++++++++++
> drivers/gpu/drm/amd/amdgpu/psp_v10_0.h | 2 ++
> drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 23 +++++++++++++++++++++++
> drivers/gpu/drm/amd/amdgpu/psp_v3_1.h | 2 ++
> 6 files changed, 54 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 4c429f4..1ea879d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -57,6 +57,7 @@ static int psp_sw_init(void *handle)
> psp->prep_cmd_buf = psp_v3_1_prep_cmd_buf;
> psp->ring_init = psp_v3_1_ring_init;
> psp->ring_create = psp_v3_1_ring_create;
> + psp->ring_stop = psp_v3_1_ring_stop;
> psp->ring_destroy = psp_v3_1_ring_destroy;
> psp->cmd_submit = psp_v3_1_cmd_submit;
> psp->compare_sram_data = psp_v3_1_compare_sram_data;
> @@ -69,6 +70,7 @@ static int psp_sw_init(void *handle)
> psp->prep_cmd_buf = psp_v10_0_prep_cmd_buf;
> psp->ring_init = psp_v10_0_ring_init;
> psp->ring_create = psp_v10_0_ring_create;
> + psp->ring_stop = psp_v10_0_ring_stop;
> psp->ring_destroy = psp_v10_0_ring_destroy;
As introduced ring_stop interface, we can re-use ring_top in ring_destroy
handler. Because ring_destroy is actually equal to ring_stop and ring
buffer free.
Thanks
Rui
> psp->cmd_submit = psp_v10_0_cmd_submit;
> psp->compare_sram_data = psp_v10_0_compare_sram_data;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> index 538fa9d..e79795b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> @@ -66,6 +66,8 @@ struct psp_context
> struct psp_gfx_cmd_resp *cmd);
> int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
> int (*ring_create)(struct psp_context *psp, enum psp_ring_type ring_type);
> + int (*ring_stop)(struct psp_context *psp,
> + enum psp_ring_type ring_type);
> int (*ring_destroy)(struct psp_context *psp,
> enum psp_ring_type ring_type);
> int (*cmd_submit)(struct psp_context *psp, struct amdgpu_firmware_info *ucode,
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> index 702d68d..5826a83 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> @@ -208,6 +208,29 @@ int psp_v10_0_ring_create(struct psp_context *psp, enum psp_ring_type ring_type)
> return ret;
> }
>
> +int psp_v10_0_ring_stop(struct psp_context *psp, enum psp_ring_type ring_type)
> +{
> + int ret = 0;
> + struct psp_ring *ring;
> + unsigned int psp_ring_reg = 0;
> + struct amdgpu_device *adev = psp->adev;
> +
> + ring = &psp->km_ring;
> +
> + /* Write the ring destroy command to C2PMSG_64 */
> + psp_ring_reg = 3 << 16;
> + WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
> +
> + /* There might be handshake issue with hardware which needs delay */
> + mdelay(20);
> +
> + /* Wait for response flag (bit 31) in C2PMSG_64 */
> + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
> + 0x80000000, 0x80000000, false);
> +
> + return ret;
> +}
> +
> int psp_v10_0_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type)
> {
> int ret = 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
> index e76cde2..3af3ad1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
> @@ -34,6 +34,8 @@ extern int psp_v10_0_ring_init(struct psp_context *psp,
> enum psp_ring_type ring_type);
> extern int psp_v10_0_ring_create(struct psp_context *psp,
> enum psp_ring_type ring_type);
> +extern int psp_v10_0_ring_stop(struct psp_context *psp,
> + enum psp_ring_type ring_type);
> extern int psp_v10_0_ring_destroy(struct psp_context *psp,
> enum psp_ring_type ring_type);
> extern int psp_v10_0_cmd_submit(struct psp_context *psp,
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> index 23106e3..80c4f97 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> @@ -319,6 +319,29 @@ int psp_v3_1_ring_create(struct psp_context *psp, enum psp_ring_type ring_type)
> return ret;
> }
>
> +int psp_v3_1_ring_stop(struct psp_context *psp, enum psp_ring_type ring_type)
> +{
> + int ret = 0;
> + struct psp_ring *ring;
> + unsigned int psp_ring_reg = 0;
> + struct amdgpu_device *adev = psp->adev;
> +
> + ring = &psp->km_ring;
> +
> + /* Write the ring destroy command to C2PMSG_64 */
> + psp_ring_reg = 3 << 16;
> + WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
> +
> + /* there might be handshake issue with hardware which needs delay */
> + mdelay(20);
> +
> + /* Wait for response flag (bit 31) in C2PMSG_64 */
> + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
> + 0x80000000, 0x80000000, false);
> +
> + return ret;
> +}
> +
> int psp_v3_1_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type)
> {
> int ret = 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h
> index 9dcd0b2..5af2231 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h
> @@ -41,6 +41,8 @@ extern int psp_v3_1_ring_init(struct psp_context *psp,
> enum psp_ring_type ring_type);
> extern int psp_v3_1_ring_create(struct psp_context *psp,
> enum psp_ring_type ring_type);
> +extern int psp_v3_1_ring_stop(struct psp_context *psp,
> + enum psp_ring_type ring_type);
> extern int psp_v3_1_ring_destroy(struct psp_context *psp,
> enum psp_ring_type ring_type);
> extern int psp_v3_1_cmd_submit(struct psp_context *psp,
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 4/4] drm/amdgpu: enable raven to load firmwares by psp at default
[not found] ` <1505092926-9029-4-git-send-email-evan.quan-5C7GfCeVMHo@public.gmane.org>
@ 2017-09-11 8:55 ` Huang Rui
0 siblings, 0 replies; 9+ messages in thread
From: Huang Rui @ 2017-09-11 8:55 UTC (permalink / raw)
To: Evan Quan; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
On Mon, Sep 11, 2017 at 09:22:05AM +0800, Evan Quan wrote:
> Change-Id: I7a0427555b34111e4e7600aa1e8b9cae31b44af7
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 --
> drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 +-
> 2 files changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 1157eb4..8a1ee97 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -64,9 +64,7 @@ static int psp_sw_init(void *handle)
> psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk;
> break;
> case CHIP_RAVEN:
> -#if 0
> psp->init_microcode = psp_v10_0_init_microcode;
> -#endif
> psp->prep_cmd_buf = psp_v10_0_prep_cmd_buf;
> psp->ring_init = psp_v10_0_ring_init;
> psp->ring_create = psp_v10_0_ring_create;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
> index 36c7633..4073e08 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
> @@ -275,7 +275,7 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
> else
> return AMDGPU_FW_LOAD_PSP;
> case CHIP_RAVEN:
> - if (load_type != 2)
> + if (!load_type)
> return AMDGPU_FW_LOAD_DIRECT;
> else
> return AMDGPU_FW_LOAD_PSP;
case CHIP_VEGA10:
case CHIP_RAVEN:
if (!load_type)
return AMDGPU_FW_LOAD_DIRECT;
else
return AMDGPU_FW_LOAD_PSP;
We can re-use "VEGA10 case" here.
Thanks,
Rui
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amd-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/4] drm/amdgpu: fixed raven psp cmd prepare and submit
[not found] ` <1505092926-9029-1-git-send-email-evan.quan-5C7GfCeVMHo@public.gmane.org>
` (3 preceding siblings ...)
2017-09-11 1:42 ` [PATCH 1/4] drm/amdgpu: fixed raven psp cmd prepare and submit Zhang, Jerry (Junwei)
@ 2017-09-11 8:58 ` Huang Rui
4 siblings, 0 replies; 9+ messages in thread
From: Huang Rui @ 2017-09-11 8:58 UTC (permalink / raw)
To: Evan Quan; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Patch 1, 3 are Reviewed-by: Huang Rui <ray.huang@amd.com>
With minor comments on Patch 2 and 4, with that fixed, please feel free to
add Reviewed-by: Huang Rui <ray.huang@amd.com>
Thanks,
Rui
On Mon, Sep 11, 2017 at 09:22:02AM +0800, Evan Quan wrote:
> Change-Id: I9b7ebc99b7c75c03fb46d16c4c49348dd551325e
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 16 +++++++++-------
> 1 file changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> index 5283113..702d68d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> @@ -137,15 +137,13 @@ int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cm
> {
> int ret;
> uint64_t fw_mem_mc_addr = ucode->mc_addr;
> - struct common_firmware_header *header;
>
> memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
> - header = (struct common_firmware_header *)ucode->fw;
>
> cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
> cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
> cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
> - cmd->cmd.cmd_load_ip_fw.fw_size = le32_to_cpu(header->ucode_size_bytes);
> + cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
>
> ret = psp_v10_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
> if (ret)
> @@ -246,15 +244,20 @@ int psp_v10_0_cmd_submit(struct psp_context *psp,
> struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
> struct psp_ring *ring = &psp->km_ring;
> struct amdgpu_device *adev = psp->adev;
> + uint32_t ring_size_dw = ring->ring_size / 4;
> + uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
>
> /* KM (GPCOM) prepare write pointer */
> psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
>
> /* Update KM RB frame pointer to new frame */
> - if ((psp_write_ptr_reg % ring->ring_size) == 0)
> + if ((psp_write_ptr_reg % ring_size_dw) == 0)
> write_frame = ring->ring_mem;
> else
> - write_frame = ring->ring_mem + (psp_write_ptr_reg / (sizeof(struct psp_gfx_rb_frame) / 4));
> + write_frame = ring->ring_mem + (psp_write_ptr_reg / rb_frame_size_dw);
> +
> + /* Initialize KM RB frame */
> + memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
>
> /* Update KM RB frame */
> write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
> @@ -264,8 +267,7 @@ int psp_v10_0_cmd_submit(struct psp_context *psp,
> write_frame->fence_value = index;
>
> /* Update the write Pointer in DWORDs */
> - psp_write_ptr_reg += sizeof(struct psp_gfx_rb_frame) / 4;
> - psp_write_ptr_reg = (psp_write_ptr_reg >= ring->ring_size) ? 0 : psp_write_ptr_reg;
> + psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
> WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
>
> return 0;
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2017-09-11 8:58 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-09-11 1:22 [PATCH 1/4] drm/amdgpu: fixed raven psp cmd prepare and submit Evan Quan
[not found] ` <1505092926-9029-1-git-send-email-evan.quan-5C7GfCeVMHo@public.gmane.org>
2017-09-11 1:22 ` [PATCH 2/4] drm/amdgpu: added api for stopping psp ring Evan Quan
[not found] ` <1505092926-9029-2-git-send-email-evan.quan-5C7GfCeVMHo@public.gmane.org>
2017-09-11 8:51 ` Huang Rui
2017-09-11 1:22 ` [PATCH 3/4] drm/amdgpu: stop psp ring on suspend Evan Quan
2017-09-11 1:22 ` [PATCH 4/4] drm/amdgpu: enable raven to load firmwares by psp at default Evan Quan
[not found] ` <1505092926-9029-4-git-send-email-evan.quan-5C7GfCeVMHo@public.gmane.org>
2017-09-11 8:55 ` Huang Rui
2017-09-11 1:42 ` [PATCH 1/4] drm/amdgpu: fixed raven psp cmd prepare and submit Zhang, Jerry (Junwei)
[not found] ` <59B5E9F9.2000803-5C7GfCeVMHo@public.gmane.org>
2017-09-11 7:51 ` Christian König
2017-09-11 8:58 ` Huang Rui
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