[PATCH 00/28] DC Linux Patches Sep 11, 2017

[PATCH 00/28] DC Linux Patches Sep 11, 2017

[Harry Wentland]

 * Bunch of Raven fixes and other work
 * Stop powering down clock sources in atomic check
 * Stop using amdgpu_connector and use our own
 * Fix display unplug during S3 or fbcon

Andrew Jiang (1):
  drm/amd/display: Fix context alloc failed logging

Charlene Liu (1):
  drm/amd/display: fix crc_source_select use hardcoded color depth

Eric Bernstein (1):
  drm/amd/display: remove output_format from ipp_setup

Harry Wentland (10):
  drm/amd/display: Enable dcn10_power_on_fe log by default
  drm/amd/display: Don't reset clock source at unref
  drm/amd/display: Power down clock source at commit
  drm/amd/display: Remove switching of clk sources at end of commit
  drm/amd/display: No need to keep track of unreffed clk sources
  drm/amd/display: Break out amdgpu_dm_connector
  drm/amd/display: Create fake sink if needed when commit stream
  drm/amd/display: Format changes to bring in line with internal tree
  drm/amd/display: Change comments to bring in line with internal tree
  drm/amd/display: Update include to bring in line with internal tree

Hersen Wu (2):
  drm/amd/display: Request to have DCN RV pipe Harvesting
  drm/amd/display: USB-C to HDMI dongle not light

Logatharshan Thothiralingam (1):
  drm/amd/display: Get OTG info if OTG master enabled

Martin Tsai (1):
  drm/amd/display: To prevent detecting new sink from spurious HPD

Roman Li (1):
  drm/amd/display: Disable FBC for linear tiling

Shirish S (1):
  drm/amd/display: dce110: fix plane validation

Tony Cheng (1):
  drm/amd/display: fix default dithering

Vitaly Prosyak (1):
  drm/amd/display: Update DPP registers

Wenjing Liu (2):
  drm/amd/display: Use TPS4 instead of CP2520_3 for phy pattern 7
  drm/amd/display: set CP2520 Test pattern to use
    DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE

Yongqiang Sun (2):
  drm/amd/display: Added negative check for vertical line start.
  drm/amd/display: Remove sanity check.

Yue Hin Lau (2):
  drm/amd/display: seperate dpp_cm_helper functions into new file
  drm/amd/display: move dwb registers to header file

pana (1):
  drm/amd/display: Add 2X Cursor Magnification Code

 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  | 184 +++++++------
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h  |  55 +++-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c  |  20 +-
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c  |  16 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c    |  34 +--
 .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.h    |   4 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c           |  29 +--
 drivers/gpu/drm/amd/display/dc/core/dc_link.c      |  80 ++++--
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c   |   4 +-
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  |  38 ++-
 drivers/gpu/drm/amd/display/dc/dc.h                |   8 +-
 .../amd/display/dc/dce110/dce110_hw_sequencer.c    |  87 +++----
 .../drm/amd/display/dc/dce110/dce110_resource.c    |  19 +-
 drivers/gpu/drm/amd/display/dc/dcn10/Makefile      |   2 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c   |   3 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h   |  23 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c    | 263 ++++++++-----------
 .../drm/amd/display/dc/dcn10/dcn10_dpp_cm_helper.c | 123 +++++++++
 .../drm/amd/display/dc/dcn10/dcn10_dpp_cm_helper.h |  99 +++++++
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c   | 288 +--------------------
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h   | 247 +++++++++++++++++-
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  34 +--
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c   |   2 -
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h   |  11 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |  97 ++++++-
 .../amd/display/dc/dcn10/dcn10_timing_generator.c  |  13 +-
 .../amd/display/dc/dcn10/dcn10_timing_generator.h  |   1 +
 drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c   |   1 -
 .../display/dc/i2caux/dce110/aux_engine_dce110.c   |   2 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h        |   3 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/transform.h  |   3 +-
 drivers/gpu/drm/amd/display/dc/inc/resource.h      |   2 +-
 drivers/gpu/drm/amd/display/include/dal_asic_id.h  |   1 +
 33 files changed, 1048 insertions(+), 748 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm_helper.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm_helper.h

-- 
2.11.0

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[PATCH 01/28] drm/amd/display: Get OTG info if OTG master enabled

[Harry Wentland]

From: Logatharshan Thothiralingam <logatharshan.thothiralingam@amd.com>

Signed-off-by: Logatharshan Thothiralingam <logatharshan.thothiralingam@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c     | 6 +++++-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c | 3 +++
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h | 1 +
 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 7ea274475598..4fa856e9a872 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -203,10 +203,14 @@ static void dcn10_log_hw_state(struct dc *dc)
 
 	for (i = 0; i < pool->pipe_count; i++) {
 		struct timing_generator *tg = pool->timing_generators[i];
-		struct dcn_otg_state s;
+		struct dcn_otg_state s = {0};
 
 		tgn10_read_otg_state(DCN10TG_FROM_TG(tg), &s);
 
+		//only print if OTG master is enabled
+		if ((s.otg_enabled & 1) == 0)
+			continue;
+
 		DTN_INFO("[%d]:\t %d \t %d \t %d \t %d \t "
 				"%d \t %d \t %d \t %d \t %d \t %d \t "
 				"%d \t %d \t %d \t %d \t %d \t ",
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
index 15f1f44e102a..405f595f219a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
@@ -1100,6 +1100,9 @@ static bool tgn10_is_stereo_left_eye(struct timing_generator *tg)
 void tgn10_read_otg_state(struct dcn10_timing_generator *tgn10,
 		struct dcn_otg_state *s)
 {
+	REG_GET(OTG_CONTROL,
+			OTG_MASTER_EN, &s->otg_enabled);
+
 	REG_GET_2(OTG_V_BLANK_START_END,
 			OTG_V_BLANK_START, &s->v_blank_start,
 			OTG_V_BLANK_END, &s->v_blank_end);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
index 38d3dcf89d60..69da293e9b4a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
@@ -370,6 +370,7 @@ struct dcn_otg_state {
 	uint32_t h_sync_a_pol;
 	uint32_t h_total;
 	uint32_t underflow_occurred_status;
+	uint32_t otg_enabled;
 };
 
 void tgn10_read_otg_state(struct dcn10_timing_generator *tgn10,
-- 
2.11.0

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[PATCH 02/28] drm/amd/display: Added negative check for vertical line start.

[Harry Wentland]

From: Yongqiang Sun <yongqiang.sun@amd.com>

	In case of vstartup happens before vsync, set vertical line
	start to 0.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
index 405f595f219a..2d3dd9a3a196 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
@@ -118,7 +118,7 @@ static void tgn10_program_timing(
 	uint32_t start_point = 0;
 	uint32_t field_num = 0;
 	uint32_t h_div_2;
-	uint32_t vertial_line_start;
+	int32_t vertical_line_start;
 
 	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
 
@@ -216,9 +216,13 @@ static void tgn10_program_timing(
 	/* Use OTG_VERTICAL_INTERRUPT2 replace VUPDATE interrupt,
 	 * program the reg for interrupt postition.
 	 */
-	vertial_line_start = asic_blank_end - tg->dlg_otg_param.vstartup_start + 1;
+	vertical_line_start = asic_blank_end - tg->dlg_otg_param.vstartup_start + 1;
+	if (vertical_line_start < 0) {
+		ASSERT(0);
+		vertical_line_start = 0;
+	}
 	REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0,
-			OTG_VERTICAL_INTERRUPT2_LINE_START, vertial_line_start);
+			OTG_VERTICAL_INTERRUPT2_LINE_START, vertical_line_start);
 
 	/* v_sync polarity */
 	v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ?
-- 
2.11.0

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[PATCH 03/28] drm/amd/display: Remove sanity check.

[Harry Wentland]

From: Yongqiang Sun <yongqiang.sun@amd.com>

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 4fa856e9a872..a6015c2c20c6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2828,12 +2828,6 @@ void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
 	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 	struct timing_generator *tg = pipe_ctx->stream_res.tg;
 
-	if (plane_state->ctx->dc->debug.sanity_checks) {
-		struct dc *dc = plane_state->ctx->dc;
-
-		verify_allow_pstate_change_high(dc->hwseq);
-	}
-
 	if (plane_state == NULL)
 		return;
 
-- 
2.11.0

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[PATCH 04/28] drm/amd/display: Use TPS4 instead of CP2520_3 for phy pattern 7

[Harry Wentland]

From: Wenjing Liu <Wenjing.Liu@amd.com>

[Description]
We originally use TPS4 phy test pattern for test pattern 7.
On RV we switched to a new method to use CP2520.
CP2520 should produce the same result.
However in reality, it fails DP PHY automation test.
We use the original method instead.

Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 527cc0400fd3..1aec586b0367 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1756,7 +1756,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
 		test_pattern = DP_TEST_PATTERN_CP2520_2;
 		break;
 	case PHY_TEST_PATTERN_CP2520_3:
-		test_pattern = DP_TEST_PATTERN_CP2520_3;
+		test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
 		break;
 	default:
 		test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
-- 
2.11.0

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[PATCH 05/28] drm/amd/display: Request to have DCN RV pipe Harvesting

[Harry Wentland]

From: Hersen Wu <hersenxs.wu@amd.com>

TODO: Current change only work for sucessive last fused pipe,
like p3, or p3,p2. It does not work for fused p1,p2.

Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  | 55 +++++++++++++++++-----
 1 file changed, 43 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index fff86ad0c411..ac6d01ec0505 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -1207,13 +1207,23 @@ static struct resource_funcs dcn10_res_pool_funcs = {
 	.add_stream_to_ctx = dcn10_add_stream_to_ctx
 };
 
+static uint32_t read_pipe_fuses(struct dc_context *ctx)
+{
+	uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);
+	/* RV1 support max 4 pipes */
+	value = value & 0xf;
+	return value;
+}
+
 static bool construct(
 	uint8_t num_virtual_links,
 	struct dc *dc,
 	struct dcn10_resource_pool *pool)
 {
 	int i;
+	int j;
 	struct dc_context *ctx = dc->ctx;
+	uint32_t pipe_fuses = read_pipe_fuses(ctx);
 
 	ctx->dc_bios->regs = &bios_regs;
 
@@ -1230,8 +1240,9 @@ static bool construct(
 	 *************************************************/
 	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
 
-	/* TODO: Hardcode to correct number of functional controllers */
-	pool->base.pipe_count = 4;
+	/* max pipe num for ASIC before check pipe fuses */
+	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
+
 	dc->caps.max_downscale_ratio = 200;
 	dc->caps.i2c_speed_in_khz = 100;
 	dc->caps.max_cursor_size = 256;
@@ -1355,48 +1366,68 @@ static bool construct(
 	#endif
 	}
 
+	/* index to valid pipe resource  */
+	j = 0;
 	/* mem input -> ipp -> dpp -> opp -> TG */
 	for (i = 0; i < pool->base.pipe_count; i++) {
-		pool->base.mis[i] = dcn10_mem_input_create(ctx, i);
-		if (pool->base.mis[i] == NULL) {
+		/* if pipe is disabled, skip instance of HW pipe,
+		 * i.e, skip ASIC register instance
+		 */
+		if ((pipe_fuses & (1 << i)) != 0)
+			continue;
+
+		pool->base.mis[j] = dcn10_mem_input_create(ctx, i);
+		if (pool->base.mis[j] == NULL) {
 			BREAK_TO_DEBUGGER();
 			dm_error(
 				"DC: failed to create memory input!\n");
 			goto mi_create_fail;
 		}
 
-		pool->base.ipps[i] = dcn10_ipp_create(ctx, i);
-		if (pool->base.ipps[i] == NULL) {
+		pool->base.ipps[j] = dcn10_ipp_create(ctx, i);
+		if (pool->base.ipps[j] == NULL) {
 			BREAK_TO_DEBUGGER();
 			dm_error(
 				"DC: failed to create input pixel processor!\n");
 			goto ipp_create_fail;
 		}
 
-		pool->base.transforms[i] = dcn10_dpp_create(ctx, i);
-		if (pool->base.transforms[i] == NULL) {
+		pool->base.transforms[j] = dcn10_dpp_create(ctx, i);
+		if (pool->base.transforms[j] == NULL) {
 			BREAK_TO_DEBUGGER();
 			dm_error(
 				"DC: failed to create dpp!\n");
 			goto dpp_create_fail;
 		}
 
-		pool->base.opps[i] = dcn10_opp_create(ctx, i);
-		if (pool->base.opps[i] == NULL) {
+		pool->base.opps[j] = dcn10_opp_create(ctx, i);
+		if (pool->base.opps[j] == NULL) {
 			BREAK_TO_DEBUGGER();
 			dm_error(
 				"DC: failed to create output pixel processor!\n");
 			goto opp_create_fail;
 		}
 
-		pool->base.timing_generators[i] = dcn10_timing_generator_create(
+		pool->base.timing_generators[j] = dcn10_timing_generator_create(
 				ctx, i);
-		if (pool->base.timing_generators[i] == NULL) {
+		if (pool->base.timing_generators[j] == NULL) {
 			BREAK_TO_DEBUGGER();
 			dm_error("DC: failed to create tg!\n");
 			goto otg_create_fail;
 		}
+		/* check next valid pipe */
+		j++;
 	}
+
+	/* valid pipe num */
+	pool->base.pipe_count = j;
+
+	/* within dml lib, it is hard code to 4. If ASIC pipe is fused,
+	 * the value may be changed
+	 */
+	dc->dml.ip.max_num_dpp = pool->base.pipe_count;
+	dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
+
 	pool->base.mpc = dcn10_mpc_create(ctx);
 	if (pool->base.mpc == NULL) {
 		BREAK_TO_DEBUGGER();
-- 
2.11.0

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[PATCH 06/28] drm/amd/display: dce110: fix plane validation

[Harry Wentland]

From: Shirish S <shirish.s@amd.com>

For MPO to work with per surface rendering and flipping,
the previous logic of restricting plane[1] only as underlay
needs to be removed.
validate_surface_sets() now checks only the width and height
bounds in case of underlay rather than checking format.

Without this patch one cannot set underlay only.

Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
 .../gpu/drm/amd/display/dc/dce110/dce110_resource.c   | 19 ++++++-------------
 1 file changed, 6 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index 41bfddf9574e..25eda52c32ef 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -891,21 +891,14 @@ static bool dce110_validate_surface_sets(
 		if (context->stream_status[i].plane_count > 2)
 			return false;
 
-		if (context->stream_status[i].plane_states[0]->format
-				>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
+		if ((context->stream_status[i].plane_states[i]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) &&
+		    (context->stream_status[i].plane_states[i]->src_rect.width > 1920 ||
+		     context->stream_status[i].plane_states[i]->src_rect.height > 1080))
 			return false;
 
-		if (context->stream_status[i].plane_count == 2) {
-			if (context->stream_status[i].plane_states[1]->format
-					< SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
-				return false;
-			if (context->stream_status[i].plane_states[1]->src_rect.width > 1920
-					|| context->stream_status[i].plane_states[1]->src_rect.height > 1080)
-				return false;
-
-			if (context->streams[i]->timing.pixel_encoding != PIXEL_ENCODING_RGB)
-				return false;
-		}
+		/* irrespective of plane format, stream should be RGB encoded */
+		if (context->streams[i]->timing.pixel_encoding != PIXEL_ENCODING_RGB)
+			return false;
 	}
 
 	return true;
-- 
2.11.0

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[PATCH 07/28] drm/amd/display: USB-C to HDMI dongle not light

[Harry Wentland]

From: Hersen Wu <hersenxs.wu@amd.com>

Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  9 ++++---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c     | 32 +++++++++++++++--------
 drivers/gpu/drm/amd/display/dc/dc.h               |  8 +++++-
 3 files changed, 33 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 7a408d753be8..9b5158cceece 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -639,7 +639,7 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev )
 			continue;
 
 		mutex_lock(&aconnector->hpd_lock);
-		dc_link_detect(aconnector->dc_link, false);
+		dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
 		aconnector->dc_sink = NULL;
 		amdgpu_dm_update_connector_after_detect(aconnector);
 		mutex_unlock(&aconnector->hpd_lock);
@@ -870,7 +870,7 @@ static void handle_hpd_irq(void *param)
 	 * since (for MST case) MST does this in it's own context.
 	 */
 	mutex_lock(&aconnector->hpd_lock);
-	if (dc_link_detect(aconnector->dc_link, false)) {
+	if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
 		amdgpu_dm_update_connector_after_detect(aconnector);
 
 
@@ -980,7 +980,7 @@ static void handle_hpd_rx_irq(void *param)
 	if (dc_link_handle_hpd_rx_irq(aconnector->dc_link, NULL) &&
 			!is_mst_root_connector) {
 		/* Downstream Port status changed. */
-		if (dc_link_detect(aconnector->dc_link, false)) {
+		if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPDRX)) {
 			amdgpu_dm_update_connector_after_detect(aconnector);
 
 
@@ -1368,7 +1368,8 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 			goto fail_free_encoder;
 		}
 
-		if (dc_link_detect(dc_get_link_at_index(dm->dc, i), true))
+		if (dc_link_detect(dc_get_link_at_index(dm->dc, i),
+				DETECT_REASON_BOOT))
 			amdgpu_dm_update_connector_after_detect(aconnector);
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index cea8dafd2edc..845ec421d861 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -355,7 +355,9 @@ static bool is_dp_sink_present(struct dc_link *link)
  * @brief
  * Detect output sink type
  */
-static enum signal_type link_detect_sink(struct dc_link *link)
+static enum signal_type link_detect_sink(
+	struct dc_link *link,
+	enum dc_detect_reason reason)
 {
 	enum signal_type result = get_basic_signal_type(
 		link->link_enc->id, link->link_id);
@@ -388,12 +390,17 @@ static enum signal_type link_detect_sink(struct dc_link *link)
 	}
 	break;
 	case CONNECTOR_ID_DISPLAY_PORT: {
-
-		/* Check whether DP signal detected: if not -
-		 * we assume signal is DVI; it could be corrected
-		 * to HDMI after dongle detection */
-		if (!is_dp_sink_present(link))
-			result = SIGNAL_TYPE_DVI_SINGLE_LINK;
+		/* DP HPD short pulse. Passive DP dongle will not
+		 * have short pulse
+		 */
+		if (reason != DETECT_REASON_HPDRX) {
+			/* Check whether DP signal detected: if not -
+			 * we assume signal is DVI; it could be corrected
+			 * to HDMI after dongle detection
+			 */
+			if (!is_dp_sink_present(link))
+				result = SIGNAL_TYPE_DVI_SINGLE_LINK;
+		}
 	}
 	break;
 	default:
@@ -460,9 +467,10 @@ static void detect_dp(
 	struct display_sink_capability *sink_caps,
 	bool *converter_disable_audio,
 	struct audio_support *audio_support,
-	bool boot)
+	enum dc_detect_reason reason)
 {
-	sink_caps->signal = link_detect_sink(link);
+	bool boot = false;
+	sink_caps->signal = link_detect_sink(link, reason);
 	sink_caps->transaction_type =
 		get_ddc_transaction_type(sink_caps->signal);
 
@@ -513,6 +521,8 @@ static void detect_dp(
 			 * Need check ->sink usages in case ->sink = NULL
 			 * TODO: s3 resume check
 			 */
+			if (reason == DETECT_REASON_BOOT)
+				boot = true;
 
 			if (dm_helpers_dp_mst_start_top_mgr(
 				link->ctx,
@@ -531,7 +541,7 @@ static void detect_dp(
 	}
 }
 
-bool dc_link_detect(struct dc_link *link, bool boot)
+bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
 {
 	struct dc_sink_init_data sink_init_data = { 0 };
 	struct display_sink_capability sink_caps = { 0 };
@@ -596,7 +606,7 @@ bool dc_link_detect(struct dc_link *link, bool boot)
 				link,
 				&sink_caps,
 				&converter_disable_audio,
-				aud_support, boot);
+				aud_support, reason);
 
 			/* Active dongle downstream unplug */
 			if (link->type == dc_connection_active_dongle
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index f005add1aba3..bf2d42561362 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -884,7 +884,13 @@ bool dc_link_setup_psr(struct dc_link *dc_link,
  * true otherwise. True meaning further action is required (status update
  * and OS notification).
  */
-bool dc_link_detect(struct dc_link *dc_link, bool boot);
+enum dc_detect_reason {
+	DETECT_REASON_BOOT,
+	DETECT_REASON_HPD,
+	DETECT_REASON_HPDRX,
+};
+
+bool dc_link_detect(struct dc_link *dc_link, enum dc_detect_reason reason);
 
 /* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt).
  * Return:
-- 
2.11.0

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[PATCH 08/28] drm/amd/display: set CP2520 Test pattern to use DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE

[Harry Wentland]

From: Wenjing Liu <Wenjing.Liu@amd.com>

Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 1aec586b0367..38ccc011004d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1750,7 +1750,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
 		test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
 		break;
 	case PHY_TEST_PATTERN_CP2520_1:
-		test_pattern = DP_TEST_PATTERN_CP2520_1;
+		test_pattern = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
 		break;
 	case PHY_TEST_PATTERN_CP2520_2:
 		test_pattern = DP_TEST_PATTERN_CP2520_2;
-- 
2.11.0

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[PATCH 09/28] drm/amd/display: fix crc_source_select use hardcoded color depth

[Harry Wentland]

From: Charlene Liu <charlene.liu@amd.com>

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 .../drm/amd/display/dc/dce110/dce110_hw_sequencer.c  | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 9fb0ba7e7b7d..47e8b582445e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -667,7 +667,25 @@ static enum dc_status bios_parser_crtc_source_select(
 	crtc_source_select.signal = pipe_ctx->stream->signal;
 	crtc_source_select.enable_dp_audio = false;
 	crtc_source_select.sink_signal = pipe_ctx->stream->signal;
-	crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
+
+	switch (pipe_ctx->stream->timing.display_color_depth) {
+	case COLOR_DEPTH_666:
+		crtc_source_select.display_output_bit_depth = PANEL_6BIT_COLOR;
+		break;
+	case COLOR_DEPTH_888:
+		crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
+		break;
+	case COLOR_DEPTH_101010:
+		crtc_source_select.display_output_bit_depth = PANEL_10BIT_COLOR;
+		break;
+	case COLOR_DEPTH_121212:
+		crtc_source_select.display_output_bit_depth = PANEL_12BIT_COLOR;
+		break;
+	default:
+		BREAK_TO_DEBUGGER();
+		crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
+		break;
+	}
 
 	dcb = sink->ctx->dc_bios;
 
-- 
2.11.0

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[PATCH 10/28] drm/amd/display: Enable dcn10_power_on_fe log by default

[Harry Wentland]

This should only happen on full update. If this ever happens
on regular pageflips it needs to be debugged.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index a6015c2c20c6..6b76fc417456 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1975,7 +1975,7 @@ static void dcn10_power_on_fe(
 	/*TODO: REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, 0x1f);*/
 
 	if (plane_state) {
-		dm_logger_write(dc->ctx->logger, LOG_DEBUG,
+		dm_logger_write(dc->ctx->logger, LOG_DC,
 				"Pipe:%d 0x%x: addr hi:0x%x, "
 				"addr low:0x%x, "
 				"src: %d, %d, %d,"
@@ -1993,7 +1993,7 @@ static void dcn10_power_on_fe(
 				plane_state->dst_rect.width,
 				plane_state->dst_rect.height);
 
-		dm_logger_write(dc->ctx->logger, LOG_DEBUG,
+		dm_logger_write(dc->ctx->logger, LOG_DC,
 				"Pipe %d: width, height, x, y\n"
 				"viewport:%d, %d, %d, %d\n"
 				"recout:  %d, %d, %d, %d\n",
-- 
2.11.0

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[PATCH 11/28] drm/amd/display: fix default dithering

[Harry Wentland]

From: Tony Cheng <tony.cheng@amd.com>

bug: default is mapped to no dithering.

default to spatial dithering based on color depth

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c             | 20 +++-----------------
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c    | 16 ++++++++++++++++
 .../drm/amd/display/dc/dce110/dce110_hw_sequencer.c  | 14 +++++---------
 3 files changed, 24 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 15ba9c9887fd..0187188dafd6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -341,23 +341,9 @@ void set_dither_option(struct dc_stream_state *stream,
 		return;
 	if (option > DITHER_OPTION_MAX)
 		return;
-	if (option == DITHER_OPTION_DEFAULT) {
-		switch (stream->timing.display_color_depth) {
-		case COLOR_DEPTH_666:
-			stream->dither_option = DITHER_OPTION_SPATIAL6;
-			break;
-		case COLOR_DEPTH_888:
-			stream->dither_option = DITHER_OPTION_SPATIAL8;
-			break;
-		case COLOR_DEPTH_101010:
-			stream->dither_option = DITHER_OPTION_SPATIAL10;
-			break;
-		default:
-			option = DITHER_OPTION_DISABLE;
-		}
-	} else {
-		stream->dither_option = option;
-	}
+
+	stream->dither_option = option;
+
 	resource_build_bit_depth_reduction_params(stream,
 				&params);
 	stream->bit_depth_params = params;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 8e60e838b455..3eba2e55639b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2607,6 +2607,22 @@ void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
 
 	memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
 
+	if (option == DITHER_OPTION_DEFAULT) {
+		switch (stream->timing.display_color_depth) {
+		case COLOR_DEPTH_666:
+			option = DITHER_OPTION_SPATIAL6;
+			break;
+		case COLOR_DEPTH_888:
+			option = DITHER_OPTION_SPATIAL8;
+			break;
+		case COLOR_DEPTH_101010:
+			option = DITHER_OPTION_SPATIAL10;
+			break;
+		default:
+			option = DITHER_OPTION_DISABLE;
+		}
+	}
+
 	if (option == DITHER_OPTION_DISABLE)
 		return;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 47e8b582445e..b36220bc619d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1104,15 +1104,11 @@ static enum dc_status apply_single_controller_ctx_to_hw(
 		stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
 
 
-/*vbios crtc_source_selection and encoder_setup will override fmt_C*/
-	if (pipe_ctx->stream->signal != SIGNAL_TYPE_EDP &&
-		pipe_ctx->stream->signal != SIGNAL_TYPE_LVDS) {
-	/*for embedded panel, don't override VBIOS's setting*/
-		pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
-			pipe_ctx->stream_res.opp,
-			&stream->bit_depth_params,
-			&stream->clamping);
-	}
+	pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
+		pipe_ctx->stream_res.opp,
+		&stream->bit_depth_params,
+		&stream->clamping);
+
 	if (dc_is_dp_signal(pipe_ctx->stream->signal))
 		pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
 			pipe_ctx->stream_res.stream_enc,
-- 
2.11.0

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[PATCH 12/28] drm/amd/display: Fix context alloc failed logging

[Harry Wentland]

From: Andrew Jiang <Andrew.Jiang@amd.com>

Since there was no return statement in the fail block immediately
preceding the context_alloc_fail block, any failure within the
function caused a context alloc failed error message to be printed.
Since the context_alloc_fail block is only used once, move it to
where the goto is directly and accompany it with a return statement.

Signed-off-by: Andrew Jiang <Andrew.Jiang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 0187188dafd6..dd86b864efe6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1270,8 +1270,10 @@ void dc_update_planes_and_stream(struct dc *dc,
 
 		/* initialize scratch memory for building context */
 		context = dm_alloc(sizeof(*context));
-		if (context == NULL)
-				goto context_alloc_fail;
+		if (context == NULL) {
+			DC_ERROR("Failed to allocate new validate context!\n");
+			return;
+		}
 
 		atomic_inc(&context->ref_count);
 
@@ -1527,9 +1529,6 @@ void dc_update_planes_and_stream(struct dc *dc,
 
 fail:
 	dc_release_state(context);
-
-context_alloc_fail:
-	DC_ERROR("Failed to allocate new validate context!\n");
 }
 
 uint8_t dc_get_current_stream_count(struct dc *dc)
-- 
2.11.0

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[PATCH 13/28] drm/amd/display: seperate dpp_cm_helper functions into new file

[Harry Wentland]

From: Yue Hin Lau <Yuehin.Lau@amd.com>

Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/Makefile      |   2 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h   |   2 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c    | 259 +++++++++------------
 .../drm/amd/display/dc/dcn10/dcn10_dpp_cm_helper.c | 123 ++++++++++
 .../drm/amd/display/dc/dcn10/dcn10_dpp_cm_helper.h |  99 ++++++++
 5 files changed, 330 insertions(+), 155 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm_helper.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm_helper.h

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
index 52b56d19ca40..e92ac2997a1a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
@@ -4,7 +4,7 @@
 DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \
 		dcn10_dpp.o dcn10_opp.o dcn10_timing_generator.o \
 		dcn10_mem_input.o dcn10_mpc.o dcn10_dwb.o \
-		dcn10_dpp_dscl.o dcn10_dpp_cm.o
+		dcn10_dpp_dscl.o dcn10_dpp_cm.o dcn10_dpp_cm_helper.o
 
 AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10))
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
index 4bbd3b4f7ae6..70d6ba09501b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -1262,6 +1262,8 @@ struct dcn10_dpp {
 	bool is_write_to_ram_a_safe;
 };
 
+
+
 enum dcn10_input_csc_select {
 	INPUT_CSC_SELECT_BYPASS = 0,
 	INPUT_CSC_SELECT_ICSC,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
index d698fccdef68..840dd0346782 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
@@ -29,6 +29,7 @@
 
 #include "reg_helper.h"
 #include "dcn10_dpp.h"
+#include "dcn10_dpp_cm_helper.h"
 #include "basics/conversion.h"
 
 #define NUM_PHASES    64
@@ -116,37 +117,7 @@ static const struct dcn10_input_csc_matrix dcn10_input_csc_matrix[] = {
 						0x2568, 0x43ee, 0xdbb2} }
 };
 
-static void dpp_cm_program_color_registers(
-		struct dcn10_dpp *xfm,
-		const uint16_t *regval,
-		uint32_t cm_reg_start,
-		uint32_t cm_reg_end)
-{
-	uint32_t reg_region_cur;
-	unsigned int i = 0;
-
-#undef REG
-#define REG(reg) reg
-
-	for (reg_region_cur = cm_reg_start;
-			reg_region_cur <= cm_reg_end;
-			reg_region_cur++) {
-
-		const uint16_t *regval0 = &(regval[2 * i]);
-		const uint16_t *regval1 = &(regval[(2 * i) + 1]);
 
-		REG_SET_2(reg_region_cur, 0,
-				CM_GAMUT_REMAP_C11, *regval0,
-				CM_GAMUT_REMAP_C12, *regval1);
-
-		i++;
-	}
-
-#undef REG
-#define REG(reg)\
-	xfm->tf_regs->reg
-
-}
 
 static void program_gamut_remap(
 		struct dcn10_dpp *xfm,
@@ -154,6 +125,7 @@ static void program_gamut_remap(
 		enum gamut_remap_select select)
 {
 	 uint16_t selection = 0;
+	struct color_matrices_reg gam_regs;
 
 	if (regval == NULL || select == GAMUT_REMAP_BYPASS) {
 		REG_SET(CM_GAMUT_REMAP_CONTROL, 0,
@@ -174,30 +146,40 @@ static void program_gamut_remap(
 		break;
 	}
 
+	gam_regs.shifts.csc_c11 = xfm->tf_shift->CM_GAMUT_REMAP_C11;
+	gam_regs.masks.csc_c11  = xfm->tf_mask->CM_GAMUT_REMAP_C11;
+	gam_regs.shifts.csc_c12 = xfm->tf_shift->CM_GAMUT_REMAP_C12;
+	gam_regs.masks.csc_c12 = xfm->tf_mask->CM_GAMUT_REMAP_C12;
+
 
 	if (select == GAMUT_REMAP_COEFF) {
+		gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12);
+		gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34);
 
-		dpp_cm_program_color_registers(
-				xfm,
+		cm_helper_program_color_matrices(
+				xfm->base.ctx,
 				regval,
-				REG(CM_GAMUT_REMAP_C11_C12),
-				REG(CM_GAMUT_REMAP_C33_C34));
+				&gam_regs);
 
 	} else  if (select == GAMUT_REMAP_COMA_COEFF) {
 
-		dpp_cm_program_color_registers(
-				xfm,
+		gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12);
+		gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34);
+
+		cm_helper_program_color_matrices(
+				xfm->base.ctx,
 				regval,
-				REG(CM_COMA_C11_C12),
-				REG(CM_COMA_C33_C34));
+				&gam_regs);
 
 	} else {
 
-		dpp_cm_program_color_registers(
-				xfm,
+		gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12);
+		gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34);
+
+		cm_helper_program_color_matrices(
+				xfm->base.ctx,
 				regval,
-				REG(CM_COMB_C11_C12),
-				REG(CM_COMB_C33_C34));
+				&gam_regs);
 	}
 
 	REG_SET(
@@ -278,11 +260,39 @@ void dcn10_dpp_cm_set_output_csc_default(
 
 }
 
+static void dcn10_dpp_cm_get_reg_field(
+		struct dcn10_dpp *xfm,
+		struct xfer_func_reg *reg)
+{
+	reg->shifts.exp_region0_lut_offset = xfm->tf_shift->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;
+	reg->masks.exp_region0_lut_offset = xfm->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;
+	reg->shifts.exp_region0_num_segments = xfm->tf_shift->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
+	reg->masks.exp_region0_num_segments = xfm->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
+	reg->shifts.exp_region1_lut_offset = xfm->tf_shift->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;
+	reg->masks.exp_region1_lut_offset = xfm->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;
+	reg->shifts.exp_region1_num_segments = xfm->tf_shift->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
+	reg->masks.exp_region1_num_segments = xfm->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
+
+	reg->shifts.field_region_end = xfm->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_B;
+	reg->masks.field_region_end = xfm->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B;
+	reg->shifts.field_region_end_slope = xfm->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B;
+	reg->masks.field_region_end_slope = xfm->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B;
+	reg->shifts.field_region_end_base = xfm->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_BASE_B;
+	reg->masks.field_region_end_base = xfm->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_BASE_B;
+	reg->shifts.field_region_linear_slope = xfm->tf_shift->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;
+	reg->masks.field_region_linear_slope = xfm->tf_mask->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;
+	reg->shifts.exp_region_start = xfm->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_B;
+	reg->masks.exp_region_start = xfm->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_B;
+	reg->shifts.exp_resion_start_segment = xfm->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B;
+	reg->masks.exp_resion_start_segment = xfm->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B;
+}
+
 static void dcn10_dpp_cm_program_color_matrix(
 		struct dcn10_dpp *xfm,
 		const struct out_csc_color_matrix *tbl_entry)
 {
 	uint32_t mode;
+	struct color_matrices_reg gam_regs;
 
 	REG_GET(CM_OCSC_CONTROL, CM_OCSC_MODE, &mode);
 
@@ -291,21 +301,30 @@ static void dcn10_dpp_cm_program_color_matrix(
 		return;
 	}
 
+	gam_regs.shifts.csc_c11 = xfm->tf_shift->CM_OCSC_C11;
+	gam_regs.masks.csc_c11  = xfm->tf_mask->CM_OCSC_C11;
+	gam_regs.shifts.csc_c12 = xfm->tf_shift->CM_OCSC_C12;
+	gam_regs.masks.csc_c12 = xfm->tf_mask->CM_OCSC_C12;
+
 	if (mode == 4) {
 
-		dpp_cm_program_color_registers(
-				xfm,
+		gam_regs.csc_c11_c12 = REG(CM_OCSC_C11_C12);
+		gam_regs.csc_c33_c34 = REG(CM_OCSC_C33_C34);
+
+		cm_helper_program_color_matrices(
+				xfm->base.ctx,
 				tbl_entry->regval,
-				REG(CM_OCSC_C11_C12),
-				REG(CM_OCSC_C33_C34));
+				&gam_regs);
 
 	} else {
 
-		dpp_cm_program_color_registers(
-				xfm,
+		gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12);
+		gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34);
+
+		cm_helper_program_color_matrices(
+				xfm->base.ctx,
 				tbl_entry->regval,
-				REG(CM_COMB_C11_C12),
-				REG(CM_COMB_C33_C34));
+				&gam_regs);
 	}
 }
 
@@ -394,101 +413,15 @@ void dcn10_dpp_cm_configure_regamma_lut(
 	REG_SET(CM_RGAM_LUT_INDEX, 0, CM_RGAM_LUT_INDEX, 0);
 }
 
-struct cm_gam_ram_reg {
-	uint32_t start_cntl_b;
-	uint32_t start_cntl_g;
-	uint32_t start_cntl_r;
-	uint32_t start_slope_cntl_b;
-	uint32_t start_slope_cntl_g;
-	uint32_t start_slope_cntl_r;
-	uint32_t start_end_cntl1_b;
-	uint32_t start_end_cntl2_b;
-	uint32_t start_end_cntl1_g;
-	uint32_t start_end_cntl2_g;
-	uint32_t start_end_cntl1_r;
-	uint32_t start_end_cntl2_r;
-	uint32_t region_start;
-	uint32_t region_end;
-};
-
-static void dpp_cm_program_region_lut(
-		struct transform *xfm_base,
-		const struct pwl_params *params,
-		const struct cm_gam_ram_reg *reg)
-{
-	struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base);
-	uint32_t reg_region_cur;
-	unsigned int i = 0;
-
-#undef REG
-#define REG(reg) reg
-
-	REG_SET_2(reg->start_cntl_b, 0,
-		CM_RGAM_RAMA_EXP_REGION_START_B, params->arr_points[0].custom_float_x,
-		CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B, 0);
-	REG_SET_2(reg->start_cntl_g, 0,
-		CM_RGAM_RAMA_EXP_REGION_START_G, params->arr_points[0].custom_float_x,
-		CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G, 0);
-	REG_SET_2(reg->start_cntl_r, 0,
-		CM_RGAM_RAMA_EXP_REGION_START_R, params->arr_points[0].custom_float_x,
-		CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R, 0);
-
-	REG_SET(reg->start_slope_cntl_b, 0,
-		CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, params->arr_points[0].custom_float_slope);
-	REG_SET(reg->start_slope_cntl_g, 0,
-		CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, params->arr_points[0].custom_float_slope);
-	REG_SET(reg->start_slope_cntl_r, 0,
-		CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, params->arr_points[0].custom_float_slope);
-
-	REG_SET(reg->start_end_cntl1_b, 0,
-		CM_RGAM_RAMA_EXP_REGION_END_B, params->arr_points[1].custom_float_x);
-	REG_SET_2(reg->start_end_cntl2_b, 0,
-		CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B, params->arr_points[1].custom_float_slope,
-		CM_RGAM_RAMA_EXP_REGION_END_BASE_B, params->arr_points[1].custom_float_y);
-
-	REG_SET(reg->start_end_cntl1_g, 0,
-		CM_RGAM_RAMA_EXP_REGION_END_G, params->arr_points[1].custom_float_x);
-	REG_SET_2(reg->start_end_cntl2_g, 0,
-		CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G, params->arr_points[1].custom_float_slope,
-		CM_RGAM_RAMA_EXP_REGION_END_BASE_G, params->arr_points[1].custom_float_y);
-
-	REG_SET(reg->start_end_cntl1_r, 0,
-		CM_RGAM_RAMA_EXP_REGION_END_R, params->arr_points[1].custom_float_x);
-	REG_SET_2(reg->start_end_cntl2_r, 0,
-		CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R, params->arr_points[1].custom_float_slope,
-		CM_RGAM_RAMA_EXP_REGION_END_BASE_R, params->arr_points[1].custom_float_y);
-
-	for (reg_region_cur = reg->region_start;
-			reg_region_cur <= reg->region_end;
-			reg_region_cur++) {
-
-		const struct gamma_curve *curve0 = &(params->arr_curve_points[2 * i]);
-		const struct gamma_curve *curve1 = &(params->arr_curve_points[(2 * i) + 1]);
-
-		REG_SET_4(reg_region_cur, 0,
-			CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET, curve0->offset,
-			CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, curve0->segments_num,
-			CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET, curve1->offset,
-			CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, curve1->segments_num);
-
-		i++;
-	}
-
-#undef REG
-#define REG(reg)\
-	xfm->tf_regs->reg
-
-}
-
-
-
 /*program re gamma RAM A*/
 void dcn10_dpp_cm_program_regamma_luta_settings(
 		struct transform *xfm_base,
 		const struct pwl_params *params)
 {
 	struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base);
-	struct cm_gam_ram_reg gam_regs;
+	struct xfer_func_reg gam_regs;
+
+	dcn10_dpp_cm_get_reg_field(xfm, &gam_regs);
 
 	gam_regs.start_cntl_b = REG(CM_RGAM_RAMA_START_CNTL_B);
 	gam_regs.start_cntl_g = REG(CM_RGAM_RAMA_START_CNTL_G);
@@ -505,7 +438,7 @@ void dcn10_dpp_cm_program_regamma_luta_settings(
 	gam_regs.region_start = REG(CM_RGAM_RAMA_REGION_0_1);
 	gam_regs.region_end = REG(CM_RGAM_RAMA_REGION_32_33);
 
-	dpp_cm_program_region_lut(xfm_base, params, &gam_regs);
+	cm_helper_program_xfer_func(xfm->base.ctx, params, &gam_regs);
 
 }
 
@@ -515,7 +448,9 @@ void dcn10_dpp_cm_program_regamma_lutb_settings(
 		const struct pwl_params *params)
 {
 	struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base);
-	struct cm_gam_ram_reg gam_regs;
+	struct xfer_func_reg gam_regs;
+
+	dcn10_dpp_cm_get_reg_field(xfm, &gam_regs);
 
 	gam_regs.start_cntl_b = REG(CM_RGAM_RAMB_START_CNTL_B);
 	gam_regs.start_cntl_g = REG(CM_RGAM_RAMB_START_CNTL_G);
@@ -532,7 +467,7 @@ void dcn10_dpp_cm_program_regamma_lutb_settings(
 	gam_regs.region_start = REG(CM_RGAM_RAMB_REGION_0_1);
 	gam_regs.region_end = REG(CM_RGAM_RAMB_REGION_32_33);
 
-	dpp_cm_program_region_lut(xfm_base, params, &gam_regs);
+	cm_helper_program_xfer_func(xfm->base.ctx, params, &gam_regs);
 }
 
 void ippn10_program_input_csc(
@@ -545,6 +480,7 @@ void ippn10_program_input_csc(
 	int arr_size = sizeof(dcn10_input_csc_matrix)/sizeof(struct dcn10_input_csc_matrix);
 	const uint16_t *regval = NULL;
 	uint32_t selection = 1;
+	struct color_matrices_reg gam_regs;
 
 	if (select == INPUT_CSC_SELECT_BYPASS) {
 		REG_SET(CM_ICSC_CONTROL, 0, CM_ICSC_MODE, 0);
@@ -567,20 +503,30 @@ void ippn10_program_input_csc(
 	REG_SET(CM_ICSC_CONTROL, 0,
 			CM_ICSC_MODE, selection);
 
+	gam_regs.shifts.csc_c11 = xfm->tf_shift->CM_ICSC_C11;
+	gam_regs.masks.csc_c11  = xfm->tf_mask->CM_ICSC_C11;
+	gam_regs.shifts.csc_c12 = xfm->tf_shift->CM_ICSC_C12;
+	gam_regs.masks.csc_c12 = xfm->tf_mask->CM_ICSC_C12;
+
+
 	if (select == INPUT_CSC_SELECT_ICSC) {
 
-		dpp_cm_program_color_registers(
-				xfm,
+		gam_regs.csc_c11_c12 = REG(CM_ICSC_C11_C12);
+		gam_regs.csc_c33_c34 = REG(CM_ICSC_C33_C34);
+
+		cm_helper_program_color_matrices(
+				xfm->base.ctx,
 				regval,
-				REG(CM_ICSC_C11_C12),
-				REG(CM_ICSC_C33_C34));
+				&gam_regs);
 	} else {
 
-		dpp_cm_program_color_registers(
-				xfm,
+		gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12);
+		gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34);
+
+		cm_helper_program_color_matrices(
+				xfm->base.ctx,
 				regval,
-				REG(CM_COMA_C11_C12),
-				REG(CM_COMA_C33_C34));
+				&gam_regs);
 	}
 }
 
@@ -590,7 +536,9 @@ void ippn10_program_degamma_lutb_settings(
 		const struct pwl_params *params)
 {
 	struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base);
-	struct cm_gam_ram_reg gam_regs;
+	struct xfer_func_reg gam_regs;
+
+	dcn10_dpp_cm_get_reg_field(xfm, &gam_regs);
 
 	gam_regs.start_cntl_b = REG(CM_DGAM_RAMB_START_CNTL_B);
 	gam_regs.start_cntl_g = REG(CM_DGAM_RAMB_START_CNTL_G);
@@ -607,7 +555,8 @@ void ippn10_program_degamma_lutb_settings(
 	gam_regs.region_start = REG(CM_DGAM_RAMB_REGION_0_1);
 	gam_regs.region_end = REG(CM_DGAM_RAMB_REGION_14_15);
 
-	dpp_cm_program_region_lut(xfm_base, params, &gam_regs);
+
+	cm_helper_program_xfer_func(xfm->base.ctx, params, &gam_regs);
 }
 
 /*program de gamma RAM A*/
@@ -616,7 +565,9 @@ void ippn10_program_degamma_luta_settings(
 		const struct pwl_params *params)
 {
 	struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base);
-	struct cm_gam_ram_reg gam_regs;
+	struct xfer_func_reg gam_regs;
+
+	dcn10_dpp_cm_get_reg_field(xfm, &gam_regs);
 
 	gam_regs.start_cntl_b = REG(CM_DGAM_RAMA_START_CNTL_B);
 	gam_regs.start_cntl_g = REG(CM_DGAM_RAMA_START_CNTL_G);
@@ -633,7 +584,7 @@ void ippn10_program_degamma_luta_settings(
 	gam_regs.region_start = REG(CM_DGAM_RAMA_REGION_0_1);
 	gam_regs.region_end = REG(CM_DGAM_RAMA_REGION_14_15);
 
-	dpp_cm_program_region_lut(xfm_base, params, &gam_regs);
+	cm_helper_program_xfer_func(xfm->base.ctx, params, &gam_regs);
 }
 
 void ippn10_power_on_degamma_lut(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm_helper.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm_helper.c
new file mode 100644
index 000000000000..f616e08759de
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm_helper.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "reg_helper.h"
+#include "dcn10_dpp.h"
+
+#include "dcn10_dpp_cm_helper.h"
+
+#define REG(reg) reg
+
+#define CTX \
+	ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+	reg->shifts.field_name, reg->masks.field_name
+
+void cm_helper_program_color_matrices(
+		struct dc_context *ctx,
+		const uint16_t *regval,
+		const struct color_matrices_reg *reg)
+{
+	uint32_t cur_csc_reg;
+	unsigned int i = 0;
+
+	for (cur_csc_reg = reg->csc_c11_c12;
+			cur_csc_reg <= reg->csc_c33_c34;
+			cur_csc_reg++) {
+
+		const uint16_t *regval0 = &(regval[2 * i]);
+		const uint16_t *regval1 = &(regval[(2 * i) + 1]);
+
+		REG_SET_2(cur_csc_reg, 0,
+				csc_c11, *regval0,
+				csc_c12, *regval1);
+
+		i++;
+	}
+
+}
+
+void cm_helper_program_xfer_func(
+		struct dc_context *ctx,
+		const struct pwl_params *params,
+		const struct xfer_func_reg *reg)
+{
+	uint32_t reg_region_cur;
+	unsigned int i = 0;
+
+	REG_SET_2(reg->start_cntl_b, 0,
+			exp_region_start, params->arr_points[0].custom_float_x,
+			exp_resion_start_segment, 0);
+	REG_SET_2(reg->start_cntl_g, 0,
+			exp_region_start, params->arr_points[0].custom_float_x,
+			exp_resion_start_segment, 0);
+	REG_SET_2(reg->start_cntl_r, 0,
+			exp_region_start, params->arr_points[0].custom_float_x,
+			exp_resion_start_segment, 0);
+
+	REG_SET(reg->start_slope_cntl_b, 0,
+			field_region_linear_slope, params->arr_points[0].custom_float_slope);
+	REG_SET(reg->start_slope_cntl_g, 0,
+			field_region_linear_slope, params->arr_points[0].custom_float_slope);
+	REG_SET(reg->start_slope_cntl_r, 0,
+			field_region_linear_slope, params->arr_points[0].custom_float_slope);
+
+	REG_SET(reg->start_end_cntl1_b, 0,
+			field_region_end, params->arr_points[1].custom_float_x);
+	REG_SET_2(reg->start_end_cntl2_b, 0,
+			field_region_end_slope, params->arr_points[1].custom_float_slope,
+			field_region_end_base, params->arr_points[1].custom_float_y);
+
+	REG_SET(reg->start_end_cntl1_g, 0,
+			field_region_end, params->arr_points[1].custom_float_x);
+	REG_SET_2(reg->start_end_cntl2_g, 0,
+			field_region_end_slope, params->arr_points[1].custom_float_slope,
+		field_region_end_base, params->arr_points[1].custom_float_y);
+
+	REG_SET(reg->start_end_cntl1_r, 0,
+			field_region_end, params->arr_points[1].custom_float_x);
+	REG_SET_2(reg->start_end_cntl2_r, 0,
+			field_region_end_slope, params->arr_points[1].custom_float_slope,
+		field_region_end_base, params->arr_points[1].custom_float_y);
+
+	for (reg_region_cur = reg->region_start;
+			reg_region_cur <= reg->region_end;
+			reg_region_cur++) {
+
+		const struct gamma_curve *curve0 = &(params->arr_curve_points[2 * i]);
+		const struct gamma_curve *curve1 = &(params->arr_curve_points[(2 * i) + 1]);
+
+		REG_SET_4(reg_region_cur, 0,
+				exp_region0_lut_offset, curve0->offset,
+				exp_region0_num_segments, curve0->segments_num,
+				exp_region1_lut_offset, curve1->offset,
+				exp_region1_num_segments, curve1->segments_num);
+
+		i++;
+	}
+
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm_helper.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm_helper.h
new file mode 100644
index 000000000000..1155ee522898
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm_helper.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_DPP_DCN10_CM_HELPER_H__
+#define __DAL_DPP_DCN10_CM_HELPER_H__
+
+#define TF_HELPER_REG_FIELD_LIST(type) \
+	type exp_region0_lut_offset; \
+	type exp_region0_num_segments; \
+	type exp_region1_lut_offset; \
+	type exp_region1_num_segments;\
+	type field_region_end;\
+	type field_region_end_slope;\
+	type field_region_end_base;\
+	type exp_region_start;\
+	type exp_resion_start_segment;\
+	type field_region_linear_slope
+
+#define TF_CM_REG_FIELD_LIST(type) \
+	type csc_c11; \
+	type csc_c12
+
+struct xfer_func_shift {
+	TF_HELPER_REG_FIELD_LIST(uint8_t);
+};
+
+struct xfer_func_mask {
+	TF_HELPER_REG_FIELD_LIST(uint32_t);
+};
+
+struct xfer_func_reg {
+	struct xfer_func_shift shifts;
+	struct xfer_func_mask masks;
+
+	uint32_t start_cntl_b;
+	uint32_t start_cntl_g;
+	uint32_t start_cntl_r;
+	uint32_t start_slope_cntl_b;
+	uint32_t start_slope_cntl_g;
+	uint32_t start_slope_cntl_r;
+	uint32_t start_end_cntl1_b;
+	uint32_t start_end_cntl2_b;
+	uint32_t start_end_cntl1_g;
+	uint32_t start_end_cntl2_g;
+	uint32_t start_end_cntl1_r;
+	uint32_t start_end_cntl2_r;
+	uint32_t region_start;
+	uint32_t region_end;
+};
+
+struct cm_color_matrix_shift {
+	TF_CM_REG_FIELD_LIST(uint8_t);
+};
+
+struct cm_color_matrix_mask {
+	TF_CM_REG_FIELD_LIST(uint32_t);
+};
+
+struct color_matrices_reg{
+	struct cm_color_matrix_shift shifts;
+	struct cm_color_matrix_mask masks;
+
+	uint32_t csc_c11_c12;
+	uint32_t csc_c33_c34;
+};
+
+void cm_helper_program_color_matrices(
+		struct dc_context *ctx,
+		const uint16_t *regval,
+		const struct color_matrices_reg *reg);
+
+void cm_helper_program_xfer_func(
+		struct dc_context *ctx,
+		const struct pwl_params *params,
+		const struct xfer_func_reg *reg);
+
+#endif
-- 
2.11.0

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[PATCH 14/28] drm/amd/display: Don't reset clock source at unref

[Harry Wentland]

Powering down the clock source during unref is unsafe as we might want
to unref during atomic_check

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  | 25 ++++++++++++++--------
 .../amd/display/dc/dce110/dce110_hw_sequencer.c    | 16 +++++++++-----
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  9 +++++---
 drivers/gpu/drm/amd/display/dc/inc/resource.h      |  4 ++--
 4 files changed, 35 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 3eba2e55639b..bc0cf87216dd 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -261,31 +261,34 @@ bool resource_construct(
 }
 
 
-void resource_unreference_clock_source(
+bool resource_unreference_clock_source(
 		struct resource_context *res_ctx,
 		const struct resource_pool *pool,
-		struct clock_source **clock_source)
+		struct clock_source *clock_source)
 {
 	int i;
+	bool need_reset = false;
+
 	for (i = 0; i < pool->clk_src_count; i++) {
-		if (pool->clock_sources[i] != *clock_source)
+		if (pool->clock_sources[i] != clock_source)
 			continue;
 
 		res_ctx->clock_source_ref_count[i]--;
 
 		if (res_ctx->clock_source_ref_count[i] == 0)
-			(*clock_source)->funcs->cs_power_down(*clock_source);
+			need_reset = true;
 
 		break;
 	}
 
-	if (pool->dp_clock_source == *clock_source) {
+	if (pool->dp_clock_source == clock_source) {
 		res_ctx->dp_clock_source_ref_count--;
 
 		if (res_ctx->dp_clock_source_ref_count == 0)
-			(*clock_source)->funcs->cs_power_down(*clock_source);
+			need_reset = true;
 	}
-	*clock_source = NULL;
+
+	return need_reset;
 }
 
 void resource_reference_clock_source(
@@ -1756,10 +1759,14 @@ bool dc_validate_global_state(
 			if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
 				!find_pll_sharable_stream(stream, new_ctx)) {
 
-				resource_unreference_clock_source(
+				if (resource_unreference_clock_source(
 						&new_ctx->res_ctx,
 						dc->res_pool,
-						&pipe_ctx->clock_source);
+						pipe_ctx->clock_source)) {
+					pipe_ctx->clock_source->funcs->cs_power_down(pipe_ctx->clock_source);
+					pipe_ctx->clock_source = NULL;
+				}
+
 				pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
 				resource_reference_clock_source(
 						&new_ctx->res_ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index b36220bc619d..75c636cba545 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1362,9 +1362,12 @@ static void switch_dp_clock_sources(
 
 			if (clk_src &&
 				clk_src != pipe_ctx->clock_source) {
-				resource_unreference_clock_source(
-					res_ctx, dc->res_pool,
-					&pipe_ctx->clock_source);
+				if (resource_unreference_clock_source(res_ctx,
+				    dc->res_pool, pipe_ctx->clock_source)) {
+					pipe_ctx->clock_source->funcs->cs_power_down(pipe_ctx->clock_source);
+					pipe_ctx->clock_source = NULL;
+				}
+
 				pipe_ctx->clock_source = clk_src;
 				resource_reference_clock_source(
 						res_ctx, dc->res_pool, clk_src);
@@ -1680,9 +1683,12 @@ static void dce110_reset_hw_ctx_wrap(
 			pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
 			pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
 					pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
-			resource_unreference_clock_source(
+			if (resource_unreference_clock_source(
 					&dc->current_state->res_ctx, dc->res_pool,
-					&pipe_ctx_old->clock_source);
+					pipe_ctx_old->clock_source)) {
+				pipe_ctx_old->clock_source->funcs->cs_power_down(pipe_ctx_old->clock_source);
+				pipe_ctx_old->clock_source = NULL;
+			}
 
 			dc->hwss.power_down_front_end(dc, pipe_ctx_old->pipe_idx);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 6b76fc417456..7460560fbefc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1045,9 +1045,12 @@ static void reset_back_end_for_pipe(
 	}
 
 	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
-		resource_unreference_clock_source(
-			&context->res_ctx, dc->res_pool,
-			&pipe_ctx->clock_source);
+		if (resource_unreference_clock_source(&context->res_ctx,
+		    dc->res_pool, pipe_ctx->clock_source)) {
+			pipe_ctx->clock_source->funcs->cs_power_down(pipe_ctx->clock_source);
+			pipe_ctx->clock_source = NULL;
+		}
+
 
 	for (i = 0; i < dc->res_pool->pipe_count; i++)
 		if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h
index 41437da5fb9b..cf1797c191e9 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
@@ -92,10 +92,10 @@ enum dc_status resource_build_scaling_params_for_context(
 
 void resource_build_info_frame(struct pipe_ctx *pipe_ctx);
 
-void resource_unreference_clock_source(
+bool resource_unreference_clock_source(
 		struct resource_context *res_ctx,
 		const struct resource_pool *pool,
-		struct clock_source **clock_source);
+		struct clock_source *clock_source);
 
 void resource_reference_clock_source(
 		struct resource_context *res_ctx,
-- 
2.11.0

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[PATCH 15/28] drm/amd/display: Power down clock source at commit

[Harry Wentland]

Still one more in dc_validate_global

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  | 19 ++++++++++-------
 .../amd/display/dc/dce110/dce110_hw_sequencer.c    | 22 ++++++++++++++------
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 24 ++++++++++++++--------
 drivers/gpu/drm/amd/display/dc/inc/core_types.h    |  2 ++
 4 files changed, 46 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index bc0cf87216dd..b17e1f60d34f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -275,8 +275,10 @@ bool resource_unreference_clock_source(
 
 		res_ctx->clock_source_ref_count[i]--;
 
-		if (res_ctx->clock_source_ref_count[i] == 0)
+		if (res_ctx->clock_source_ref_count[i] == 0) {
+			res_ctx->clock_source_changed[i] = true;
 			need_reset = true;
+		}
 
 		break;
 	}
@@ -284,8 +286,10 @@ bool resource_unreference_clock_source(
 	if (pool->dp_clock_source == clock_source) {
 		res_ctx->dp_clock_source_ref_count--;
 
-		if (res_ctx->dp_clock_source_ref_count == 0)
+		if (res_ctx->dp_clock_source_ref_count == 0) {
+			res_ctx->dp_clock_source_changed = true;
 			need_reset = true;
+		}
 	}
 
 	return need_reset;
@@ -1502,6 +1506,10 @@ bool dc_remove_stream_from_ctx(
 					del_pipe->stream_res.audio,
 					false);
 
+			resource_unreference_clock_source(&new_ctx->res_ctx,
+							  dc->res_pool,
+							  del_pipe->clock_source);
+
 			memset(del_pipe, 0, sizeof(*del_pipe));
 
 			break;
@@ -1759,13 +1767,10 @@ bool dc_validate_global_state(
 			if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
 				!find_pll_sharable_stream(stream, new_ctx)) {
 
-				if (resource_unreference_clock_source(
+				resource_unreference_clock_source(
 						&new_ctx->res_ctx,
 						dc->res_pool,
-						pipe_ctx->clock_source)) {
-					pipe_ctx->clock_source->funcs->cs_power_down(pipe_ctx->clock_source);
-					pipe_ctx->clock_source = NULL;
-				}
+						pipe_ctx->clock_source);
 
 				pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
 				resource_reference_clock_source(
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 75c636cba545..96db166b7fba 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1683,18 +1683,28 @@ static void dce110_reset_hw_ctx_wrap(
 			pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
 			pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
 					pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
-			if (resource_unreference_clock_source(
-					&dc->current_state->res_ctx, dc->res_pool,
-					pipe_ctx_old->clock_source)) {
-				pipe_ctx_old->clock_source->funcs->cs_power_down(pipe_ctx_old->clock_source);
-				pipe_ctx_old->clock_source = NULL;
-			}
 
 			dc->hwss.power_down_front_end(dc, pipe_ctx_old->pipe_idx);
 
 			pipe_ctx_old->stream = NULL;
 		}
 	}
+
+	/* power down changed clock sources */
+	for (i = 0; i < dc->res_pool->clk_src_count; i++)
+		if (context->res_ctx.clock_source_changed[i]) {
+			struct clock_source *clk = dc->res_pool->clock_sources[i];
+
+			clk->funcs->cs_power_down(clk);
+			context->res_ctx.clock_source_changed[i] = false;
+		}
+
+	if (context->res_ctx.dp_clock_source_changed) {
+		struct clock_source *clk = dc->res_pool->dp_clock_source;
+
+		clk->funcs->cs_power_down(clk);
+		context->res_ctx.clock_source_changed[i] = false;
+	}
 }
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 7460560fbefc..a1f4a00e5e04 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1044,14 +1044,6 @@ static void reset_back_end_for_pipe(
 		pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
 	}
 
-	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
-		if (resource_unreference_clock_source(&context->res_ctx,
-		    dc->res_pool, pipe_ctx->clock_source)) {
-			pipe_ctx->clock_source->funcs->cs_power_down(pipe_ctx->clock_source);
-			pipe_ctx->clock_source = NULL;
-		}
-
-
 	for (i = 0; i < dc->res_pool->pipe_count; i++)
 		if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
 			break;
@@ -1273,6 +1265,22 @@ static void reset_hw_ctx_wrap(
 			plane_atomic_power_down(dc, i);
 	}
 
+	/* power down changed clock sources */
+	for (i = 0; i < dc->res_pool->clk_src_count; i++)
+		if (context->res_ctx.clock_source_changed[i]) {
+			struct clock_source *clk = dc->res_pool->clock_sources[i];
+
+			clk->funcs->cs_power_down(clk);
+			context->res_ctx.clock_source_changed[i] = false;
+		}
+
+	if (context->res_ctx.dp_clock_source_changed) {
+		struct clock_source *clk = dc->res_pool->dp_clock_source;
+
+		clk->funcs->cs_power_down(clk);
+		context->res_ctx.dp_clock_source_changed = false;
+	}
+
 	/* Reset Back End*/
 	for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
 		struct pipe_ctx *pipe_ctx_old =
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 915d5c10361b..b6a513d6feda 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -213,7 +213,9 @@ struct resource_context {
 	bool is_stream_enc_acquired[MAX_PIPES * 2];
 	bool is_audio_acquired[MAX_PIPES];
 	uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];
+	bool clock_source_changed[MAX_CLOCK_SOURCES];
 	uint8_t dp_clock_source_ref_count;
+	bool dp_clock_source_changed;
 };
 
 struct dce_bw_output {
-- 
2.11.0

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[PATCH 16/28] drm/amd/display: Remove switching of clk sources at end of commit

[Harry Wentland]

This should be taken care of in validate now.

All of timing sync is quite broken at the moment anyways. Will submit
another patch set to address that.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 .../amd/display/dc/dce110/dce110_hw_sequencer.c    | 36 ----------------------
 1 file changed, 36 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 96db166b7fba..c57dc45d6677 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1344,40 +1344,6 @@ static void set_safe_displaymarks(
 	}
 }
 
-static void switch_dp_clock_sources(
-	const struct dc *dc,
-	struct resource_context *res_ctx)
-{
-	uint8_t i;
-	for (i = 0; i < MAX_PIPES; i++) {
-		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
-
-		if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
-			continue;
-
-		if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
-			struct clock_source *clk_src =
-				resource_find_used_clk_src_for_sharing(
-						res_ctx, pipe_ctx);
-
-			if (clk_src &&
-				clk_src != pipe_ctx->clock_source) {
-				if (resource_unreference_clock_source(res_ctx,
-				    dc->res_pool, pipe_ctx->clock_source)) {
-					pipe_ctx->clock_source->funcs->cs_power_down(pipe_ctx->clock_source);
-					pipe_ctx->clock_source = NULL;
-				}
-
-				pipe_ctx->clock_source = clk_src;
-				resource_reference_clock_source(
-						res_ctx, dc->res_pool, clk_src);
-
-				dce_crtc_switch_to_clk_src(dc->hwseq, clk_src, i);
-			}
-		}
-	}
-}
-
 /*******************************************************************************
  * Public functions
  ******************************************************************************/
@@ -1939,8 +1905,6 @@ enum dc_status dce110_apply_ctx_to_hw(
 
 	dcb->funcs->set_scratch_critical_state(dcb, false);
 
-	switch_dp_clock_sources(dc, &context->res_ctx);
-
 #ifdef ENABLE_FBC
 	if (dc->fbc_compressor)
 		enable_fbc(dc, context);
-- 
2.11.0

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[PATCH 17/28] drm/amd/display: remove output_format from ipp_setup

[Harry Wentland]

From: Eric Bernstein <eric.bernstein@amd.com>

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c          | 3 +--
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h          | 3 +--
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c       | 4 ++--
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 +--
 drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h               | 3 +--
 drivers/gpu/drm/amd/display/dc/inc/hw/transform.h         | 3 +--
 6 files changed, 7 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index 99caafb27b37..487694125ea4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -266,8 +266,7 @@ static void ippn10_set_degamma_format_float(
 void ippn10_cnv_setup (
 		struct transform *xfm_base,
 		enum surface_pixel_format input_format,
-		enum expansion_mode mode,
-		enum ipp_output_format cnv_out_format)
+		enum expansion_mode mode)
 {
 	uint32_t pixel_format;
 	uint32_t alpha_en;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
index 70d6ba09501b..34e501979b55 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -1358,8 +1358,7 @@ void dcn10_dpp_dscl_set_scaler_manual_scale(
 void ippn10_cnv_setup (
 		struct transform *xfm_base,
 		enum surface_pixel_format input_format,
-		enum expansion_mode mode,
-		enum ipp_output_format cnv_out_format);
+		enum expansion_mode mode);
 
 void ippn10_full_bypass(struct transform *xfm_base);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
index 840dd0346782..d0e72acfc1d5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
@@ -727,11 +727,11 @@ void ippn10_full_bypass(struct transform *xfm_base)
 			FORMAT_EXPANSION_MODE, 0);
 
 	/* COLOR_KEYER_CONTROL.COLOR_KEYER_EN = 0 this should be default */
-	REG_SET(CM_CONTROL, 0, CM_BYPASS_EN, 1);
+	if (xfm->tf_mask->CM_BYPASS_EN)
+		REG_SET(CM_CONTROL, 0, CM_BYPASS_EN, 1);
 
 	/* Setting degamma bypass for now */
 	REG_SET(CM_DGAM_CONTROL, 0, CM_DGAM_LUT_MODE, 0);
-	REG_SET(CM_IGAM_CONTROL, 0, CM_IGAM_LUT_MODE, 0);
 }
 
 static bool ippn10_ingamma_ram_inuse(struct transform *xfm_base,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index a1f4a00e5e04..6fee6957c1a6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2316,8 +2316,7 @@ static void update_dchubp_dpp(
 
 	xfm->funcs->ipp_setup(xfm,
 			plane_state->format,
-			1,
-			IPP_OUTPUT_FORMAT_12_BIT_FIX);
+			EXPANSION_MODE_ZERO);
 
 	mpcc_cfg.mi = mi;
 	mpcc_cfg.opp = pipe_ctx->stream_res.opp;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h
index 7ebfdc1c19c1..f11aa484f46e 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h
@@ -86,8 +86,7 @@ struct ipp_funcs {
 	void (*ipp_setup)(
 		struct input_pixel_processor *ipp,
 		enum surface_pixel_format input_format,
-		enum expansion_mode mode,
-		enum ipp_output_format output_format);
+		enum expansion_mode mode);
 
 	/* DCE function to setup IPP.  TODO: see if we can consolidate to setup */
 	void (*ipp_program_prescale)(
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
index 623042d2c272..32947450e702 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
@@ -234,8 +234,7 @@ struct transform_funcs {
 	void (*ipp_setup)(
 			struct transform *xfm_base,
 			enum surface_pixel_format input_format,
-			enum expansion_mode mode,
-			enum ipp_output_format cnv_out_format);
+			enum expansion_mode mode);
 
 	void (*ipp_full_bypass)(struct transform *xfm_base);
 
-- 
2.11.0

_______________________________________________
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amd-gfx@lists.freedesktop.org
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[PATCH 18/28] drm/amd/display: move dwb registers to header file

[Harry Wentland]

From: Yue Hin Lau <Yuehin.Lau@amd.com>

Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c   | 288 +--------------------
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h   | 247 +++++++++++++++++-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |  42 +++
 3 files changed, 289 insertions(+), 288 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
index 684241cb40d7..4ec5554f0f5b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
@@ -29,32 +29,7 @@
 #include "resource.h"
 #include "dwb.h"
 #include "dcn10_dwb.h"
-#include "vega10/soc15ip.h"
-#include "raven1/DCN/dcn_1_0_offset.h"
-#include "raven1/DCN/dcn_1_0_sh_mask.h"
 
-/* DCN */
-#define BASE_INNER(seg) \
-	DCE_BASE__INST0_SEG ## seg
-
-#define BASE(seg) \
-	BASE_INNER(seg)
-
-#define SR(reg_name)\
-		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
-					mm ## reg_name
-
-#define SRI(reg_name, block, id)\
-	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
-					mm ## block ## id ## _ ## reg_name
-
-
-#define SRII(reg_name, block, id)\
-	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
-					mm ## block ## id ## _ ## reg_name
-
-#define SF(reg_name, field_name, post_fix)\
-	.field_name = reg_name ## __ ## field_name ## post_fix
 
 #define REG(reg)\
 	dwbc10->dwbc_regs->reg
@@ -69,240 +44,6 @@
 #define TO_DCN10_DWBC(dwbc_base) \
 	container_of(dwbc_base, struct dcn10_dwbc, base)
 
-#define DWBC_COMMON_REG_LIST_DCN1_0(inst) \
-	SRI(WB_ENABLE, CNV, inst),\
-	SRI(WB_EC_CONFIG, CNV, inst),\
-	SRI(CNV_MODE, CNV, inst),\
-	SRI(WB_SOFT_RESET, CNV, inst),\
-	SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
-	SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\
-	SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
-	SRI(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MCIF_WB, inst),\
-	SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\
-	SRI(MCIF_WB_WATERMARK, MCIF_WB, inst),\
-	SRI(MCIF_WB_WARM_UP_CNTL, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst),\
-	.DWB_SOURCE_SELECT = mmDWB_SOURCE_SELECT\
-
-#define DWBC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh) \
-	SF(CNV0_WB_ENABLE, WB_ENABLE, mask_sh),\
-	SF(CNV0_WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
-	SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
-	SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
-	SF(CNV0_WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
-	SF(CNV0_WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
-	SF(CNV0_CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\
-	SF(CNV0_CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
-	SF(CNV0_CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\
-	SF(CNV0_CNV_MODE, CNV_EYE_SELECTION, mask_sh),\
-	SF(CNV0_CNV_MODE, CNV_STEREO_POLARITY, mask_sh),\
-	SF(CNV0_CNV_MODE, CNV_INTERLACED_FIELD_ORDER, mask_sh),\
-	SF(CNV0_CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\
-	SF(CNV0_CNV_MODE, CNV_NEW_CONTENT, mask_sh),\
-	SF(CNV0_CNV_MODE, CNV_FRAME_CAPTURE_EN, mask_sh),\
-	SF(CNV0_WB_SOFT_RESET, WB_SOFT_RESET, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_DUALSIZE_REQ, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_CHROMA_PITCH, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, WM_CHANGE_ACK_FORCE_ON, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB_BUF_2_ADDR_C_OFFSET, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB_BUF_4_ADDR_C_OFFSET, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK_IGNORE, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_ACK, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_FORCE_ON, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_ALLOW_FOR_URGENT, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_WARM_UP_CNTL, MCIF_WB_PITCH_SIZE_WARMUP, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, mask_sh),\
-	SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
-	SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh)
-
-#define DWBC_REG_FIELD_LIST(type) \
-	type WB_ENABLE;\
-	type DISPCLK_R_WB_GATE_DIS;\
-	type DISPCLK_G_WB_GATE_DIS;\
-	type DISPCLK_G_WBSCL_GATE_DIS;\
-	type WB_LB_LS_DIS;\
-	type WB_LB_SD_DIS;\
-	type WB_LUT_LS_DIS;\
-	type CNV_WINDOW_CROP_EN;\
-	type CNV_STEREO_TYPE;\
-	type CNV_INTERLACED_MODE;\
-	type CNV_EYE_SELECTION;\
-	type CNV_STEREO_POLARITY;\
-	type CNV_INTERLACED_FIELD_ORDER;\
-	type CNV_STEREO_SPLIT;\
-	type CNV_NEW_CONTENT;\
-	type CNV_FRAME_CAPTURE_EN;\
-	type WB_SOFT_RESET;\
-	type MCIF_WB_BUFMGR_ENABLE;\
-	type MCIF_WB_BUF_DUALSIZE_REQ;\
-	type MCIF_WB_BUFMGR_SW_INT_EN;\
-	type MCIF_WB_BUFMGR_SW_INT_ACK;\
-	type MCIF_WB_BUFMGR_SW_SLICE_INT_EN;\
-	type MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN;\
-	type MCIF_WB_BUFMGR_SW_LOCK;\
-	type MCIF_WB_P_VMID;\
-	type MCIF_WB_BUF_ADDR_FENCE_EN;\
-	type MCIF_WB_BUF_LUMA_PITCH;\
-	type MCIF_WB_BUF_CHROMA_PITCH;\
-	type MCIF_WB_CLIENT_ARBITRATION_SLICE;\
-	type MCIF_WB_TIME_PER_PIXEL;\
-	type WM_CHANGE_ACK_FORCE_ON;\
-	type MCIF_WB_CLI_WATERMARK_MASK;\
-	type MCIF_WB_BUF_1_ADDR_Y;\
-	type MCIF_WB_BUF_1_ADDR_Y_OFFSET;\
-	type MCIF_WB_BUF_1_ADDR_C;\
-	type MCIF_WB_BUF_1_ADDR_C_OFFSET;\
-	type MCIF_WB_BUF_2_ADDR_Y;\
-	type MCIF_WB_BUF_2_ADDR_Y_OFFSET;\
-	type MCIF_WB_BUF_2_ADDR_C;\
-	type MCIF_WB_BUF_2_ADDR_C_OFFSET;\
-	type MCIF_WB_BUF_3_ADDR_Y;\
-	type MCIF_WB_BUF_3_ADDR_Y_OFFSET;\
-	type MCIF_WB_BUF_3_ADDR_C;\
-	type MCIF_WB_BUF_3_ADDR_C_OFFSET;\
-	type MCIF_WB_BUF_4_ADDR_Y;\
-	type MCIF_WB_BUF_4_ADDR_Y_OFFSET;\
-	type MCIF_WB_BUF_4_ADDR_C;\
-	type MCIF_WB_BUF_4_ADDR_C_OFFSET;\
-	type MCIF_WB_BUFMGR_VCE_LOCK_IGNORE;\
-	type MCIF_WB_BUFMGR_VCE_INT_EN;\
-	type MCIF_WB_BUFMGR_VCE_INT_ACK;\
-	type MCIF_WB_BUFMGR_VCE_SLICE_INT_EN;\
-	type MCIF_WB_BUFMGR_VCE_LOCK;\
-	type MCIF_WB_BUFMGR_SLICE_SIZE;\
-	type NB_PSTATE_CHANGE_REFRESH_WATERMARK;\
-	type NB_PSTATE_CHANGE_URGENT_DURING_REQUEST;\
-	type NB_PSTATE_CHANGE_FORCE_ON;\
-	type NB_PSTATE_ALLOW_FOR_URGENT;\
-	type NB_PSTATE_CHANGE_WATERMARK_MASK;\
-	type MCIF_WB_CLI_WATERMARK;\
-	type MCIF_WB_CLI_CLOCK_GATER_OVERRIDE;\
-	type MCIF_WB_PITCH_SIZE_WARMUP;\
-	type MCIF_WB_BUF_LUMA_SIZE;\
-	type MCIF_WB_BUF_CHROMA_SIZE;\
-	type OPTC_DWB0_SOURCE_SELECT;\
-	type OPTC_DWB1_SOURCE_SELECT;\
-
-struct dcn10_dwbc_registers {
-	uint32_t WB_ENABLE;
-	uint32_t WB_EC_CONFIG;
-	uint32_t CNV_MODE;
-	uint32_t WB_SOFT_RESET;
-	uint32_t MCIF_WB_BUFMGR_SW_CONTROL;
-	uint32_t MCIF_WB_BUF_PITCH;
-	uint32_t MCIF_WB_ARBITRATION_CONTROL;
-	uint32_t MCIF_WB_SCLK_CHANGE;
-	uint32_t MCIF_WB_BUF_1_ADDR_Y;
-	uint32_t MCIF_WB_BUF_1_ADDR_Y_OFFSET;
-	uint32_t MCIF_WB_BUF_1_ADDR_C;
-	uint32_t MCIF_WB_BUF_1_ADDR_C_OFFSET;
-	uint32_t MCIF_WB_BUF_2_ADDR_Y;
-	uint32_t MCIF_WB_BUF_2_ADDR_Y_OFFSET;
-	uint32_t MCIF_WB_BUF_2_ADDR_C;
-	uint32_t MCIF_WB_BUF_2_ADDR_C_OFFSET;
-	uint32_t MCIF_WB_BUF_3_ADDR_Y;
-	uint32_t MCIF_WB_BUF_3_ADDR_Y_OFFSET;
-	uint32_t MCIF_WB_BUF_3_ADDR_C;
-	uint32_t MCIF_WB_BUF_3_ADDR_C_OFFSET;
-	uint32_t MCIF_WB_BUF_4_ADDR_Y;
-	uint32_t MCIF_WB_BUF_4_ADDR_Y_OFFSET;
-	uint32_t MCIF_WB_BUF_4_ADDR_C;
-	uint32_t MCIF_WB_BUF_4_ADDR_C_OFFSET;
-	uint32_t MCIF_WB_BUFMGR_VCE_CONTROL;
-	uint32_t MCIF_WB_NB_PSTATE_LATENCY_WATERMARK;
-	uint32_t MCIF_WB_NB_PSTATE_CONTROL;
-	uint32_t MCIF_WB_WATERMARK;
-	uint32_t MCIF_WB_WARM_UP_CNTL;
-	uint32_t MCIF_WB_BUF_LUMA_SIZE;
-	uint32_t MCIF_WB_BUF_CHROMA_SIZE;
-	uint32_t DWB_SOURCE_SELECT;
-};
-struct dcn10_dwbc_mask {
-	DWBC_REG_FIELD_LIST(uint32_t)
-};
-struct dcn10_dwbc_shift {
-	DWBC_REG_FIELD_LIST(uint8_t)
-};
-struct dcn10_dwbc {
-	struct dwbc base;
-	const struct dcn10_dwbc_registers *dwbc_regs;
-	const struct dcn10_dwbc_shift *dwbc_shift;
-	const struct dcn10_dwbc_mask *dwbc_mask;
-};
-
-#define dwbc_regs(id)\
-[id] = {\
-	DWBC_COMMON_REG_LIST_DCN1_0(id),\
-}
-
-static const struct dcn10_dwbc_registers dwbc10_regs[] = {
-	dwbc_regs(0),
-	dwbc_regs(1),
-};
-
-static const struct dcn10_dwbc_shift dwbc10_shift = {
-	DWBC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
-};
-
-static const struct dcn10_dwbc_mask dwbc10_mask = {
-	DWBC_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
-};
-
-
 static bool get_caps(struct dwbc *dwbc, struct dwb_caps *caps)
 {
 	if (caps) {
@@ -603,7 +344,7 @@ const struct dwbc_funcs dcn10_dwbc_funcs = {
 	.reset_advanced_settings = reset_advanced_settings,
 };
 
-static void dcn10_dwbc_construct(struct dcn10_dwbc *dwbc10,
+void dcn10_dwbc_construct(struct dcn10_dwbc *dwbc10,
 						  struct dc_context *ctx,
 						  const struct dcn10_dwbc_registers *dwbc_regs,
 						  const struct dcn10_dwbc_shift *dwbc_shift,
@@ -620,32 +361,5 @@ static void dcn10_dwbc_construct(struct dcn10_dwbc *dwbc10,
 	dwbc10->dwbc_mask = dwbc_mask;
 }
 
-bool dcn10_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
-{
-	int i;
-	uint32_t pipe_count = pool->res_cap->num_dwb;
-
-	ASSERT(pipe_count > 0);
 
-	for (i = 0; i < pipe_count; i++) {
-		struct dcn10_dwbc *dwbc10 = dm_alloc(sizeof(struct dcn10_dwbc));
-
-		if (!dwbc10)
-			return false;
-
-		dcn10_dwbc_construct(dwbc10, ctx,
-				&dwbc10_regs[i],
-				&dwbc10_shift,
-				&dwbc10_mask,
-				i);
-
-		pool->dwbc[i] = &dwbc10->base;
-		if (pool->dwbc[i] == NULL) {
-			BREAK_TO_DEBUGGER();
-			dm_error("DC: failed to create dwbc10!\n");
-			return false;
-		}
-	}
-	return true;
-}
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
index cf530aed4e1c..1fdc2be42fa9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
@@ -26,7 +26,252 @@
 
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 
-bool dcn10_dwbc_create(struct dc_context *ctx, struct resource_pool *pool);
+/* DCN */
+#define BASE_INNER(seg) \
+	DCE_BASE__INST0_SEG ## seg
+
+#define BASE(seg) \
+	BASE_INNER(seg)
+
+#define SR(reg_name)\
+		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
+					mm ## reg_name
+
+#define SRI(reg_name, block, id)\
+	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					mm ## block ## id ## _ ## reg_name
+
+
+#define SRII(reg_name, block, id)\
+	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					mm ## block ## id ## _ ## reg_name
+
+#define SF(reg_name, field_name, post_fix)\
+	.field_name = reg_name ## __ ## field_name ## post_fix
+
+
+#define DWBC_COMMON_REG_LIST_DCN1_0(inst) \
+	SRI(WB_ENABLE, CNV, inst),\
+	SRI(WB_EC_CONFIG, CNV, inst),\
+	SRI(CNV_MODE, CNV, inst),\
+	SRI(WB_SOFT_RESET, CNV, inst),\
+	SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
+	SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\
+	SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
+	SRI(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MCIF_WB, inst),\
+	SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\
+	SRI(MCIF_WB_WATERMARK, MCIF_WB, inst),\
+	SRI(MCIF_WB_WARM_UP_CNTL, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst),\
+	.DWB_SOURCE_SELECT = mmDWB_SOURCE_SELECT\
+
+#define DWBC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh) \
+	SF(CNV0_WB_ENABLE, WB_ENABLE, mask_sh),\
+	SF(CNV0_WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
+	SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
+	SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
+	SF(CNV0_WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
+	SF(CNV0_WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
+	SF(CNV0_CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\
+	SF(CNV0_CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
+	SF(CNV0_CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\
+	SF(CNV0_CNV_MODE, CNV_EYE_SELECTION, mask_sh),\
+	SF(CNV0_CNV_MODE, CNV_STEREO_POLARITY, mask_sh),\
+	SF(CNV0_CNV_MODE, CNV_INTERLACED_FIELD_ORDER, mask_sh),\
+	SF(CNV0_CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\
+	SF(CNV0_CNV_MODE, CNV_NEW_CONTENT, mask_sh),\
+	SF(CNV0_CNV_MODE, CNV_FRAME_CAPTURE_EN, mask_sh),\
+	SF(CNV0_WB_SOFT_RESET, WB_SOFT_RESET, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_DUALSIZE_REQ, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_CHROMA_PITCH, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, WM_CHANGE_ACK_FORCE_ON, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB_BUF_2_ADDR_C_OFFSET, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB_BUF_4_ADDR_C_OFFSET, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK_IGNORE, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_ACK, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_FORCE_ON, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_ALLOW_FOR_URGENT, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_WARM_UP_CNTL, MCIF_WB_PITCH_SIZE_WARMUP, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, mask_sh),\
+	SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
+	SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh)
+
+#define DWBC_REG_FIELD_LIST(type) \
+	type WB_ENABLE;\
+	type DISPCLK_R_WB_GATE_DIS;\
+	type DISPCLK_G_WB_GATE_DIS;\
+	type DISPCLK_G_WBSCL_GATE_DIS;\
+	type WB_LB_LS_DIS;\
+	type WB_LB_SD_DIS;\
+	type WB_LUT_LS_DIS;\
+	type CNV_WINDOW_CROP_EN;\
+	type CNV_STEREO_TYPE;\
+	type CNV_INTERLACED_MODE;\
+	type CNV_EYE_SELECTION;\
+	type CNV_STEREO_POLARITY;\
+	type CNV_INTERLACED_FIELD_ORDER;\
+	type CNV_STEREO_SPLIT;\
+	type CNV_NEW_CONTENT;\
+	type CNV_FRAME_CAPTURE_EN;\
+	type WB_SOFT_RESET;\
+	type MCIF_WB_BUFMGR_ENABLE;\
+	type MCIF_WB_BUF_DUALSIZE_REQ;\
+	type MCIF_WB_BUFMGR_SW_INT_EN;\
+	type MCIF_WB_BUFMGR_SW_INT_ACK;\
+	type MCIF_WB_BUFMGR_SW_SLICE_INT_EN;\
+	type MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN;\
+	type MCIF_WB_BUFMGR_SW_LOCK;\
+	type MCIF_WB_P_VMID;\
+	type MCIF_WB_BUF_ADDR_FENCE_EN;\
+	type MCIF_WB_BUF_LUMA_PITCH;\
+	type MCIF_WB_BUF_CHROMA_PITCH;\
+	type MCIF_WB_CLIENT_ARBITRATION_SLICE;\
+	type MCIF_WB_TIME_PER_PIXEL;\
+	type WM_CHANGE_ACK_FORCE_ON;\
+	type MCIF_WB_CLI_WATERMARK_MASK;\
+	type MCIF_WB_BUF_1_ADDR_Y;\
+	type MCIF_WB_BUF_1_ADDR_Y_OFFSET;\
+	type MCIF_WB_BUF_1_ADDR_C;\
+	type MCIF_WB_BUF_1_ADDR_C_OFFSET;\
+	type MCIF_WB_BUF_2_ADDR_Y;\
+	type MCIF_WB_BUF_2_ADDR_Y_OFFSET;\
+	type MCIF_WB_BUF_2_ADDR_C;\
+	type MCIF_WB_BUF_2_ADDR_C_OFFSET;\
+	type MCIF_WB_BUF_3_ADDR_Y;\
+	type MCIF_WB_BUF_3_ADDR_Y_OFFSET;\
+	type MCIF_WB_BUF_3_ADDR_C;\
+	type MCIF_WB_BUF_3_ADDR_C_OFFSET;\
+	type MCIF_WB_BUF_4_ADDR_Y;\
+	type MCIF_WB_BUF_4_ADDR_Y_OFFSET;\
+	type MCIF_WB_BUF_4_ADDR_C;\
+	type MCIF_WB_BUF_4_ADDR_C_OFFSET;\
+	type MCIF_WB_BUFMGR_VCE_LOCK_IGNORE;\
+	type MCIF_WB_BUFMGR_VCE_INT_EN;\
+	type MCIF_WB_BUFMGR_VCE_INT_ACK;\
+	type MCIF_WB_BUFMGR_VCE_SLICE_INT_EN;\
+	type MCIF_WB_BUFMGR_VCE_LOCK;\
+	type MCIF_WB_BUFMGR_SLICE_SIZE;\
+	type NB_PSTATE_CHANGE_REFRESH_WATERMARK;\
+	type NB_PSTATE_CHANGE_URGENT_DURING_REQUEST;\
+	type NB_PSTATE_CHANGE_FORCE_ON;\
+	type NB_PSTATE_ALLOW_FOR_URGENT;\
+	type NB_PSTATE_CHANGE_WATERMARK_MASK;\
+	type MCIF_WB_CLI_WATERMARK;\
+	type MCIF_WB_CLI_CLOCK_GATER_OVERRIDE;\
+	type MCIF_WB_PITCH_SIZE_WARMUP;\
+	type MCIF_WB_BUF_LUMA_SIZE;\
+	type MCIF_WB_BUF_CHROMA_SIZE;\
+	type OPTC_DWB0_SOURCE_SELECT;\
+	type OPTC_DWB1_SOURCE_SELECT;\
+
+struct dcn10_dwbc_registers {
+	uint32_t WB_ENABLE;
+	uint32_t WB_EC_CONFIG;
+	uint32_t CNV_MODE;
+	uint32_t WB_SOFT_RESET;
+	uint32_t MCIF_WB_BUFMGR_SW_CONTROL;
+	uint32_t MCIF_WB_BUF_PITCH;
+	uint32_t MCIF_WB_ARBITRATION_CONTROL;
+	uint32_t MCIF_WB_SCLK_CHANGE;
+	uint32_t MCIF_WB_BUF_1_ADDR_Y;
+	uint32_t MCIF_WB_BUF_1_ADDR_Y_OFFSET;
+	uint32_t MCIF_WB_BUF_1_ADDR_C;
+	uint32_t MCIF_WB_BUF_1_ADDR_C_OFFSET;
+	uint32_t MCIF_WB_BUF_2_ADDR_Y;
+	uint32_t MCIF_WB_BUF_2_ADDR_Y_OFFSET;
+	uint32_t MCIF_WB_BUF_2_ADDR_C;
+	uint32_t MCIF_WB_BUF_2_ADDR_C_OFFSET;
+	uint32_t MCIF_WB_BUF_3_ADDR_Y;
+	uint32_t MCIF_WB_BUF_3_ADDR_Y_OFFSET;
+	uint32_t MCIF_WB_BUF_3_ADDR_C;
+	uint32_t MCIF_WB_BUF_3_ADDR_C_OFFSET;
+	uint32_t MCIF_WB_BUF_4_ADDR_Y;
+	uint32_t MCIF_WB_BUF_4_ADDR_Y_OFFSET;
+	uint32_t MCIF_WB_BUF_4_ADDR_C;
+	uint32_t MCIF_WB_BUF_4_ADDR_C_OFFSET;
+	uint32_t MCIF_WB_BUFMGR_VCE_CONTROL;
+	uint32_t MCIF_WB_NB_PSTATE_LATENCY_WATERMARK;
+	uint32_t MCIF_WB_NB_PSTATE_CONTROL;
+	uint32_t MCIF_WB_WATERMARK;
+	uint32_t MCIF_WB_WARM_UP_CNTL;
+	uint32_t MCIF_WB_BUF_LUMA_SIZE;
+	uint32_t MCIF_WB_BUF_CHROMA_SIZE;
+	uint32_t DWB_SOURCE_SELECT;
+};
+struct dcn10_dwbc_mask {
+	DWBC_REG_FIELD_LIST(uint32_t)
+};
+struct dcn10_dwbc_shift {
+	DWBC_REG_FIELD_LIST(uint8_t)
+};
+struct dcn10_dwbc {
+	struct dwbc base;
+	const struct dcn10_dwbc_registers *dwbc_regs;
+	const struct dcn10_dwbc_shift *dwbc_shift;
+	const struct dcn10_dwbc_mask *dwbc_mask;
+};
+
+void dcn10_dwbc_construct(struct dcn10_dwbc *dwbc10,
+		struct dc_context *ctx,
+		const struct dcn10_dwbc_registers *dwbc_regs,
+		const struct dcn10_dwbc_shift *dwbc_shift,
+		const struct dcn10_dwbc_mask *dwbc_mask,
+		int inst);
+
 #endif
 
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index ac6d01ec0505..298eb44ad9bf 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -326,6 +326,24 @@ static const struct dcn_dpp_mask tf_mask = {
 	TF_REG_LIST_SH_MASK_DCN10(_MASK),
 };
 
+#define dwbc_regs(id)\
+[id] = {\
+	DWBC_COMMON_REG_LIST_DCN1_0(id),\
+}
+
+static const struct dcn10_dwbc_registers dwbc10_regs[] = {
+	dwbc_regs(0),
+	dwbc_regs(1),
+};
+
+static const struct dcn10_dwbc_shift dwbc10_shift = {
+	DWBC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
+};
+
+static const struct dcn10_dwbc_mask dwbc10_mask = {
+	DWBC_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
+};
+
 static const struct dcn_mpc_registers mpc_regs = {
 		MPC_COMMON_REG_LIST_DCN1_0(0),
 		MPC_COMMON_REG_LIST_DCN1_0(1),
@@ -1215,6 +1233,30 @@ static uint32_t read_pipe_fuses(struct dc_context *ctx)
 	return value;
 }
 
+static bool dcn10_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
+{
+	int i;
+	uint32_t dwb_count = pool->res_cap->num_dwb;
+
+	for (i = 0; i < dwb_count; i++) {
+		struct dcn10_dwbc *dwbc10 = dm_alloc(sizeof(struct dcn10_dwbc));
+
+		if (!dwbc10) {
+			dm_error("DC: failed to create dwbc10!\n");
+			return false;
+		}
+
+		dcn10_dwbc_construct(dwbc10, ctx,
+				&dwbc10_regs[i],
+				&dwbc10_shift,
+				&dwbc10_mask,
+				i);
+
+		pool->dwbc[i] = &dwbc10->base;
+	}
+	return true;
+}
+
 static bool construct(
 	uint8_t num_virtual_links,
 	struct dc *dc,
-- 
2.11.0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 19/28] drm/amd/display: No need to keep track of unreffed clk sources

[Harry Wentland]

This simplifies clock source reprogramming a bit.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  | 18 ++--------------
 .../amd/display/dc/dce110/dce110_hw_sequencer.c    | 21 +++++-------------
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 25 +++++++---------------
 drivers/gpu/drm/amd/display/dc/inc/core_types.h    |  2 --
 drivers/gpu/drm/amd/display/dc/inc/resource.h      |  2 +-
 5 files changed, 16 insertions(+), 52 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index b17e1f60d34f..d4706578a47e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -261,13 +261,12 @@ bool resource_construct(
 }
 
 
-bool resource_unreference_clock_source(
+void resource_unreference_clock_source(
 		struct resource_context *res_ctx,
 		const struct resource_pool *pool,
 		struct clock_source *clock_source)
 {
 	int i;
-	bool need_reset = false;
 
 	for (i = 0; i < pool->clk_src_count; i++) {
 		if (pool->clock_sources[i] != clock_source)
@@ -275,24 +274,11 @@ bool resource_unreference_clock_source(
 
 		res_ctx->clock_source_ref_count[i]--;
 
-		if (res_ctx->clock_source_ref_count[i] == 0) {
-			res_ctx->clock_source_changed[i] = true;
-			need_reset = true;
-		}
-
 		break;
 	}
 
-	if (pool->dp_clock_source == clock_source) {
+	if (pool->dp_clock_source == clock_source)
 		res_ctx->dp_clock_source_ref_count--;
-
-		if (res_ctx->dp_clock_source_ref_count == 0) {
-			res_ctx->dp_clock_source_changed = true;
-			need_reset = true;
-		}
-	}
-
-	return need_reset;
 }
 
 void resource_reference_clock_source(
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index c57dc45d6677..31592e53f504 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1640,6 +1640,8 @@ static void dce110_reset_hw_ctx_wrap(
 
 		if (!pipe_ctx->stream ||
 				pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
+			struct clock_source *old_clk = pipe_ctx_old->clock_source;
+
 			core_link_disable_stream(pipe_ctx_old);
 			pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
 			if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
@@ -1650,27 +1652,14 @@ static void dce110_reset_hw_ctx_wrap(
 			pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
 					pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
 
+			if (old_clk)
+				old_clk->funcs->cs_power_down(old_clk);
+
 			dc->hwss.power_down_front_end(dc, pipe_ctx_old->pipe_idx);
 
 			pipe_ctx_old->stream = NULL;
 		}
 	}
-
-	/* power down changed clock sources */
-	for (i = 0; i < dc->res_pool->clk_src_count; i++)
-		if (context->res_ctx.clock_source_changed[i]) {
-			struct clock_source *clk = dc->res_pool->clock_sources[i];
-
-			clk->funcs->cs_power_down(clk);
-			context->res_ctx.clock_source_changed[i] = false;
-		}
-
-	if (context->res_ctx.dp_clock_source_changed) {
-		struct clock_source *clk = dc->res_pool->dp_clock_source;
-
-		clk->funcs->cs_power_down(clk);
-		context->res_ctx.clock_source_changed[i] = false;
-	}
 }
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 6fee6957c1a6..c8c4b951ee1d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1265,22 +1265,6 @@ static void reset_hw_ctx_wrap(
 			plane_atomic_power_down(dc, i);
 	}
 
-	/* power down changed clock sources */
-	for (i = 0; i < dc->res_pool->clk_src_count; i++)
-		if (context->res_ctx.clock_source_changed[i]) {
-			struct clock_source *clk = dc->res_pool->clock_sources[i];
-
-			clk->funcs->cs_power_down(clk);
-			context->res_ctx.clock_source_changed[i] = false;
-		}
-
-	if (context->res_ctx.dp_clock_source_changed) {
-		struct clock_source *clk = dc->res_pool->dp_clock_source;
-
-		clk->funcs->cs_power_down(clk);
-		context->res_ctx.dp_clock_source_changed = false;
-	}
-
 	/* Reset Back End*/
 	for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
 		struct pipe_ctx *pipe_ctx_old =
@@ -1291,9 +1275,16 @@ static void reset_hw_ctx_wrap(
 			continue;
 
 		if (!pipe_ctx->stream ||
-				pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
+				pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
+			struct clock_source *old_clk = pipe_ctx_old->clock_source;
+
 			reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
+
+			if (old_clk)
+				old_clk->funcs->cs_power_down(old_clk);
+		}
 	}
+
 }
 
 static bool patch_address_for_sbs_tb_stereo(
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index b6a513d6feda..915d5c10361b 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -213,9 +213,7 @@ struct resource_context {
 	bool is_stream_enc_acquired[MAX_PIPES * 2];
 	bool is_audio_acquired[MAX_PIPES];
 	uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];
-	bool clock_source_changed[MAX_CLOCK_SOURCES];
 	uint8_t dp_clock_source_ref_count;
-	bool dp_clock_source_changed;
 };
 
 struct dce_bw_output {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h
index cf1797c191e9..614bb691ab59 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
@@ -92,7 +92,7 @@ enum dc_status resource_build_scaling_params_for_context(
 
 void resource_build_info_frame(struct pipe_ctx *pipe_ctx);
 
-bool resource_unreference_clock_source(
+void resource_unreference_clock_source(
 		struct resource_context *res_ctx,
 		const struct resource_pool *pool,
 		struct clock_source *clock_source);
-- 
2.11.0

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Re: [PATCH 07/28] drm/amd/display: USB-C to HDMI dongle not light

[Dave Airlie]

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This seems to lack a commit msg

Dave.

On 12 Sep. 2017 4:15 am, "Harry Wentland" <harry.wentland-5C7GfCeVMHo@public.gmane.org> wrote:

> From: Hersen Wu <hersenxs.wu-5C7GfCeVMHo@public.gmane.org>
>
> Signed-off-by: Hersen Wu <hersenxs.wu-5C7GfCeVMHo@public.gmane.org>
> Reviewed-by: Tony Cheng <Tony.Cheng-5C7GfCeVMHo@public.gmane.org>
> Acked-by: Harry Wentland <Harry.Wentland-5C7GfCeVMHo@public.gmane.org>
> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  9 ++++---
>  drivers/gpu/drm/amd/display/dc/core/dc_link.c     | 32
> +++++++++++++++--------
>  drivers/gpu/drm/amd/display/dc/dc.h               |  8 +++++-
>  3 files changed, 33 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 7a408d753be8..9b5158cceece 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -639,7 +639,7 @@ int amdgpu_dm_display_resume(struct amdgpu_device
> *adev )
>                         continue;
>
>                 mutex_lock(&aconnector->hpd_lock);
> -               dc_link_detect(aconnector->dc_link, false);
> +               dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
>                 aconnector->dc_sink = NULL;
>                 amdgpu_dm_update_connector_after_detect(aconnector);
>                 mutex_unlock(&aconnector->hpd_lock);
> @@ -870,7 +870,7 @@ static void handle_hpd_irq(void *param)
>          * since (for MST case) MST does this in it's own context.
>          */
>         mutex_lock(&aconnector->hpd_lock);
> -       if (dc_link_detect(aconnector->dc_link, false)) {
> +       if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
>                 amdgpu_dm_update_connector_after_detect(aconnector);
>
>
> @@ -980,7 +980,7 @@ static void handle_hpd_rx_irq(void *param)
>         if (dc_link_handle_hpd_rx_irq(aconnector->dc_link, NULL) &&
>                         !is_mst_root_connector) {
>                 /* Downstream Port status changed. */
> -               if (dc_link_detect(aconnector->dc_link, false)) {
> +               if (dc_link_detect(aconnector->dc_link,
> DETECT_REASON_HPDRX)) {
>                         amdgpu_dm_update_connector_
> after_detect(aconnector);
>
>
> @@ -1368,7 +1368,8 @@ int amdgpu_dm_initialize_drm_device(struct
> amdgpu_device *adev)
>                         goto fail_free_encoder;
>                 }
>
> -               if (dc_link_detect(dc_get_link_at_index(dm->dc, i), true))
> +               if (dc_link_detect(dc_get_link_at_index(dm->dc, i),
> +                               DETECT_REASON_BOOT))
>                         amdgpu_dm_update_connector_
> after_detect(aconnector);
>         }
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> index cea8dafd2edc..845ec421d861 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> @@ -355,7 +355,9 @@ static bool is_dp_sink_present(struct dc_link *link)
>   * @brief
>   * Detect output sink type
>   */
> -static enum signal_type link_detect_sink(struct dc_link *link)
> +static enum signal_type link_detect_sink(
> +       struct dc_link *link,
> +       enum dc_detect_reason reason)
>  {
>         enum signal_type result = get_basic_signal_type(
>                 link->link_enc->id, link->link_id);
> @@ -388,12 +390,17 @@ static enum signal_type link_detect_sink(struct
> dc_link *link)
>         }
>         break;
>         case CONNECTOR_ID_DISPLAY_PORT: {
> -
> -               /* Check whether DP signal detected: if not -
> -                * we assume signal is DVI; it could be corrected
> -                * to HDMI after dongle detection */
> -               if (!is_dp_sink_present(link))
> -                       result = SIGNAL_TYPE_DVI_SINGLE_LINK;
> +               /* DP HPD short pulse. Passive DP dongle will not
> +                * have short pulse
> +                */
> +               if (reason != DETECT_REASON_HPDRX) {
> +                       /* Check whether DP signal detected: if not -
> +                        * we assume signal is DVI; it could be corrected
> +                        * to HDMI after dongle detection
> +                        */
> +                       if (!is_dp_sink_present(link))
> +                               result = SIGNAL_TYPE_DVI_SINGLE_LINK;
> +               }
>         }
>         break;
>         default:
> @@ -460,9 +467,10 @@ static void detect_dp(
>         struct display_sink_capability *sink_caps,
>         bool *converter_disable_audio,
>         struct audio_support *audio_support,
> -       bool boot)
> +       enum dc_detect_reason reason)
>  {
> -       sink_caps->signal = link_detect_sink(link);
> +       bool boot = false;
> +       sink_caps->signal = link_detect_sink(link, reason);
>         sink_caps->transaction_type =
>                 get_ddc_transaction_type(sink_caps->signal);
>
> @@ -513,6 +521,8 @@ static void detect_dp(
>                          * Need check ->sink usages in case ->sink = NULL
>                          * TODO: s3 resume check
>                          */
> +                       if (reason == DETECT_REASON_BOOT)
> +                               boot = true;
>
>                         if (dm_helpers_dp_mst_start_top_mgr(
>                                 link->ctx,
> @@ -531,7 +541,7 @@ static void detect_dp(
>         }
>  }
>
> -bool dc_link_detect(struct dc_link *link, bool boot)
> +bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
>  {
>         struct dc_sink_init_data sink_init_data = { 0 };
>         struct display_sink_capability sink_caps = { 0 };
> @@ -596,7 +606,7 @@ bool dc_link_detect(struct dc_link *link, bool boot)
>                                 link,
>                                 &sink_caps,
>                                 &converter_disable_audio,
> -                               aud_support, boot);
> +                               aud_support, reason);
>
>                         /* Active dongle downstream unplug */
>                         if (link->type == dc_connection_active_dongle
> diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
> b/drivers/gpu/drm/amd/display/dc/dc.h
> index f005add1aba3..bf2d42561362 100644
> --- a/drivers/gpu/drm/amd/display/dc/dc.h
> +++ b/drivers/gpu/drm/amd/display/dc/dc.h
> @@ -884,7 +884,13 @@ bool dc_link_setup_psr(struct dc_link *dc_link,
>   * true otherwise. True meaning further action is required (status update
>   * and OS notification).
>   */
> -bool dc_link_detect(struct dc_link *dc_link, bool boot);
> +enum dc_detect_reason {
> +       DETECT_REASON_BOOT,
> +       DETECT_REASON_HPD,
> +       DETECT_REASON_HPDRX,
> +};
> +
> +bool dc_link_detect(struct dc_link *dc_link, enum dc_detect_reason
> reason);
>
>  /* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt).
>   * Return:
> --
> 2.11.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>

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