* [PATCH] ARC: [plat-axs10x]: DTS: fix sdio ciu frequency
@ 2017-09-12 18:20 ` Eugeniy Paltsev
0 siblings, 0 replies; 8+ messages in thread
From: Eugeniy Paltsev @ 2017-09-12 18:20 UTC (permalink / raw)
To: linux-snps-arc
Cc: linux-kernel, Vineet Gupta, Alexey Brodkin, Rob Herring,
devicetree, Eugeniy Paltsev
DW sdio controller has external ciu clock divider controlled
via register in SDIO IP. It divides sdio_ref_clk
(which comes from CGU) by 16 for default. So default mmcclk
clock (which comes to sdk_in) is 25000000 Hz.
So fix wrong current value (50000000 Hz) to actual 25000000 Hz.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
---
arch/arc/boot/dts/axs10x_mb.dtsi | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi
index 0ff7e07..7bdf581 100644
--- a/arch/arc/boot/dts/axs10x_mb.dtsi
+++ b/arch/arc/boot/dts/axs10x_mb.dtsi
@@ -44,7 +44,14 @@
mmcclk: mmcclk {
compatible = "fixed-clock";
- clock-frequency = <50000000>;
+ /*
+ * DW sdio controller has external ciu clock divider
+ * controlled via register in SDIO IP. It divides
+ * sdio_ref_clk (which comes from CGU) by 16 for
+ * default. So default mmcclk clock (which comes
+ * to sdk_in) is 25000000 Hz.
+ */
+ clock-frequency = <25000000>;
#clock-cells = <0>;
};
--
2.9.3
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH] ARC: [plat-axs10x]: DTS: fix sdio ciu frequency
@ 2017-09-12 18:20 ` Eugeniy Paltsev
0 siblings, 0 replies; 8+ messages in thread
From: Eugeniy Paltsev @ 2017-09-12 18:20 UTC (permalink / raw)
To: linux-snps-arc
DW sdio controller has external ciu clock divider controlled
via register in SDIO IP. It divides sdio_ref_clk
(which comes from CGU) by 16 for default. So default mmcclk
clock (which comes to sdk_in) is 25000000 Hz.
So fix wrong current value (50000000 Hz) to actual 25000000 Hz.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com>
---
arch/arc/boot/dts/axs10x_mb.dtsi | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi
index 0ff7e07..7bdf581 100644
--- a/arch/arc/boot/dts/axs10x_mb.dtsi
+++ b/arch/arc/boot/dts/axs10x_mb.dtsi
@@ -44,7 +44,14 @@
mmcclk: mmcclk {
compatible = "fixed-clock";
- clock-frequency = <50000000>;
+ /*
+ * DW sdio controller has external ciu clock divider
+ * controlled via register in SDIO IP. It divides
+ * sdio_ref_clk (which comes from CGU) by 16 for
+ * default. So default mmcclk clock (which comes
+ * to sdk_in) is 25000000 Hz.
+ */
+ clock-frequency = <25000000>;
#clock-cells = <0>;
};
--
2.9.3
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH] ARC: [plat-axs10x]: DTS: fix sdio ciu frequency
@ 2017-09-12 18:38 ` Vineet Gupta
0 siblings, 0 replies; 8+ messages in thread
From: Vineet Gupta @ 2017-09-12 18:38 UTC (permalink / raw)
To: Eugeniy Paltsev, linux-snps-arc
Cc: linux-kernel, Alexey Brodkin, Rob Herring, devicetree
On 09/12/2017 11:20 AM, Eugeniy Paltsev wrote:
> DW sdio controller has external ciu clock divider controlled
> via register in SDIO IP. It divides sdio_ref_clk
> (which comes from CGU) by 16 for default. So default mmcclk
> clock (which comes to sdk_in) is 25000000 Hz.
>
> So fix wrong current value (50000000 Hz) to actual 25000000 Hz.
Is this a preventive fix or there are known issues with what we have today.
Is this triggered after addition of AXS clk driver ?
>
> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
> ---
> arch/arc/boot/dts/axs10x_mb.dtsi | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi
> index 0ff7e07..7bdf581 100644
> --- a/arch/arc/boot/dts/axs10x_mb.dtsi
> +++ b/arch/arc/boot/dts/axs10x_mb.dtsi
> @@ -44,7 +44,14 @@
>
> mmcclk: mmcclk {
> compatible = "fixed-clock";
> - clock-frequency = <50000000>;
> + /*
> + * DW sdio controller has external ciu clock divider
> + * controlled via register in SDIO IP. It divides
> + * sdio_ref_clk (which comes from CGU) by 16 for
> + * default. So default mmcclk clock (which comes
> + * to sdk_in) is 25000000 Hz.
> + */
> + clock-frequency = <25000000>;
> #clock-cells = <0>;
> };
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] ARC: [plat-axs10x]: DTS: fix sdio ciu frequency
@ 2017-09-12 18:38 ` Vineet Gupta
0 siblings, 0 replies; 8+ messages in thread
From: Vineet Gupta @ 2017-09-12 18:38 UTC (permalink / raw)
To: Eugeniy Paltsev, linux-snps-arc-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA, Alexey Brodkin, Rob Herring,
devicetree-u79uwXL29TY76Z2rM5mHXA
On 09/12/2017 11:20 AM, Eugeniy Paltsev wrote:
> DW sdio controller has external ciu clock divider controlled
> via register in SDIO IP. It divides sdio_ref_clk
> (which comes from CGU) by 16 for default. So default mmcclk
> clock (which comes to sdk_in) is 25000000 Hz.
>
> So fix wrong current value (50000000 Hz) to actual 25000000 Hz.
Is this a preventive fix or there are known issues with what we have today.
Is this triggered after addition of AXS clk driver ?
>
> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev-HKixBCOQz3hWk0Htik3J/w@public.gmane.org>
> ---
> arch/arc/boot/dts/axs10x_mb.dtsi | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi
> index 0ff7e07..7bdf581 100644
> --- a/arch/arc/boot/dts/axs10x_mb.dtsi
> +++ b/arch/arc/boot/dts/axs10x_mb.dtsi
> @@ -44,7 +44,14 @@
>
> mmcclk: mmcclk {
> compatible = "fixed-clock";
> - clock-frequency = <50000000>;
> + /*
> + * DW sdio controller has external ciu clock divider
> + * controlled via register in SDIO IP. It divides
> + * sdio_ref_clk (which comes from CGU) by 16 for
> + * default. So default mmcclk clock (which comes
> + * to sdk_in) is 25000000 Hz.
> + */
> + clock-frequency = <25000000>;
> #clock-cells = <0>;
> };
>
--
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH] ARC: [plat-axs10x]: DTS: fix sdio ciu frequency
@ 2017-09-12 18:38 ` Vineet Gupta
0 siblings, 0 replies; 8+ messages in thread
From: Vineet Gupta @ 2017-09-12 18:38 UTC (permalink / raw)
To: linux-snps-arc
On 09/12/2017 11:20 AM, Eugeniy Paltsev wrote:
> DW sdio controller has external ciu clock divider controlled
> via register in SDIO IP. It divides sdio_ref_clk
> (which comes from CGU) by 16 for default. So default mmcclk
> clock (which comes to sdk_in) is 25000000 Hz.
>
> So fix wrong current value (50000000 Hz) to actual 25000000 Hz.
Is this a preventive fix or there are known issues with what we have today.
Is this triggered after addition of AXS clk driver ?
>
> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com>
> ---
> arch/arc/boot/dts/axs10x_mb.dtsi | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi
> index 0ff7e07..7bdf581 100644
> --- a/arch/arc/boot/dts/axs10x_mb.dtsi
> +++ b/arch/arc/boot/dts/axs10x_mb.dtsi
> @@ -44,7 +44,14 @@
>
> mmcclk: mmcclk {
> compatible = "fixed-clock";
> - clock-frequency = <50000000>;
> + /*
> + * DW sdio controller has external ciu clock divider
> + * controlled via register in SDIO IP. It divides
> + * sdio_ref_clk (which comes from CGU) by 16 for
> + * default. So default mmcclk clock (which comes
> + * to sdk_in) is 25000000 Hz.
> + */
> + clock-frequency = <25000000>;
> #clock-cells = <0>;
> };
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] ARC: [plat-axs10x]: DTS: fix sdio ciu frequency
2017-09-12 18:38 ` Vineet Gupta
(?)
@ 2017-09-13 15:14 ` Eugeniy Paltsev
-1 siblings, 0 replies; 8+ messages in thread
From: Eugeniy Paltsev @ 2017-09-13 15:14 UTC (permalink / raw)
To: Vineet Gupta, linux-snps-arc
Cc: linux-kernel, Alexey Brodkin, robh+dt, devicetree
On Tue, 2017-09-12 at 11:38 -0700, Vineet Gupta wrote:
> On 09/12/2017 11:20 AM, Eugeniy Paltsev wrote:
> > DW sdio controller has external ciu clock divider controlled
> > via register in SDIO IP. It divides sdio_ref_clk
> > (which comes from CGU) by 16 for default. So default mmcclk
> > clock (which comes to sdk_in) is 25000000 Hz.
> >
> > So fix wrong current value (50000000 Hz) to actual 25000000 Hz.
>
> Is this a preventive fix or there are known issues with what we have today.
Yes, it's kinda a preventive fix.
We check axs10x ciu frequency when we found what hsdk ciu frequency was wrong
and found that it is wring too.
I tried to run SD stress test with wrong ciu frequency (50000000 Hz) and it passed
successfully, but we must take into account the fact that it depends on SD
card itself. For example: this SD card mostly works fine on HSDK with ciu
frequency 8x times higher than expected!
Alexey says that he faced with unstable SD card work on axs103 earlier but
he didn't save any artifacts about it.
> Is this triggered after addition of AXS clk driver ?
No.
> >
> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
> > ---
> > arch/arc/boot/dts/axs10x_mb.dtsi | 9 ++++++++-
> > 1 file changed, 8 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi
> > index 0ff7e07..7bdf581 100644
> > --- a/arch/arc/boot/dts/axs10x_mb.dtsi
> > +++ b/arch/arc/boot/dts/axs10x_mb.dtsi
> > @@ -44,7 +44,14 @@
> >
> > mmcclk: mmcclk {
> > compatible = "fixed-clock";
> > - clock-frequency = <50000000>;
> > + /*
> > + * DW sdio controller has external ciu clock divider
> > + * controlled via register in SDIO IP. It divides
> > + * sdio_ref_clk (which comes from CGU) by 16 for
> > + * default. So default mmcclk clock (which comes
> > + * to sdk_in) is 25000000 Hz.
> > + */
> > + clock-frequency = <25000000>;
> > #clock-cells = <0>;
> > };
> >
>
>
--
Eugeniy Paltsev
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] ARC: [plat-axs10x]: DTS: fix sdio ciu frequency
@ 2017-09-13 15:14 ` Eugeniy Paltsev
0 siblings, 0 replies; 8+ messages in thread
From: Eugeniy Paltsev @ 2017-09-13 15:14 UTC (permalink / raw)
To: Vineet Gupta, linux-snps-arc
Cc: linux-kernel, Alexey Brodkin, robh+dt, devicetree
On Tue, 2017-09-12 at 11:38 -0700, Vineet Gupta wrote:
> On 09/12/2017 11:20 AM, Eugeniy Paltsev wrote:
> > DW sdio controller has external ciu clock divider controlled
> > via register in SDIO IP. It divides sdio_ref_clk
> > (which comes from CGU) by 16 for default. So default mmcclk
> > clock (which comes to sdk_in) is 25000000 Hz.
> >
> > So fix wrong current value (50000000 Hz) to actual 25000000 Hz.
>
> Is this a preventive fix or there are known issues with what we have today.
Yes, it's kinda a preventive fix.
We check axs10x ciu frequency when we found what hsdk ciu frequency was wrong
and found that it is wring too.
I tried to run SD stress test with wrong ciu frequency (50000000 Hz) and it passed
successfully, but we must take into account the fact that it depends on SD
card itself. For example: this SD card mostly works fine on HSDK with ciu
frequency 8x times higher than expected!
Alexey says that he faced with unstable SD card work on axs103 earlier but
he didn't save any artifacts about it.
> Is this triggered after addition of AXS clk driver ?
No.
> >
> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
> > ---
> > arch/arc/boot/dts/axs10x_mb.dtsi | 9 ++++++++-
> > 1 file changed, 8 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi
> > index 0ff7e07..7bdf581 100644
> > --- a/arch/arc/boot/dts/axs10x_mb.dtsi
> > +++ b/arch/arc/boot/dts/axs10x_mb.dtsi
> > @@ -44,7 +44,14 @@
> >
> > mmcclk: mmcclk {
> > compatible = "fixed-clock";
> > - clock-frequency = <50000000>;
> > + /*
> > + * DW sdio controller has external ciu clock divider
> > + * controlled via register in SDIO IP. It divides
> > + * sdio_ref_clk (which comes from CGU) by 16 for
> > + * default. So default mmcclk clock (which comes
> > + * to sdk_in) is 25000000 Hz.
> > + */
> > + clock-frequency = <25000000>;
> > #clock-cells = <0>;
> > };
> >
>
>
--
Eugeniy Paltsev
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH] ARC: [plat-axs10x]: DTS: fix sdio ciu frequency
@ 2017-09-13 15:14 ` Eugeniy Paltsev
0 siblings, 0 replies; 8+ messages in thread
From: Eugeniy Paltsev @ 2017-09-13 15:14 UTC (permalink / raw)
To: linux-snps-arc
On Tue, 2017-09-12@11:38 -0700, Vineet Gupta wrote:
> On 09/12/2017 11:20 AM, Eugeniy Paltsev wrote:
> > DW sdio controller has external ciu clock divider controlled
> > via register in SDIO IP. It divides sdio_ref_clk
> > (which comes from CGU) by 16 for default. So default mmcclk
> > clock (which comes to sdk_in) is 25000000 Hz.
> >
> > So fix wrong current value (50000000 Hz) to actual 25000000 Hz.
>
> Is this a preventive fix or there are known issues with what we have today.
Yes, it's kinda a preventive fix.
We check axs10x?ciu frequency when we found what hsdk?ciu frequency was wrong
and found that it is wring too.
I tried to run SD stress test with wrong ciu?frequency (50000000 Hz) and it passed
successfully, but we must take into account the fact that it depends on SD
card itself. For example: this SD card mostly works fine on HSDK with ciu?
frequency 8x times?higher than expected!
Alexey says that he faced with unstable SD card work on axs103 earlier but
he didn't save any artifacts about it.
> Is this triggered after addition of AXS clk driver ?
No.
> >
> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com>
> > ---
> > ? arch/arc/boot/dts/axs10x_mb.dtsi | 9 ++++++++-
> > ? 1 file changed, 8 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi
> > index 0ff7e07..7bdf581 100644
> > --- a/arch/arc/boot/dts/axs10x_mb.dtsi
> > +++ b/arch/arc/boot/dts/axs10x_mb.dtsi
> > @@ -44,7 +44,14 @@
> > ??
> > ?? mmcclk: mmcclk {
> > ?? compatible = "fixed-clock";
> > - clock-frequency = <50000000>;
> > + /*
> > + ?* DW sdio controller has external ciu clock divider
> > + ?* controlled via register in SDIO IP. It divides
> > + ?* sdio_ref_clk (which comes from CGU) by 16 for
> > + ?* default. So default mmcclk clock (which comes
> > + ?* to sdk_in) is 25000000 Hz.
> > + ?*/
> > + clock-frequency = <25000000>;
> > ?? #clock-cells = <0>;
> > ?? };
> > ??
>
>
--
?Eugeniy Paltsev
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2017-09-13 15:14 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-09-12 18:20 [PATCH] ARC: [plat-axs10x]: DTS: fix sdio ciu frequency Eugeniy Paltsev
2017-09-12 18:20 ` Eugeniy Paltsev
2017-09-12 18:38 ` Vineet Gupta
2017-09-12 18:38 ` Vineet Gupta
2017-09-12 18:38 ` Vineet Gupta
2017-09-13 15:14 ` Eugeniy Paltsev
2017-09-13 15:14 ` Eugeniy Paltsev
2017-09-13 15:14 ` Eugeniy Paltsev
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