[PATCH v2 0/6] drm/i915: Convert gen4- watermarks to atomic.

[PATCH v2 0/6] drm/i915: Convert gen4- watermarks to atomic.

[Maarten Lankhorst]

Calculate watermarks for gen4 and lower atomically.

Changes since first version:
- Address review feedback in first patch.
- Rename sr/hpll.yyy to sr/hpll.yyy_wm.
- Clarify comment in calculate gen4 watermarks semiatomically.

Maarten Lankhorst (6):
  drm/i915: Calculate gen3- watermarks semi-atomically, v3.
  drm/i915: Program gen3- watermarks atomically
  drm/i915: Calculate gen4 watermarks semiatomically.
  drm/i915: Program gen4 watermarks atomically
  drm/i915: Kill off intel_crtc_active.
  drm/i915: Rip out legacy watermark infrastructure

 drivers/gpu/drm/i915/i915_drv.h      |   6 +-
 drivers/gpu/drm/i915/intel_atomic.c  |   2 -
 drivers/gpu/drm/i915/intel_display.c |  93 +----
 drivers/gpu/drm/i915/intel_drv.h     |  19 +-
 drivers/gpu/drm/i915/intel_fbc.c     |   2 +-
 drivers/gpu/drm/i915/intel_pm.c      | 654 ++++++++++++++++++++++-------------
 6 files changed, 448 insertions(+), 328 deletions(-)

-- 
2.14.1

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[PATCH v2 1/6] drm/i915: Calculate gen3- watermarks semi-atomically, v3.

[Maarten Lankhorst]

The gen3 watermark calculations are converted to atomic,
but the wm update calls are still done through the legacy
functions.

This will make it easier to bisect things if they go wrong.

CI was having issues on the kms_cursor_legacy tests with too
much debug info printed out, in order to reduce the chattiness
we will kill the prints from intel_calculate_wm.

Changes since v1:
- Neuter intel_calculate_wm spam.
Changes since v2:
- Calculate plane_wm for gen2 correctly. (Mahesh)
- Small fixes from review feedback. (Mahesh)

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   3 +-
 drivers/gpu/drm/i915/intel_drv.h     |  15 +++
 drivers/gpu/drm/i915/intel_pm.c      | 237 ++++++++++++++++++++---------------
 3 files changed, 156 insertions(+), 99 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 524217d6292e..f0e5ab2ac2ee 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15153,7 +15153,8 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
 		skl_wm_get_hw_state(dev);
 	} else if (HAS_PCH_SPLIT(dev_priv)) {
 		ilk_wm_get_hw_state(dev);
-	}
+	} else if (INTEL_GEN(dev_priv) <= 3 && !IS_PINEVIEW(dev_priv))
+		i9xx_wm_get_hw_state(dev);
 
 	for_each_intel_crtc(dev, crtc) {
 		u64 put_domains;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 307807672896..78554f23e264 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -549,6 +549,15 @@ struct g4x_wm_state {
 	bool fbc_en;
 };
 
+struct i9xx_wm_state {
+	uint16_t plane_wm;
+	bool cxsr;
+
+	struct {
+		uint16_t plane_wm;
+	} sr;
+};
+
 struct intel_crtc_wm_state {
 	union {
 		struct {
@@ -593,6 +602,10 @@ struct intel_crtc_wm_state {
 			/* optimal watermarks */
 			struct g4x_wm_state optimal;
 		} g4x;
+
+		struct {
+			struct i9xx_wm_state optimal;
+		} i9xx;
 	};
 
 	/*
@@ -826,6 +839,7 @@ struct intel_crtc {
 			struct intel_pipe_wm ilk;
 			struct vlv_wm_state vlv;
 			struct g4x_wm_state g4x;
+			struct i9xx_wm_state i9xx;
 		} active;
 	} wm;
 
@@ -1877,6 +1891,7 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv);
 void gen6_rps_boost(struct drm_i915_gem_request *rq,
 		    struct intel_rps_client *rps);
 void g4x_wm_get_hw_state(struct drm_device *dev);
+void i9xx_wm_get_hw_state(struct drm_device *dev);
 void vlv_wm_get_hw_state(struct drm_device *dev);
 void ilk_wm_get_hw_state(struct drm_device *dev);
 void skl_wm_get_hw_state(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index fa9055a4f790..6f7be0a2be05 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -771,10 +771,8 @@ static unsigned int intel_calculate_wm(int pixel_rate,
 				   latency_ns / 100);
 	entries = DIV_ROUND_UP(entries, wm->cacheline_size) +
 		wm->guard_size;
-	DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries);
 
 	wm_size = fifo_size - entries;
-	DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
 
 	/* Don't promote wm_size to unsigned... */
 	if (wm_size > wm->max_wm)
@@ -2244,89 +2242,156 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
 
 #undef FW_WM
 
-static void i9xx_update_wm(struct intel_crtc *unused_crtc)
+static const struct intel_watermark_params *i9xx_get_wm_info(struct drm_i915_private *dev_priv,
+							     struct intel_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
-	const struct intel_watermark_params *wm_info;
-	uint32_t fwater_lo;
-	uint32_t fwater_hi;
-	int cwm, srwm = 1;
-	int fifo_size;
-	int planea_wm, planeb_wm;
-	struct intel_crtc *crtc, *enabled = NULL;
+	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
 
 	if (IS_I945GM(dev_priv))
-		wm_info = &i945_wm_info;
+		return &i945_wm_info;
 	else if (!IS_GEN2(dev_priv))
-		wm_info = &i915_wm_info;
+		return &i915_wm_info;
+	else if (plane->plane == PLANE_A)
+		return &i830_a_wm_info;
 	else
-		wm_info = &i830_a_wm_info;
+		return &i830_bc_wm_info;
+}
 
-	fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0);
-	crtc = intel_get_crtc_for_plane(dev_priv, 0);
-	if (intel_crtc_active(crtc)) {
-		const struct drm_display_mode *adjusted_mode =
-			&crtc->config->base.adjusted_mode;
-		const struct drm_framebuffer *fb =
-			crtc->base.primary->state->fb;
-		int cpp;
+static int i9xx_compute_pipe_wm(struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct intel_atomic_state *state =
+		to_intel_atomic_state(crtc_state->base.state);
+	struct i9xx_wm_state *wm_state = &crtc_state->wm.i9xx.optimal;
+	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
+	const struct drm_plane_state *plane_state = NULL;
+	int fifo_size;
+	const struct intel_watermark_params *wm_info;
 
-		if (IS_GEN2(dev_priv))
-			cpp = 4;
-		else
-			cpp = fb->format->cpp[0];
+	fifo_size = dev_priv->display.get_fifo_size(dev_priv, plane->plane);
 
-		planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
-					       wm_info, fifo_size, cpp,
-					       pessimal_latency_ns);
-		enabled = crtc;
+	wm_info = i9xx_get_wm_info(dev_priv, crtc);
+
+	wm_state->cxsr = false;
+	memset(&wm_state->sr, 0, sizeof(wm_state->sr));
+
+	if (crtc_state->base.plane_mask & BIT(drm_plane_index(&plane->base)))
+		plane_state = __drm_atomic_get_current_plane_state(&state->base, &plane->base);
+
+	if (!plane_state || !intel_wm_plane_visible(crtc_state, to_intel_plane_state(plane_state))) {
+		wm_state->plane_wm = fifo_size - wm_info->guard_size;
+		if (wm_state->plane_wm > (long)wm_info->max_wm)
+			wm_state->plane_wm = wm_info->max_wm;
 	} else {
-		planea_wm = fifo_size - wm_info->guard_size;
-		if (planea_wm > (long)wm_info->max_wm)
-			planea_wm = wm_info->max_wm;
+		struct drm_framebuffer *fb = plane_state->fb;
+		unsigned cpp = IS_GEN2(dev_priv) ? 4 : fb->format->cpp[0];
+		const struct drm_display_mode *adjusted_mode =
+			&crtc_state->base.adjusted_mode;
+		unsigned active_crtcs;
+		bool may_cxsr = false;
+
+		if (HAS_FW_BLC(dev_priv)) {
+			if (state->modeset)
+				active_crtcs = state->active_crtcs;
+			else
+				active_crtcs = dev_priv->active_crtcs;
+
+			/* CxSR can only be enabled when a single CRTC is enabled. */
+			may_cxsr = active_crtcs == drm_crtc_mask(&crtc->base);
+
+			if (IS_I915GM(dev_priv) && i915_gem_object_is_tiled(intel_fb_obj(fb)))
+				may_cxsr = false;
+		}
+
+		wm_state->plane_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
+							wm_info, fifo_size, cpp,
+							pessimal_latency_ns);
+
+		DRM_DEBUG_KMS("FIFO watermarks - plane watermarks: %d\n", wm_state->plane_wm);
+
+		if (may_cxsr) {
+			static const int sr_latency_ns = 6000;
+			unsigned long entries;
+
+			entries = intel_wm_method2(adjusted_mode->crtc_clock,
+						   adjusted_mode->crtc_htotal,
+						   crtc_state->pipe_src_w, cpp,
+						   sr_latency_ns / 100);
+			entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
+
+			DRM_DEBUG_KMS("self-refresh entries: %ld\n", entries);
+
+			if (wm_info->fifo_size >= entries) {
+				wm_state->cxsr = true;
+				wm_state->sr.plane_wm = wm_info->fifo_size - entries;
+			}
+		}
+
+		DRM_DEBUG_KMS("FIFO watermarks - plane watermarks: %d, can cxsr: %s, SR size: %d\n",
+			      wm_state->plane_wm, yesno(wm_state->cxsr), wm_state->sr.plane_wm);
 	}
 
-	if (IS_GEN2(dev_priv))
-		wm_info = &i830_bc_wm_info;
+	return 0;
+}
 
-	fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1);
-	crtc = intel_get_crtc_for_plane(dev_priv, 1);
-	if (intel_crtc_active(crtc)) {
-		const struct drm_display_mode *adjusted_mode =
-			&crtc->config->base.adjusted_mode;
-		const struct drm_framebuffer *fb =
-			crtc->base.primary->state->fb;
-		int cpp;
+void i9xx_wm_get_hw_state(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_crtc *crtc;
+	uint32_t fwater_lo, planea_wm, planeb_wm;
+
+	fwater_lo = I915_READ(FW_BLC);
+
+	planea_wm = fwater_lo & 0x3f;
+	planeb_wm = (fwater_lo >> 16) & 0x3f;
+
+	for_each_intel_crtc(dev, crtc) {
+		struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->base.state);
+		struct i9xx_wm_state *wm_state = &cstate->wm.i9xx.optimal;
+		struct intel_plane *plane = to_intel_plane(crtc->base.primary);
+
+		memset(&wm_state->sr, 0, sizeof(wm_state->sr));
+		wm_state->cxsr = false;
 
-		if (IS_GEN2(dev_priv))
-			cpp = 4;
+		if (plane->plane == PLANE_A)
+			wm_state->plane_wm = planea_wm;
 		else
-			cpp = fb->format->cpp[0];
+			wm_state->plane_wm = planeb_wm;
+
+		crtc->wm.active.i9xx = *wm_state;
+	}
+}
 
-		planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
-					       wm_info, fifo_size, cpp,
-					       pessimal_latency_ns);
+static void i9xx_update_wm(struct intel_crtc *crtc)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	uint32_t fwater_lo;
+	uint32_t fwater_hi;
+	int cwm, srwm = -1;
+	int planea_wm, planeb_wm;
+	struct intel_crtc *enabled = NULL;
+
+	crtc->wm.active.i9xx = crtc->config->wm.i9xx.optimal;
+
+	crtc = intel_get_crtc_for_plane(dev_priv, 0);
+	planea_wm = crtc->wm.active.i9xx.plane_wm;
+	if (intel_crtc_active(crtc))
+		enabled = crtc;
+
+	crtc = intel_get_crtc_for_plane(dev_priv, 1);
+	if (intel_crtc_active(crtc)) {
 		if (enabled == NULL)
 			enabled = crtc;
 		else
 			enabled = NULL;
-	} else {
-		planeb_wm = fifo_size - wm_info->guard_size;
-		if (planeb_wm > (long)wm_info->max_wm)
-			planeb_wm = wm_info->max_wm;
 	}
+	planeb_wm = crtc->wm.active.i9xx.plane_wm;
 
 	DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
 
-	if (IS_I915GM(dev_priv) && enabled) {
-		struct drm_i915_gem_object *obj;
-
-		obj = intel_fb_obj(enabled->base.primary->state->fb);
-
-		/* self-refresh seems busted with untiled */
-		if (!i915_gem_object_is_tiled(obj))
-			enabled = NULL;
-	}
+	if (!enabled->wm.active.i9xx.cxsr)
+		enabled = NULL;
 
 	/*
 	 * Overlay gets an aggressive default since video jitter is bad.
@@ -2337,31 +2402,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
 	intel_set_memory_cxsr(dev_priv, false);
 
 	/* Calc sr entries for one plane configs */
-	if (HAS_FW_BLC(dev_priv) && enabled) {
-		/* self-refresh has much higher latency */
-		static const int sr_latency_ns = 6000;
-		const struct drm_display_mode *adjusted_mode =
-			&enabled->config->base.adjusted_mode;
-		const struct drm_framebuffer *fb =
-			enabled->base.primary->state->fb;
-		int clock = adjusted_mode->crtc_clock;
-		int htotal = adjusted_mode->crtc_htotal;
-		int hdisplay = enabled->config->pipe_src_w;
-		int cpp;
-		int entries;
-
-		if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
-			cpp = 4;
-		else
-			cpp = fb->format->cpp[0];
-
-		entries = intel_wm_method2(clock, htotal, hdisplay, cpp,
-					   sr_latency_ns / 100);
-		entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
-		DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
-		srwm = wm_info->fifo_size - entries;
-		if (srwm < 0)
-			srwm = 1;
+	if (enabled && enabled->wm.active.i9xx.cxsr) {
+		srwm = enabled->wm.active.i9xx.sr.plane_wm;
 
 		if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
 			I915_WRITE(FW_BLC_SELF,
@@ -2387,23 +2429,18 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
 		intel_set_memory_cxsr(dev_priv, true);
 }
 
-static void i845_update_wm(struct intel_crtc *unused_crtc)
+static void i845_update_wm(struct intel_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
-	struct intel_crtc *crtc;
-	const struct drm_display_mode *adjusted_mode;
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	uint32_t fwater_lo;
 	int planea_wm;
 
-	crtc = single_enabled_crtc(dev_priv);
-	if (crtc == NULL)
+	if (!intel_crtc_active(crtc))
 		return;
 
-	adjusted_mode = &crtc->config->base.adjusted_mode;
-	planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
-				       &i845_wm_info,
-				       dev_priv->display.get_fifo_size(dev_priv, 0),
-				       4, pessimal_latency_ns);
+	crtc->wm.active.i9xx = crtc->config->wm.i9xx.optimal;
+	planea_wm = crtc->wm.active.i9xx.plane_wm;
+
 	fwater_lo = I915_READ(FW_BLC) & ~0xfff;
 	fwater_lo |= (3<<8) | planea_wm;
 
@@ -9003,9 +9040,13 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
 	} else if (IS_GEN4(dev_priv)) {
 		dev_priv->display.update_wm = i965_update_wm;
 	} else if (IS_GEN3(dev_priv)) {
+		dev_priv->display.compute_pipe_wm = i9xx_compute_pipe_wm;
 		dev_priv->display.update_wm = i9xx_update_wm;
+
 		dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
 	} else if (IS_GEN2(dev_priv)) {
+		dev_priv->display.compute_pipe_wm = i9xx_compute_pipe_wm;
+
 		if (INTEL_INFO(dev_priv)->num_pipes == 1) {
 			dev_priv->display.update_wm = i845_update_wm;
 			dev_priv->display.get_fifo_size = i845_get_fifo_size;
-- 
2.14.1

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[PATCH v2 2/6] drm/i915: Program gen3- watermarks atomically

[Maarten Lankhorst]

With the atomic watermark calculations calculate intermediary watermark
values and update the watermarks atomically.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h  |   5 +
 drivers/gpu/drm/i915/intel_drv.h |   5 +-
 drivers/gpu/drm/i915/intel_pm.c  | 241 +++++++++++++++++++++++++++++----------
 3 files changed, 191 insertions(+), 60 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1cc31a5b049f..e67c46b6eb98 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1811,6 +1811,10 @@ struct g4x_wm_values {
 	bool fbc_en;
 };
 
+struct i9xx_wm_values {
+	bool cxsr;
+};
+
 struct skl_ddb_entry {
 	uint16_t start, end;	/* in number of blocks, 'end' is exclusive */
 };
@@ -2492,6 +2496,7 @@ struct drm_i915_private {
 			struct skl_wm_values skl_hw;
 			struct vlv_wm_values vlv;
 			struct g4x_wm_values g4x;
+			struct i9xx_wm_values i9xx;
 		};
 
 		uint8_t max_level;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 78554f23e264..81937048ff43 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -555,7 +555,8 @@ struct i9xx_wm_state {
 
 	struct {
 		uint16_t plane_wm;
-	} sr;
+		uint16_t cursor_wm;
+	} sr, hpll;
 };
 
 struct intel_crtc_wm_state {
@@ -604,7 +605,7 @@ struct intel_crtc_wm_state {
 		} g4x;
 
 		struct {
-			struct i9xx_wm_state optimal;
+			struct i9xx_wm_state optimal, intermediate;
 		} i9xx;
 	};
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6f7be0a2be05..b4f479072cba 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -459,6 +459,8 @@ bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 		dev_priv->wm.vlv.cxsr = enable;
 	else if (IS_G4X(dev_priv))
 		dev_priv->wm.g4x.cxsr = enable;
+	else if (INTEL_GEN(dev_priv) <= 4)
+		dev_priv->wm.i9xx.cxsr = enable;
 	mutex_unlock(&dev_priv->wm.wm_mutex);
 
 	return ret;
@@ -846,13 +848,17 @@ static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
 	return enabled;
 }
 
-static void pineview_update_wm(struct intel_crtc *unused_crtc)
+static int pnv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
-	struct intel_crtc *crtc;
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct i9xx_wm_state *wm_state = &crtc_state->wm.i9xx.optimal;
+	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
+	struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->base.state);
+	const struct drm_plane_state *primary_plane_state = NULL;
 	const struct cxsr_latency *latency;
-	u32 reg;
-	unsigned int wm;
+
+	memset(wm_state, 0, sizeof(*wm_state));
 
 	latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
 					 dev_priv->is_ddr3,
@@ -860,60 +866,94 @@ static void pineview_update_wm(struct intel_crtc *unused_crtc)
 					 dev_priv->mem_freq);
 	if (!latency) {
 		DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
-		intel_set_memory_cxsr(dev_priv, false);
-		return;
+
+		return 0;
 	}
 
-	crtc = single_enabled_crtc(dev_priv);
-	if (crtc) {
-		const struct drm_display_mode *adjusted_mode =
-			&crtc->config->base.adjusted_mode;
+	if (crtc_state->base.plane_mask & BIT(drm_plane_index(&plane->base)))
+		primary_plane_state = __drm_atomic_get_current_plane_state(&state->base, &plane->base);
+
+	if (primary_plane_state) {
 		const struct drm_framebuffer *fb =
-			crtc->base.primary->state->fb;
+			primary_plane_state->fb;
 		int cpp = fb->format->cpp[0];
-		int clock = adjusted_mode->crtc_clock;
+		const struct drm_display_mode *adjusted_mode =
+			&crtc_state->base.adjusted_mode;
+		unsigned active_crtcs;
+
+		if (state->modeset)
+			active_crtcs = state->active_crtcs;
+		else
+			active_crtcs = dev_priv->active_crtcs;
+
+		wm_state->cxsr = active_crtcs == drm_crtc_mask(&crtc->base);
+
+		wm_state->sr.plane_wm =
+			intel_calculate_wm(adjusted_mode->crtc_clock,
+					   &pineview_display_wm,
+					   pineview_display_wm.fifo_size,
+					   cpp, latency->display_sr);
+
+		wm_state->sr.cursor_wm =
+			intel_calculate_wm(adjusted_mode->crtc_clock,
+					   &pineview_cursor_wm,
+					   pineview_display_wm.fifo_size,
+					   4, latency->cursor_sr);
+
+		wm_state->hpll.plane_wm =
+			intel_calculate_wm(adjusted_mode->crtc_clock,
+					   &pineview_display_hplloff_wm,
+					   pineview_display_hplloff_wm.fifo_size,
+					   cpp, latency->display_hpll_disable);
+
+		wm_state->hpll.cursor_wm =
+			intel_calculate_wm(adjusted_mode->crtc_clock,
+					   &pineview_cursor_hplloff_wm,
+					   pineview_display_hplloff_wm.fifo_size,
+					   4, latency->cursor_hpll_disable);
+
+		DRM_DEBUG_KMS("FIFO watermarks - can cxsr: %s, display plane %d, cursor SR size: %d\n",
+			      yesno(wm_state->cxsr), wm_state->sr.plane_wm, wm_state->sr.cursor_wm);
+	} else
+		wm_state->cxsr = false;
+
+	return 0;
+}
+
+static void pnv_program_watermarks(struct drm_i915_private *dev_priv)
+{
+	struct intel_crtc *crtc;
+	struct i9xx_wm_state *wm_state = NULL;
+
+	crtc = single_enabled_crtc(dev_priv);
+	if (crtc)
+		wm_state = &crtc->wm.active.i9xx;
+
+	if (wm_state && wm_state->cxsr) {
+		u32 reg;
 
 		/* Display SR */
-		wm = intel_calculate_wm(clock, &pineview_display_wm,
-					pineview_display_wm.fifo_size,
-					cpp, latency->display_sr);
 		reg = I915_READ(DSPFW1);
 		reg &= ~DSPFW_SR_MASK;
-		reg |= FW_WM(wm, SR);
+		reg |= FW_WM(wm_state->sr.plane_wm, SR);
 		I915_WRITE(DSPFW1, reg);
 		DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 
 		/* cursor SR */
-		wm = intel_calculate_wm(clock, &pineview_cursor_wm,
-					pineview_display_wm.fifo_size,
-					4, latency->cursor_sr);
 		reg = I915_READ(DSPFW3);
-		reg &= ~DSPFW_CURSOR_SR_MASK;
-		reg |= FW_WM(wm, CURSOR_SR);
+		reg &= ~(DSPFW_CURSOR_SR_MASK | DSPFW_HPLL_SR_MASK | DSPFW_HPLL_CURSOR_MASK);
+		reg |= FW_WM(wm_state->sr.cursor_wm, CURSOR_SR);
+		reg |= FW_WM(wm_state->hpll.plane_wm, HPLL_SR);
+		reg |= FW_WM(wm_state->hpll.cursor_wm, HPLL_SR);
 		I915_WRITE(DSPFW3, reg);
 
-		/* Display HPLL off SR */
-		wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
-					pineview_display_hplloff_wm.fifo_size,
-					cpp, latency->display_hpll_disable);
-		reg = I915_READ(DSPFW3);
-		reg &= ~DSPFW_HPLL_SR_MASK;
-		reg |= FW_WM(wm, HPLL_SR);
-		I915_WRITE(DSPFW3, reg);
-
-		/* cursor HPLL off SR */
-		wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
-					pineview_display_hplloff_wm.fifo_size,
-					4, latency->cursor_hpll_disable);
-		reg = I915_READ(DSPFW3);
-		reg &= ~DSPFW_HPLL_CURSOR_MASK;
-		reg |= FW_WM(wm, HPLL_CURSOR);
-		I915_WRITE(DSPFW3, reg);
 		DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 
-		intel_set_memory_cxsr(dev_priv, true);
+		_intel_set_memory_cxsr(dev_priv, true);
+		dev_priv->wm.i9xx.cxsr = true;
 	} else {
-		intel_set_memory_cxsr(dev_priv, false);
+		_intel_set_memory_cxsr(dev_priv, false);
+		dev_priv->wm.i9xx.cxsr = false;
 	}
 }
 
@@ -2335,6 +2375,47 @@ static int i9xx_compute_pipe_wm(struct intel_crtc_state *crtc_state)
 	return 0;
 }
 
+static int i9xx_compute_intermediate_wm(struct drm_device *dev,
+				       struct intel_crtc *intel_crtc,
+				       struct intel_crtc_state *newstate)
+{
+	struct i9xx_wm_state *intermediate = &newstate->wm.i9xx.intermediate;
+	const struct drm_crtc_state *old_drm_state =
+		drm_atomic_get_old_crtc_state(newstate->base.state, &intel_crtc->base);
+	const struct i9xx_wm_state *old = &to_intel_crtc_state(old_drm_state)->wm.i9xx.optimal;
+	const struct i9xx_wm_state *optimal = &newstate->wm.i9xx.optimal;
+
+	/*
+	 * Start with the final, target watermarks, then combine with the
+	 * currently active watermarks to get values that are safe both before
+	 * and after the vblank.
+	 */
+	*intermediate = *optimal;
+	if (newstate->disable_cxsr)
+		intermediate->cxsr = false;
+
+	if (!newstate->base.active ||
+	    drm_atomic_crtc_needs_modeset(&newstate->base))
+		goto out;
+
+	intermediate->plane_wm = min(old->plane_wm, optimal->plane_wm);
+	intermediate->sr.plane_wm = min(old->sr.plane_wm, optimal->sr.plane_wm);
+	intermediate->sr.cursor_wm = min(old->sr.cursor_wm, optimal->sr.cursor_wm);
+	intermediate->hpll.plane_wm = min(old->hpll.plane_wm, optimal->hpll.plane_wm);
+	intermediate->hpll.cursor_wm = min(old->hpll.cursor_wm, optimal->hpll.cursor_wm);
+
+out:
+	/*
+	 * If our intermediate WM are identical to the final WM, then we can
+	 * omit the post-vblank programming; only update if it's different.
+	 */
+	if (newstate->base.active &&
+	    memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
+		newstate->wm.need_postvbl_update = true;
+
+	return 0;
+}
+
 void i9xx_wm_get_hw_state(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
@@ -2363,17 +2444,15 @@ void i9xx_wm_get_hw_state(struct drm_device *dev)
 	}
 }
 
-static void i9xx_update_wm(struct intel_crtc *crtc)
+static void i9xx_program_watermarks(struct drm_i915_private *dev_priv)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct intel_crtc *crtc;
 	uint32_t fwater_lo;
 	uint32_t fwater_hi;
 	int cwm, srwm = -1;
 	int planea_wm, planeb_wm;
 	struct intel_crtc *enabled = NULL;
 
-	crtc->wm.active.i9xx = crtc->config->wm.i9xx.optimal;
-
 	crtc = intel_get_crtc_for_plane(dev_priv, 0);
 	planea_wm = crtc->wm.active.i9xx.plane_wm;
 	if (intel_crtc_active(crtc))
@@ -2399,7 +2478,7 @@ static void i9xx_update_wm(struct intel_crtc *crtc)
 	cwm = 2;
 
 	/* Play safe and disable self-refresh before adjusting watermarks. */
-	intel_set_memory_cxsr(dev_priv, false);
+	_intel_set_memory_cxsr(dev_priv, false);
 
 	/* Calc sr entries for one plane configs */
 	if (enabled && enabled->wm.active.i9xx.cxsr) {
@@ -2426,19 +2505,17 @@ static void i9xx_update_wm(struct intel_crtc *crtc)
 	I915_WRITE(FW_BLC2, fwater_hi);
 
 	if (enabled)
-		intel_set_memory_cxsr(dev_priv, true);
+		_intel_set_memory_cxsr(dev_priv, true);
+
+	dev_priv->wm.i9xx.cxsr = enabled;
 }
 
-static void i845_update_wm(struct intel_crtc *crtc)
+static void i845_program_watermarks(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	uint32_t fwater_lo;
 	int planea_wm;
 
-	if (!intel_crtc_active(crtc))
-		return;
-
-	crtc->wm.active.i9xx = crtc->config->wm.i9xx.optimal;
 	planea_wm = crtc->wm.active.i9xx.plane_wm;
 
 	fwater_lo = I915_READ(FW_BLC) & ~0xfff;
@@ -2449,6 +2526,45 @@ static void i845_update_wm(struct intel_crtc *crtc)
 	I915_WRITE(FW_BLC, fwater_lo);
 }
 
+
+static void i9xx_initial_watermarks(struct intel_atomic_state *state,
+				   struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+
+	mutex_lock(&dev_priv->wm.wm_mutex);
+	crtc->wm.active.i9xx = crtc_state->wm.i9xx.intermediate;
+	if (IS_PINEVIEW(dev_priv))
+		pnv_program_watermarks(dev_priv);
+	else if (INTEL_INFO(dev_priv)->num_pipes == 1)
+		i845_program_watermarks(intel_crtc);
+	else
+		i9xx_program_watermarks(dev_priv);
+	mutex_unlock(&dev_priv->wm.wm_mutex);
+}
+
+static void i9xx_optimize_watermarks(struct intel_atomic_state *state,
+				    struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+
+	if (!crtc_state->wm.need_postvbl_update)
+		return;
+
+	mutex_lock(&dev_priv->wm.wm_mutex);
+	intel_crtc->wm.active.i9xx = crtc_state->wm.i9xx.optimal;
+	if (IS_PINEVIEW(dev_priv))
+		pnv_program_watermarks(dev_priv);
+	else if (INTEL_INFO(dev_priv)->num_pipes == 1)
+		i845_program_watermarks(intel_crtc);
+	else
+		i9xx_program_watermarks(dev_priv);
+	mutex_unlock(&dev_priv->wm.wm_mutex);
+}
+
 /* latency must be in 0.1us units. */
 static unsigned int ilk_wm_method1(unsigned int pixel_rate,
 				   unsigned int cpp,
@@ -9034,24 +9150,33 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
 				 dev_priv->fsb_freq, dev_priv->mem_freq);
 			/* Disable CxSR and never update its watermark again */
 			intel_set_memory_cxsr(dev_priv, false);
-			dev_priv->display.update_wm = NULL;
-		} else
-			dev_priv->display.update_wm = pineview_update_wm;
+			dev_priv->display.compute_pipe_wm = NULL;
+			dev_priv->display.initial_watermarks = NULL;
+			dev_priv->display.optimize_watermarks = NULL;
+		} else {
+			dev_priv->display.compute_pipe_wm = pnv_compute_pipe_wm;
+			dev_priv->display.initial_watermarks = i9xx_initial_watermarks;
+			dev_priv->display.optimize_watermarks = i9xx_optimize_watermarks;
+		}
 	} else if (IS_GEN4(dev_priv)) {
 		dev_priv->display.update_wm = i965_update_wm;
 	} else if (IS_GEN3(dev_priv)) {
 		dev_priv->display.compute_pipe_wm = i9xx_compute_pipe_wm;
-		dev_priv->display.update_wm = i9xx_update_wm;
+		dev_priv->display.compute_intermediate_wm = i9xx_compute_intermediate_wm;
+
+		dev_priv->display.initial_watermarks = i9xx_initial_watermarks;
+		dev_priv->display.optimize_watermarks = i9xx_optimize_watermarks;
 
 		dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
 	} else if (IS_GEN2(dev_priv)) {
 		dev_priv->display.compute_pipe_wm = i9xx_compute_pipe_wm;
+		dev_priv->display.compute_intermediate_wm = i9xx_compute_intermediate_wm;
+		dev_priv->display.initial_watermarks = i9xx_initial_watermarks;
+		dev_priv->display.optimize_watermarks = i9xx_optimize_watermarks;
 
 		if (INTEL_INFO(dev_priv)->num_pipes == 1) {
-			dev_priv->display.update_wm = i845_update_wm;
 			dev_priv->display.get_fifo_size = i845_get_fifo_size;
 		} else {
-			dev_priv->display.update_wm = i9xx_update_wm;
 			dev_priv->display.get_fifo_size = i830_get_fifo_size;
 		}
 	} else {
-- 
2.14.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v2 3/6] drm/i915: Calculate gen4 watermarks semiatomically.

[Maarten Lankhorst]

Gen4 watermark is handled same as gen3-. Calculate
the optimal watermarks atomically first, and program
it in the legacy helper.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 141 ++++++++++++++++++++++++++++------------
 1 file changed, 100 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b4f479072cba..093c4b35522a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2209,58 +2209,114 @@ static void vlv_optimize_watermarks(struct intel_atomic_state *state,
 	mutex_unlock(&dev_priv->wm.wm_mutex);
 }
 
-static void i965_update_wm(struct intel_crtc *unused_crtc)
+static int i965_compute_pipe_wm(struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
-	struct intel_crtc *crtc;
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct intel_atomic_state *state =
+		to_intel_atomic_state(crtc_state->base.state);
+	struct i9xx_wm_state *wm_state = &crtc_state->wm.i9xx.optimal;
+	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
+	const struct drm_plane_state *primary_plane_state = NULL;
+	const struct drm_plane_state *cursor_plane_state = NULL;
+
+	memset(wm_state, 0, sizeof(*wm_state));
+
+	if (crtc_state->base.plane_mask & BIT(drm_plane_index(&plane->base)))
+		primary_plane_state = __drm_atomic_get_current_plane_state(&state->base, &plane->base);
+
+	if (crtc_state->base.plane_mask & BIT(drm_plane_index(crtc->base.cursor)))
+		cursor_plane_state = __drm_atomic_get_current_plane_state(&state->base, crtc->base.cursor);
+
+	if (primary_plane_state) {
+		static const int sr_latency_ns = 12000;
+		const struct drm_display_mode *adjusted_mode =
+			&crtc_state->base.adjusted_mode;
+		unsigned active_crtcs;
+		unsigned long entries;
+		bool may_cxsr;
+
+		if (state->modeset)
+			active_crtcs = state->active_crtcs;
+		else
+			active_crtcs = dev_priv->active_crtcs;
+
+		may_cxsr = active_crtcs == drm_crtc_mask(&crtc->base);
+
+		if (may_cxsr && intel_wm_plane_visible(crtc_state, to_intel_plane_state(primary_plane_state))) {
+			struct drm_framebuffer *fb = primary_plane_state->fb;
+			unsigned cpp = fb->format->cpp[0];
+
+			entries = intel_wm_method2(adjusted_mode->crtc_clock,
+						   adjusted_mode->crtc_htotal,
+						   crtc_state->pipe_src_w, cpp,
+						   sr_latency_ns / 100);
+			entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
+			if (entries < I965_FIFO_SIZE)
+				wm_state->sr.plane_wm = I965_FIFO_SIZE - entries;
+			else
+				may_cxsr = false;
+
+			DRM_DEBUG_KMS("self-refresh entries: %ld\n", entries);
+		}
+
+		/*
+		 * No need to use intel_wm_plane_visible here, since having
+		 * a non-null cursor_plane_state means the cursor is bound
+		 * to a fb and is always treated as visible.
+		 */
+		if (may_cxsr && cursor_plane_state && crtc_state->base.active) {
+			entries = intel_wm_method2(adjusted_mode->crtc_clock,
+						   adjusted_mode->crtc_htotal,
+						   cursor_plane_state->crtc_w, 4,
+						   sr_latency_ns / 100);
+
+			entries = DIV_ROUND_UP(entries,
+					      i965_cursor_wm_info.cacheline_size) +
+				i965_cursor_wm_info.guard_size;
+
+			if (entries < i965_cursor_wm_info.fifo_size)
+				wm_state->sr.cursor_wm =
+					min(i965_cursor_wm_info.fifo_size - entries,
+					    (unsigned long)(i965_cursor_wm_info.max_wm));
+			else
+				may_cxsr = false;
+		} else if (may_cxsr)
+			wm_state->sr.cursor_wm = 16;
+
+		wm_state->cxsr = may_cxsr;
+
+		DRM_DEBUG_KMS("FIFO watermarks - can cxsr: %s, display plane %d, cursor SR size: %d\n",
+			      yesno(wm_state->cxsr), wm_state->sr.plane_wm, wm_state->sr.cursor_wm);
+	}
+
+	return 0;
+}
+
+static void i965_update_wm(struct intel_crtc *crtc)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	int srwm = 1;
 	int cursor_sr = 16;
-	bool cxsr_enabled;
+	bool cxsr_enabled = false;
+
+	crtc->wm.active.i9xx = crtc->config->wm.i9xx.optimal;
 
 	/* Calc sr entries for one plane configs */
 	crtc = single_enabled_crtc(dev_priv);
-	if (crtc) {
-		/* self-refresh has much higher latency */
-		static const int sr_latency_ns = 12000;
-		const struct drm_display_mode *adjusted_mode =
-			&crtc->config->base.adjusted_mode;
-		const struct drm_framebuffer *fb =
-			crtc->base.primary->state->fb;
-		int clock = adjusted_mode->crtc_clock;
-		int htotal = adjusted_mode->crtc_htotal;
-		int hdisplay = crtc->config->pipe_src_w;
-		int cpp = fb->format->cpp[0];
-		int entries;
-
-		entries = intel_wm_method2(clock, htotal,
-					   hdisplay, cpp, sr_latency_ns / 100);
-		entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
-		srwm = I965_FIFO_SIZE - entries;
-		if (srwm < 0)
-			srwm = 1;
-		srwm &= 0x1ff;
-		DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
-			      entries, srwm);
-
-		entries = intel_wm_method2(clock, htotal,
-					   crtc->base.cursor->state->crtc_w, 4,
-					   sr_latency_ns / 100);
-		entries = DIV_ROUND_UP(entries,
-				       i965_cursor_wm_info.cacheline_size) +
-			i965_cursor_wm_info.guard_size;
-
-		cursor_sr = i965_cursor_wm_info.fifo_size - entries;
-		if (cursor_sr > i965_cursor_wm_info.max_wm)
-			cursor_sr = i965_cursor_wm_info.max_wm;
+	if (crtc && crtc->wm.active.i9xx.cxsr) {
+		struct i9xx_wm_state *wm_state = &crtc->wm.active.i9xx;
+
+		srwm = wm_state->sr.plane_wm;
+		cursor_sr = wm_state->sr.cursor_wm;
 
 		DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
 			      "cursor %d\n", srwm, cursor_sr);
 
 		cxsr_enabled = true;
-	} else {
-		cxsr_enabled = false;
+	} else if (dev_priv->wm.i9xx.cxsr) {
 		/* Turn off self refresh if both pipes are enabled */
-		intel_set_memory_cxsr(dev_priv, false);
+		_intel_set_memory_cxsr(dev_priv, false);
 	}
 
 	DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
@@ -2277,7 +2333,9 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
 	I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
 
 	if (cxsr_enabled)
-		intel_set_memory_cxsr(dev_priv, true);
+		_intel_set_memory_cxsr(dev_priv, true);
+
+	dev_priv->wm.i9xx.cxsr = cxsr_enabled;
 }
 
 #undef FW_WM
@@ -9159,6 +9217,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
 			dev_priv->display.optimize_watermarks = i9xx_optimize_watermarks;
 		}
 	} else if (IS_GEN4(dev_priv)) {
+		dev_priv->display.compute_pipe_wm = i965_compute_pipe_wm;
 		dev_priv->display.update_wm = i965_update_wm;
 	} else if (IS_GEN3(dev_priv)) {
 		dev_priv->display.compute_pipe_wm = i9xx_compute_pipe_wm;
-- 
2.14.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v2 4/6] drm/i915: Program gen4 watermarks atomically

[Maarten Lankhorst]

We're already calculating the watermarks correctly, now we have to
program them too.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 25 +++++++++++++++----------
 1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 093c4b35522a..ddef0568c477 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2293,20 +2293,20 @@ static int i965_compute_pipe_wm(struct intel_crtc_state *crtc_state)
 	return 0;
 }
 
-static void i965_update_wm(struct intel_crtc *crtc)
+static void i965_program_watermarks(struct drm_i915_private *dev_priv)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct intel_crtc *crtc;
+	struct i9xx_wm_state *wm_state = NULL;
 	int srwm = 1;
 	int cursor_sr = 16;
 	bool cxsr_enabled = false;
 
-	crtc->wm.active.i9xx = crtc->config->wm.i9xx.optimal;
-
-	/* Calc sr entries for one plane configs */
 	crtc = single_enabled_crtc(dev_priv);
-	if (crtc && crtc->wm.active.i9xx.cxsr) {
-		struct i9xx_wm_state *wm_state = &crtc->wm.active.i9xx;
+	if (crtc)
+		wm_state = &crtc->wm.active.i9xx;
 
+	/* Calc sr entries for one plane configs */
+	if (wm_state && wm_state->cxsr) {
 		srwm = wm_state->sr.plane_wm;
 		cursor_sr = wm_state->sr.cursor_wm;
 
@@ -2598,8 +2598,10 @@ static void i9xx_initial_watermarks(struct intel_atomic_state *state,
 		pnv_program_watermarks(dev_priv);
 	else if (INTEL_INFO(dev_priv)->num_pipes == 1)
 		i845_program_watermarks(intel_crtc);
-	else
+	else if (INTEL_GEN(dev_priv) < 4)
 		i9xx_program_watermarks(dev_priv);
+	else
+		i965_program_watermarks(dev_priv);
 	mutex_unlock(&dev_priv->wm.wm_mutex);
 }
 
@@ -2618,8 +2620,10 @@ static void i9xx_optimize_watermarks(struct intel_atomic_state *state,
 		pnv_program_watermarks(dev_priv);
 	else if (INTEL_INFO(dev_priv)->num_pipes == 1)
 		i845_program_watermarks(intel_crtc);
-	else
+	else if (INTEL_GEN(dev_priv) < 4)
 		i9xx_program_watermarks(dev_priv);
+	else
+		i965_program_watermarks(dev_priv);
 	mutex_unlock(&dev_priv->wm.wm_mutex);
 }
 
@@ -9218,7 +9222,8 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
 		}
 	} else if (IS_GEN4(dev_priv)) {
 		dev_priv->display.compute_pipe_wm = i965_compute_pipe_wm;
-		dev_priv->display.update_wm = i965_update_wm;
+		dev_priv->display.initial_watermarks = i9xx_initial_watermarks;
+		dev_priv->display.optimize_watermarks = i9xx_optimize_watermarks;
 	} else if (IS_GEN3(dev_priv)) {
 		dev_priv->display.compute_pipe_wm = i9xx_compute_pipe_wm;
 		dev_priv->display.compute_intermediate_wm = i9xx_compute_intermediate_wm;
-- 
2.14.1

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[PATCH v2 5/6] drm/i915: Kill off intel_crtc_active.

[Maarten Lankhorst]

Use crtc->active directly instead. This is still not completely
optimal and needs fixing, but it's about as good as using
intel_crtc_active.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 19 -------------------
 drivers/gpu/drm/i915/intel_drv.h     |  1 -
 drivers/gpu/drm/i915/intel_fbc.c     |  2 +-
 drivers/gpu/drm/i915/intel_pm.c      |  6 +++---
 4 files changed, 4 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f0e5ab2ac2ee..6d051e372327 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -973,25 +973,6 @@ bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 				  target_clock, refclk, NULL, best_clock);
 }
 
-bool intel_crtc_active(struct intel_crtc *crtc)
-{
-	/* Be paranoid as we can arrive here with only partial
-	 * state retrieved from the hardware during setup.
-	 *
-	 * We can ditch the adjusted_mode.crtc_clock check as soon
-	 * as Haswell has gained clock readout/fastboot support.
-	 *
-	 * We can ditch the crtc->primary->fb check as soon as we can
-	 * properly reconstruct framebuffers.
-	 *
-	 * FIXME: The intel_crtc->active here should be switched to
-	 * crtc->state->active once we have proper CRTC states wired up
-	 * for atomic.
-	 */
-	return crtc->active && crtc->base.primary->state->fb &&
-		crtc->config->base.adjusted_mode.crtc_clock;
-}
-
 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 					     enum pipe pipe)
 {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 81937048ff43..44f524849b41 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1493,7 +1493,6 @@ bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 			struct dpll *best_clock);
 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
 
-bool intel_crtc_active(struct intel_crtc *crtc);
 void hsw_enable_ips(struct intel_crtc *crtc);
 void hsw_disable_ips(struct intel_crtc *crtc);
 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 58a772de6672..286bffdda5f7 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -1294,7 +1294,7 @@ void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv)
 		return;
 
 	for_each_intel_crtc(&dev_priv->drm, crtc)
-		if (intel_crtc_active(crtc) &&
+		if (crtc->base.state->active &&
 		    crtc->base.primary->state->visible)
 			dev_priv->fbc.visible_pipes_mask |= (1 << crtc->pipe);
 }
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ddef0568c477..67c8e8fcbe76 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -838,7 +838,7 @@ static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
 	struct intel_crtc *crtc, *enabled = NULL;
 
 	for_each_intel_crtc(&dev_priv->drm, crtc) {
-		if (intel_crtc_active(crtc)) {
+		if (crtc->active) {
 			if (enabled)
 				return NULL;
 			enabled = crtc;
@@ -2513,11 +2513,11 @@ static void i9xx_program_watermarks(struct drm_i915_private *dev_priv)
 
 	crtc = intel_get_crtc_for_plane(dev_priv, 0);
 	planea_wm = crtc->wm.active.i9xx.plane_wm;
-	if (intel_crtc_active(crtc))
+	if (crtc->active)
 		enabled = crtc;
 
 	crtc = intel_get_crtc_for_plane(dev_priv, 1);
-	if (intel_crtc_active(crtc)) {
+	if (crtc->active) {
 		if (enabled == NULL)
 			enabled = crtc;
 		else
-- 
2.14.1

_______________________________________________
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[PATCH v2 6/6] drm/i915: Rip out legacy watermark infrastructure

[Maarten Lankhorst]

The legacy watermark infrastructure is now unused, so remove it.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  1 -
 drivers/gpu/drm/i915/intel_atomic.c  |  2 -
 drivers/gpu/drm/i915/intel_display.c | 71 ++----------------------------------
 drivers/gpu/drm/i915/intel_drv.h     |  2 -
 drivers/gpu/drm/i915/intel_pm.c      | 42 ---------------------
 5 files changed, 3 insertions(+), 115 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e67c46b6eb98..554af97abb73 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -711,7 +711,6 @@ struct drm_i915_display_funcs {
 	void (*optimize_watermarks)(struct intel_atomic_state *state,
 				    struct intel_crtc_state *cstate);
 	int (*compute_global_watermarks)(struct drm_atomic_state *state);
-	void (*update_wm)(struct intel_crtc *crtc);
 	int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
 	/* Returns the active state of the crtc, and if the crtc is active,
 	 * fills out the pipe-config with the hw state. */
diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index 36d4e635e4ce..e2b4ca518a04 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -173,8 +173,6 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
 	crtc_state->update_pipe = false;
 	crtc_state->disable_lp_wm = false;
 	crtc_state->disable_cxsr = false;
-	crtc_state->update_wm_pre = false;
-	crtc_state->update_wm_post = false;
 	crtc_state->fb_changed = false;
 	crtc_state->fifo_changed = false;
 	crtc_state->wm.need_postvbl_update = false;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6d051e372327..9f2cddf9f279 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5107,8 +5107,6 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
 
 	intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
 
-	if (pipe_config->update_wm_post && pipe_config->base.active)
-		intel_update_watermarks(crtc);
 
 	if (old_pri_state) {
 		struct intel_plane_state *primary_state =
@@ -5201,8 +5199,6 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
 	if (dev_priv->display.initial_watermarks != NULL)
 		dev_priv->display.initial_watermarks(old_intel_state,
 						     pipe_config);
-	else if (pipe_config->update_wm_pre)
-		intel_update_watermarks(crtc);
 }
 
 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
@@ -5884,8 +5880,6 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
 	if (dev_priv->display.initial_watermarks != NULL)
 		dev_priv->display.initial_watermarks(old_intel_state,
 						     intel_crtc->config);
-	else
-		intel_update_watermarks(intel_crtc);
 	intel_enable_pipe(intel_crtc);
 
 	assert_vblank_disabled(crtc);
@@ -5950,9 +5944,6 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
 	if (!IS_GEN2(dev_priv))
 		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
 
-	if (!dev_priv->display.initial_watermarks)
-		intel_update_watermarks(intel_crtc);
-
 	/* clock the pipe down to 640x480@60 to potentially save power */
 	if (IS_I830(dev_priv))
 		i830_enable_pipe(dev_priv, pipe);
@@ -6013,7 +6004,6 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
 		encoder->base.crtc = NULL;
 
 	intel_fbc_disable(intel_crtc);
-	intel_update_watermarks(intel_crtc);
 	intel_disable_shared_dpll(intel_crtc);
 
 	domains = intel_crtc->enabled_power_domains;
@@ -10290,40 +10280,6 @@ static void intel_crtc_destroy(struct drm_crtc *crtc)
 	kfree(intel_crtc);
 }
 
-/**
- * intel_wm_need_update - Check whether watermarks need updating
- * @plane: drm plane
- * @state: new plane state
- *
- * Check current plane state versus the new one to determine whether
- * watermarks need to be recalculated.
- *
- * Returns true or false.
- */
-static bool intel_wm_need_update(struct drm_plane *plane,
-				 struct drm_plane_state *state)
-{
-	struct intel_plane_state *new = to_intel_plane_state(state);
-	struct intel_plane_state *cur = to_intel_plane_state(plane->state);
-
-	/* Update watermarks on tiling or size changes. */
-	if (new->base.visible != cur->base.visible)
-		return true;
-
-	if (!cur->base.fb || !new->base.fb)
-		return false;
-
-	if (cur->base.fb->modifier != new->base.fb->modifier ||
-	    cur->base.rotation != new->base.rotation ||
-	    drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
-	    drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
-	    drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
-	    drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
-		return true;
-
-	return false;
-}
-
 static bool needs_scaling(const struct intel_plane_state *state)
 {
 	int src_w = drm_rect_width(&state->base.src) >> 16;
@@ -10400,27 +10356,9 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
 			 was_visible, visible,
 			 turn_off, turn_on, mode_changed);
 
-	if (turn_on) {
-		if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
-			pipe_config->update_wm_pre = true;
-
-		/* must disable cxsr around plane enable/disable */
-		if (plane->id != PLANE_CURSOR)
-			pipe_config->disable_cxsr = true;
-	} else if (turn_off) {
-		if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
-			pipe_config->update_wm_post = true;
-
-		/* must disable cxsr around plane enable/disable */
-		if (plane->id != PLANE_CURSOR)
-			pipe_config->disable_cxsr = true;
-	} else if (intel_wm_need_update(&plane->base, plane_state)) {
-		if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
-			/* FIXME bollocks */
-			pipe_config->update_wm_pre = true;
-			pipe_config->update_wm_post = true;
-		}
-	}
+	/* must disable cxsr around plane enable/disable */
+	if ((turn_on || turn_off) && plane->id != PLANE_CURSOR)
+		pipe_config->disable_cxsr = true;
 
 	if (visible || was_visible)
 		pipe_config->fb_bits |= plane->frontbuffer_bit;
@@ -10481,9 +10419,6 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
 	int ret;
 	bool mode_changed = needs_modeset(crtc_state);
 
-	if (mode_changed && !crtc_state->active)
-		pipe_config->update_wm_post = true;
-
 	if (mode_changed && crtc_state->enable &&
 	    dev_priv->display.crtc_compute_clock &&
 	    !WARN_ON(pipe_config->shared_dpll)) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 44f524849b41..8d32a24c6c22 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -635,7 +635,6 @@ struct intel_crtc_state {
 	unsigned fb_bits; /* framebuffers to flip */
 	bool update_pipe; /* can a fast modeset be performed? */
 	bool disable_cxsr;
-	bool update_wm_pre, update_wm_post; /* watermarks are updated */
 	bool fb_changed; /* fb on any of the planes is changed */
 	bool fifo_changed; /* FIFO split is changed */
 
@@ -1872,7 +1871,6 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
 void intel_suspend_hw(struct drm_i915_private *dev_priv);
 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
-void intel_update_watermarks(struct intel_crtc *crtc);
 void intel_init_pm(struct drm_i915_private *dev_priv);
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
 void intel_pm_setup(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 67c8e8fcbe76..af69280bc5d1 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5312,8 +5312,6 @@ skl_compute_wm(struct drm_atomic_state *state)
 		if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
 			/* This pipe's WM's did not change */
 			continue;
-
-		intel_cstate->update_wm_pre = true;
 	}
 
 	skl_print_wm_changes(state);
@@ -5999,46 +5997,6 @@ void ilk_wm_get_hw_state(struct drm_device *dev)
 		!(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
 }
 
-/**
- * intel_update_watermarks - update FIFO watermark values based on current modes
- *
- * Calculate watermark values for the various WM regs based on current mode
- * and plane configuration.
- *
- * There are several cases to deal with here:
- *   - normal (i.e. non-self-refresh)
- *   - self-refresh (SR) mode
- *   - lines are large relative to FIFO size (buffer can hold up to 2)
- *   - lines are small relative to FIFO size (buffer can hold more than 2
- *     lines), so need to account for TLB latency
- *
- *   The normal calculation is:
- *     watermark = dotclock * bytes per pixel * latency
- *   where latency is platform & configuration dependent (we assume pessimal
- *   values here).
- *
- *   The SR calculation is:
- *     watermark = (trunc(latency/line time)+1) * surface width *
- *       bytes per pixel
- *   where
- *     line time = htotal / dotclock
- *     surface width = hdisplay for normal plane and 64 for cursor
- *   and latency is assumed to be high, as above.
- *
- * The final value programmed to the register should always be rounded up,
- * and include an extra 2 entries to account for clock crossings.
- *
- * We don't use the sprite, so we can ignore that.  And on Crestline we have
- * to set the non-SR watermarks to 8.
- */
-void intel_update_watermarks(struct intel_crtc *crtc)
-{
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-
-	if (dev_priv->display.update_wm)
-		dev_priv->display.update_wm(crtc);
-}
-
 void intel_enable_ipc(struct drm_i915_private *dev_priv)
 {
 	u32 val;
-- 
2.14.1

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✓ Fi.CI.BAT: success for drm/i915: Convert gen4- watermarks to atomic. (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: Convert gen4- watermarks to atomic. (rev4)
URL   : https://patchwork.freedesktop.org/series/23954/
State : success

== Summary ==

Series 23954v4 drm/i915: Convert gen4- watermarks to atomic.
https://patchwork.freedesktop.org/api/1.0/series/23954/revisions/4/mbox/

fi-bdw-5557u     total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  time:439s
fi-bdw-gvtdvm    total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:454s
fi-blb-e6850     total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  time:380s
fi-bsw-n3050     total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  time:530s
fi-bwr-2160      total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 time:271s
fi-bxt-j4205     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:510s
fi-byt-j1900     total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  time:502s
fi-byt-n2820     total:289  pass:250  dwarn:1   dfail:0   fail:0   skip:38  time:495s
fi-cfl-s         total:289  pass:222  dwarn:35  dfail:0   fail:0   skip:32  time:550s
fi-elk-e7500     total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  time:444s
fi-glk-2a        total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:590s
fi-hsw-4770      total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:430s
fi-hsw-4770r     total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:408s
fi-ilk-650       total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  time:436s
fi-ivb-3520m     total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:485s
fi-ivb-3770      total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:461s
fi-kbl-7500u     total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  time:486s
fi-kbl-7560u     total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  time:576s
fi-kbl-r         total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:586s
fi-pnv-d510      total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  time:555s
fi-skl-6260u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:457s
fi-skl-6700k     total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:514s
fi-skl-6770hq    total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:494s
fi-skl-gvtdvm    total:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  time:465s
fi-skl-x1585l    total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  time:474s
fi-snb-2520m     total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  time:567s
fi-snb-2600      total:289  pass:249  dwarn:0   dfail:0   fail:1   skip:39  time:426s

3a1a0bacb6e4e1dceb233c927d859e33b62dabaa drm-tip: 2017y-09m-13d-08h-04m-49s UTC integration manifest
38a8be193df9 drm/i915: Rip out legacy watermark infrastructure
7aa07096059f drm/i915: Kill off intel_crtc_active.
9d281ae94cdb drm/i915: Program gen4 watermarks atomically
737c6f68e76b drm/i915: Calculate gen4 watermarks semiatomically.
f776467bf60b drm/i915: Program gen3- watermarks atomically
930d90d591a2 drm/i915: Calculate gen3- watermarks semi-atomically, v3.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5673/
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✗ Fi.CI.IGT: failure for drm/i915: Convert gen4- watermarks to atomic. (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: Convert gen4- watermarks to atomic. (rev4)
URL   : https://patchwork.freedesktop.org/series/23954/
State : failure

== Summary ==

Test kms_setmode:
        Subgroup basic:
                fail       -> PASS       (shard-hsw) fdo#99912
Test kms_flip:
        Subgroup wf_vblank-vs-modeset:
                dmesg-warn -> PASS       (shard-hsw)
        Subgroup flip-vs-wf_vblank-interruptible:
                pass       -> FAIL       (shard-hsw)
Test kms_plane:
        Subgroup plane-panning-bottom-right-suspend-pipe-C-planes:
                skip       -> PASS       (shard-hsw)

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-hsw        total:2419 pass:1322 dwarn:2   dfail:0   fail:14  skip:1081 time:9662s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5673/shards.html
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