* [Qemu-devel] [PATCH v2 0/5] generalize parsing of cpu_model (x86/arm)
@ 2017-09-13 16:04 Igor Mammedov
2017-09-13 16:04 ` [Qemu-devel] [PATCH v2 1/5] qom: cpus: split cpu_generic_init() on feature parsing and cpu creation parts Igor Mammedov
` (5 more replies)
0 siblings, 6 replies; 17+ messages in thread
From: Igor Mammedov @ 2017-09-13 16:04 UTC (permalink / raw)
To: qemu-devel
Changelog since v1:
* fix merge conflicts with ignore_memory_transaction_failures
* fix couple merge conflicts where SoC type string where replaced by type macro
* keep plain prefix string in: strncmp(cpu_type, "pxa27", 5)
* s/"%s" ARM_CPU_TYPE_SUFFIX/ARM_CPU_TYPE_NAME("%s")/
* drop not needed assert
* instead of checking error/reporting/exiting explicitly
use error_fatal which will do all of it for us
* squash in "cpu: rename cpu_parse_features() to cpu_parse_cpu_model()"
Issue 1:
Some callers call CPUClass->parse_features manually to convert
'-cpu cpufoo,featurestr' string to cpu type and featurestr
into a set of global properties and then do controlled
cpu creation with setting properties and completing it with realize.
That's a lot of code duplication as they all are practically
reimplement the same parsing logic.
Some use cpu_generic_init() instead which does the same parsing
along with creation/realizing cpu within one wrapper.
And some trying to switch to controlled cpu creation,
implement object_new()/set properties/realize steps
but forget feature parsing logic witch leads to 'bugs'
commit (00909b585 hw/arm/integratorcp: Support specifying features via -cpu)
Issue 2:
Default cpu model selection logic is spread over all board's
machine_init() fuctions but it's basicallyi hardcodes default
cpu model string in init function.
if (!cpu_model) {
cpu_model = "some cpu model string";
}
and written in different ways.
it forces machine_init callbacks to parse cpu_model string
either by using cpu_generic_init() or by manually calling
cpu_class_by_name()/CPUClass::parse_features to perform
name to cpu type translation.
This series moves -cpu option parsing to generic machine code
that removes some of code duplication and makes cpus creation
process more generic/simple:
* unify default (fallback) cpu type handling by replacing
hardcoded cpu_model strings with cpu type directly in
machine_foo_class_init() {
MachineClass::default_cpu_type = BOARD_DEFAULT_CPU_TYPE
}
which allows to generalize move cpu model parsing instead of
parsing it in each board.
* make generic machine vl.c parse cpu_model into properties/cpu_type
and let boards use cpu_type without any cpu_model prasing.
Generic parsing will kick in only if board advertises its support
by setting MachineClass::default_cpu_type to a cpu type.
PS:
I intend make tree-wide conversion but as one series it's too many patches,
so I'm splitting out it into an intial series that implements generic
part and several patchsets that will do per target conversion.
As part of initial series x86 and ARM targets conversion is included
to showcase generalization usage. Per target conversions are done
as 1 patch per target, it might be too much for targets that have lots
of boards (ARM) so let me know if you'd like to split it on per board
basis (then I'll respin it as separate series on top of generic patches)
github tree for testing:
https://github.com/imammedo/qemu.git default_machine_cpu_type_PC_ARM_v2
Igor Mammedov (5):
qom: cpus: split cpu_generic_init() on feature parsing and cpu
creation parts
cpu: make cpu_generic_init() abort QEMU on error
vl.c: convert cpu_model to cpu type and set of global properties
before machine_init()
pc: use generic cpu_model parsing
arm: drop intermediate cpu_model -> cpu type parsing and use cpu type
directly
include/hw/arm/armv7m.h | 2 +-
include/hw/arm/aspeed_soc.h | 2 +-
include/hw/arm/stm32f205_soc.h | 2 +-
include/hw/boards.h | 6 ++++++
include/qom/cpu.h | 22 +++++++++++++++++++
target/arm/cpu.h | 3 +++
target/i386/cpu.h | 9 ++++++++
bsd-user/main.c | 4 ----
hw/alpha/dp264.c | 4 ----
hw/arm/armv7m.c | 40 +++++-----------------------------
hw/arm/aspeed_soc.c | 13 +++++------
hw/arm/collie.c | 10 +++------
hw/arm/exynos4210.c | 6 +-----
hw/arm/gumstix.c | 5 +++--
hw/arm/highbank.c | 10 ++++-----
hw/arm/integratorcp.c | 30 ++------------------------
hw/arm/mainstone.c | 9 ++++----
hw/arm/mps2.c | 17 ++++++---------
hw/arm/musicpal.c | 11 ++--------
hw/arm/netduino2.c | 2 +-
hw/arm/nseries.c | 4 +++-
hw/arm/omap1.c | 11 ++--------
hw/arm/omap2.c | 8 ++-----
hw/arm/omap_sx1.c | 5 ++++-
hw/arm/palm.c | 5 +++--
hw/arm/pxa2xx.c | 18 ++++------------
hw/arm/realview.c | 25 +++++----------------
hw/arm/spitz.c | 12 ++++++-----
hw/arm/stellaris.c | 16 ++++++--------
hw/arm/stm32f205_soc.c | 4 ++--
hw/arm/strongarm.c | 15 +++----------
hw/arm/tosa.c | 4 ----
hw/arm/versatilepb.c | 15 +++----------
hw/arm/vexpress.c | 32 +++++++++------------------
hw/arm/virt.c | 46 ++++++++-------------------------------
hw/arm/xilinx_zynq.c | 10 ++-------
hw/arm/z2.c | 9 +++-----
hw/i386/pc.c | 41 +++++------------------------------
hw/i386/pc_piix.c | 4 +---
hw/lm32/lm32_boards.c | 8 -------
hw/lm32/milkymist.c | 4 ----
hw/m68k/an5206.c | 4 ----
hw/m68k/mcf5208.c | 4 ----
hw/mips/cps.c | 4 ----
hw/mips/mips_fulong2e.c | 4 ----
hw/mips/mips_jazz.c | 4 ----
hw/mips/mips_malta.c | 4 ----
hw/mips/mips_mipssim.c | 4 ----
hw/mips/mips_r4k.c | 4 ----
hw/moxie/moxiesim.c | 4 ----
hw/openrisc/openrisc_sim.c | 4 ----
hw/ppc/e500.c | 4 ----
hw/ppc/mac_newworld.c | 4 ----
hw/ppc/mac_oldworld.c | 4 ----
hw/ppc/ppc440_bamboo.c | 4 ----
hw/ppc/ppc4xx_devs.c | 5 -----
hw/ppc/prep.c | 9 --------
hw/ppc/virtex_ml507.c | 4 ----
hw/sh4/r2d.c | 4 ----
hw/sh4/shix.c | 4 ----
hw/sparc/leon3.c | 4 ----
hw/sparc/sun4m.c | 4 ----
hw/sparc64/sparc64.c | 4 ----
hw/tricore/tricore_testboard.c | 4 ----
hw/unicore32/puv3.c | 4 ----
hw/xtensa/sim.c | 5 -----
hw/xtensa/xtfpga.c | 5 -----
linux-user/main.c | 4 ----
qom/cpu.c | 49 +++++++++++++++++++++++-------------------
target/arm/cpu.c | 2 +-
target/i386/cpu.c | 3 ---
vl.c | 10 +++++++++
72 files changed, 194 insertions(+), 489 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH v2 1/5] qom: cpus: split cpu_generic_init() on feature parsing and cpu creation parts
2017-09-13 16:04 [Qemu-devel] [PATCH v2 0/5] generalize parsing of cpu_model (x86/arm) Igor Mammedov
@ 2017-09-13 16:04 ` Igor Mammedov
2017-09-13 16:04 ` [Qemu-devel] [PATCH v2 2/5] cpu: make cpu_generic_init() abort QEMU on error Igor Mammedov
` (4 subsequent siblings)
5 siblings, 0 replies; 17+ messages in thread
From: Igor Mammedov @ 2017-09-13 16:04 UTC (permalink / raw)
To: qemu-devel
it would allow to reuse feature parsing part in various machines
that have CPU features instead of re-implementing the same feature
parsing each time.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2:
- squash in "cpu: rename cpu_parse_features() to cpu_parse_cpu_model()"
---
include/qom/cpu.h | 21 +++++++++++++++++++++
qom/cpu.c | 46 ++++++++++++++++++++++++++++++----------------
2 files changed, 51 insertions(+), 16 deletions(-)
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 995a7be..885276c 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -645,6 +645,27 @@ void cpu_reset(CPUState *cpu);
ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model);
/**
+ * cpu_create:
+ * @typename: The CPU type.
+ *
+ * Instantiates a CPU and realizes the CPU.
+ *
+ * Returns: A #CPUState or %NULL if an error occurred.
+ */
+CPUState *cpu_create(const char *typename);
+
+/**
+ * cpu_parse_cpu_model:
+ * @typename: The CPU base type or CPU type.
+ * @cpu_model: The model string including optional parameters.
+ *
+ * processes optional parameters and registers them as global properties
+ *
+ * Returns: type of CPU to create or %NULL if an error occurred.
+ */
+const char *cpu_parse_cpu_model(const char *typename, const char *cpu_model);
+
+/**
* cpu_generic_init:
* @typename: The CPU base type.
* @cpu_model: The model string including optional parameters.
diff --git a/qom/cpu.c b/qom/cpu.c
index dc5392d..483f26a 100644
--- a/qom/cpu.c
+++ b/qom/cpu.c
@@ -54,13 +54,26 @@ bool cpu_exists(int64_t id)
return !!cpu_by_arch_id(id);
}
-CPUState *cpu_generic_init(const char *typename, const char *cpu_model)
+CPUState *cpu_create(const char *typename)
+{
+ Error *err = NULL;
+ CPUState *cpu = CPU(object_new(typename));
+ object_property_set_bool(OBJECT(cpu), true, "realized", &err);
+ if (err != NULL) {
+ error_report_err(err);
+ object_unref(OBJECT(cpu));
+ return NULL;
+ }
+ return cpu;
+}
+
+const char *cpu_parse_cpu_model(const char *typename, const char *cpu_model)
{
- CPUState *cpu = NULL;
ObjectClass *oc;
CPUClass *cc;
Error *err = NULL;
gchar **model_pieces;
+ const char *cpu_type;
model_pieces = g_strsplit(cpu_model, ",", 2);
@@ -70,27 +83,28 @@ CPUState *cpu_generic_init(const char *typename, const char *cpu_model)
return NULL;
}
+ cpu_type = object_class_get_name(oc);
cc = CPU_CLASS(oc);
- /* TODO: all callers of cpu_generic_init() need to be converted to
- * call parse_features() only once, before calling cpu_generic_init().
- */
- cc->parse_features(object_class_get_name(oc), model_pieces[1], &err);
+ cc->parse_features(cpu_type, model_pieces[1], &err);
g_strfreev(model_pieces);
if (err != NULL) {
- goto out;
- }
-
- cpu = CPU(object_new(object_class_get_name(oc)));
- object_property_set_bool(OBJECT(cpu), true, "realized", &err);
-
-out:
- if (err != NULL) {
error_report_err(err);
- object_unref(OBJECT(cpu));
return NULL;
}
+ return cpu_type;
+}
- return cpu;
+CPUState *cpu_generic_init(const char *typename, const char *cpu_model)
+{
+ /* TODO: all callers of cpu_generic_init() need to be converted to
+ * call cpu_parse_features() only once, before calling cpu_generic_init().
+ */
+ const char *cpu_type = cpu_parse_cpu_model(typename, cpu_model);
+
+ if (cpu_type) {
+ return cpu_create(cpu_type);
+ }
+ return NULL;
}
bool cpu_paging_enabled(const CPUState *cpu)
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH v2 2/5] cpu: make cpu_generic_init() abort QEMU on error
2017-09-13 16:04 [Qemu-devel] [PATCH v2 0/5] generalize parsing of cpu_model (x86/arm) Igor Mammedov
2017-09-13 16:04 ` [Qemu-devel] [PATCH v2 1/5] qom: cpus: split cpu_generic_init() on feature parsing and cpu creation parts Igor Mammedov
@ 2017-09-13 16:04 ` Igor Mammedov
2017-09-13 16:04 ` [Qemu-devel] [PATCH v2 3/5] vl.c: convert cpu_model to cpu type and set of global properties before machine_init() Igor Mammedov
` (3 subsequent siblings)
5 siblings, 0 replies; 17+ messages in thread
From: Igor Mammedov @ 2017-09-13 16:04 UTC (permalink / raw)
To: qemu-devel
Almost every user of cpu_generic_init() checks for
returned NULL and then reports failure in a custom way
and aborts process.
Some users assume that call can't fail and don't check
for failure, though they should have checked for it.
In either cases cpu_generic_init() failure is fatal,
so instead of checking for failure and reporting
it various ways, make cpu_generic_init() report
errors in consistent way and terminate QEMU on failure.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
Even though it's tree wide change, it's trivial so all
affected call sites are included within one patch.
v2:
- drop not needed assert
- instead of checking error/reporting/exiting explicitly
use error_fatal which will do all of it for us
---
include/qom/cpu.h | 3 ++-
bsd-user/main.c | 4 ----
hw/alpha/dp264.c | 4 ----
hw/arm/musicpal.c | 4 ----
hw/arm/omap1.c | 4 ----
hw/arm/omap2.c | 4 ----
hw/arm/pxa2xx.c | 8 --------
hw/arm/strongarm.c | 5 -----
hw/lm32/lm32_boards.c | 8 --------
hw/lm32/milkymist.c | 4 ----
hw/m68k/an5206.c | 4 ----
hw/m68k/mcf5208.c | 4 ----
hw/mips/cps.c | 4 ----
hw/mips/mips_fulong2e.c | 4 ----
hw/mips/mips_jazz.c | 4 ----
hw/mips/mips_malta.c | 4 ----
hw/mips/mips_mipssim.c | 4 ----
hw/mips/mips_r4k.c | 4 ----
hw/moxie/moxiesim.c | 4 ----
hw/openrisc/openrisc_sim.c | 4 ----
hw/ppc/e500.c | 4 ----
hw/ppc/mac_newworld.c | 4 ----
hw/ppc/mac_oldworld.c | 4 ----
hw/ppc/ppc440_bamboo.c | 4 ----
hw/ppc/ppc4xx_devs.c | 5 -----
hw/ppc/prep.c | 9 ---------
hw/ppc/virtex_ml507.c | 4 ----
hw/sh4/r2d.c | 4 ----
hw/sh4/shix.c | 4 ----
hw/sparc/leon3.c | 4 ----
hw/sparc/sun4m.c | 4 ----
hw/sparc64/sparc64.c | 4 ----
hw/tricore/tricore_testboard.c | 4 ----
hw/unicore32/puv3.c | 4 ----
hw/xtensa/sim.c | 5 -----
hw/xtensa/xtfpga.c | 5 -----
linux-user/main.c | 4 ----
qom/cpu.c | 19 +++++--------------
38 files changed, 7 insertions(+), 176 deletions(-)
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 885276c..6d33cf1 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -661,7 +661,8 @@ CPUState *cpu_create(const char *typename);
*
* processes optional parameters and registers them as global properties
*
- * Returns: type of CPU to create or %NULL if an error occurred.
+ * Returns: type of CPU to create or prints error and terminates process
+ * if an error occurred.
*/
const char *cpu_parse_cpu_model(const char *typename, const char *cpu_model);
diff --git a/bsd-user/main.c b/bsd-user/main.c
index 8a6706a..836daac 100644
--- a/bsd-user/main.c
+++ b/bsd-user/main.c
@@ -902,10 +902,6 @@ int main(int argc, char **argv)
/* NOTE: we need to init the CPU at this stage to get
qemu_host_page_size */
cpu = cpu_init(cpu_model);
- if (!cpu) {
- fprintf(stderr, "Unable to find CPU definition\n");
- exit(1);
- }
env = cpu->env_ptr;
#if defined(TARGET_SPARC) || defined(TARGET_PPC)
cpu_reset(cpu);
diff --git a/hw/alpha/dp264.c b/hw/alpha/dp264.c
index 1c5a177..1b12130 100644
--- a/hw/alpha/dp264.c
+++ b/hw/alpha/dp264.c
@@ -68,10 +68,6 @@ static void clipper_init(MachineState *machine)
memset(cpus, 0, sizeof(cpus));
for (i = 0; i < smp_cpus; ++i) {
cpus[i] = ALPHA_CPU(cpu_generic_init(TYPE_ALPHA_CPU, cpu_model));
- if (!cpus[i]) {
- error_report("Unable to find CPU definition");
- exit(1);
- }
}
cpus[0]->env.trap_arg0 = ram_size;
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
index ab4ba31..7a6c0a6 100644
--- a/hw/arm/musicpal.c
+++ b/hw/arm/musicpal.c
@@ -1594,10 +1594,6 @@ static void musicpal_init(MachineState *machine)
cpu_model = "arm926";
}
cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
- if (!cpu) {
- fprintf(stderr, "Unable to find CPU definition\n");
- exit(1);
- }
/* For now we use a fixed - the original - RAM size */
memory_region_allocate_system_memory(ram, NULL, "musicpal.ram",
diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
index 400ba30..04e65ce 100644
--- a/hw/arm/omap1.c
+++ b/hw/arm/omap1.c
@@ -3864,10 +3864,6 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
/* Core */
s->mpu_model = omap310;
s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, core));
- if (s->cpu == NULL) {
- fprintf(stderr, "Unable to find CPU definition\n");
- exit(1);
- }
s->sdram_size = sdram_size;
s->sram_size = OMAP15XX_SRAM_SIZE;
diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
index ece25ae..5821477 100644
--- a/hw/arm/omap2.c
+++ b/hw/arm/omap2.c
@@ -2262,10 +2262,6 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
/* Core */
s->mpu_model = omap2420;
s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, core ?: "arm1136-r2"));
- if (s->cpu == NULL) {
- fprintf(stderr, "Unable to find CPU definition\n");
- exit(1);
- }
s->sdram_size = sdram_size;
s->sram_size = OMAP242X_SRAM_SIZE;
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index b0ac3cf..c16657d 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -2067,10 +2067,6 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
revision = "pxa270";
s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, revision));
- if (s->cpu == NULL) {
- fprintf(stderr, "Unable to find CPU definition\n");
- exit(1);
- }
s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0);
/* SDRAM & Internal Memory Storage */
@@ -2197,10 +2193,6 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
s = g_new0(PXA2xxState, 1);
s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, "pxa255"));
- if (s->cpu == NULL) {
- fprintf(stderr, "Unable to find CPU definition\n");
- exit(1);
- }
s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0);
/* SDRAM & Internal Memory Storage */
diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
index 884242b..c1145dd 100644
--- a/hw/arm/strongarm.c
+++ b/hw/arm/strongarm.c
@@ -1599,11 +1599,6 @@ StrongARMState *sa1110_init(MemoryRegion *sysmem,
s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, rev));
- if (!s->cpu) {
- error_report("Unable to find CPU definition");
- exit(1);
- }
-
memory_region_allocate_system_memory(&s->sdram, NULL, "strongarm.sdram",
sdram_size);
memory_region_add_subregion(sysmem, SA_SDCS0, &s->sdram);
diff --git a/hw/lm32/lm32_boards.c b/hw/lm32/lm32_boards.c
index eccf0ac..b0bb3ef 100644
--- a/hw/lm32/lm32_boards.c
+++ b/hw/lm32/lm32_boards.c
@@ -105,10 +105,6 @@ static void lm32_evr_init(MachineState *machine)
cpu_model = "lm32-full";
}
cpu = LM32_CPU(cpu_generic_init(TYPE_LM32_CPU, cpu_model));
- if (cpu == NULL) {
- fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
- exit(1);
- }
env = &cpu->env;
reset_info->cpu = cpu;
@@ -206,10 +202,6 @@ static void lm32_uclinux_init(MachineState *machine)
cpu_model = "lm32-full";
}
cpu = LM32_CPU(cpu_generic_init(TYPE_LM32_CPU, cpu_model));
- if (cpu == NULL) {
- fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
- exit(1);
- }
env = &cpu->env;
reset_info->cpu = cpu;
diff --git a/hw/lm32/milkymist.c b/hw/lm32/milkymist.c
index dffd879..4db4d2d 100644
--- a/hw/lm32/milkymist.c
+++ b/hw/lm32/milkymist.c
@@ -112,10 +112,6 @@ milkymist_init(MachineState *machine)
cpu_model = "lm32-full";
}
cpu = LM32_CPU(cpu_generic_init(TYPE_LM32_CPU, cpu_model));
- if (cpu == NULL) {
- fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
- exit(1);
- }
env = &cpu->env;
reset_info->cpu = cpu;
diff --git a/hw/m68k/an5206.c b/hw/m68k/an5206.c
index 7b9b15d..9002c46 100644
--- a/hw/m68k/an5206.c
+++ b/hw/m68k/an5206.c
@@ -43,10 +43,6 @@ static void an5206_init(MachineState *machine)
cpu_model = "m5206";
}
cpu = M68K_CPU(cpu_generic_init(TYPE_M68K_CPU, cpu_model));
- if (!cpu) {
- error_report("Unable to find m68k CPU definition");
- exit(1);
- }
env = &cpu->env;
/* Initialize CPU registers. */
diff --git a/hw/m68k/mcf5208.c b/hw/m68k/mcf5208.c
index 1a0f180..b9dde75 100644
--- a/hw/m68k/mcf5208.c
+++ b/hw/m68k/mcf5208.c
@@ -233,10 +233,6 @@ static void mcf5208evb_init(MachineState *machine)
cpu_model = "m5208";
}
cpu = M68K_CPU(cpu_generic_init(TYPE_M68K_CPU, cpu_model));
- if (!cpu) {
- fprintf(stderr, "Unable to find m68k CPU definition\n");
- exit(1);
- }
env = &cpu->env;
/* Initialize CPU registers. */
diff --git a/hw/mips/cps.c b/hw/mips/cps.c
index 4ef337d..79d4c5e 100644
--- a/hw/mips/cps.c
+++ b/hw/mips/cps.c
@@ -72,10 +72,6 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
for (i = 0; i < s->num_vp; i++) {
cpu = cpu_mips_init(s->cpu_model);
- if (cpu == NULL) {
- error_setg(errp, "%s: CPU initialization failed", __func__);
- return;
- }
/* Init internal devices */
cpu_mips_irq_init_cpu(cpu);
diff --git a/hw/mips/mips_fulong2e.c b/hw/mips/mips_fulong2e.c
index 3532399..439a3d7 100644
--- a/hw/mips/mips_fulong2e.c
+++ b/hw/mips/mips_fulong2e.c
@@ -281,10 +281,6 @@ static void mips_fulong2e_init(MachineState *machine)
cpu_model = "Loongson-2E";
}
cpu = cpu_mips_init(cpu_model);
- if (cpu == NULL) {
- fprintf(stderr, "Unable to find CPU definition\n");
- exit(1);
- }
env = &cpu->env;
qemu_register_reset(main_cpu_reset, cpu);
diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c
index df2262a..ae10670 100644
--- a/hw/mips/mips_jazz.c
+++ b/hw/mips/mips_jazz.c
@@ -152,10 +152,6 @@ static void mips_jazz_init(MachineState *machine,
cpu_model = "R4000";
}
cpu = cpu_mips_init(cpu_model);
- if (cpu == NULL) {
- fprintf(stderr, "Unable to find CPU definition\n");
- exit(1);
- }
env = &cpu->env;
qemu_register_reset(main_cpu_reset, cpu);
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index af678f5..c82e0af 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -932,10 +932,6 @@ static void create_cpu_without_cps(const char *cpu_model,
for (i = 0; i < smp_cpus; i++) {
cpu = cpu_mips_init(cpu_model);
- if (cpu == NULL) {
- fprintf(stderr, "Unable to find CPU definition\n");
- exit(1);
- }
/* Init internal devices */
cpu_mips_irq_init_cpu(cpu);
diff --git a/hw/mips/mips_mipssim.c b/hw/mips/mips_mipssim.c
index 07fc4c2..49cd38d 100644
--- a/hw/mips/mips_mipssim.c
+++ b/hw/mips/mips_mipssim.c
@@ -164,10 +164,6 @@ mips_mipssim_init(MachineState *machine)
#endif
}
cpu = cpu_mips_init(cpu_model);
- if (cpu == NULL) {
- fprintf(stderr, "Unable to find CPU definition\n");
- exit(1);
- }
env = &cpu->env;
reset_info = g_malloc0(sizeof(ResetData));
diff --git a/hw/mips/mips_r4k.c b/hw/mips/mips_r4k.c
index 2f5ced7..60da607 100644
--- a/hw/mips/mips_r4k.c
+++ b/hw/mips/mips_r4k.c
@@ -194,10 +194,6 @@ void mips_r4k_init(MachineState *machine)
#endif
}
cpu = cpu_mips_init(cpu_model);
- if (cpu == NULL) {
- fprintf(stderr, "Unable to find CPU definition\n");
- exit(1);
- }
env = &cpu->env;
reset_info = g_malloc0(sizeof(ResetData));
diff --git a/hw/moxie/moxiesim.c b/hw/moxie/moxiesim.c
index 4c27b45..5ea8dd3 100644
--- a/hw/moxie/moxiesim.c
+++ b/hw/moxie/moxiesim.c
@@ -119,10 +119,6 @@ static void moxiesim_init(MachineState *machine)
cpu_model = "MoxieLite-moxie-cpu";
}
cpu = MOXIE_CPU(cpu_generic_init(TYPE_MOXIE_CPU, cpu_model));
- if (!cpu) {
- fprintf(stderr, "Unable to find CPU definition\n");
- exit(1);
- }
env = &cpu->env;
qemu_register_reset(main_cpu_reset, cpu);
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 243d802..86bf284 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc/openrisc_sim.c
@@ -110,10 +110,6 @@ static void openrisc_sim_init(MachineState *machine)
for (n = 0; n < smp_cpus; n++) {
cpu = OPENRISC_CPU(cpu_generic_init(TYPE_OPENRISC_CPU, cpu_model));
- if (cpu == NULL) {
- fprintf(stderr, "Unable to find CPU definition!\n");
- exit(1);
- }
qemu_register_reset(main_cpu_reset, cpu);
main_cpu_reset(cpu);
}
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 55cad78..db0e49a 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -817,10 +817,6 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU,
machine->cpu_model));
- if (cpu == NULL) {
- fprintf(stderr, "Unable to initialize CPU!\n");
- exit(1);
- }
env = &cpu->env;
cs = CPU(cpu);
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index d466634..33b46cb 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -189,10 +189,6 @@ static void ppc_core99_init(MachineState *machine)
for (i = 0; i < smp_cpus; i++) {
cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU,
machine->cpu_model));
- if (cpu == NULL) {
- fprintf(stderr, "Unable to find PowerPC CPU definition\n");
- exit(1);
- }
env = &cpu->env;
/* Set time-base frequency to 100 Mhz */
diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c
index fcac399..193b904 100644
--- a/hw/ppc/mac_oldworld.c
+++ b/hw/ppc/mac_oldworld.c
@@ -118,10 +118,6 @@ static void ppc_heathrow_init(MachineState *machine)
for (i = 0; i < smp_cpus; i++) {
cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU,
machine->cpu_model));
- if (cpu == NULL) {
- fprintf(stderr, "Unable to find PowerPC CPU definition\n");
- exit(1);
- }
env = &cpu->env;
/* Set time-base frequency to 16.6 Mhz */
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index ca26398..f92d47f 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -187,10 +187,6 @@ static void bamboo_init(MachineState *machine)
machine->cpu_model = "440EP";
}
cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, machine->cpu_model));
- if (cpu == NULL) {
- fprintf(stderr, "Unable to initialize CPU!\n");
- exit(1);
- }
env = &cpu->env;
if (env->mmu_model != POWERPC_MMU_BOOKE) {
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index ec90f13..6d7f785 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -57,11 +57,6 @@ PowerPCCPU *ppc4xx_init(const char *cpu_model,
/* init CPUs */
cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, cpu_model));
- if (cpu == NULL) {
- fprintf(stderr, "Unable to find PowerPC %s CPU definition\n",
- cpu_model);
- exit(1);
- }
env = &cpu->env;
cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */
diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
index 00f3321..94138a4 100644
--- a/hw/ppc/prep.c
+++ b/hw/ppc/prep.c
@@ -522,10 +522,6 @@ static void ppc_prep_init(MachineState *machine)
for (i = 0; i < smp_cpus; i++) {
cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU,
machine->cpu_model));
- if (cpu == NULL) {
- fprintf(stderr, "Unable to find PowerPC CPU definition\n");
- exit(1);
- }
env = &cpu->env;
if (env->flags & POWERPC_FLAG_RTC_CLK) {
@@ -726,11 +722,6 @@ static void ibm_40p_init(MachineState *machine)
machine->cpu_model = "604";
}
cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, machine->cpu_model));
- if (!cpu) {
- error_report("could not initialize CPU '%s'",
- machine->cpu_model);
- exit(1);
- }
env = &cpu->env;
if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
error_report("only 6xx bus is supported on this machine");
diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c
index d5fdc16..ed9b406 100644
--- a/hw/ppc/virtex_ml507.c
+++ b/hw/ppc/virtex_ml507.c
@@ -97,10 +97,6 @@ static PowerPCCPU *ppc440_init_xilinx(ram_addr_t *ram_size,
qemu_irq *irqs;
cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, cpu_model));
- if (cpu == NULL) {
- fprintf(stderr, "Unable to initialize CPU!\n");
- exit(1);
- }
env = &cpu->env;
ppc_booke_timers_init(cpu, sysclk, 0/* no flags */);
diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c
index 22bc534..16b9ed2 100644
--- a/hw/sh4/r2d.c
+++ b/hw/sh4/r2d.c
@@ -247,10 +247,6 @@ static void r2d_init(MachineState *machine)
}
cpu = SUPERH_CPU(cpu_generic_init(TYPE_SUPERH_CPU, cpu_model));
- if (cpu == NULL) {
- fprintf(stderr, "Unable to find CPU definition\n");
- exit(1);
- }
env = &cpu->env;
reset_info = g_malloc0(sizeof(ResetData));
diff --git a/hw/sh4/shix.c b/hw/sh4/shix.c
index 7f8a4b6..50ee36a 100644
--- a/hw/sh4/shix.c
+++ b/hw/sh4/shix.c
@@ -57,10 +57,6 @@ static void shix_init(MachineState *machine)
cpu_model = "any";
cpu = SUPERH_CPU(cpu_generic_init(TYPE_SUPERH_CPU, cpu_model));
- if (cpu == NULL) {
- fprintf(stderr, "Unable to find CPU definition\n");
- exit(1);
- }
/* Allocate memory space */
memory_region_init_ram(rom, NULL, "shix.rom", 0x4000, &error_fatal);
diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c
index 56512ec..ec2816b 100644
--- a/hw/sparc/leon3.c
+++ b/hw/sparc/leon3.c
@@ -127,10 +127,6 @@ static void leon3_generic_hw_init(MachineState *machine)
}
cpu = SPARC_CPU(cpu_generic_init(TYPE_SPARC_CPU, cpu_model));
- if (cpu == NULL) {
- fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
- exit(1);
- }
env = &cpu->env;
cpu_sparc_set_id(env, 0);
diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
index cf47dca..e1bdd48 100644
--- a/hw/sparc/sun4m.c
+++ b/hw/sparc/sun4m.c
@@ -798,10 +798,6 @@ static void cpu_devinit(const char *cpu_model, unsigned int id,
CPUSPARCState *env;
cpu = SPARC_CPU(cpu_generic_init(TYPE_SPARC_CPU, cpu_model));
- if (cpu == NULL) {
- fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
- exit(1);
- }
env = &cpu->env;
cpu_sparc_set_id(env, id);
diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c
index ecf38a4..097d529 100644
--- a/hw/sparc64/sparc64.c
+++ b/hw/sparc64/sparc64.c
@@ -354,10 +354,6 @@ SPARCCPU *sparc64_cpu_devinit(const char *cpu_model,
cpu_model = default_cpu_model;
}
cpu = SPARC_CPU(cpu_generic_init(TYPE_SPARC_CPU, cpu_model));
- if (cpu == NULL) {
- fprintf(stderr, "Unable to find Sparc CPU definition\n");
- exit(1);
- }
env = &cpu->env;
env->tick = cpu_timer_create("tick", cpu, tick_irq,
diff --git a/hw/tricore/tricore_testboard.c b/hw/tricore/tricore_testboard.c
index 3fcd8bb..0486f8a 100644
--- a/hw/tricore/tricore_testboard.c
+++ b/hw/tricore/tricore_testboard.c
@@ -75,10 +75,6 @@ static void tricore_testboard_init(MachineState *machine, int board_id)
machine->cpu_model = "tc1796";
}
cpu = TRICORE_CPU(cpu_generic_init(TYPE_TRICORE_CPU, machine->cpu_model));
- if (!cpu) {
- error_report("Unable to find CPU definition");
- exit(1);
- }
env = &cpu->env;
memory_region_init_ram(ext_cram, NULL, "powerlink_ext_c.ram",
2 * 1024 * 1024, &error_fatal);
diff --git a/hw/unicore32/puv3.c b/hw/unicore32/puv3.c
index eb9862f..504ea46 100644
--- a/hw/unicore32/puv3.c
+++ b/hw/unicore32/puv3.c
@@ -128,10 +128,6 @@ static void puv3_init(MachineState *machine)
}
cpu = UNICORE32_CPU(cpu_generic_init(TYPE_UNICORE32_CPU, cpu_model));
- if (!cpu) {
- error_report("Unable to find CPU definition");
- exit(1);
- }
env = &cpu->env;
puv3_soc_init(env);
diff --git a/hw/xtensa/sim.c b/hw/xtensa/sim.c
index 1b4767f..b3580b1 100644
--- a/hw/xtensa/sim.c
+++ b/hw/xtensa/sim.c
@@ -85,11 +85,6 @@ static void xtensa_sim_init(MachineState *machine)
for (n = 0; n < smp_cpus; n++) {
cpu = XTENSA_CPU(cpu_generic_init(TYPE_XTENSA_CPU, cpu_model));
- if (cpu == NULL) {
- error_report("unable to find CPU definition '%s'",
- cpu_model);
- exit(EXIT_FAILURE);
- }
env = &cpu->env;
env->sregs[PRID] = n;
diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c
index 182ec1e..a19cceb 100644
--- a/hw/xtensa/xtfpga.c
+++ b/hw/xtensa/xtfpga.c
@@ -233,11 +233,6 @@ static void lx_init(const LxBoardDesc *board, MachineState *machine)
for (n = 0; n < smp_cpus; n++) {
cpu = XTENSA_CPU(cpu_generic_init(TYPE_XTENSA_CPU, cpu_model));
- if (cpu == NULL) {
- error_report("unable to find CPU definition '%s'",
- cpu_model);
- exit(EXIT_FAILURE);
- }
env = &cpu->env;
env->sregs[PRID] = n;
diff --git a/linux-user/main.c b/linux-user/main.c
index 03666ef..829f974 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -4323,10 +4323,6 @@ int main(int argc, char **argv, char **envp)
/* NOTE: we need to init the CPU at this stage to get
qemu_host_page_size */
cpu = cpu_init(cpu_model);
- if (!cpu) {
- fprintf(stderr, "Unable to find CPU definition\n");
- exit(EXIT_FAILURE);
- }
env = cpu->env_ptr;
cpu_reset(cpu);
diff --git a/qom/cpu.c b/qom/cpu.c
index 483f26a..94fa8fe 100644
--- a/qom/cpu.c
+++ b/qom/cpu.c
@@ -62,7 +62,7 @@ CPUState *cpu_create(const char *typename)
if (err != NULL) {
error_report_err(err);
object_unref(OBJECT(cpu));
- return NULL;
+ exit(EXIT_FAILURE);
}
return cpu;
}
@@ -71,7 +71,6 @@ const char *cpu_parse_cpu_model(const char *typename, const char *cpu_model)
{
ObjectClass *oc;
CPUClass *cc;
- Error *err = NULL;
gchar **model_pieces;
const char *cpu_type;
@@ -79,18 +78,15 @@ const char *cpu_parse_cpu_model(const char *typename, const char *cpu_model)
oc = cpu_class_by_name(typename, model_pieces[0]);
if (oc == NULL) {
+ error_report("unable to find CPU model '%s'", model_pieces[0]);
g_strfreev(model_pieces);
- return NULL;
+ exit(EXIT_FAILURE);
}
cpu_type = object_class_get_name(oc);
cc = CPU_CLASS(oc);
- cc->parse_features(cpu_type, model_pieces[1], &err);
+ cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
g_strfreev(model_pieces);
- if (err != NULL) {
- error_report_err(err);
- return NULL;
- }
return cpu_type;
}
@@ -99,12 +95,7 @@ CPUState *cpu_generic_init(const char *typename, const char *cpu_model)
/* TODO: all callers of cpu_generic_init() need to be converted to
* call cpu_parse_features() only once, before calling cpu_generic_init().
*/
- const char *cpu_type = cpu_parse_cpu_model(typename, cpu_model);
-
- if (cpu_type) {
- return cpu_create(cpu_type);
- }
- return NULL;
+ return cpu_create(cpu_parse_cpu_model(typename, cpu_model));
}
bool cpu_paging_enabled(const CPUState *cpu)
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH v2 3/5] vl.c: convert cpu_model to cpu type and set of global properties before machine_init()
2017-09-13 16:04 [Qemu-devel] [PATCH v2 0/5] generalize parsing of cpu_model (x86/arm) Igor Mammedov
2017-09-13 16:04 ` [Qemu-devel] [PATCH v2 1/5] qom: cpus: split cpu_generic_init() on feature parsing and cpu creation parts Igor Mammedov
2017-09-13 16:04 ` [Qemu-devel] [PATCH v2 2/5] cpu: make cpu_generic_init() abort QEMU on error Igor Mammedov
@ 2017-09-13 16:04 ` Igor Mammedov
2017-09-14 18:19 ` Philippe Mathieu-Daudé
2017-09-13 16:04 ` [Qemu-devel] [PATCH v2 4/5] pc: use generic cpu_model parsing Igor Mammedov
` (2 subsequent siblings)
5 siblings, 1 reply; 17+ messages in thread
From: Igor Mammedov @ 2017-09-13 16:04 UTC (permalink / raw)
To: qemu-devel
All machines that support user specified cpu_model either call
cpu_generic_init() or cpu_class_by_name()/CPUClass::parse_features
to parse feature string and to get CPU type to create.
Which leads to code duplication and hard-codding default CPU model
within machine_foo_init() code. Which makes it impossible to
get CPU type before machine_init() is run.
So instead of setting default CPUs models and doing parsing in
target specific machine_foo_init() in various ways, provide
a generic data driven cpu_model parsing before machine_init()
is called.
in follow up per target patches, it will allow to:
* define default CPU type in consistent/generic manner
per machine type and drop custom code that fallbacks
to default if cpu_model is NULL
* drop custom features parsing in targets and do it
in centralized way.
* for cases of
cpu_generic_init(TYPE_BASE/DEFAULT_CPU, "some_cpu")
replace it with
cpu_create(machine->cpu_type) || cpu_create(TYPE_FOO)
depending if CPU type is user settable or not.
not doing useless parsing and clearly documenting where
CPU model is user settable or fixed one.
Patch allows machine subclasses to define default CPU type
per machine class at class_init() time and if that is set
generic code will parse cpu_model into a MachineState::cpu_type
which will be used to create CPUs for that machine instance
and allows gradual per board conversion.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
---
Target specific changes will split into separate per target/machine
patches to make changes reviewable.
---
include/hw/boards.h | 6 ++++++
vl.c | 10 ++++++++++
2 files changed, 16 insertions(+)
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 7f044d1..6b67ada 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -125,6 +125,10 @@ typedef struct {
* Caller is responsible for freeing returned list.
* @has_hotpluggable_cpus:
* If true, board supports CPUs creation with -device/device_add.
+ * @default_cpu_type:
+ * specifies default CPU_TYPE, which will be used for parsing target
+ * specific features and for creating CPUs if CPU name wasn't provided
+ * explicitly at CLI
* @minimum_page_bits:
* If non-zero, the board promises never to create a CPU with a page size
* smaller than this, so QEMU can use a more efficient larger page
@@ -177,6 +181,7 @@ struct MachineClass {
GArray *compat_props;
const char *hw_version;
ram_addr_t default_ram_size;
+ const char *default_cpu_type;
bool option_rom_has_mr;
bool rom_file_has_mr;
int minimum_page_bits;
@@ -231,6 +236,7 @@ struct MachineState {
char *kernel_cmdline;
char *initrd_filename;
const char *cpu_model;
+ const char *cpu_type;
AccelState *accelerator;
CPUArchIdList *possible_cpus;
};
diff --git a/vl.c b/vl.c
index fb1f05b..034180f 100644
--- a/vl.c
+++ b/vl.c
@@ -4636,6 +4636,16 @@ int main(int argc, char **argv, char **envp)
current_machine->boot_order = boot_order;
current_machine->cpu_model = cpu_model;
+
+ /* parse features once if machine provides default cpu_type */
+ if (machine_class->default_cpu_type) {
+ current_machine->cpu_type = machine_class->default_cpu_type;
+ if (cpu_model) {
+ current_machine->cpu_type =
+ cpu_parse_cpu_model(machine_class->default_cpu_type, cpu_model);
+ }
+ }
+
machine_run_board_init(current_machine);
realtime_init();
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH v2 4/5] pc: use generic cpu_model parsing
2017-09-13 16:04 [Qemu-devel] [PATCH v2 0/5] generalize parsing of cpu_model (x86/arm) Igor Mammedov
` (2 preceding siblings ...)
2017-09-13 16:04 ` [Qemu-devel] [PATCH v2 3/5] vl.c: convert cpu_model to cpu type and set of global properties before machine_init() Igor Mammedov
@ 2017-09-13 16:04 ` Igor Mammedov
2017-09-13 16:04 ` [Qemu-devel] [PATCH v2 5/5] arm: drop intermediate cpu_model -> cpu type parsing and use cpu type directly Igor Mammedov
2017-09-15 15:03 ` [Qemu-devel] [PATCH v2 0/5] generalize parsing of cpu_model (x86/arm) Igor Mammedov
5 siblings, 0 replies; 17+ messages in thread
From: Igor Mammedov @ 2017-09-13 16:04 UTC (permalink / raw)
To: qemu-devel
define default CPU type in generic way in pc_machine_class_init()
and let common machine code to handle cpu_model parsing
Patch also introduces TARGET_DEFAULT_CPU_TYPE define for 2 purposes:
* make foo_machine_class_init() look uniform on every target
* use define in [bsd|linux]-user targets to pick default
cpu type
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/i386/cpu.h | 9 +++++++++
hw/i386/pc.c | 41 +++++------------------------------------
hw/i386/pc_piix.c | 4 +---
target/i386/cpu.c | 3 ---
4 files changed, 15 insertions(+), 42 deletions(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 525d35d..4035a11 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1508,6 +1508,15 @@ uint64_t cpu_get_tsc(CPUX86State *env);
#define cpu_init(cpu_model) cpu_generic_init(TYPE_X86_CPU, cpu_model)
+#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
+#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
+
+#ifdef TARGET_X86_64
+#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64")
+#else
+#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32")
+#endif
+
#define cpu_signal_handler cpu_x86_signal_handler
#define cpu_list x86_cpu_list
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 2108104..2247ac0 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1107,7 +1107,6 @@ static void pc_new_cpu(const char *typename, int64_t apic_id, Error **errp)
void pc_hot_add_cpu(const int64_t id, Error **errp)
{
- ObjectClass *oc;
MachineState *ms = MACHINE(qdev_get_machine());
int64_t apic_id = x86_cpu_apic_id_from_index(id);
Error *local_err = NULL;
@@ -1124,9 +1123,7 @@ void pc_hot_add_cpu(const int64_t id, Error **errp)
return;
}
- assert(ms->possible_cpus->cpus[0].cpu); /* BSP is always present */
- oc = OBJECT_CLASS(CPU_GET_CLASS(ms->possible_cpus->cpus[0].cpu));
- pc_new_cpu(object_class_get_name(oc), apic_id, &local_err);
+ pc_new_cpu(ms->cpu_type, apic_id, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
@@ -1136,39 +1133,10 @@ void pc_hot_add_cpu(const int64_t id, Error **errp)
void pc_cpus_init(PCMachineState *pcms)
{
int i;
- CPUClass *cc;
- ObjectClass *oc;
- const char *typename;
- gchar **model_pieces;
const CPUArchIdList *possible_cpus;
- MachineState *machine = MACHINE(pcms);
+ MachineState *ms = MACHINE(pcms);
MachineClass *mc = MACHINE_GET_CLASS(pcms);
- /* init CPUs */
- if (machine->cpu_model == NULL) {
-#ifdef TARGET_X86_64
- machine->cpu_model = "qemu64";
-#else
- machine->cpu_model = "qemu32";
-#endif
- }
-
- model_pieces = g_strsplit(machine->cpu_model, ",", 2);
- if (!model_pieces[0]) {
- error_report("Invalid/empty CPU model name");
- exit(1);
- }
-
- oc = cpu_class_by_name(TYPE_X86_CPU, model_pieces[0]);
- if (oc == NULL) {
- error_report("Unable to find CPU definition: %s", model_pieces[0]);
- exit(1);
- }
- typename = object_class_get_name(oc);
- cc = CPU_CLASS(oc);
- cc->parse_features(typename, model_pieces[1], &error_fatal);
- g_strfreev(model_pieces);
-
/* Calculates the limit to CPU APIC ID values
*
* Limit for the APIC ID value, so that all
@@ -1177,9 +1145,9 @@ void pc_cpus_init(PCMachineState *pcms)
* This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
*/
pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
- possible_cpus = mc->possible_cpu_arch_ids(machine);
+ possible_cpus = mc->possible_cpu_arch_ids(ms);
for (i = 0; i < smp_cpus; i++) {
- pc_new_cpu(typename, possible_cpus->cpus[i].arch_id, &error_fatal);
+ pc_new_cpu(ms->cpu_type, possible_cpus->cpus[i].arch_id, &error_fatal);
}
}
@@ -2360,6 +2328,7 @@ static void pc_machine_class_init(ObjectClass *oc, void *data)
hc->unplug_request = pc_machine_device_unplug_request_cb;
hc->unplug = pc_machine_device_unplug_cb;
nc->nmi_monitor_handler = x86_nmi;
+ mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
object_class_property_add(oc, PC_MACHINE_MEMHP_REGION_SIZE, "int",
pc_machine_get_hotplug_memory_region_size, NULL,
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index b03cc04..9ff79b1 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -378,9 +378,6 @@ static void pc_compat_0_13(MachineState *machine)
static void pc_init_isa(MachineState *machine)
{
- if (!machine->cpu_model) {
- machine->cpu_model = "486";
- }
x86_cpu_change_kvm_default("kvm-pv-eoi", NULL);
enable_compat_apic_id_mode();
pc_init1(machine, TYPE_I440FX_PCI_HOST_BRIDGE, TYPE_I440FX_PCI_DEVICE);
@@ -1113,6 +1110,7 @@ static void isapc_machine_options(MachineClass *m)
pcmc->gigabyte_align = false;
pcmc->smbios_legacy_mode = true;
pcmc->has_reserved_memory = false;
+ m->default_cpu_type = X86_CPU_TYPE_NAME("486");
}
DEFINE_PC_MACHINE(isapc, "isapc", pc_init_isa,
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 69676e1..d0000e4 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -705,9 +705,6 @@ void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
/* CPU class name definitions: */
-#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
-#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
-
/* Return type name for a given CPU model name
* Caller is responsible for freeing the returned string.
*/
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH v2 5/5] arm: drop intermediate cpu_model -> cpu type parsing and use cpu type directly
2017-09-13 16:04 [Qemu-devel] [PATCH v2 0/5] generalize parsing of cpu_model (x86/arm) Igor Mammedov
` (3 preceding siblings ...)
2017-09-13 16:04 ` [Qemu-devel] [PATCH v2 4/5] pc: use generic cpu_model parsing Igor Mammedov
@ 2017-09-13 16:04 ` Igor Mammedov
2017-09-14 3:47 ` Philippe Mathieu-Daudé
` (2 more replies)
2017-09-15 15:03 ` [Qemu-devel] [PATCH v2 0/5] generalize parsing of cpu_model (x86/arm) Igor Mammedov
5 siblings, 3 replies; 17+ messages in thread
From: Igor Mammedov @ 2017-09-13 16:04 UTC (permalink / raw)
To: qemu-devel
there are 2 use cases to deal with:
1: fixed CPU models per board/soc
2: boards with user configurable cpu_model and fallback to
default cpu_model if user hasn't specified one explicitly
For the 1st
drop intermediate cpu_model parsing and use const cpu type
directly, which replaces:
typename = object_class_get_name(
cpu_class_by_name(TYPE_ARM_CPU, cpu_model))
object_new(typename)
with
object_new(FOO_CPU_TYPE_NAME)
or
cpu_generic_init(BASE_CPU_TYPE, "my cpu model")
with
cpu_create(FOO_CPU_TYPE_NAME)
as result 1st use case doesn't have to invoke not necessary
translation and not needed code is removed.
For the 2nd
1: set default cpu type with MachineClass::default_cpu_type and
2: use generic cpu_model parsing that done before machine_init()
is run and:
2.1: drop custom cpu_model parsing where pattern is:
typename = object_class_get_name(
cpu_class_by_name(TYPE_ARM_CPU, cpu_model))
[parse_features(typename, cpu_model, &err) ]
2.2: or replace cpu_generic_init() which does what
2.1 does + create_cpu(typename) with just
create_cpu(machine->cpu_type)
as result cpu_name -> cpu_type translation is done using
generic machine code one including parsing optional features
if supported/present (removes a bunch of duplicated cpu_model
parsing code) and default cpu type is defined in an uniform way
within machine_class_init callbacks instead of adhoc places
in boadr's machine_init code.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
---
v2:
- fix merge conflicts with ignore_memory_transaction_failures
- fix couple merge conflicts where SoC type string where replaced by type macro
- keep plain prefix string in: strncmp(cpu_type, "pxa27", 5)
- s/"%s" ARM_CPU_TYPE_SUFFIX/ARM_CPU_TYPE_NAME("%s")/
---
include/hw/arm/armv7m.h | 2 +-
include/hw/arm/aspeed_soc.h | 2 +-
include/hw/arm/stm32f205_soc.h | 2 +-
target/arm/cpu.h | 3 +++
hw/arm/armv7m.c | 40 +++++-------------------------------
hw/arm/aspeed_soc.c | 13 +++++-------
hw/arm/collie.c | 10 +++------
hw/arm/exynos4210.c | 6 +-----
hw/arm/gumstix.c | 5 +++--
hw/arm/highbank.c | 10 ++++-----
hw/arm/integratorcp.c | 30 ++-------------------------
hw/arm/mainstone.c | 9 ++++-----
hw/arm/mps2.c | 17 +++++++---------
hw/arm/musicpal.c | 7 ++-----
hw/arm/netduino2.c | 2 +-
hw/arm/nseries.c | 4 +++-
hw/arm/omap1.c | 7 ++-----
hw/arm/omap2.c | 4 ++--
hw/arm/omap_sx1.c | 5 ++++-
hw/arm/palm.c | 5 +++--
hw/arm/pxa2xx.c | 10 ++++-----
hw/arm/realview.c | 25 +++++------------------
hw/arm/spitz.c | 12 ++++++-----
hw/arm/stellaris.c | 16 +++++++--------
hw/arm/stm32f205_soc.c | 4 ++--
hw/arm/strongarm.c | 10 +++------
hw/arm/tosa.c | 4 ----
hw/arm/versatilepb.c | 15 +++-----------
hw/arm/vexpress.c | 32 +++++++++--------------------
hw/arm/virt.c | 46 +++++++++---------------------------------
hw/arm/xilinx_zynq.c | 10 ++-------
hw/arm/z2.c | 9 +++------
target/arm/cpu.c | 2 +-
33 files changed, 114 insertions(+), 264 deletions(-)
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
index 10eb058..68cb30d 100644
--- a/include/hw/arm/armv7m.h
+++ b/include/hw/arm/armv7m.h
@@ -55,7 +55,7 @@ typedef struct ARMv7MState {
MemoryRegion container;
/* Properties */
- char *cpu_model;
+ char *cpu_type;
/* MemoryRegion the board provides to us (with its devices, RAM, etc) */
MemoryRegion *board_memory;
} ARMv7MState;
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 0b88baa..f26914a 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -49,7 +49,7 @@ typedef struct AspeedSoCState {
typedef struct AspeedSoCInfo {
const char *name;
- const char *cpu_model;
+ const char *cpu_type;
uint32_t silicon_rev;
hwaddr sdram_base;
uint64_t sram_size;
diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h
index e2dce11..922a733 100644
--- a/include/hw/arm/stm32f205_soc.h
+++ b/include/hw/arm/stm32f205_soc.h
@@ -52,7 +52,7 @@ typedef struct STM32F205State {
SysBusDevice parent_obj;
/*< public >*/
- char *cpu_model;
+ char *cpu_type;
ARMv7MState armv7m;
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 98b9b26..1bfdd8d 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2088,6 +2088,9 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
#define cpu_init(cpu_model) cpu_generic_init(TYPE_ARM_CPU, cpu_model)
+#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
+#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
+
#define cpu_signal_handler cpu_arm_signal_handler
#define cpu_list arm_cpu_list
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index b64a409..57a6806 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -151,10 +151,6 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
SysBusDevice *sbd;
Error *err = NULL;
int i;
- char **cpustr;
- ObjectClass *oc;
- const char *typename;
- CPUClass *cc;
if (!s->board_memory) {
error_setg(errp, "memory property was not set");
@@ -163,29 +159,7 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
- cpustr = g_strsplit(s->cpu_model, ",", 2);
-
- oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);
- if (!oc) {
- error_setg(errp, "Unknown CPU model %s", cpustr[0]);
- g_strfreev(cpustr);
- return;
- }
-
- cc = CPU_CLASS(oc);
- typename = object_class_get_name(oc);
- cc->parse_features(typename, cpustr[1], &err);
- g_strfreev(cpustr);
- if (err) {
- error_propagate(errp, err);
- return;
- }
-
- s->cpu = ARM_CPU(object_new(typename));
- if (!s->cpu) {
- error_setg(errp, "Unknown CPU model %s", s->cpu_model);
- return;
- }
+ s->cpu = ARM_CPU(object_new(s->cpu_type));
object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), "memory",
&error_abort);
@@ -241,7 +215,7 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
}
static Property armv7m_properties[] = {
- DEFINE_PROP_STRING("cpu-model", ARMv7MState, cpu_model),
+ DEFINE_PROP_STRING("cpu-type", ARMv7MState, cpu_type),
DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION,
MemoryRegion *),
DEFINE_PROP_END_OF_LIST(),
@@ -275,20 +249,16 @@ static void armv7m_reset(void *opaque)
Returns the ARMv7M device. */
DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
- const char *kernel_filename, const char *cpu_model)
+ const char *kernel_filename, const char *cpu_type)
{
DeviceState *armv7m;
- if (cpu_model == NULL) {
- cpu_model = "cortex-m3";
- }
-
armv7m = qdev_create(NULL, TYPE_ARMV7M);
qdev_prop_set_uint32(armv7m, "num-irq", num_irq);
- qdev_prop_set_string(armv7m, "cpu-model", cpu_model);
+ qdev_prop_set_string(armv7m, "cpu-type", cpu_type);
object_property_set_link(OBJECT(armv7m), OBJECT(get_system_memory()),
"memory", &error_abort);
- /* This will exit with an error if the user passed us a bad cpu_model */
+ /* This will exit with an error if the user passed us a bad cpu_type */
qdev_init_nofail(armv7m);
armv7m_load_kernel(ARM_CPU(first_cpu), kernel_filename, mem_size);
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index 13c6393..5aa3d2d 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -54,7 +54,7 @@ static const char *aspeed_soc_ast2500_typenames[] = {
static const AspeedSoCInfo aspeed_socs[] = {
{
.name = "ast2400-a0",
- .cpu_model = "arm926",
+ .cpu_type = ARM_CPU_TYPE_NAME("arm926"),
.silicon_rev = AST2400_A0_SILICON_REV,
.sdram_base = AST2400_SDRAM_BASE,
.sram_size = 0x8000,
@@ -65,7 +65,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
.wdts_num = 2,
}, {
.name = "ast2400-a1",
- .cpu_model = "arm926",
+ .cpu_type = ARM_CPU_TYPE_NAME("arm926"),
.silicon_rev = AST2400_A1_SILICON_REV,
.sdram_base = AST2400_SDRAM_BASE,
.sram_size = 0x8000,
@@ -76,7 +76,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
.wdts_num = 2,
}, {
.name = "ast2400",
- .cpu_model = "arm926",
+ .cpu_type = ARM_CPU_TYPE_NAME("arm926"),
.silicon_rev = AST2400_A0_SILICON_REV,
.sdram_base = AST2400_SDRAM_BASE,
.sram_size = 0x8000,
@@ -87,7 +87,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
.wdts_num = 2,
}, {
.name = "ast2500-a1",
- .cpu_model = "arm1176",
+ .cpu_type = ARM_CPU_TYPE_NAME("arm1176"),
.silicon_rev = AST2500_A1_SILICON_REV,
.sdram_base = AST2500_SDRAM_BASE,
.sram_size = 0x9000,
@@ -128,13 +128,10 @@ static void aspeed_soc_init(Object *obj)
{
AspeedSoCState *s = ASPEED_SOC(obj);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
- char *cpu_typename;
int i;
- cpu_typename = g_strdup_printf("%s-" TYPE_ARM_CPU, sc->info->cpu_model);
- object_initialize(&s->cpu, sizeof(s->cpu), cpu_typename);
+ object_initialize(&s->cpu, sizeof(s->cpu), sc->info->cpu_type);
object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL);
- g_free(cpu_typename);
object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC);
object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL);
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
index 8830192..f8c566e 100644
--- a/hw/arm/collie.c
+++ b/hw/arm/collie.c
@@ -18,7 +18,7 @@
#include "hw/block/flash.h"
#include "sysemu/block-backend.h"
#include "exec/address-spaces.h"
-#include "qom/cpu.h"
+#include "cpu.h"
static struct arm_boot_info collie_binfo = {
.loader_start = SA_SDCS0,
@@ -27,7 +27,6 @@ static struct arm_boot_info collie_binfo = {
static void collie_init(MachineState *machine)
{
- const char *cpu_model = machine->cpu_model;
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
@@ -35,11 +34,7 @@ static void collie_init(MachineState *machine)
DriveInfo *dinfo;
MemoryRegion *sysmem = get_system_memory();
- if (!cpu_model) {
- cpu_model = "sa1110";
- }
-
- s = sa1110_init(sysmem, collie_binfo.ram_size, cpu_model);
+ s = sa1110_init(sysmem, collie_binfo.ram_size, machine->cpu_type);
dinfo = drive_get(IF_PFLASH, 0, 0);
pflash_cfi01_register(SA_CS0, NULL, "collie.fl1", 0x02000000,
@@ -65,6 +60,7 @@ static void collie_machine_init(MachineClass *mc)
mc->desc = "Sharp SL-5500 (Collie) PDA (SA-1110)";
mc->init = collie_init;
mc->ignore_memory_transaction_failures = true;
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("sa1110");
}
DEFINE_MACHINE("collie", collie_machine_init)
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index ee1438a..e8e1d81 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -169,15 +169,11 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
Exynos4210State *s = g_new(Exynos4210State, 1);
qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
SysBusDevice *busdev;
- ObjectClass *cpu_oc;
DeviceState *dev;
int i, n;
- cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, "cortex-a9");
- assert(cpu_oc);
-
for (n = 0; n < EXYNOS4210_NCPUS; n++) {
- Object *cpuobj = object_new(object_class_get_name(cpu_oc));
+ Object *cpuobj = object_new(ARM_CPU_TYPE_NAME("cortex-a9"));
/* By default A9 CPUs have EL3 enabled. This board does not currently
* support EL3 so the CPU EL3 property is disabled before realization.
diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c
index 092ce36..bba9e9f 100644
--- a/hw/arm/gumstix.c
+++ b/hw/arm/gumstix.c
@@ -44,6 +44,7 @@
#include "sysemu/block-backend.h"
#include "exec/address-spaces.h"
#include "sysemu/qtest.h"
+#include "cpu.h"
static const int sector_len = 128 * 1024;
@@ -86,7 +87,6 @@ static void connex_init(MachineState *machine)
static void verdex_init(MachineState *machine)
{
- const char *cpu_model = machine->cpu_model;
PXA2xxState *cpu;
DriveInfo *dinfo;
int be;
@@ -95,7 +95,7 @@ static void verdex_init(MachineState *machine)
uint32_t verdex_rom = 0x02000000;
uint32_t verdex_ram = 0x10000000;
- cpu = pxa270_init(address_space_mem, verdex_ram, cpu_model ?: "pxa270-c0");
+ cpu = pxa270_init(address_space_mem, verdex_ram, machine->cpu_type);
dinfo = drive_get(IF_PFLASH, 0, 0);
if (!dinfo && !qtest_enabled()) {
@@ -144,6 +144,7 @@ static void verdex_class_init(ObjectClass *oc, void *data)
mc->desc = "Gumstix Verdex (PXA270)";
mc->init = verdex_init;
mc->ignore_memory_transaction_failures = true;
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
}
static const TypeInfo verdex_type = {
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index ba27789..354c6b2 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -222,7 +222,6 @@ enum cxmachines {
static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
{
ram_addr_t ram_size = machine->ram_size;
- const char *cpu_model = machine->cpu_model;
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
@@ -239,19 +238,20 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
switch (machine_id) {
case CALXEDA_HIGHBANK:
- cpu_model = "cortex-a9";
+ machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
break;
case CALXEDA_MIDWAY:
- cpu_model = "cortex-a15";
+ machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
break;
+ default:
+ assert(0);
}
for (n = 0; n < smp_cpus; n++) {
- ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
Object *cpuobj;
ARMCPU *cpu;
- cpuobj = object_new(object_class_get_name(oc));
+ cpuobj = object_new(machine->cpu_type);
cpu = ARM_CPU(cpuobj);
object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_SMC,
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
index d603af9..e8303b8 100644
--- a/hw/arm/integratorcp.c
+++ b/hw/arm/integratorcp.c
@@ -572,46 +572,19 @@ static struct arm_boot_info integrator_binfo = {
static void integratorcp_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
- const char *cpu_model = machine->cpu_model;
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
- char **cpustr;
- ObjectClass *cpu_oc;
- CPUClass *cc;
Object *cpuobj;
ARMCPU *cpu;
- const char *typename;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
qemu_irq pic[32];
DeviceState *dev, *sic, *icp;
int i;
- Error *err = NULL;
- if (!cpu_model) {
- cpu_model = "arm926";
- }
-
- cpustr = g_strsplit(cpu_model, ",", 2);
-
- cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);
- if (!cpu_oc) {
- fprintf(stderr, "Unable to find CPU definition\n");
- exit(1);
- }
- typename = object_class_get_name(cpu_oc);
-
- cc = CPU_CLASS(cpu_oc);
- cc->parse_features(typename, cpustr[1], &err);
- g_strfreev(cpustr);
- if (err) {
- error_report_err(err);
- exit(1);
- }
-
- cpuobj = object_new(typename);
+ cpuobj = object_new(machine->cpu_type);
/* By default ARM1176 CPUs have EL3 enabled. This board does not
* currently support EL3 so the CPU EL3 property is disabled before
@@ -682,6 +655,7 @@ static void integratorcp_machine_init(MachineClass *mc)
mc->desc = "ARM Integrator/CP (ARM926EJ-S)";
mc->init = integratorcp_init;
mc->ignore_memory_transaction_failures = true;
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
}
DEFINE_MACHINE("integratorcp", integratorcp_machine_init)
diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
index 637f52c..d07972a 100644
--- a/hw/arm/mainstone.c
+++ b/hw/arm/mainstone.c
@@ -24,6 +24,7 @@
#include "hw/sysbus.h"
#include "exec/address-spaces.h"
#include "sysemu/qtest.h"
+#include "cpu.h"
/* Device addresses */
#define MST_FPGA_PHYS 0x08000000
@@ -121,13 +122,10 @@ static void mainstone_common_init(MemoryRegion *address_space_mem,
int i;
int be;
MemoryRegion *rom = g_new(MemoryRegion, 1);
- const char *cpu_model = machine->cpu_model;
-
- if (!cpu_model)
- cpu_model = "pxa270-c5";
/* Setup CPU & memory */
- mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size, cpu_model);
+ mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size,
+ machine->cpu_type);
memory_region_init_ram(rom, NULL, "mainstone.rom", MAINSTONE_ROM,
&error_fatal);
memory_region_set_readonly(rom, true);
@@ -197,6 +195,7 @@ static void mainstone2_machine_init(MachineClass *mc)
mc->desc = "Mainstone II (PXA27x)";
mc->init = mainstone_init;
mc->ignore_memory_transaction_failures = true;
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5");
}
DEFINE_MACHINE("mainstone", mainstone2_machine_init)
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index abb0ab6..aeaad80 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -46,7 +46,6 @@ typedef enum MPS2FPGAType {
typedef struct {
MachineClass parent;
MPS2FPGAType fpga_type;
- const char *cpu_model;
uint32_t scc_id;
} MPS2MachineClass;
@@ -107,14 +106,12 @@ static void mps2_common_init(MachineState *machine)
MPS2MachineState *mms = MPS2_MACHINE(machine);
MPS2MachineClass *mmc = MPS2_MACHINE_GET_CLASS(machine);
MemoryRegion *system_memory = get_system_memory();
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
DeviceState *armv7m, *sccdev;
- if (!machine->cpu_model) {
- machine->cpu_model = mmc->cpu_model;
- }
-
- if (strcmp(machine->cpu_model, mmc->cpu_model) != 0) {
- error_report("This board can only be used with CPU %s", mmc->cpu_model);
+ if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
+ error_report("This board can only be used with CPU %s",
+ mc->default_cpu_type);
exit(1);
}
@@ -188,7 +185,7 @@ static void mps2_common_init(MachineState *machine)
default:
g_assert_not_reached();
}
- qdev_prop_set_string(armv7m, "cpu-model", machine->cpu_model);
+ qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type);
object_property_set_link(OBJECT(&mms->armv7m), OBJECT(system_memory),
"memory", &error_abort);
object_property_set_bool(OBJECT(&mms->armv7m), true, "realized",
@@ -339,7 +336,7 @@ static void mps2_an385_class_init(ObjectClass *oc, void *data)
mc->desc = "ARM MPS2 with AN385 FPGA image for Cortex-M3";
mmc->fpga_type = FPGA_AN385;
- mmc->cpu_model = "cortex-m3";
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
mmc->scc_id = 0x41040000 | (385 << 4);
}
@@ -350,7 +347,7 @@ static void mps2_an511_class_init(ObjectClass *oc, void *data)
mc->desc = "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3";
mmc->fpga_type = FPGA_AN511;
- mmc->cpu_model = "cortex-m3";
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
mmc->scc_id = 0x4104000 | (511 << 4);
}
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
index 7a6c0a6..b648770 100644
--- a/hw/arm/musicpal.c
+++ b/hw/arm/musicpal.c
@@ -1570,7 +1570,6 @@ static struct arm_boot_info musicpal_binfo = {
static void musicpal_init(MachineState *machine)
{
- const char *cpu_model = machine->cpu_model;
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
@@ -1590,10 +1589,7 @@ static void musicpal_init(MachineState *machine)
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *sram = g_new(MemoryRegion, 1);
- if (!cpu_model) {
- cpu_model = "arm926";
- }
- cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
+ cpu = ARM_CPU(cpu_create(machine->cpu_type));
/* For now we use a fixed - the original - RAM size */
memory_region_allocate_system_memory(ram, NULL, "musicpal.ram",
@@ -1715,6 +1711,7 @@ static void musicpal_machine_init(MachineClass *mc)
mc->desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)";
mc->init = musicpal_init;
mc->ignore_memory_transaction_failures = true;
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
}
DEFINE_MACHINE("musicpal", musicpal_machine_init)
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
index 9d34d4c..f936017 100644
--- a/hw/arm/netduino2.c
+++ b/hw/arm/netduino2.c
@@ -34,7 +34,7 @@ static void netduino2_init(MachineState *machine)
DeviceState *dev;
dev = qdev_create(NULL, TYPE_STM32F205_SOC);
- qdev_prop_set_string(dev, "cpu-model", "cortex-m3");
+ qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);
armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
index a32ac82..58005b6 100644
--- a/hw/arm/nseries.c
+++ b/hw/arm/nseries.c
@@ -1310,7 +1310,7 @@ static void n8x0_init(MachineState *machine,
struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s));
int sdram_size = binfo->ram_size;
- s->mpu = omap2420_mpu_init(sysmem, sdram_size, machine->cpu_model);
+ s->mpu = omap2420_mpu_init(sysmem, sdram_size, machine->cpu_type);
/* Setup peripherals
*
@@ -1426,6 +1426,7 @@ static void n800_class_init(ObjectClass *oc, void *data)
mc->init = n800_init;
mc->default_boot_order = "";
mc->ignore_memory_transaction_failures = true;
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm1136-r2");
}
static const TypeInfo n800_type = {
@@ -1442,6 +1443,7 @@ static void n810_class_init(ObjectClass *oc, void *data)
mc->init = n810_init;
mc->default_boot_order = "";
mc->ignore_memory_transaction_failures = true;
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm1136-r2");
}
static const TypeInfo n810_type = {
diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
index 04e65ce..b3e7625 100644
--- a/hw/arm/omap1.c
+++ b/hw/arm/omap1.c
@@ -3850,7 +3850,7 @@ static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
unsigned long sdram_size,
- const char *core)
+ const char *cpu_type)
{
int i;
struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1);
@@ -3858,12 +3858,9 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
DriveInfo *dinfo;
SysBusDevice *busdev;
- if (!core)
- core = "ti925t";
-
/* Core */
s->mpu_model = omap310;
- s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, core));
+ s->cpu = ARM_CPU(cpu_create(cpu_type));
s->sdram_size = sdram_size;
s->sram_size = OMAP15XX_SRAM_SIZE;
diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
index 5821477..3f6076e 100644
--- a/hw/arm/omap2.c
+++ b/hw/arm/omap2.c
@@ -2250,7 +2250,7 @@ static const struct dma_irq_map omap2_dma_irq_map[] = {
struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
unsigned long sdram_size,
- const char *core)
+ const char *cpu_type)
{
struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1);
qemu_irq dma_irqs[4];
@@ -2261,7 +2261,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
/* Core */
s->mpu_model = omap2420;
- s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, core ?: "arm1136-r2"));
+ s->cpu = ARM_CPU(cpu_create(cpu_type));
s->sdram_size = sdram_size;
s->sram_size = OMAP242X_SRAM_SIZE;
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
index 4535617..9a14270 100644
--- a/hw/arm/omap_sx1.c
+++ b/hw/arm/omap_sx1.c
@@ -36,6 +36,7 @@
#include "sysemu/block-backend.h"
#include "sysemu/qtest.h"
#include "exec/address-spaces.h"
+#include "cpu.h"
/*****************************************************************************/
/* Siemens SX1 Cellphone V1 */
@@ -120,7 +121,7 @@ static void sx1_init(MachineState *machine, const int version)
}
mpu = omap310_mpu_init(address_space, sx1_binfo.ram_size,
- machine->cpu_model);
+ machine->cpu_type);
/* External Flash (EMIFS) */
memory_region_init_ram(flash, NULL, "omap_sx1.flash0-0", flash_size,
@@ -224,6 +225,7 @@ static void sx1_machine_v2_class_init(ObjectClass *oc, void *data)
mc->desc = "Siemens SX1 (OMAP310) V2";
mc->init = sx1_init_v2;
mc->ignore_memory_transaction_failures = true;
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
}
static const TypeInfo sx1_machine_v2_type = {
@@ -239,6 +241,7 @@ static void sx1_machine_v1_class_init(ObjectClass *oc, void *data)
mc->desc = "Siemens SX1 (OMAP310) V1";
mc->init = sx1_init_v1;
mc->ignore_memory_transaction_failures = true;
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
}
static const TypeInfo sx1_machine_v1_type = {
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
index bf070a2..b8753e2 100644
--- a/hw/arm/palm.c
+++ b/hw/arm/palm.c
@@ -29,6 +29,7 @@
#include "hw/devices.h"
#include "hw/loader.h"
#include "exec/address-spaces.h"
+#include "cpu.h"
static uint32_t static_readb(void *opaque, hwaddr offset)
{
@@ -195,7 +196,6 @@ static struct arm_boot_info palmte_binfo = {
static void palmte_init(MachineState *machine)
{
- const char *cpu_model = machine->cpu_model;
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
@@ -211,7 +211,7 @@ static void palmte_init(MachineState *machine)
MemoryRegion *flash = g_new(MemoryRegion, 1);
MemoryRegion *cs = g_new(MemoryRegion, 4);
- mpu = omap310_mpu_init(address_space_mem, sdram_size, cpu_model);
+ mpu = omap310_mpu_init(address_space_mem, sdram_size, machine->cpu_type);
/* External Flash (EMIFS) */
memory_region_init_ram(flash, NULL, "palmte.flash", flash_size,
@@ -275,6 +275,7 @@ static void palmte_machine_init(MachineClass *mc)
mc->desc = "Palm Tungsten|E aka. Cheetah PDA (OMAP310)";
mc->init = palmte_init;
mc->ignore_memory_transaction_failures = true;
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
}
DEFINE_MACHINE("cheetah", palmte_machine_init)
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index c16657d..cf07234 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -2052,21 +2052,19 @@ static void pxa2xx_reset(void *opaque, int line, int level)
/* Initialise a PXA270 integrated chip (ARM based core). */
PXA2xxState *pxa270_init(MemoryRegion *address_space,
- unsigned int sdram_size, const char *revision)
+ unsigned int sdram_size, const char *cpu_type)
{
PXA2xxState *s;
int i;
DriveInfo *dinfo;
s = g_new0(PXA2xxState, 1);
- if (revision && strncmp(revision, "pxa27", 5)) {
+ if (strncmp(cpu_type, "pxa27", 5)) {
fprintf(stderr, "Machine requires a PXA27x processor.\n");
exit(1);
}
- if (!revision)
- revision = "pxa270";
- s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, revision));
+ s->cpu = ARM_CPU(cpu_create(cpu_type));
s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0);
/* SDRAM & Internal Memory Storage */
@@ -2192,7 +2190,7 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
s = g_new0(PXA2xxState, 1);
- s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, "pxa255"));
+ s->cpu = ARM_CPU(cpu_create(ARM_CPU_TYPE_NAME("pxa255")));
s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0);
/* SDRAM & Internal Memory Storage */
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index f3a49b6..87cd1e5 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -57,7 +57,6 @@ static void realview_init(MachineState *machine,
{
ARMCPU *cpu = NULL;
CPUARMState *env;
- ObjectClass *cpu_oc;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram_lo;
MemoryRegion *ram_hi = g_new(MemoryRegion, 1);
@@ -98,14 +97,8 @@ static void realview_init(MachineState *machine,
break;
}
- cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, machine->cpu_model);
- if (!cpu_oc) {
- fprintf(stderr, "Unable to find CPU definition\n");
- exit(1);
- }
-
for (n = 0; n < smp_cpus; n++) {
- Object *cpuobj = object_new(object_class_get_name(cpu_oc));
+ Object *cpuobj = object_new(machine->cpu_type);
/* By default A9,A15 and ARM1176 CPUs have EL3 enabled. This board
* does not currently support EL3 so the CPU EL3 property is disabled
@@ -361,33 +354,21 @@ static void realview_init(MachineState *machine,
static void realview_eb_init(MachineState *machine)
{
- if (!machine->cpu_model) {
- machine->cpu_model = "arm926";
- }
realview_init(machine, BOARD_EB);
}
static void realview_eb_mpcore_init(MachineState *machine)
{
- if (!machine->cpu_model) {
- machine->cpu_model = "arm11mpcore";
- }
realview_init(machine, BOARD_EB_MPCORE);
}
static void realview_pb_a8_init(MachineState *machine)
{
- if (!machine->cpu_model) {
- machine->cpu_model = "cortex-a8";
- }
realview_init(machine, BOARD_PB_A8);
}
static void realview_pbx_a9_init(MachineState *machine)
{
- if (!machine->cpu_model) {
- machine->cpu_model = "cortex-a9";
- }
realview_init(machine, BOARD_PBX_A9);
}
@@ -399,6 +380,7 @@ static void realview_eb_class_init(ObjectClass *oc, void *data)
mc->init = realview_eb_init;
mc->block_default_type = IF_SCSI;
mc->ignore_memory_transaction_failures = true;
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
}
static const TypeInfo realview_eb_type = {
@@ -416,6 +398,7 @@ static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data)
mc->block_default_type = IF_SCSI;
mc->max_cpus = 4;
mc->ignore_memory_transaction_failures = true;
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm11mpcore");
}
static const TypeInfo realview_eb_mpcore_type = {
@@ -431,6 +414,7 @@ static void realview_pb_a8_class_init(ObjectClass *oc, void *data)
mc->desc = "ARM RealView Platform Baseboard for Cortex-A8";
mc->init = realview_pb_a8_init;
mc->ignore_memory_transaction_failures = true;
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a8");
}
static const TypeInfo realview_pb_a8_type = {
@@ -447,6 +431,7 @@ static void realview_pbx_a9_class_init(ObjectClass *oc, void *data)
mc->init = realview_pbx_a9_init;
mc->max_cpus = 4;
mc->ignore_memory_transaction_failures = true;
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
}
static const TypeInfo realview_pbx_a9_type = {
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index 6406421..feccdb0 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -30,6 +30,7 @@
#include "hw/sysbus.h"
#include "exec/address-spaces.h"
#include "sysemu/sysemu.h"
+#include "cpu.h"
#undef REG_FMT
#define REG_FMT "0x%02lx"
@@ -909,13 +910,10 @@ static void spitz_common_init(MachineState *machine,
DeviceState *scp0, *scp1 = NULL;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *rom = g_new(MemoryRegion, 1);
- const char *cpu_model = machine->cpu_model;
-
- if (!cpu_model)
- cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0";
/* Setup CPU & memory */
- mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size, cpu_model);
+ mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size,
+ machine->cpu_type);
sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
@@ -984,6 +982,7 @@ static void akitapda_class_init(ObjectClass *oc, void *data)
mc->desc = "Sharp SL-C1000 (Akita) PDA (PXA270)";
mc->init = akita_init;
mc->ignore_memory_transaction_failures = true;
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
}
static const TypeInfo akitapda_type = {
@@ -1000,6 +999,7 @@ static void spitzpda_class_init(ObjectClass *oc, void *data)
mc->init = spitz_init;
mc->block_default_type = IF_IDE;
mc->ignore_memory_transaction_failures = true;
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
}
static const TypeInfo spitzpda_type = {
@@ -1016,6 +1016,7 @@ static void borzoipda_class_init(ObjectClass *oc, void *data)
mc->init = borzoi_init;
mc->block_default_type = IF_IDE;
mc->ignore_memory_transaction_failures = true;
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
}
static const TypeInfo borzoipda_type = {
@@ -1032,6 +1033,7 @@ static void terrierpda_class_init(ObjectClass *oc, void *data)
mc->init = terrier_init;
mc->block_default_type = IF_IDE;
mc->ignore_memory_transaction_failures = true;
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5");
}
static const TypeInfo terrierpda_type = {
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index b3aad23..de7c0fc 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -22,6 +22,7 @@
#include "sysemu/sysemu.h"
#include "hw/char/pl011.h"
#include "hw/misc/unimp.h"
+#include "cpu.h"
#define GPIO_A 0
#define GPIO_B 1
@@ -1225,8 +1226,7 @@ static stellaris_board_info stellaris_boards[] = {
}
};
-static void stellaris_init(const char *kernel_filename, const char *cpu_model,
- stellaris_board_info *board)
+static void stellaris_init(MachineState *ms, stellaris_board_info *board)
{
static const int uart_irq[] = {5, 6, 33, 34};
static const int timer_irq[] = {19, 21, 23, 35};
@@ -1298,7 +1298,7 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
memory_region_add_subregion(system_memory, 0x20000000, sram);
nvic = armv7m_init(system_memory, flash_size, NUM_IRQ_LINES,
- kernel_filename, cpu_model);
+ ms->kernel_filename, ms->cpu_type);
qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0,
qemu_allocate_irq(&do_sys_reset, NULL, 0));
@@ -1435,16 +1435,12 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
/* FIXME: Figure out how to generate these from stellaris_boards. */
static void lm3s811evb_init(MachineState *machine)
{
- const char *cpu_model = machine->cpu_model;
- const char *kernel_filename = machine->kernel_filename;
- stellaris_init(kernel_filename, cpu_model, &stellaris_boards[0]);
+ stellaris_init(machine, &stellaris_boards[0]);
}
static void lm3s6965evb_init(MachineState *machine)
{
- const char *cpu_model = machine->cpu_model;
- const char *kernel_filename = machine->kernel_filename;
- stellaris_init(kernel_filename, cpu_model, &stellaris_boards[1]);
+ stellaris_init(machine, &stellaris_boards[1]);
}
static void lm3s811evb_class_init(ObjectClass *oc, void *data)
@@ -1454,6 +1450,7 @@ static void lm3s811evb_class_init(ObjectClass *oc, void *data)
mc->desc = "Stellaris LM3S811EVB";
mc->init = lm3s811evb_init;
mc->ignore_memory_transaction_failures = true;
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
}
static const TypeInfo lm3s811evb_type = {
@@ -1469,6 +1466,7 @@ static void lm3s6965evb_class_init(ObjectClass *oc, void *data)
mc->desc = "Stellaris LM3S6965EVB";
mc->init = lm3s6965evb_init;
mc->ignore_memory_transaction_failures = true;
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
}
static const TypeInfo lm3s6965evb_type = {
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
index f61e735..1cd6374 100644
--- a/hw/arm/stm32f205_soc.c
+++ b/hw/arm/stm32f205_soc.c
@@ -112,7 +112,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
armv7m = DEVICE(&s->armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 96);
- qdev_prop_set_string(armv7m, "cpu-model", s->cpu_model);
+ qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
"memory", &error_abort);
object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
@@ -200,7 +200,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
}
static Property stm32f205_soc_properties[] = {
- DEFINE_PROP_STRING("cpu-model", STM32F205State, cpu_model),
+ DEFINE_PROP_STRING("cpu-type", STM32F205State, cpu_type),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
index c1145dd..3d1a231 100644
--- a/hw/arm/strongarm.c
+++ b/hw/arm/strongarm.c
@@ -1581,23 +1581,19 @@ static const TypeInfo strongarm_ssp_info = {
/* Main CPU functions */
StrongARMState *sa1110_init(MemoryRegion *sysmem,
- unsigned int sdram_size, const char *rev)
+ unsigned int sdram_size, const char *cpu_type)
{
StrongARMState *s;
int i;
s = g_new0(StrongARMState, 1);
- if (!rev) {
- rev = "sa1110-b5";
- }
-
- if (strncmp(rev, "sa1110", 6)) {
+ if (strncmp(cpu_type, "sa1110", 6)) {
error_report("Machine requires a SA1110 processor.");
exit(1);
}
- s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, rev));
+ s->cpu = ARM_CPU(cpu_create(cpu_type));
memory_region_allocate_system_memory(&s->sdram, NULL, "strongarm.sdram",
sdram_size);
diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
index 1134cf7..0447963 100644
--- a/hw/arm/tosa.c
+++ b/hw/arm/tosa.c
@@ -219,7 +219,6 @@ static struct arm_boot_info tosa_binfo = {
static void tosa_init(MachineState *machine)
{
- const char *cpu_model = machine->cpu_model;
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
@@ -229,9 +228,6 @@ static void tosa_init(MachineState *machine)
TC6393xbState *tmio;
DeviceState *scp0, *scp1;
- if (!cpu_model)
- cpu_model = "pxa255";
-
mpu = pxa255_init(address_space_mem, tosa_binfo.ram_size);
memory_region_init_ram(rom, NULL, "tosa.rom", TOSA_ROM, &error_fatal);
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
index 76664e4..418792c 100644
--- a/hw/arm/versatilepb.c
+++ b/hw/arm/versatilepb.c
@@ -181,7 +181,6 @@ static struct arm_boot_info versatile_binfo;
static void versatile_init(MachineState *machine, int board_id)
{
- ObjectClass *cpu_oc;
Object *cpuobj;
ARMCPU *cpu;
MemoryRegion *sysmem = get_system_memory();
@@ -207,17 +206,7 @@ static void versatile_init(MachineState *machine, int board_id)
exit(1);
}
- if (!machine->cpu_model) {
- machine->cpu_model = "arm926";
- }
-
- cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, machine->cpu_model);
- if (!cpu_oc) {
- fprintf(stderr, "Unable to find CPU definition\n");
- exit(1);
- }
-
- cpuobj = object_new(object_class_get_name(cpu_oc));
+ cpuobj = object_new(machine->cpu_type);
/* By default ARM1176 CPUs have EL3 enabled. This board does not
* currently support EL3 so the CPU EL3 property is disabled before
@@ -404,6 +393,7 @@ static void versatilepb_class_init(ObjectClass *oc, void *data)
mc->init = vpb_init;
mc->block_default_type = IF_SCSI;
mc->ignore_memory_transaction_failures = true;
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
}
static const TypeInfo versatilepb_type = {
@@ -420,6 +410,7 @@ static void versatileab_class_init(ObjectClass *oc, void *data)
mc->init = vab_init;
mc->block_default_type = IF_SCSI;
mc->ignore_memory_transaction_failures = true;
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
}
static const TypeInfo versatileab_type = {
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index e3acab6..2e5f670 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -186,7 +186,7 @@ typedef struct {
typedef void DBoardInitFn(const VexpressMachineState *machine,
ram_addr_t ram_size,
- const char *cpu_model,
+ const char *cpu_type,
qemu_irq *pic);
struct VEDBoardInfo {
@@ -202,22 +202,16 @@ struct VEDBoardInfo {
DBoardInitFn *init;
};
-static void init_cpus(const char *cpu_model, const char *privdev,
+static void init_cpus(const char *cpu_type, const char *privdev,
hwaddr periphbase, qemu_irq *pic, bool secure)
{
- ObjectClass *cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
DeviceState *dev;
SysBusDevice *busdev;
int n;
- if (!cpu_oc) {
- fprintf(stderr, "Unable to find CPU definition\n");
- exit(1);
- }
-
/* Create the actual CPUs */
for (n = 0; n < smp_cpus; n++) {
- Object *cpuobj = object_new(object_class_get_name(cpu_oc));
+ Object *cpuobj = object_new(cpu_type);
if (!secure) {
object_property_set_bool(cpuobj, false, "has_el3", NULL);
@@ -262,7 +256,7 @@ static void init_cpus(const char *cpu_model, const char *privdev,
static void a9_daughterboard_init(const VexpressMachineState *vms,
ram_addr_t ram_size,
- const char *cpu_model,
+ const char *cpu_type,
qemu_irq *pic)
{
MemoryRegion *sysmem = get_system_memory();
@@ -270,10 +264,6 @@ static void a9_daughterboard_init(const VexpressMachineState *vms,
MemoryRegion *lowram = g_new(MemoryRegion, 1);
ram_addr_t low_ram_size;
- if (!cpu_model) {
- cpu_model = "cortex-a9";
- }
-
if (ram_size > 0x40000000) {
/* 1GB is the maximum the address space permits */
fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM\n");
@@ -295,7 +285,7 @@ static void a9_daughterboard_init(const VexpressMachineState *vms,
memory_region_add_subregion(sysmem, 0x60000000, ram);
/* 0x1e000000 A9MPCore (SCU) private memory region */
- init_cpus(cpu_model, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, vms->secure);
+ init_cpus(cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, vms->secure);
/* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
@@ -351,17 +341,13 @@ static VEDBoardInfo a9_daughterboard = {
static void a15_daughterboard_init(const VexpressMachineState *vms,
ram_addr_t ram_size,
- const char *cpu_model,
+ const char *cpu_type,
qemu_irq *pic)
{
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *sram = g_new(MemoryRegion, 1);
- if (!cpu_model) {
- cpu_model = "cortex-a15";
- }
-
{
/* We have to use a separate 64 bit variable here to avoid the gcc
* "comparison is always false due to limited range of data type"
@@ -380,7 +366,7 @@ static void a15_daughterboard_init(const VexpressMachineState *vms,
memory_region_add_subregion(sysmem, 0x80000000, ram);
/* 0x2c000000 A15MPCore private memory region (GIC) */
- init_cpus(cpu_model, TYPE_A15MPCORE_PRIV, 0x2c000000, pic, vms->secure);
+ init_cpus(cpu_type, TYPE_A15MPCORE_PRIV, 0x2c000000, pic, vms->secure);
/* A15 daughterboard peripherals: */
@@ -560,7 +546,7 @@ static void vexpress_common_init(MachineState *machine)
const hwaddr *map = daughterboard->motherboard_map;
int i;
- daughterboard->init(vms, machine->ram_size, machine->cpu_model, pic);
+ daughterboard->init(vms, machine->ram_size, machine->cpu_type, pic);
/*
* If a bios file was provided, attempt to map it into memory
@@ -761,6 +747,7 @@ static void vexpress_a9_class_init(ObjectClass *oc, void *data)
VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
mc->desc = "ARM Versatile Express for Cortex-A9";
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
vmc->daughterboard = &a9_daughterboard;
}
@@ -771,6 +758,7 @@ static void vexpress_a15_class_init(ObjectClass *oc, void *data)
VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
mc->desc = "ARM Versatile Express for Cortex-A15";
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
vmc->daughterboard = &a15_daughterboard;
}
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index fe96557..fe26e99 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -163,13 +163,13 @@ static const int a15irqmap[] = {
};
static const char *valid_cpus[] = {
- "cortex-a15",
- "cortex-a53",
- "cortex-a57",
- "host",
+ ARM_CPU_TYPE_NAME("cortex-a15"),
+ ARM_CPU_TYPE_NAME("cortex-a53"),
+ ARM_CPU_TYPE_NAME("cortex-a57"),
+ ARM_CPU_TYPE_NAME("host"),
};
-static bool cpuname_valid(const char *cpu)
+static bool cpu_type_valid(const char *cpu)
{
int i;
@@ -1258,18 +1258,8 @@ static void machvirt_init(MachineState *machine)
MemoryRegion *secure_sysmem = NULL;
int n, virt_max_cpus;
MemoryRegion *ram = g_new(MemoryRegion, 1);
- const char *cpu_model = machine->cpu_model;
- char **cpustr;
- ObjectClass *oc;
- const char *typename;
- CPUClass *cc;
- Error *err = NULL;
bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0);
- if (!cpu_model) {
- cpu_model = "cortex-a15";
- }
-
/* We can probe only here because during property set
* KVM is not available yet
*/
@@ -1286,11 +1276,8 @@ static void machvirt_init(MachineState *machine)
}
}
- /* Separate the actual CPU model name from any appended features */
- cpustr = g_strsplit(cpu_model, ",", 2);
-
- if (!cpuname_valid(cpustr[0])) {
- error_report("mach-virt: CPU %s not supported", cpustr[0]);
+ if (!cpu_type_valid(machine->cpu_type)) {
+ error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
exit(1);
}
@@ -1360,22 +1347,6 @@ static void machvirt_init(MachineState *machine)
create_fdt(vms);
- oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);
- if (!oc) {
- error_report("Unable to find CPU definition");
- exit(1);
- }
- typename = object_class_get_name(oc);
-
- /* convert -smp CPU options specified by the user into global props */
- cc = CPU_CLASS(oc);
- cc->parse_features(typename, cpustr[1], &err);
- g_strfreev(cpustr);
- if (err) {
- error_report_err(err);
- exit(1);
- }
-
possible_cpus = mc->possible_cpu_arch_ids(machine);
for (n = 0; n < possible_cpus->len; n++) {
Object *cpuobj;
@@ -1385,7 +1356,7 @@ static void machvirt_init(MachineState *machine)
break;
}
- cpuobj = object_new(typename);
+ cpuobj = object_new(machine->cpu_type);
object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id,
"mp-affinity", NULL);
@@ -1630,6 +1601,7 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
mc->minimum_page_bits = 12;
mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
}
static const TypeInfo virt_machine_info = {
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 3759cf8..1836a4e 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -158,11 +158,9 @@ static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
static void zynq_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
- const char *cpu_model = machine->cpu_model;
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
- ObjectClass *cpu_oc;
ARMCPU *cpu;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
@@ -174,12 +172,7 @@ static void zynq_init(MachineState *machine)
qemu_irq pic[64];
int n;
- if (!cpu_model) {
- cpu_model = "cortex-a9";
- }
- cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
-
- cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc)));
+ cpu = ARM_CPU(object_new(machine->cpu_type));
/* By default A9 CPUs have EL3 enabled. This board does not
* currently support EL3 so the CPU EL3 property is disabled before
@@ -327,6 +320,7 @@ static void zynq_machine_init(MachineClass *mc)
mc->max_cpus = 1;
mc->no_sdcard = 1;
mc->ignore_memory_transaction_failures = true;
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
}
DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init)
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
index 417bc1a..60561c7 100644
--- a/hw/arm/z2.c
+++ b/hw/arm/z2.c
@@ -26,6 +26,7 @@
#include "audio/audio.h"
#include "exec/address-spaces.h"
#include "sysemu/qtest.h"
+#include "cpu.h"
#ifdef DEBUG_Z2
#define DPRINTF(fmt, ...) \
@@ -296,7 +297,6 @@ static const TypeInfo aer915_info = {
static void z2_init(MachineState *machine)
{
- const char *cpu_model = machine->cpu_model;
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
@@ -309,12 +309,8 @@ static void z2_init(MachineState *machine)
I2CBus *bus;
DeviceState *wm;
- if (!cpu_model) {
- cpu_model = "pxa270-c5";
- }
-
/* Setup CPU & memory */
- mpu = pxa270_init(address_space_mem, z2_binfo.ram_size, cpu_model);
+ mpu = pxa270_init(address_space_mem, z2_binfo.ram_size, machine->cpu_type);
#ifdef TARGET_WORDS_BIGENDIAN
be = 1;
@@ -371,6 +367,7 @@ static void z2_machine_init(MachineClass *mc)
mc->desc = "Zipit Z2 (PXA27x)";
mc->init = z2_init;
mc->ignore_memory_transaction_failures = true;
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5");
}
DEFINE_MACHINE("z2", z2_machine_init)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index a1acce3..ff7ff28 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -905,7 +905,7 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
}
cpuname = g_strsplit(cpu_model, ",", 1);
- typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]);
+ typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpuname[0]);
oc = object_class_by_name(typename);
g_strfreev(cpuname);
g_free(typename);
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [Qemu-devel] [PATCH v2 5/5] arm: drop intermediate cpu_model -> cpu type parsing and use cpu type directly
2017-09-13 16:04 ` [Qemu-devel] [PATCH v2 5/5] arm: drop intermediate cpu_model -> cpu type parsing and use cpu type directly Igor Mammedov
@ 2017-09-14 3:47 ` Philippe Mathieu-Daudé
2017-09-14 7:50 ` Igor Mammedov
2017-09-14 17:57 ` Alistair Francis
2017-09-18 21:53 ` [Qemu-devel] [PATCH] !fixup arm: missed comment update Philippe Mathieu-Daudé
2 siblings, 1 reply; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-09-14 3:47 UTC (permalink / raw)
To: Igor Mammedov, qemu-arm; +Cc: qemu-devel
Hi Igor,
awesome clean refactor!
just 1 comment inlined.
On 09/13/2017 01:04 PM, Igor Mammedov wrote:
> there are 2 use cases to deal with:
> 1: fixed CPU models per board/soc
> 2: boards with user configurable cpu_model and fallback to
> default cpu_model if user hasn't specified one explicitly
>
> For the 1st
> drop intermediate cpu_model parsing and use const cpu type
> directly, which replaces:
> typename = object_class_get_name(
> cpu_class_by_name(TYPE_ARM_CPU, cpu_model))
> object_new(typename)
> with
> object_new(FOO_CPU_TYPE_NAME)
> or
> cpu_generic_init(BASE_CPU_TYPE, "my cpu model")
> with
> cpu_create(FOO_CPU_TYPE_NAME)
>
> as result 1st use case doesn't have to invoke not necessary
> translation and not needed code is removed.
>
> For the 2nd
> 1: set default cpu type with MachineClass::default_cpu_type and
> 2: use generic cpu_model parsing that done before machine_init()
> is run and:
> 2.1: drop custom cpu_model parsing where pattern is:
> typename = object_class_get_name(
> cpu_class_by_name(TYPE_ARM_CPU, cpu_model))
> [parse_features(typename, cpu_model, &err) ]
>
> 2.2: or replace cpu_generic_init() which does what
> 2.1 does + create_cpu(typename) with just
> create_cpu(machine->cpu_type)
> as result cpu_name -> cpu_type translation is done using
> generic machine code one including parsing optional features
> if supported/present (removes a bunch of duplicated cpu_model
> parsing code) and default cpu type is defined in an uniform way
> within machine_class_init callbacks instead of adhoc places
> in boadr's machine_init code.
>
> Signed-off-by: Igor Mammedov <imammedo@redhat.com>
> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
> ---
> v2:
> - fix merge conflicts with ignore_memory_transaction_failures
> - fix couple merge conflicts where SoC type string where replaced by type macro
> - keep plain prefix string in: strncmp(cpu_type, "pxa27", 5)
> - s/"%s" ARM_CPU_TYPE_SUFFIX/ARM_CPU_TYPE_NAME("%s")/
> ---
> include/hw/arm/armv7m.h | 2 +-
> include/hw/arm/aspeed_soc.h | 2 +-
> include/hw/arm/stm32f205_soc.h | 2 +-
> target/arm/cpu.h | 3 +++
> hw/arm/armv7m.c | 40 +++++-------------------------------
> hw/arm/aspeed_soc.c | 13 +++++-------
> hw/arm/collie.c | 10 +++------
> hw/arm/exynos4210.c | 6 +-----
> hw/arm/gumstix.c | 5 +++--
> hw/arm/highbank.c | 10 ++++-----
> hw/arm/integratorcp.c | 30 ++-------------------------
> hw/arm/mainstone.c | 9 ++++-----
> hw/arm/mps2.c | 17 +++++++---------
> hw/arm/musicpal.c | 7 ++-----
> hw/arm/netduino2.c | 2 +-
> hw/arm/nseries.c | 4 +++-
> hw/arm/omap1.c | 7 ++-----
> hw/arm/omap2.c | 4 ++--
> hw/arm/omap_sx1.c | 5 ++++-
> hw/arm/palm.c | 5 +++--
> hw/arm/pxa2xx.c | 10 ++++-----
> hw/arm/realview.c | 25 +++++------------------
> hw/arm/spitz.c | 12 ++++++-----
> hw/arm/stellaris.c | 16 +++++++--------
> hw/arm/stm32f205_soc.c | 4 ++--
> hw/arm/strongarm.c | 10 +++------
> hw/arm/tosa.c | 4 ----
> hw/arm/versatilepb.c | 15 +++-----------
> hw/arm/vexpress.c | 32 +++++++++--------------------
> hw/arm/virt.c | 46 +++++++++---------------------------------
> hw/arm/xilinx_zynq.c | 10 ++-------
> hw/arm/z2.c | 9 +++------
> target/arm/cpu.c | 2 +-
> 33 files changed, 114 insertions(+), 264 deletions(-)
>
> diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
> index 10eb058..68cb30d 100644
> --- a/include/hw/arm/armv7m.h
> +++ b/include/hw/arm/armv7m.h
> @@ -55,7 +55,7 @@ typedef struct ARMv7MState {
> MemoryRegion container;
>
> /* Properties */
> - char *cpu_model;
> + char *cpu_type;
> /* MemoryRegion the board provides to us (with its devices, RAM, etc) */
> MemoryRegion *board_memory;
> } ARMv7MState;
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index 0b88baa..f26914a 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -49,7 +49,7 @@ typedef struct AspeedSoCState {
>
> typedef struct AspeedSoCInfo {
> const char *name;
> - const char *cpu_model;
> + const char *cpu_type;
> uint32_t silicon_rev;
> hwaddr sdram_base;
> uint64_t sram_size;
> diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h
> index e2dce11..922a733 100644
> --- a/include/hw/arm/stm32f205_soc.h
> +++ b/include/hw/arm/stm32f205_soc.h
> @@ -52,7 +52,7 @@ typedef struct STM32F205State {
> SysBusDevice parent_obj;
> /*< public >*/
>
> - char *cpu_model;
> + char *cpu_type;
>
> ARMv7MState armv7m;
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 98b9b26..1bfdd8d 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -2088,6 +2088,9 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
>
> #define cpu_init(cpu_model) cpu_generic_init(TYPE_ARM_CPU, cpu_model)
>
> +#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
> +#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
> +
> #define cpu_signal_handler cpu_arm_signal_handler
> #define cpu_list arm_cpu_list
>
> diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
> index b64a409..57a6806 100644
> --- a/hw/arm/armv7m.c
> +++ b/hw/arm/armv7m.c
> @@ -151,10 +151,6 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
> SysBusDevice *sbd;
> Error *err = NULL;
> int i;
> - char **cpustr;
> - ObjectClass *oc;
> - const char *typename;
> - CPUClass *cc;
>
> if (!s->board_memory) {
> error_setg(errp, "memory property was not set");
> @@ -163,29 +159,7 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
>
> memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
>
> - cpustr = g_strsplit(s->cpu_model, ",", 2);
> -
> - oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);
> - if (!oc) {
> - error_setg(errp, "Unknown CPU model %s", cpustr[0]);
> - g_strfreev(cpustr);
> - return;
> - }
> -
> - cc = CPU_CLASS(oc);
> - typename = object_class_get_name(oc);
> - cc->parse_features(typename, cpustr[1], &err);
> - g_strfreev(cpustr);
> - if (err) {
> - error_propagate(errp, err);
> - return;
> - }
> -
> - s->cpu = ARM_CPU(object_new(typename));
> - if (!s->cpu) {
> - error_setg(errp, "Unknown CPU model %s", s->cpu_model);
> - return;
> - }
> + s->cpu = ARM_CPU(object_new(s->cpu_type));
>
> object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), "memory",
> &error_abort);
> @@ -241,7 +215,7 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
> }
>
> static Property armv7m_properties[] = {
> - DEFINE_PROP_STRING("cpu-model", ARMv7MState, cpu_model),
> + DEFINE_PROP_STRING("cpu-type", ARMv7MState, cpu_type),
> DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION,
> MemoryRegion *),
> DEFINE_PROP_END_OF_LIST(),
> @@ -275,20 +249,16 @@ static void armv7m_reset(void *opaque)
> Returns the ARMv7M device. */
>
> DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
> - const char *kernel_filename, const char *cpu_model)
> + const char *kernel_filename, const char *cpu_type)
> {
> DeviceState *armv7m;
>
> - if (cpu_model == NULL) {
> - cpu_model = "cortex-m3";
> - }
> -
> armv7m = qdev_create(NULL, TYPE_ARMV7M);
> qdev_prop_set_uint32(armv7m, "num-irq", num_irq);
> - qdev_prop_set_string(armv7m, "cpu-model", cpu_model);
> + qdev_prop_set_string(armv7m, "cpu-type", cpu_type);
> object_property_set_link(OBJECT(armv7m), OBJECT(get_system_memory()),
> "memory", &error_abort);
> - /* This will exit with an error if the user passed us a bad cpu_model */
> + /* This will exit with an error if the user passed us a bad cpu_type */
> qdev_init_nofail(armv7m);
>
> armv7m_load_kernel(ARM_CPU(first_cpu), kernel_filename, mem_size);
> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
> index 13c6393..5aa3d2d 100644
> --- a/hw/arm/aspeed_soc.c
> +++ b/hw/arm/aspeed_soc.c
> @@ -54,7 +54,7 @@ static const char *aspeed_soc_ast2500_typenames[] = {
> static const AspeedSoCInfo aspeed_socs[] = {
> {
> .name = "ast2400-a0",
> - .cpu_model = "arm926",
> + .cpu_type = ARM_CPU_TYPE_NAME("arm926"),
> .silicon_rev = AST2400_A0_SILICON_REV,
> .sdram_base = AST2400_SDRAM_BASE,
> .sram_size = 0x8000,
> @@ -65,7 +65,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
> .wdts_num = 2,
> }, {
> .name = "ast2400-a1",
> - .cpu_model = "arm926",
> + .cpu_type = ARM_CPU_TYPE_NAME("arm926"),
> .silicon_rev = AST2400_A1_SILICON_REV,
> .sdram_base = AST2400_SDRAM_BASE,
> .sram_size = 0x8000,
> @@ -76,7 +76,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
> .wdts_num = 2,
> }, {
> .name = "ast2400",
> - .cpu_model = "arm926",
> + .cpu_type = ARM_CPU_TYPE_NAME("arm926"),
> .silicon_rev = AST2400_A0_SILICON_REV,
> .sdram_base = AST2400_SDRAM_BASE,
> .sram_size = 0x8000,
> @@ -87,7 +87,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
> .wdts_num = 2,
> }, {
> .name = "ast2500-a1",
> - .cpu_model = "arm1176",
> + .cpu_type = ARM_CPU_TYPE_NAME("arm1176"),
> .silicon_rev = AST2500_A1_SILICON_REV,
> .sdram_base = AST2500_SDRAM_BASE,
> .sram_size = 0x9000,
> @@ -128,13 +128,10 @@ static void aspeed_soc_init(Object *obj)
> {
> AspeedSoCState *s = ASPEED_SOC(obj);
> AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> - char *cpu_typename;
> int i;
>
> - cpu_typename = g_strdup_printf("%s-" TYPE_ARM_CPU, sc->info->cpu_model);
> - object_initialize(&s->cpu, sizeof(s->cpu), cpu_typename);
> + object_initialize(&s->cpu, sizeof(s->cpu), sc->info->cpu_type);
> object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL);
> - g_free(cpu_typename);
>
> object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC);
> object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL);
> diff --git a/hw/arm/collie.c b/hw/arm/collie.c
> index 8830192..f8c566e 100644
> --- a/hw/arm/collie.c
> +++ b/hw/arm/collie.c
> @@ -18,7 +18,7 @@
> #include "hw/block/flash.h"
> #include "sysemu/block-backend.h"
> #include "exec/address-spaces.h"
> -#include "qom/cpu.h"
> +#include "cpu.h"
>
> static struct arm_boot_info collie_binfo = {
> .loader_start = SA_SDCS0,
> @@ -27,7 +27,6 @@ static struct arm_boot_info collie_binfo = {
>
> static void collie_init(MachineState *machine)
> {
> - const char *cpu_model = machine->cpu_model;
> const char *kernel_filename = machine->kernel_filename;
> const char *kernel_cmdline = machine->kernel_cmdline;
> const char *initrd_filename = machine->initrd_filename;
> @@ -35,11 +34,7 @@ static void collie_init(MachineState *machine)
> DriveInfo *dinfo;
> MemoryRegion *sysmem = get_system_memory();
>
> - if (!cpu_model) {
> - cpu_model = "sa1110";
> - }
> -
> - s = sa1110_init(sysmem, collie_binfo.ram_size, cpu_model);
> + s = sa1110_init(sysmem, collie_binfo.ram_size, machine->cpu_type);
>
> dinfo = drive_get(IF_PFLASH, 0, 0);
> pflash_cfi01_register(SA_CS0, NULL, "collie.fl1", 0x02000000,
> @@ -65,6 +60,7 @@ static void collie_machine_init(MachineClass *mc)
> mc->desc = "Sharp SL-5500 (Collie) PDA (SA-1110)";
> mc->init = collie_init;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("sa1110");
> }
>
> DEFINE_MACHINE("collie", collie_machine_init)
> diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
> index ee1438a..e8e1d81 100644
> --- a/hw/arm/exynos4210.c
> +++ b/hw/arm/exynos4210.c
> @@ -169,15 +169,11 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
> Exynos4210State *s = g_new(Exynos4210State, 1);
> qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
> SysBusDevice *busdev;
> - ObjectClass *cpu_oc;
> DeviceState *dev;
> int i, n;
>
> - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, "cortex-a9");
> - assert(cpu_oc);
> -
> for (n = 0; n < EXYNOS4210_NCPUS; n++) {
> - Object *cpuobj = object_new(object_class_get_name(cpu_oc));
> + Object *cpuobj = object_new(ARM_CPU_TYPE_NAME("cortex-a9"));
>
> /* By default A9 CPUs have EL3 enabled. This board does not currently
> * support EL3 so the CPU EL3 property is disabled before realization.
> diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c
> index 092ce36..bba9e9f 100644
> --- a/hw/arm/gumstix.c
> +++ b/hw/arm/gumstix.c
> @@ -44,6 +44,7 @@
> #include "sysemu/block-backend.h"
> #include "exec/address-spaces.h"
> #include "sysemu/qtest.h"
> +#include "cpu.h"
>
> static const int sector_len = 128 * 1024;
>
> @@ -86,7 +87,6 @@ static void connex_init(MachineState *machine)
>
> static void verdex_init(MachineState *machine)
> {
> - const char *cpu_model = machine->cpu_model;
> PXA2xxState *cpu;
> DriveInfo *dinfo;
> int be;
> @@ -95,7 +95,7 @@ static void verdex_init(MachineState *machine)
> uint32_t verdex_rom = 0x02000000;
> uint32_t verdex_ram = 0x10000000;
>
> - cpu = pxa270_init(address_space_mem, verdex_ram, cpu_model ?: "pxa270-c0");
> + cpu = pxa270_init(address_space_mem, verdex_ram, machine->cpu_type);
>
> dinfo = drive_get(IF_PFLASH, 0, 0);
> if (!dinfo && !qtest_enabled()) {
> @@ -144,6 +144,7 @@ static void verdex_class_init(ObjectClass *oc, void *data)
> mc->desc = "Gumstix Verdex (PXA270)";
> mc->init = verdex_init;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
> }
>
> static const TypeInfo verdex_type = {
> diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
> index ba27789..354c6b2 100644
> --- a/hw/arm/highbank.c
> +++ b/hw/arm/highbank.c
> @@ -222,7 +222,6 @@ enum cxmachines {
> static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
> {
> ram_addr_t ram_size = machine->ram_size;
> - const char *cpu_model = machine->cpu_model;
> const char *kernel_filename = machine->kernel_filename;
> const char *kernel_cmdline = machine->kernel_cmdline;
> const char *initrd_filename = machine->initrd_filename;
> @@ -239,19 +238,20 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
>
> switch (machine_id) {
> case CALXEDA_HIGHBANK:
> - cpu_model = "cortex-a9";
> + machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
> break;
> case CALXEDA_MIDWAY:
> - cpu_model = "cortex-a15";
> + machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
> break;
> + default:
> + assert(0);
> }
>
> for (n = 0; n < smp_cpus; n++) {
> - ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
> Object *cpuobj;
> ARMCPU *cpu;
>
> - cpuobj = object_new(object_class_get_name(oc));
> + cpuobj = object_new(machine->cpu_type);
> cpu = ARM_CPU(cpuobj);
>
> object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_SMC,
> diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
> index d603af9..e8303b8 100644
> --- a/hw/arm/integratorcp.c
> +++ b/hw/arm/integratorcp.c
> @@ -572,46 +572,19 @@ static struct arm_boot_info integrator_binfo = {
> static void integratorcp_init(MachineState *machine)
> {
> ram_addr_t ram_size = machine->ram_size;
> - const char *cpu_model = machine->cpu_model;
> const char *kernel_filename = machine->kernel_filename;
> const char *kernel_cmdline = machine->kernel_cmdline;
> const char *initrd_filename = machine->initrd_filename;
> - char **cpustr;
> - ObjectClass *cpu_oc;
> - CPUClass *cc;
> Object *cpuobj;
> ARMCPU *cpu;
> - const char *typename;
> MemoryRegion *address_space_mem = get_system_memory();
> MemoryRegion *ram = g_new(MemoryRegion, 1);
> MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
> qemu_irq pic[32];
> DeviceState *dev, *sic, *icp;
> int i;
> - Error *err = NULL;
>
> - if (!cpu_model) {
> - cpu_model = "arm926";
> - }
> -
> - cpustr = g_strsplit(cpu_model, ",", 2);
> -
> - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);
> - if (!cpu_oc) {
> - fprintf(stderr, "Unable to find CPU definition\n");
> - exit(1);
> - }
> - typename = object_class_get_name(cpu_oc);
> -
> - cc = CPU_CLASS(cpu_oc);
> - cc->parse_features(typename, cpustr[1], &err);
> - g_strfreev(cpustr);
> - if (err) {
> - error_report_err(err);
> - exit(1);
> - }
> -
> - cpuobj = object_new(typename);
> + cpuobj = object_new(machine->cpu_type);
>
> /* By default ARM1176 CPUs have EL3 enabled. This board does not
> * currently support EL3 so the CPU EL3 property is disabled before
> @@ -682,6 +655,7 @@ static void integratorcp_machine_init(MachineClass *mc)
> mc->desc = "ARM Integrator/CP (ARM926EJ-S)";
> mc->init = integratorcp_init;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
> }
>
> DEFINE_MACHINE("integratorcp", integratorcp_machine_init)
> diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
> index 637f52c..d07972a 100644
> --- a/hw/arm/mainstone.c
> +++ b/hw/arm/mainstone.c
> @@ -24,6 +24,7 @@
> #include "hw/sysbus.h"
> #include "exec/address-spaces.h"
> #include "sysemu/qtest.h"
> +#include "cpu.h"
>
> /* Device addresses */
> #define MST_FPGA_PHYS 0x08000000
> @@ -121,13 +122,10 @@ static void mainstone_common_init(MemoryRegion *address_space_mem,
> int i;
> int be;
> MemoryRegion *rom = g_new(MemoryRegion, 1);
> - const char *cpu_model = machine->cpu_model;
> -
> - if (!cpu_model)
> - cpu_model = "pxa270-c5";
>
> /* Setup CPU & memory */
> - mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size, cpu_model);
> + mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size,
> + machine->cpu_type);
> memory_region_init_ram(rom, NULL, "mainstone.rom", MAINSTONE_ROM,
> &error_fatal);
> memory_region_set_readonly(rom, true);
> @@ -197,6 +195,7 @@ static void mainstone2_machine_init(MachineClass *mc)
> mc->desc = "Mainstone II (PXA27x)";
> mc->init = mainstone_init;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5");
> }
>
> DEFINE_MACHINE("mainstone", mainstone2_machine_init)
> diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
> index abb0ab6..aeaad80 100644
> --- a/hw/arm/mps2.c
> +++ b/hw/arm/mps2.c
> @@ -46,7 +46,6 @@ typedef enum MPS2FPGAType {
> typedef struct {
> MachineClass parent;
> MPS2FPGAType fpga_type;
> - const char *cpu_model;
> uint32_t scc_id;
> } MPS2MachineClass;
>
> @@ -107,14 +106,12 @@ static void mps2_common_init(MachineState *machine)
> MPS2MachineState *mms = MPS2_MACHINE(machine);
> MPS2MachineClass *mmc = MPS2_MACHINE_GET_CLASS(machine);
> MemoryRegion *system_memory = get_system_memory();
> + MachineClass *mc = MACHINE_GET_CLASS(machine);
> DeviceState *armv7m, *sccdev;
>
> - if (!machine->cpu_model) {
> - machine->cpu_model = mmc->cpu_model;
> - }
> -
> - if (strcmp(machine->cpu_model, mmc->cpu_model) != 0) {
> - error_report("This board can only be used with CPU %s", mmc->cpu_model);
> + if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
> + error_report("This board can only be used with CPU %s",
> + mc->default_cpu_type);
> exit(1);
> }
>
> @@ -188,7 +185,7 @@ static void mps2_common_init(MachineState *machine)
> default:
> g_assert_not_reached();
> }
> - qdev_prop_set_string(armv7m, "cpu-model", machine->cpu_model);
> + qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type);
> object_property_set_link(OBJECT(&mms->armv7m), OBJECT(system_memory),
> "memory", &error_abort);
> object_property_set_bool(OBJECT(&mms->armv7m), true, "realized",
> @@ -339,7 +336,7 @@ static void mps2_an385_class_init(ObjectClass *oc, void *data)
>
> mc->desc = "ARM MPS2 with AN385 FPGA image for Cortex-M3";
> mmc->fpga_type = FPGA_AN385;
> - mmc->cpu_model = "cortex-m3";
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
> mmc->scc_id = 0x41040000 | (385 << 4);
> }
>
> @@ -350,7 +347,7 @@ static void mps2_an511_class_init(ObjectClass *oc, void *data)
>
> mc->desc = "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3";
> mmc->fpga_type = FPGA_AN511;
> - mmc->cpu_model = "cortex-m3";
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
> mmc->scc_id = 0x4104000 | (511 << 4);
> }
>
> diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
> index 7a6c0a6..b648770 100644
> --- a/hw/arm/musicpal.c
> +++ b/hw/arm/musicpal.c
> @@ -1570,7 +1570,6 @@ static struct arm_boot_info musicpal_binfo = {
>
> static void musicpal_init(MachineState *machine)
> {
> - const char *cpu_model = machine->cpu_model;
> const char *kernel_filename = machine->kernel_filename;
> const char *kernel_cmdline = machine->kernel_cmdline;
> const char *initrd_filename = machine->initrd_filename;
> @@ -1590,10 +1589,7 @@ static void musicpal_init(MachineState *machine)
> MemoryRegion *ram = g_new(MemoryRegion, 1);
> MemoryRegion *sram = g_new(MemoryRegion, 1);
>
> - if (!cpu_model) {
> - cpu_model = "arm926";
> - }
> - cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
> + cpu = ARM_CPU(cpu_create(machine->cpu_type));
>
> /* For now we use a fixed - the original - RAM size */
> memory_region_allocate_system_memory(ram, NULL, "musicpal.ram",
> @@ -1715,6 +1711,7 @@ static void musicpal_machine_init(MachineClass *mc)
> mc->desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)";
> mc->init = musicpal_init;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
> }
>
> DEFINE_MACHINE("musicpal", musicpal_machine_init)
> diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
> index 9d34d4c..f936017 100644
> --- a/hw/arm/netduino2.c
> +++ b/hw/arm/netduino2.c
> @@ -34,7 +34,7 @@ static void netduino2_init(MachineState *machine)
> DeviceState *dev;
>
> dev = qdev_create(NULL, TYPE_STM32F205_SOC);
> - qdev_prop_set_string(dev, "cpu-model", "cortex-m3");
> + qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
> object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);
>
> armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
> diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
> index a32ac82..58005b6 100644
> --- a/hw/arm/nseries.c
> +++ b/hw/arm/nseries.c
> @@ -1310,7 +1310,7 @@ static void n8x0_init(MachineState *machine,
> struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s));
> int sdram_size = binfo->ram_size;
>
> - s->mpu = omap2420_mpu_init(sysmem, sdram_size, machine->cpu_model);
> + s->mpu = omap2420_mpu_init(sysmem, sdram_size, machine->cpu_type);
>
> /* Setup peripherals
> *
> @@ -1426,6 +1426,7 @@ static void n800_class_init(ObjectClass *oc, void *data)
> mc->init = n800_init;
> mc->default_boot_order = "";
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm1136-r2");
> }
>
> static const TypeInfo n800_type = {
> @@ -1442,6 +1443,7 @@ static void n810_class_init(ObjectClass *oc, void *data)
> mc->init = n810_init;
> mc->default_boot_order = "";
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm1136-r2");
> }
>
> static const TypeInfo n810_type = {
> diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
> index 04e65ce..b3e7625 100644
> --- a/hw/arm/omap1.c
> +++ b/hw/arm/omap1.c
> @@ -3850,7 +3850,7 @@ static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
>
> struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
> unsigned long sdram_size,
> - const char *core)
> + const char *cpu_type)
> {
> int i;
> struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1);
> @@ -3858,12 +3858,9 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
> DriveInfo *dinfo;
> SysBusDevice *busdev;
>
> - if (!core)
> - core = "ti925t";
> -
> /* Core */
> s->mpu_model = omap310;
> - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, core));
> + s->cpu = ARM_CPU(cpu_create(cpu_type));
> s->sdram_size = sdram_size;
> s->sram_size = OMAP15XX_SRAM_SIZE;
>
> diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
> index 5821477..3f6076e 100644
> --- a/hw/arm/omap2.c
> +++ b/hw/arm/omap2.c
> @@ -2250,7 +2250,7 @@ static const struct dma_irq_map omap2_dma_irq_map[] = {
>
> struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
> unsigned long sdram_size,
> - const char *core)
> + const char *cpu_type)
> {
> struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1);
> qemu_irq dma_irqs[4];
> @@ -2261,7 +2261,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
>
> /* Core */
> s->mpu_model = omap2420;
> - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, core ?: "arm1136-r2"));
> + s->cpu = ARM_CPU(cpu_create(cpu_type));
> s->sdram_size = sdram_size;
> s->sram_size = OMAP242X_SRAM_SIZE;
>
> diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
> index 4535617..9a14270 100644
> --- a/hw/arm/omap_sx1.c
> +++ b/hw/arm/omap_sx1.c
> @@ -36,6 +36,7 @@
> #include "sysemu/block-backend.h"
> #include "sysemu/qtest.h"
> #include "exec/address-spaces.h"
> +#include "cpu.h"
>
> /*****************************************************************************/
> /* Siemens SX1 Cellphone V1 */
> @@ -120,7 +121,7 @@ static void sx1_init(MachineState *machine, const int version)
> }
>
> mpu = omap310_mpu_init(address_space, sx1_binfo.ram_size,
> - machine->cpu_model);
> + machine->cpu_type);
>
> /* External Flash (EMIFS) */
> memory_region_init_ram(flash, NULL, "omap_sx1.flash0-0", flash_size,
> @@ -224,6 +225,7 @@ static void sx1_machine_v2_class_init(ObjectClass *oc, void *data)
> mc->desc = "Siemens SX1 (OMAP310) V2";
> mc->init = sx1_init_v2;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
> }
>
> static const TypeInfo sx1_machine_v2_type = {
> @@ -239,6 +241,7 @@ static void sx1_machine_v1_class_init(ObjectClass *oc, void *data)
> mc->desc = "Siemens SX1 (OMAP310) V1";
> mc->init = sx1_init_v1;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
> }
>
> static const TypeInfo sx1_machine_v1_type = {
> diff --git a/hw/arm/palm.c b/hw/arm/palm.c
> index bf070a2..b8753e2 100644
> --- a/hw/arm/palm.c
> +++ b/hw/arm/palm.c
> @@ -29,6 +29,7 @@
> #include "hw/devices.h"
> #include "hw/loader.h"
> #include "exec/address-spaces.h"
> +#include "cpu.h"
>
> static uint32_t static_readb(void *opaque, hwaddr offset)
> {
> @@ -195,7 +196,6 @@ static struct arm_boot_info palmte_binfo = {
>
> static void palmte_init(MachineState *machine)
> {
> - const char *cpu_model = machine->cpu_model;
> const char *kernel_filename = machine->kernel_filename;
> const char *kernel_cmdline = machine->kernel_cmdline;
> const char *initrd_filename = machine->initrd_filename;
> @@ -211,7 +211,7 @@ static void palmte_init(MachineState *machine)
> MemoryRegion *flash = g_new(MemoryRegion, 1);
> MemoryRegion *cs = g_new(MemoryRegion, 4);
>
> - mpu = omap310_mpu_init(address_space_mem, sdram_size, cpu_model);
> + mpu = omap310_mpu_init(address_space_mem, sdram_size, machine->cpu_type);
>
> /* External Flash (EMIFS) */
> memory_region_init_ram(flash, NULL, "palmte.flash", flash_size,
> @@ -275,6 +275,7 @@ static void palmte_machine_init(MachineClass *mc)
> mc->desc = "Palm Tungsten|E aka. Cheetah PDA (OMAP310)";
> mc->init = palmte_init;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
> }
>
> DEFINE_MACHINE("cheetah", palmte_machine_init)
> diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
> index c16657d..cf07234 100644
> --- a/hw/arm/pxa2xx.c
> +++ b/hw/arm/pxa2xx.c
> @@ -2052,21 +2052,19 @@ static void pxa2xx_reset(void *opaque, int line, int level)
>
> /* Initialise a PXA270 integrated chip (ARM based core). */
> PXA2xxState *pxa270_init(MemoryRegion *address_space,
> - unsigned int sdram_size, const char *revision)
> + unsigned int sdram_size, const char *cpu_type)
> {
> PXA2xxState *s;
> int i;
> DriveInfo *dinfo;
> s = g_new0(PXA2xxState, 1);
>
> - if (revision && strncmp(revision, "pxa27", 5)) {
> + if (strncmp(cpu_type, "pxa27", 5)) {
> fprintf(stderr, "Machine requires a PXA27x processor.\n");
> exit(1);
> }
> - if (!revision)
> - revision = "pxa270";
>
> - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, revision));
> + s->cpu = ARM_CPU(cpu_create(cpu_type));
> s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0);
>
> /* SDRAM & Internal Memory Storage */
> @@ -2192,7 +2190,7 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
>
> s = g_new0(PXA2xxState, 1);
>
> - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, "pxa255"));
> + s->cpu = ARM_CPU(cpu_create(ARM_CPU_TYPE_NAME("pxa255")));
> s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0);
>
> /* SDRAM & Internal Memory Storage */
> diff --git a/hw/arm/realview.c b/hw/arm/realview.c
> index f3a49b6..87cd1e5 100644
> --- a/hw/arm/realview.c
> +++ b/hw/arm/realview.c
> @@ -57,7 +57,6 @@ static void realview_init(MachineState *machine,
> {
> ARMCPU *cpu = NULL;
> CPUARMState *env;
> - ObjectClass *cpu_oc;
> MemoryRegion *sysmem = get_system_memory();
> MemoryRegion *ram_lo;
> MemoryRegion *ram_hi = g_new(MemoryRegion, 1);
> @@ -98,14 +97,8 @@ static void realview_init(MachineState *machine,
> break;
> }
>
> - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, machine->cpu_model);
> - if (!cpu_oc) {
> - fprintf(stderr, "Unable to find CPU definition\n");
> - exit(1);
> - }
> -
> for (n = 0; n < smp_cpus; n++) {
> - Object *cpuobj = object_new(object_class_get_name(cpu_oc));
> + Object *cpuobj = object_new(machine->cpu_type);
>
> /* By default A9,A15 and ARM1176 CPUs have EL3 enabled. This board
> * does not currently support EL3 so the CPU EL3 property is disabled
> @@ -361,33 +354,21 @@ static void realview_init(MachineState *machine,
>
> static void realview_eb_init(MachineState *machine)
> {
> - if (!machine->cpu_model) {
> - machine->cpu_model = "arm926";
> - }
> realview_init(machine, BOARD_EB);
> }
>
> static void realview_eb_mpcore_init(MachineState *machine)
> {
> - if (!machine->cpu_model) {
> - machine->cpu_model = "arm11mpcore";
> - }
> realview_init(machine, BOARD_EB_MPCORE);
> }
>
> static void realview_pb_a8_init(MachineState *machine)
> {
> - if (!machine->cpu_model) {
> - machine->cpu_model = "cortex-a8";
> - }
> realview_init(machine, BOARD_PB_A8);
> }
>
> static void realview_pbx_a9_init(MachineState *machine)
> {
> - if (!machine->cpu_model) {
> - machine->cpu_model = "cortex-a9";
> - }
> realview_init(machine, BOARD_PBX_A9);
> }
>
> @@ -399,6 +380,7 @@ static void realview_eb_class_init(ObjectClass *oc, void *data)
> mc->init = realview_eb_init;
> mc->block_default_type = IF_SCSI;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
> }
>
> static const TypeInfo realview_eb_type = {
> @@ -416,6 +398,7 @@ static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data)
> mc->block_default_type = IF_SCSI;
> mc->max_cpus = 4;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm11mpcore");
> }
>
> static const TypeInfo realview_eb_mpcore_type = {
> @@ -431,6 +414,7 @@ static void realview_pb_a8_class_init(ObjectClass *oc, void *data)
> mc->desc = "ARM RealView Platform Baseboard for Cortex-A8";
> mc->init = realview_pb_a8_init;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a8");
> }
>
> static const TypeInfo realview_pb_a8_type = {
> @@ -447,6 +431,7 @@ static void realview_pbx_a9_class_init(ObjectClass *oc, void *data)
> mc->init = realview_pbx_a9_init;
> mc->max_cpus = 4;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
> }
>
> static const TypeInfo realview_pbx_a9_type = {
> diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
> index 6406421..feccdb0 100644
> --- a/hw/arm/spitz.c
> +++ b/hw/arm/spitz.c
> @@ -30,6 +30,7 @@
> #include "hw/sysbus.h"
> #include "exec/address-spaces.h"
> #include "sysemu/sysemu.h"
> +#include "cpu.h"
>
> #undef REG_FMT
> #define REG_FMT "0x%02lx"
> @@ -909,13 +910,10 @@ static void spitz_common_init(MachineState *machine,
> DeviceState *scp0, *scp1 = NULL;
> MemoryRegion *address_space_mem = get_system_memory();
> MemoryRegion *rom = g_new(MemoryRegion, 1);
> - const char *cpu_model = machine->cpu_model;
> -
> - if (!cpu_model)
> - cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0";
>
> /* Setup CPU & memory */
> - mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size, cpu_model);
> + mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size,
> + machine->cpu_type);
>
> sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
>
> @@ -984,6 +982,7 @@ static void akitapda_class_init(ObjectClass *oc, void *data)
> mc->desc = "Sharp SL-C1000 (Akita) PDA (PXA270)";
> mc->init = akita_init;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
> }
>
> static const TypeInfo akitapda_type = {
> @@ -1000,6 +999,7 @@ static void spitzpda_class_init(ObjectClass *oc, void *data)
> mc->init = spitz_init;
> mc->block_default_type = IF_IDE;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
> }
>
> static const TypeInfo spitzpda_type = {
> @@ -1016,6 +1016,7 @@ static void borzoipda_class_init(ObjectClass *oc, void *data)
> mc->init = borzoi_init;
> mc->block_default_type = IF_IDE;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
> }
>
> static const TypeInfo borzoipda_type = {
> @@ -1032,6 +1033,7 @@ static void terrierpda_class_init(ObjectClass *oc, void *data)
> mc->init = terrier_init;
> mc->block_default_type = IF_IDE;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5");
> }
>
> static const TypeInfo terrierpda_type = {
> diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
> index b3aad23..de7c0fc 100644
> --- a/hw/arm/stellaris.c
> +++ b/hw/arm/stellaris.c
> @@ -22,6 +22,7 @@
> #include "sysemu/sysemu.h"
> #include "hw/char/pl011.h"
> #include "hw/misc/unimp.h"
> +#include "cpu.h"
>
> #define GPIO_A 0
> #define GPIO_B 1
> @@ -1225,8 +1226,7 @@ static stellaris_board_info stellaris_boards[] = {
> }
> };
>
> -static void stellaris_init(const char *kernel_filename, const char *cpu_model,
> - stellaris_board_info *board)
> +static void stellaris_init(MachineState *ms, stellaris_board_info *board)
> {
> static const int uart_irq[] = {5, 6, 33, 34};
> static const int timer_irq[] = {19, 21, 23, 35};
> @@ -1298,7 +1298,7 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
> memory_region_add_subregion(system_memory, 0x20000000, sram);
>
> nvic = armv7m_init(system_memory, flash_size, NUM_IRQ_LINES,
> - kernel_filename, cpu_model);
> + ms->kernel_filename, ms->cpu_type);
>
> qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0,
> qemu_allocate_irq(&do_sys_reset, NULL, 0));
> @@ -1435,16 +1435,12 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
> /* FIXME: Figure out how to generate these from stellaris_boards. */
> static void lm3s811evb_init(MachineState *machine)
> {
> - const char *cpu_model = machine->cpu_model;
> - const char *kernel_filename = machine->kernel_filename;
> - stellaris_init(kernel_filename, cpu_model, &stellaris_boards[0]);
> + stellaris_init(machine, &stellaris_boards[0]);
> }
>
> static void lm3s6965evb_init(MachineState *machine)
> {
> - const char *cpu_model = machine->cpu_model;
> - const char *kernel_filename = machine->kernel_filename;
> - stellaris_init(kernel_filename, cpu_model, &stellaris_boards[1]);
> + stellaris_init(machine, &stellaris_boards[1]);
> }
>
> static void lm3s811evb_class_init(ObjectClass *oc, void *data)
> @@ -1454,6 +1450,7 @@ static void lm3s811evb_class_init(ObjectClass *oc, void *data)
> mc->desc = "Stellaris LM3S811EVB";
> mc->init = lm3s811evb_init;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
> }
>
> static const TypeInfo lm3s811evb_type = {
> @@ -1469,6 +1466,7 @@ static void lm3s6965evb_class_init(ObjectClass *oc, void *data)
> mc->desc = "Stellaris LM3S6965EVB";
> mc->init = lm3s6965evb_init;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
> }
>
> static const TypeInfo lm3s6965evb_type = {
> diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
> index f61e735..1cd6374 100644
> --- a/hw/arm/stm32f205_soc.c
> +++ b/hw/arm/stm32f205_soc.c
> @@ -112,7 +112,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
>
> armv7m = DEVICE(&s->armv7m);
> qdev_prop_set_uint32(armv7m, "num-irq", 96);
> - qdev_prop_set_string(armv7m, "cpu-model", s->cpu_model);
> + qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
> object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
> "memory", &error_abort);
> object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
> @@ -200,7 +200,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
> }
>
> static Property stm32f205_soc_properties[] = {
> - DEFINE_PROP_STRING("cpu-model", STM32F205State, cpu_model),
> + DEFINE_PROP_STRING("cpu-type", STM32F205State, cpu_type),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
> index c1145dd..3d1a231 100644
> --- a/hw/arm/strongarm.c
> +++ b/hw/arm/strongarm.c
> @@ -1581,23 +1581,19 @@ static const TypeInfo strongarm_ssp_info = {
>
> /* Main CPU functions */
> StrongARMState *sa1110_init(MemoryRegion *sysmem,
> - unsigned int sdram_size, const char *rev)
> + unsigned int sdram_size, const char *cpu_type)
> {
> StrongARMState *s;
> int i;
>
> s = g_new0(StrongARMState, 1);
>
> - if (!rev) {
> - rev = "sa1110-b5";
> - }
> -
> - if (strncmp(rev, "sa1110", 6)) {
> + if (strncmp(cpu_type, "sa1110", 6)) {
> error_report("Machine requires a SA1110 processor.");
> exit(1);
> }
>
> - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, rev));
> + s->cpu = ARM_CPU(cpu_create(cpu_type));
>
> memory_region_allocate_system_memory(&s->sdram, NULL, "strongarm.sdram",
> sdram_size);
> diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
> index 1134cf7..0447963 100644
> --- a/hw/arm/tosa.c
> +++ b/hw/arm/tosa.c
> @@ -219,7 +219,6 @@ static struct arm_boot_info tosa_binfo = {
>
> static void tosa_init(MachineState *machine)
> {
> - const char *cpu_model = machine->cpu_model;
> const char *kernel_filename = machine->kernel_filename;
> const char *kernel_cmdline = machine->kernel_cmdline;
> const char *initrd_filename = machine->initrd_filename;
> @@ -229,9 +228,6 @@ static void tosa_init(MachineState *machine)
> TC6393xbState *tmio;
> DeviceState *scp0, *scp1;
>
> - if (!cpu_model)
> - cpu_model = "pxa255";
> -
> mpu = pxa255_init(address_space_mem, tosa_binfo.ram_size);
>
> memory_region_init_ram(rom, NULL, "tosa.rom", TOSA_ROM, &error_fatal);
> diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
> index 76664e4..418792c 100644
> --- a/hw/arm/versatilepb.c
> +++ b/hw/arm/versatilepb.c
> @@ -181,7 +181,6 @@ static struct arm_boot_info versatile_binfo;
>
> static void versatile_init(MachineState *machine, int board_id)
> {
> - ObjectClass *cpu_oc;
> Object *cpuobj;
> ARMCPU *cpu;
> MemoryRegion *sysmem = get_system_memory();
> @@ -207,17 +206,7 @@ static void versatile_init(MachineState *machine, int board_id)
> exit(1);
> }
>
> - if (!machine->cpu_model) {
> - machine->cpu_model = "arm926";
> - }
> -
> - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, machine->cpu_model);
> - if (!cpu_oc) {
> - fprintf(stderr, "Unable to find CPU definition\n");
> - exit(1);
> - }
> -
> - cpuobj = object_new(object_class_get_name(cpu_oc));
> + cpuobj = object_new(machine->cpu_type);
>
> /* By default ARM1176 CPUs have EL3 enabled. This board does not
> * currently support EL3 so the CPU EL3 property is disabled before
> @@ -404,6 +393,7 @@ static void versatilepb_class_init(ObjectClass *oc, void *data)
> mc->init = vpb_init;
> mc->block_default_type = IF_SCSI;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
> }
>
> static const TypeInfo versatilepb_type = {
> @@ -420,6 +410,7 @@ static void versatileab_class_init(ObjectClass *oc, void *data)
> mc->init = vab_init;
> mc->block_default_type = IF_SCSI;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
> }
>
> static const TypeInfo versatileab_type = {
> diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
> index e3acab6..2e5f670 100644
> --- a/hw/arm/vexpress.c
> +++ b/hw/arm/vexpress.c
> @@ -186,7 +186,7 @@ typedef struct {
>
> typedef void DBoardInitFn(const VexpressMachineState *machine,
> ram_addr_t ram_size,
> - const char *cpu_model,
> + const char *cpu_type,
> qemu_irq *pic);
>
> struct VEDBoardInfo {
> @@ -202,22 +202,16 @@ struct VEDBoardInfo {
> DBoardInitFn *init;
> };
>
> -static void init_cpus(const char *cpu_model, const char *privdev,
> +static void init_cpus(const char *cpu_type, const char *privdev,
> hwaddr periphbase, qemu_irq *pic, bool secure)
> {
> - ObjectClass *cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
> DeviceState *dev;
> SysBusDevice *busdev;
> int n;
>
> - if (!cpu_oc) {
> - fprintf(stderr, "Unable to find CPU definition\n");
> - exit(1);
> - }
> -
> /* Create the actual CPUs */
> for (n = 0; n < smp_cpus; n++) {
> - Object *cpuobj = object_new(object_class_get_name(cpu_oc));
> + Object *cpuobj = object_new(cpu_type);
>
> if (!secure) {
> object_property_set_bool(cpuobj, false, "has_el3", NULL);
> @@ -262,7 +256,7 @@ static void init_cpus(const char *cpu_model, const char *privdev,
>
> static void a9_daughterboard_init(const VexpressMachineState *vms,
> ram_addr_t ram_size,
> - const char *cpu_model,
> + const char *cpu_type,
> qemu_irq *pic)
> {
> MemoryRegion *sysmem = get_system_memory();
> @@ -270,10 +264,6 @@ static void a9_daughterboard_init(const VexpressMachineState *vms,
> MemoryRegion *lowram = g_new(MemoryRegion, 1);
> ram_addr_t low_ram_size;
>
> - if (!cpu_model) {
> - cpu_model = "cortex-a9";
> - }
> -
> if (ram_size > 0x40000000) {
> /* 1GB is the maximum the address space permits */
> fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM\n");
> @@ -295,7 +285,7 @@ static void a9_daughterboard_init(const VexpressMachineState *vms,
> memory_region_add_subregion(sysmem, 0x60000000, ram);
>
> /* 0x1e000000 A9MPCore (SCU) private memory region */
> - init_cpus(cpu_model, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, vms->secure);
> + init_cpus(cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, vms->secure);
>
> /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
>
> @@ -351,17 +341,13 @@ static VEDBoardInfo a9_daughterboard = {
>
> static void a15_daughterboard_init(const VexpressMachineState *vms,
> ram_addr_t ram_size,
> - const char *cpu_model,
> + const char *cpu_type,
> qemu_irq *pic)
> {
> MemoryRegion *sysmem = get_system_memory();
> MemoryRegion *ram = g_new(MemoryRegion, 1);
> MemoryRegion *sram = g_new(MemoryRegion, 1);
>
> - if (!cpu_model) {
> - cpu_model = "cortex-a15";
> - }
> -
> {
> /* We have to use a separate 64 bit variable here to avoid the gcc
> * "comparison is always false due to limited range of data type"
> @@ -380,7 +366,7 @@ static void a15_daughterboard_init(const VexpressMachineState *vms,
> memory_region_add_subregion(sysmem, 0x80000000, ram);
>
> /* 0x2c000000 A15MPCore private memory region (GIC) */
> - init_cpus(cpu_model, TYPE_A15MPCORE_PRIV, 0x2c000000, pic, vms->secure);
> + init_cpus(cpu_type, TYPE_A15MPCORE_PRIV, 0x2c000000, pic, vms->secure);
>
> /* A15 daughterboard peripherals: */
>
> @@ -560,7 +546,7 @@ static void vexpress_common_init(MachineState *machine)
> const hwaddr *map = daughterboard->motherboard_map;
> int i;
>
> - daughterboard->init(vms, machine->ram_size, machine->cpu_model, pic);
> + daughterboard->init(vms, machine->ram_size, machine->cpu_type, pic);
>
> /*
> * If a bios file was provided, attempt to map it into memory
> @@ -761,6 +747,7 @@ static void vexpress_a9_class_init(ObjectClass *oc, void *data)
> VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
>
> mc->desc = "ARM Versatile Express for Cortex-A9";
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
>
> vmc->daughterboard = &a9_daughterboard;
> }
> @@ -771,6 +758,7 @@ static void vexpress_a15_class_init(ObjectClass *oc, void *data)
> VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
>
> mc->desc = "ARM Versatile Express for Cortex-A15";
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
>
> vmc->daughterboard = &a15_daughterboard;
> }
> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> index fe96557..fe26e99 100644
> --- a/hw/arm/virt.c
> +++ b/hw/arm/virt.c
> @@ -163,13 +163,13 @@ static const int a15irqmap[] = {
> };
>
> static const char *valid_cpus[] = {
> - "cortex-a15",
> - "cortex-a53",
> - "cortex-a57",
> - "host",
> + ARM_CPU_TYPE_NAME("cortex-a15"),
> + ARM_CPU_TYPE_NAME("cortex-a53"),
> + ARM_CPU_TYPE_NAME("cortex-a57"),
> + ARM_CPU_TYPE_NAME("host"),
> };
>
> -static bool cpuname_valid(const char *cpu)
> +static bool cpu_type_valid(const char *cpu)
> {
> int i;
I'd just change this by:
static bool cpuname_valid(const char *cpu)
{
static const char *valid_cpus[] = {
ARM_CPU_TYPE_NAME("cortex-a15"),
ARM_CPU_TYPE_NAME("cortex-a53"),
ARM_CPU_TYPE_NAME("cortex-a57"),
};
int i;
for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
if (strcmp(cpu, valid_cpus[i]) == 0) {
return true;
}
}
return kvm_enabled() && !strcmp(cpu, ARM_CPU_TYPE_NAME("host");
}
Anyway this can be a later patch.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> @@ -1258,18 +1258,8 @@ static void machvirt_init(MachineState *machine)
> MemoryRegion *secure_sysmem = NULL;
> int n, virt_max_cpus;
> MemoryRegion *ram = g_new(MemoryRegion, 1);
> - const char *cpu_model = machine->cpu_model;
> - char **cpustr;
> - ObjectClass *oc;
> - const char *typename;
> - CPUClass *cc;
> - Error *err = NULL;
> bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0);
>
> - if (!cpu_model) {
> - cpu_model = "cortex-a15";
> - }
> -
> /* We can probe only here because during property set
> * KVM is not available yet
> */
> @@ -1286,11 +1276,8 @@ static void machvirt_init(MachineState *machine)
> }
> }
>
> - /* Separate the actual CPU model name from any appended features */
> - cpustr = g_strsplit(cpu_model, ",", 2);
> -
> - if (!cpuname_valid(cpustr[0])) {
> - error_report("mach-virt: CPU %s not supported", cpustr[0]);
> + if (!cpu_type_valid(machine->cpu_type)) {
> + error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
> exit(1);
> }
>
> @@ -1360,22 +1347,6 @@ static void machvirt_init(MachineState *machine)
>
> create_fdt(vms);
>
> - oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);
> - if (!oc) {
> - error_report("Unable to find CPU definition");
> - exit(1);
> - }
> - typename = object_class_get_name(oc);
> -
> - /* convert -smp CPU options specified by the user into global props */
> - cc = CPU_CLASS(oc);
> - cc->parse_features(typename, cpustr[1], &err);
> - g_strfreev(cpustr);
> - if (err) {
> - error_report_err(err);
> - exit(1);
> - }
> -
> possible_cpus = mc->possible_cpu_arch_ids(machine);
> for (n = 0; n < possible_cpus->len; n++) {
> Object *cpuobj;
> @@ -1385,7 +1356,7 @@ static void machvirt_init(MachineState *machine)
> break;
> }
>
> - cpuobj = object_new(typename);
> + cpuobj = object_new(machine->cpu_type);
> object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id,
> "mp-affinity", NULL);
>
> @@ -1630,6 +1601,7 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
> mc->minimum_page_bits = 12;
> mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
> mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
> }
>
> static const TypeInfo virt_machine_info = {
> diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
> index 3759cf8..1836a4e 100644
> --- a/hw/arm/xilinx_zynq.c
> +++ b/hw/arm/xilinx_zynq.c
> @@ -158,11 +158,9 @@ static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
> static void zynq_init(MachineState *machine)
> {
> ram_addr_t ram_size = machine->ram_size;
> - const char *cpu_model = machine->cpu_model;
> const char *kernel_filename = machine->kernel_filename;
> const char *kernel_cmdline = machine->kernel_cmdline;
> const char *initrd_filename = machine->initrd_filename;
> - ObjectClass *cpu_oc;
> ARMCPU *cpu;
> MemoryRegion *address_space_mem = get_system_memory();
> MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
> @@ -174,12 +172,7 @@ static void zynq_init(MachineState *machine)
> qemu_irq pic[64];
> int n;
>
> - if (!cpu_model) {
> - cpu_model = "cortex-a9";
> - }
> - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
> -
> - cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc)));
> + cpu = ARM_CPU(object_new(machine->cpu_type));
>
> /* By default A9 CPUs have EL3 enabled. This board does not
> * currently support EL3 so the CPU EL3 property is disabled before
> @@ -327,6 +320,7 @@ static void zynq_machine_init(MachineClass *mc)
> mc->max_cpus = 1;
> mc->no_sdcard = 1;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
> }
>
> DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init)
> diff --git a/hw/arm/z2.c b/hw/arm/z2.c
> index 417bc1a..60561c7 100644
> --- a/hw/arm/z2.c
> +++ b/hw/arm/z2.c
> @@ -26,6 +26,7 @@
> #include "audio/audio.h"
> #include "exec/address-spaces.h"
> #include "sysemu/qtest.h"
> +#include "cpu.h"
>
> #ifdef DEBUG_Z2
> #define DPRINTF(fmt, ...) \
> @@ -296,7 +297,6 @@ static const TypeInfo aer915_info = {
>
> static void z2_init(MachineState *machine)
> {
> - const char *cpu_model = machine->cpu_model;
> const char *kernel_filename = machine->kernel_filename;
> const char *kernel_cmdline = machine->kernel_cmdline;
> const char *initrd_filename = machine->initrd_filename;
> @@ -309,12 +309,8 @@ static void z2_init(MachineState *machine)
> I2CBus *bus;
> DeviceState *wm;
>
> - if (!cpu_model) {
> - cpu_model = "pxa270-c5";
> - }
> -
> /* Setup CPU & memory */
> - mpu = pxa270_init(address_space_mem, z2_binfo.ram_size, cpu_model);
> + mpu = pxa270_init(address_space_mem, z2_binfo.ram_size, machine->cpu_type);
>
> #ifdef TARGET_WORDS_BIGENDIAN
> be = 1;
> @@ -371,6 +367,7 @@ static void z2_machine_init(MachineClass *mc)
> mc->desc = "Zipit Z2 (PXA27x)";
> mc->init = z2_init;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5");
> }
>
> DEFINE_MACHINE("z2", z2_machine_init)
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index a1acce3..ff7ff28 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -905,7 +905,7 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
> }
>
> cpuname = g_strsplit(cpu_model, ",", 1);
> - typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]);
> + typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpuname[0]);
> oc = object_class_by_name(typename);
> g_strfreev(cpuname);
> g_free(typename);
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Qemu-devel] [PATCH v2 5/5] arm: drop intermediate cpu_model -> cpu type parsing and use cpu type directly
2017-09-14 3:47 ` Philippe Mathieu-Daudé
@ 2017-09-14 7:50 ` Igor Mammedov
2017-09-14 22:09 ` Alistair Francis
0 siblings, 1 reply; 17+ messages in thread
From: Igor Mammedov @ 2017-09-14 7:50 UTC (permalink / raw)
To: Philippe Mathieu-Daudé; +Cc: qemu-arm, qemu-devel, Alistair Francis
On Thu, 14 Sep 2017 00:47:20 -0300
Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> Hi Igor,
>
> awesome clean refactor!
Thanks,
there is more patches on this topic for other targets to post
but it's waiting on 1-3/5 to land in master so it would be
easier for maintainers to verify/test them without fishing out
dependencies from mail list.
hopefully everything will land in 2.11 so we won't have to deal
with cpu_model anywhere except of one place vl.c.
> just 1 comment inlined.
>
> On 09/13/2017 01:04 PM, Igor Mammedov wrote:
> > there are 2 use cases to deal with:
> > 1: fixed CPU models per board/soc
> > 2: boards with user configurable cpu_model and fallback to
> > default cpu_model if user hasn't specified one explicitly
> >
> > For the 1st
> > drop intermediate cpu_model parsing and use const cpu type
> > directly, which replaces:
> > typename = object_class_get_name(
> > cpu_class_by_name(TYPE_ARM_CPU, cpu_model))
> > object_new(typename)
> > with
> > object_new(FOO_CPU_TYPE_NAME)
> > or
> > cpu_generic_init(BASE_CPU_TYPE, "my cpu model")
> > with
> > cpu_create(FOO_CPU_TYPE_NAME)
> >
> > as result 1st use case doesn't have to invoke not necessary
> > translation and not needed code is removed.
> >
> > For the 2nd
> > 1: set default cpu type with MachineClass::default_cpu_type and
> > 2: use generic cpu_model parsing that done before machine_init()
> > is run and:
> > 2.1: drop custom cpu_model parsing where pattern is:
> > typename = object_class_get_name(
> > cpu_class_by_name(TYPE_ARM_CPU, cpu_model))
> > [parse_features(typename, cpu_model, &err) ]
> >
> > 2.2: or replace cpu_generic_init() which does what
> > 2.1 does + create_cpu(typename) with just
> > create_cpu(machine->cpu_type)
> > as result cpu_name -> cpu_type translation is done using
> > generic machine code one including parsing optional features
> > if supported/present (removes a bunch of duplicated cpu_model
> > parsing code) and default cpu type is defined in an uniform way
> > within machine_class_init callbacks instead of adhoc places
> > in boadr's machine_init code.
> >
> > Signed-off-by: Igor Mammedov <imammedo@redhat.com>
> > Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
> > ---
> > v2:
> > - fix merge conflicts with ignore_memory_transaction_failures
> > - fix couple merge conflicts where SoC type string where replaced by type macro
> > - keep plain prefix string in: strncmp(cpu_type, "pxa27", 5)
> > - s/"%s" ARM_CPU_TYPE_SUFFIX/ARM_CPU_TYPE_NAME("%s")/
> > ---
[...]
> > diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> > index fe96557..fe26e99 100644
> > --- a/hw/arm/virt.c
> > +++ b/hw/arm/virt.c
> > @@ -163,13 +163,13 @@ static const int a15irqmap[] = {
> > };
> >
> > static const char *valid_cpus[] = {
> > - "cortex-a15",
> > - "cortex-a53",
> > - "cortex-a57",
> > - "host",
> > + ARM_CPU_TYPE_NAME("cortex-a15"),
> > + ARM_CPU_TYPE_NAME("cortex-a53"),
> > + ARM_CPU_TYPE_NAME("cortex-a57"),
> > + ARM_CPU_TYPE_NAME("host"),
> > };
> >
> > -static bool cpuname_valid(const char *cpu)
> > +static bool cpu_type_valid(const char *cpu)
> > {
> > int i;
>
> I'd just change this by:
>
> static bool cpuname_valid(const char *cpu)
> {
> static const char *valid_cpus[] = {
> ARM_CPU_TYPE_NAME("cortex-a15"),
> ARM_CPU_TYPE_NAME("cortex-a53"),
> ARM_CPU_TYPE_NAME("cortex-a57"),
> };
> int i;
>
> for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
> if (strcmp(cpu, valid_cpus[i]) == 0) {
> return true;
> }
> }
> return kvm_enabled() && !strcmp(cpu, ARM_CPU_TYPE_NAME("host");
here is one more case to consider for valid_cpus refactoring,
CCing Alistair.
> }
>
> Anyway this can be a later patch.
this check might be removed or superseded by generic valid_cpus work
that Alistair is working on, anyways it should be part of that work
as change is not directly related to this series.
[...]
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Qemu-devel] [PATCH v2 5/5] arm: drop intermediate cpu_model -> cpu type parsing and use cpu type directly
2017-09-13 16:04 ` [Qemu-devel] [PATCH v2 5/5] arm: drop intermediate cpu_model -> cpu type parsing and use cpu type directly Igor Mammedov
2017-09-14 3:47 ` Philippe Mathieu-Daudé
@ 2017-09-14 17:57 ` Alistair Francis
2017-09-18 21:53 ` [Qemu-devel] [PATCH] !fixup arm: missed comment update Philippe Mathieu-Daudé
2 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2017-09-14 17:57 UTC (permalink / raw)
To: Igor Mammedov; +Cc: qemu-devel@nongnu.org Developers
On Wed, Sep 13, 2017 at 9:04 AM, Igor Mammedov <imammedo@redhat.com> wrote:
> there are 2 use cases to deal with:
> 1: fixed CPU models per board/soc
> 2: boards with user configurable cpu_model and fallback to
> default cpu_model if user hasn't specified one explicitly
>
> For the 1st
> drop intermediate cpu_model parsing and use const cpu type
> directly, which replaces:
> typename = object_class_get_name(
> cpu_class_by_name(TYPE_ARM_CPU, cpu_model))
> object_new(typename)
> with
> object_new(FOO_CPU_TYPE_NAME)
> or
> cpu_generic_init(BASE_CPU_TYPE, "my cpu model")
> with
> cpu_create(FOO_CPU_TYPE_NAME)
>
> as result 1st use case doesn't have to invoke not necessary
> translation and not needed code is removed.
>
> For the 2nd
> 1: set default cpu type with MachineClass::default_cpu_type and
> 2: use generic cpu_model parsing that done before machine_init()
> is run and:
> 2.1: drop custom cpu_model parsing where pattern is:
> typename = object_class_get_name(
> cpu_class_by_name(TYPE_ARM_CPU, cpu_model))
> [parse_features(typename, cpu_model, &err) ]
>
> 2.2: or replace cpu_generic_init() which does what
> 2.1 does + create_cpu(typename) with just
> create_cpu(machine->cpu_type)
> as result cpu_name -> cpu_type translation is done using
> generic machine code one including parsing optional features
> if supported/present (removes a bunch of duplicated cpu_model
> parsing code) and default cpu type is defined in an uniform way
> within machine_class_init callbacks instead of adhoc places
> in boadr's machine_init code.
>
> Signed-off-by: Igor Mammedov <imammedo@redhat.com>
> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Fox the Xilinx and Netduino stuff:
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Thanks,
Alistair
> ---
> v2:
> - fix merge conflicts with ignore_memory_transaction_failures
> - fix couple merge conflicts where SoC type string where replaced by type macro
> - keep plain prefix string in: strncmp(cpu_type, "pxa27", 5)
> - s/"%s" ARM_CPU_TYPE_SUFFIX/ARM_CPU_TYPE_NAME("%s")/
> ---
> include/hw/arm/armv7m.h | 2 +-
> include/hw/arm/aspeed_soc.h | 2 +-
> include/hw/arm/stm32f205_soc.h | 2 +-
> target/arm/cpu.h | 3 +++
> hw/arm/armv7m.c | 40 +++++-------------------------------
> hw/arm/aspeed_soc.c | 13 +++++-------
> hw/arm/collie.c | 10 +++------
> hw/arm/exynos4210.c | 6 +-----
> hw/arm/gumstix.c | 5 +++--
> hw/arm/highbank.c | 10 ++++-----
> hw/arm/integratorcp.c | 30 ++-------------------------
> hw/arm/mainstone.c | 9 ++++-----
> hw/arm/mps2.c | 17 +++++++---------
> hw/arm/musicpal.c | 7 ++-----
> hw/arm/netduino2.c | 2 +-
> hw/arm/nseries.c | 4 +++-
> hw/arm/omap1.c | 7 ++-----
> hw/arm/omap2.c | 4 ++--
> hw/arm/omap_sx1.c | 5 ++++-
> hw/arm/palm.c | 5 +++--
> hw/arm/pxa2xx.c | 10 ++++-----
> hw/arm/realview.c | 25 +++++------------------
> hw/arm/spitz.c | 12 ++++++-----
> hw/arm/stellaris.c | 16 +++++++--------
> hw/arm/stm32f205_soc.c | 4 ++--
> hw/arm/strongarm.c | 10 +++------
> hw/arm/tosa.c | 4 ----
> hw/arm/versatilepb.c | 15 +++-----------
> hw/arm/vexpress.c | 32 +++++++++--------------------
> hw/arm/virt.c | 46 +++++++++---------------------------------
> hw/arm/xilinx_zynq.c | 10 ++-------
> hw/arm/z2.c | 9 +++------
> target/arm/cpu.c | 2 +-
> 33 files changed, 114 insertions(+), 264 deletions(-)
>
> diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
> index 10eb058..68cb30d 100644
> --- a/include/hw/arm/armv7m.h
> +++ b/include/hw/arm/armv7m.h
> @@ -55,7 +55,7 @@ typedef struct ARMv7MState {
> MemoryRegion container;
>
> /* Properties */
> - char *cpu_model;
> + char *cpu_type;
> /* MemoryRegion the board provides to us (with its devices, RAM, etc) */
> MemoryRegion *board_memory;
> } ARMv7MState;
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index 0b88baa..f26914a 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -49,7 +49,7 @@ typedef struct AspeedSoCState {
>
> typedef struct AspeedSoCInfo {
> const char *name;
> - const char *cpu_model;
> + const char *cpu_type;
> uint32_t silicon_rev;
> hwaddr sdram_base;
> uint64_t sram_size;
> diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h
> index e2dce11..922a733 100644
> --- a/include/hw/arm/stm32f205_soc.h
> +++ b/include/hw/arm/stm32f205_soc.h
> @@ -52,7 +52,7 @@ typedef struct STM32F205State {
> SysBusDevice parent_obj;
> /*< public >*/
>
> - char *cpu_model;
> + char *cpu_type;
>
> ARMv7MState armv7m;
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 98b9b26..1bfdd8d 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -2088,6 +2088,9 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
>
> #define cpu_init(cpu_model) cpu_generic_init(TYPE_ARM_CPU, cpu_model)
>
> +#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
> +#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
> +
> #define cpu_signal_handler cpu_arm_signal_handler
> #define cpu_list arm_cpu_list
>
> diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
> index b64a409..57a6806 100644
> --- a/hw/arm/armv7m.c
> +++ b/hw/arm/armv7m.c
> @@ -151,10 +151,6 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
> SysBusDevice *sbd;
> Error *err = NULL;
> int i;
> - char **cpustr;
> - ObjectClass *oc;
> - const char *typename;
> - CPUClass *cc;
>
> if (!s->board_memory) {
> error_setg(errp, "memory property was not set");
> @@ -163,29 +159,7 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
>
> memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
>
> - cpustr = g_strsplit(s->cpu_model, ",", 2);
> -
> - oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);
> - if (!oc) {
> - error_setg(errp, "Unknown CPU model %s", cpustr[0]);
> - g_strfreev(cpustr);
> - return;
> - }
> -
> - cc = CPU_CLASS(oc);
> - typename = object_class_get_name(oc);
> - cc->parse_features(typename, cpustr[1], &err);
> - g_strfreev(cpustr);
> - if (err) {
> - error_propagate(errp, err);
> - return;
> - }
> -
> - s->cpu = ARM_CPU(object_new(typename));
> - if (!s->cpu) {
> - error_setg(errp, "Unknown CPU model %s", s->cpu_model);
> - return;
> - }
> + s->cpu = ARM_CPU(object_new(s->cpu_type));
>
> object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), "memory",
> &error_abort);
> @@ -241,7 +215,7 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
> }
>
> static Property armv7m_properties[] = {
> - DEFINE_PROP_STRING("cpu-model", ARMv7MState, cpu_model),
> + DEFINE_PROP_STRING("cpu-type", ARMv7MState, cpu_type),
> DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION,
> MemoryRegion *),
> DEFINE_PROP_END_OF_LIST(),
> @@ -275,20 +249,16 @@ static void armv7m_reset(void *opaque)
> Returns the ARMv7M device. */
>
> DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
> - const char *kernel_filename, const char *cpu_model)
> + const char *kernel_filename, const char *cpu_type)
> {
> DeviceState *armv7m;
>
> - if (cpu_model == NULL) {
> - cpu_model = "cortex-m3";
> - }
> -
> armv7m = qdev_create(NULL, TYPE_ARMV7M);
> qdev_prop_set_uint32(armv7m, "num-irq", num_irq);
> - qdev_prop_set_string(armv7m, "cpu-model", cpu_model);
> + qdev_prop_set_string(armv7m, "cpu-type", cpu_type);
> object_property_set_link(OBJECT(armv7m), OBJECT(get_system_memory()),
> "memory", &error_abort);
> - /* This will exit with an error if the user passed us a bad cpu_model */
> + /* This will exit with an error if the user passed us a bad cpu_type */
> qdev_init_nofail(armv7m);
>
> armv7m_load_kernel(ARM_CPU(first_cpu), kernel_filename, mem_size);
> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
> index 13c6393..5aa3d2d 100644
> --- a/hw/arm/aspeed_soc.c
> +++ b/hw/arm/aspeed_soc.c
> @@ -54,7 +54,7 @@ static const char *aspeed_soc_ast2500_typenames[] = {
> static const AspeedSoCInfo aspeed_socs[] = {
> {
> .name = "ast2400-a0",
> - .cpu_model = "arm926",
> + .cpu_type = ARM_CPU_TYPE_NAME("arm926"),
> .silicon_rev = AST2400_A0_SILICON_REV,
> .sdram_base = AST2400_SDRAM_BASE,
> .sram_size = 0x8000,
> @@ -65,7 +65,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
> .wdts_num = 2,
> }, {
> .name = "ast2400-a1",
> - .cpu_model = "arm926",
> + .cpu_type = ARM_CPU_TYPE_NAME("arm926"),
> .silicon_rev = AST2400_A1_SILICON_REV,
> .sdram_base = AST2400_SDRAM_BASE,
> .sram_size = 0x8000,
> @@ -76,7 +76,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
> .wdts_num = 2,
> }, {
> .name = "ast2400",
> - .cpu_model = "arm926",
> + .cpu_type = ARM_CPU_TYPE_NAME("arm926"),
> .silicon_rev = AST2400_A0_SILICON_REV,
> .sdram_base = AST2400_SDRAM_BASE,
> .sram_size = 0x8000,
> @@ -87,7 +87,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
> .wdts_num = 2,
> }, {
> .name = "ast2500-a1",
> - .cpu_model = "arm1176",
> + .cpu_type = ARM_CPU_TYPE_NAME("arm1176"),
> .silicon_rev = AST2500_A1_SILICON_REV,
> .sdram_base = AST2500_SDRAM_BASE,
> .sram_size = 0x9000,
> @@ -128,13 +128,10 @@ static void aspeed_soc_init(Object *obj)
> {
> AspeedSoCState *s = ASPEED_SOC(obj);
> AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> - char *cpu_typename;
> int i;
>
> - cpu_typename = g_strdup_printf("%s-" TYPE_ARM_CPU, sc->info->cpu_model);
> - object_initialize(&s->cpu, sizeof(s->cpu), cpu_typename);
> + object_initialize(&s->cpu, sizeof(s->cpu), sc->info->cpu_type);
> object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL);
> - g_free(cpu_typename);
>
> object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC);
> object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL);
> diff --git a/hw/arm/collie.c b/hw/arm/collie.c
> index 8830192..f8c566e 100644
> --- a/hw/arm/collie.c
> +++ b/hw/arm/collie.c
> @@ -18,7 +18,7 @@
> #include "hw/block/flash.h"
> #include "sysemu/block-backend.h"
> #include "exec/address-spaces.h"
> -#include "qom/cpu.h"
> +#include "cpu.h"
>
> static struct arm_boot_info collie_binfo = {
> .loader_start = SA_SDCS0,
> @@ -27,7 +27,6 @@ static struct arm_boot_info collie_binfo = {
>
> static void collie_init(MachineState *machine)
> {
> - const char *cpu_model = machine->cpu_model;
> const char *kernel_filename = machine->kernel_filename;
> const char *kernel_cmdline = machine->kernel_cmdline;
> const char *initrd_filename = machine->initrd_filename;
> @@ -35,11 +34,7 @@ static void collie_init(MachineState *machine)
> DriveInfo *dinfo;
> MemoryRegion *sysmem = get_system_memory();
>
> - if (!cpu_model) {
> - cpu_model = "sa1110";
> - }
> -
> - s = sa1110_init(sysmem, collie_binfo.ram_size, cpu_model);
> + s = sa1110_init(sysmem, collie_binfo.ram_size, machine->cpu_type);
>
> dinfo = drive_get(IF_PFLASH, 0, 0);
> pflash_cfi01_register(SA_CS0, NULL, "collie.fl1", 0x02000000,
> @@ -65,6 +60,7 @@ static void collie_machine_init(MachineClass *mc)
> mc->desc = "Sharp SL-5500 (Collie) PDA (SA-1110)";
> mc->init = collie_init;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("sa1110");
> }
>
> DEFINE_MACHINE("collie", collie_machine_init)
> diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
> index ee1438a..e8e1d81 100644
> --- a/hw/arm/exynos4210.c
> +++ b/hw/arm/exynos4210.c
> @@ -169,15 +169,11 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
> Exynos4210State *s = g_new(Exynos4210State, 1);
> qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
> SysBusDevice *busdev;
> - ObjectClass *cpu_oc;
> DeviceState *dev;
> int i, n;
>
> - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, "cortex-a9");
> - assert(cpu_oc);
> -
> for (n = 0; n < EXYNOS4210_NCPUS; n++) {
> - Object *cpuobj = object_new(object_class_get_name(cpu_oc));
> + Object *cpuobj = object_new(ARM_CPU_TYPE_NAME("cortex-a9"));
>
> /* By default A9 CPUs have EL3 enabled. This board does not currently
> * support EL3 so the CPU EL3 property is disabled before realization.
> diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c
> index 092ce36..bba9e9f 100644
> --- a/hw/arm/gumstix.c
> +++ b/hw/arm/gumstix.c
> @@ -44,6 +44,7 @@
> #include "sysemu/block-backend.h"
> #include "exec/address-spaces.h"
> #include "sysemu/qtest.h"
> +#include "cpu.h"
>
> static const int sector_len = 128 * 1024;
>
> @@ -86,7 +87,6 @@ static void connex_init(MachineState *machine)
>
> static void verdex_init(MachineState *machine)
> {
> - const char *cpu_model = machine->cpu_model;
> PXA2xxState *cpu;
> DriveInfo *dinfo;
> int be;
> @@ -95,7 +95,7 @@ static void verdex_init(MachineState *machine)
> uint32_t verdex_rom = 0x02000000;
> uint32_t verdex_ram = 0x10000000;
>
> - cpu = pxa270_init(address_space_mem, verdex_ram, cpu_model ?: "pxa270-c0");
> + cpu = pxa270_init(address_space_mem, verdex_ram, machine->cpu_type);
>
> dinfo = drive_get(IF_PFLASH, 0, 0);
> if (!dinfo && !qtest_enabled()) {
> @@ -144,6 +144,7 @@ static void verdex_class_init(ObjectClass *oc, void *data)
> mc->desc = "Gumstix Verdex (PXA270)";
> mc->init = verdex_init;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
> }
>
> static const TypeInfo verdex_type = {
> diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
> index ba27789..354c6b2 100644
> --- a/hw/arm/highbank.c
> +++ b/hw/arm/highbank.c
> @@ -222,7 +222,6 @@ enum cxmachines {
> static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
> {
> ram_addr_t ram_size = machine->ram_size;
> - const char *cpu_model = machine->cpu_model;
> const char *kernel_filename = machine->kernel_filename;
> const char *kernel_cmdline = machine->kernel_cmdline;
> const char *initrd_filename = machine->initrd_filename;
> @@ -239,19 +238,20 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
>
> switch (machine_id) {
> case CALXEDA_HIGHBANK:
> - cpu_model = "cortex-a9";
> + machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
> break;
> case CALXEDA_MIDWAY:
> - cpu_model = "cortex-a15";
> + machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
> break;
> + default:
> + assert(0);
> }
>
> for (n = 0; n < smp_cpus; n++) {
> - ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
> Object *cpuobj;
> ARMCPU *cpu;
>
> - cpuobj = object_new(object_class_get_name(oc));
> + cpuobj = object_new(machine->cpu_type);
> cpu = ARM_CPU(cpuobj);
>
> object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_SMC,
> diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
> index d603af9..e8303b8 100644
> --- a/hw/arm/integratorcp.c
> +++ b/hw/arm/integratorcp.c
> @@ -572,46 +572,19 @@ static struct arm_boot_info integrator_binfo = {
> static void integratorcp_init(MachineState *machine)
> {
> ram_addr_t ram_size = machine->ram_size;
> - const char *cpu_model = machine->cpu_model;
> const char *kernel_filename = machine->kernel_filename;
> const char *kernel_cmdline = machine->kernel_cmdline;
> const char *initrd_filename = machine->initrd_filename;
> - char **cpustr;
> - ObjectClass *cpu_oc;
> - CPUClass *cc;
> Object *cpuobj;
> ARMCPU *cpu;
> - const char *typename;
> MemoryRegion *address_space_mem = get_system_memory();
> MemoryRegion *ram = g_new(MemoryRegion, 1);
> MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
> qemu_irq pic[32];
> DeviceState *dev, *sic, *icp;
> int i;
> - Error *err = NULL;
>
> - if (!cpu_model) {
> - cpu_model = "arm926";
> - }
> -
> - cpustr = g_strsplit(cpu_model, ",", 2);
> -
> - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);
> - if (!cpu_oc) {
> - fprintf(stderr, "Unable to find CPU definition\n");
> - exit(1);
> - }
> - typename = object_class_get_name(cpu_oc);
> -
> - cc = CPU_CLASS(cpu_oc);
> - cc->parse_features(typename, cpustr[1], &err);
> - g_strfreev(cpustr);
> - if (err) {
> - error_report_err(err);
> - exit(1);
> - }
> -
> - cpuobj = object_new(typename);
> + cpuobj = object_new(machine->cpu_type);
>
> /* By default ARM1176 CPUs have EL3 enabled. This board does not
> * currently support EL3 so the CPU EL3 property is disabled before
> @@ -682,6 +655,7 @@ static void integratorcp_machine_init(MachineClass *mc)
> mc->desc = "ARM Integrator/CP (ARM926EJ-S)";
> mc->init = integratorcp_init;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
> }
>
> DEFINE_MACHINE("integratorcp", integratorcp_machine_init)
> diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
> index 637f52c..d07972a 100644
> --- a/hw/arm/mainstone.c
> +++ b/hw/arm/mainstone.c
> @@ -24,6 +24,7 @@
> #include "hw/sysbus.h"
> #include "exec/address-spaces.h"
> #include "sysemu/qtest.h"
> +#include "cpu.h"
>
> /* Device addresses */
> #define MST_FPGA_PHYS 0x08000000
> @@ -121,13 +122,10 @@ static void mainstone_common_init(MemoryRegion *address_space_mem,
> int i;
> int be;
> MemoryRegion *rom = g_new(MemoryRegion, 1);
> - const char *cpu_model = machine->cpu_model;
> -
> - if (!cpu_model)
> - cpu_model = "pxa270-c5";
>
> /* Setup CPU & memory */
> - mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size, cpu_model);
> + mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size,
> + machine->cpu_type);
> memory_region_init_ram(rom, NULL, "mainstone.rom", MAINSTONE_ROM,
> &error_fatal);
> memory_region_set_readonly(rom, true);
> @@ -197,6 +195,7 @@ static void mainstone2_machine_init(MachineClass *mc)
> mc->desc = "Mainstone II (PXA27x)";
> mc->init = mainstone_init;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5");
> }
>
> DEFINE_MACHINE("mainstone", mainstone2_machine_init)
> diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
> index abb0ab6..aeaad80 100644
> --- a/hw/arm/mps2.c
> +++ b/hw/arm/mps2.c
> @@ -46,7 +46,6 @@ typedef enum MPS2FPGAType {
> typedef struct {
> MachineClass parent;
> MPS2FPGAType fpga_type;
> - const char *cpu_model;
> uint32_t scc_id;
> } MPS2MachineClass;
>
> @@ -107,14 +106,12 @@ static void mps2_common_init(MachineState *machine)
> MPS2MachineState *mms = MPS2_MACHINE(machine);
> MPS2MachineClass *mmc = MPS2_MACHINE_GET_CLASS(machine);
> MemoryRegion *system_memory = get_system_memory();
> + MachineClass *mc = MACHINE_GET_CLASS(machine);
> DeviceState *armv7m, *sccdev;
>
> - if (!machine->cpu_model) {
> - machine->cpu_model = mmc->cpu_model;
> - }
> -
> - if (strcmp(machine->cpu_model, mmc->cpu_model) != 0) {
> - error_report("This board can only be used with CPU %s", mmc->cpu_model);
> + if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
> + error_report("This board can only be used with CPU %s",
> + mc->default_cpu_type);
> exit(1);
> }
>
> @@ -188,7 +185,7 @@ static void mps2_common_init(MachineState *machine)
> default:
> g_assert_not_reached();
> }
> - qdev_prop_set_string(armv7m, "cpu-model", machine->cpu_model);
> + qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type);
> object_property_set_link(OBJECT(&mms->armv7m), OBJECT(system_memory),
> "memory", &error_abort);
> object_property_set_bool(OBJECT(&mms->armv7m), true, "realized",
> @@ -339,7 +336,7 @@ static void mps2_an385_class_init(ObjectClass *oc, void *data)
>
> mc->desc = "ARM MPS2 with AN385 FPGA image for Cortex-M3";
> mmc->fpga_type = FPGA_AN385;
> - mmc->cpu_model = "cortex-m3";
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
> mmc->scc_id = 0x41040000 | (385 << 4);
> }
>
> @@ -350,7 +347,7 @@ static void mps2_an511_class_init(ObjectClass *oc, void *data)
>
> mc->desc = "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3";
> mmc->fpga_type = FPGA_AN511;
> - mmc->cpu_model = "cortex-m3";
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
> mmc->scc_id = 0x4104000 | (511 << 4);
> }
>
> diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
> index 7a6c0a6..b648770 100644
> --- a/hw/arm/musicpal.c
> +++ b/hw/arm/musicpal.c
> @@ -1570,7 +1570,6 @@ static struct arm_boot_info musicpal_binfo = {
>
> static void musicpal_init(MachineState *machine)
> {
> - const char *cpu_model = machine->cpu_model;
> const char *kernel_filename = machine->kernel_filename;
> const char *kernel_cmdline = machine->kernel_cmdline;
> const char *initrd_filename = machine->initrd_filename;
> @@ -1590,10 +1589,7 @@ static void musicpal_init(MachineState *machine)
> MemoryRegion *ram = g_new(MemoryRegion, 1);
> MemoryRegion *sram = g_new(MemoryRegion, 1);
>
> - if (!cpu_model) {
> - cpu_model = "arm926";
> - }
> - cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
> + cpu = ARM_CPU(cpu_create(machine->cpu_type));
>
> /* For now we use a fixed - the original - RAM size */
> memory_region_allocate_system_memory(ram, NULL, "musicpal.ram",
> @@ -1715,6 +1711,7 @@ static void musicpal_machine_init(MachineClass *mc)
> mc->desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)";
> mc->init = musicpal_init;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
> }
>
> DEFINE_MACHINE("musicpal", musicpal_machine_init)
> diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
> index 9d34d4c..f936017 100644
> --- a/hw/arm/netduino2.c
> +++ b/hw/arm/netduino2.c
> @@ -34,7 +34,7 @@ static void netduino2_init(MachineState *machine)
> DeviceState *dev;
>
> dev = qdev_create(NULL, TYPE_STM32F205_SOC);
> - qdev_prop_set_string(dev, "cpu-model", "cortex-m3");
> + qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
> object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);
>
> armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
> diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
> index a32ac82..58005b6 100644
> --- a/hw/arm/nseries.c
> +++ b/hw/arm/nseries.c
> @@ -1310,7 +1310,7 @@ static void n8x0_init(MachineState *machine,
> struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s));
> int sdram_size = binfo->ram_size;
>
> - s->mpu = omap2420_mpu_init(sysmem, sdram_size, machine->cpu_model);
> + s->mpu = omap2420_mpu_init(sysmem, sdram_size, machine->cpu_type);
>
> /* Setup peripherals
> *
> @@ -1426,6 +1426,7 @@ static void n800_class_init(ObjectClass *oc, void *data)
> mc->init = n800_init;
> mc->default_boot_order = "";
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm1136-r2");
> }
>
> static const TypeInfo n800_type = {
> @@ -1442,6 +1443,7 @@ static void n810_class_init(ObjectClass *oc, void *data)
> mc->init = n810_init;
> mc->default_boot_order = "";
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm1136-r2");
> }
>
> static const TypeInfo n810_type = {
> diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
> index 04e65ce..b3e7625 100644
> --- a/hw/arm/omap1.c
> +++ b/hw/arm/omap1.c
> @@ -3850,7 +3850,7 @@ static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
>
> struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
> unsigned long sdram_size,
> - const char *core)
> + const char *cpu_type)
> {
> int i;
> struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1);
> @@ -3858,12 +3858,9 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
> DriveInfo *dinfo;
> SysBusDevice *busdev;
>
> - if (!core)
> - core = "ti925t";
> -
> /* Core */
> s->mpu_model = omap310;
> - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, core));
> + s->cpu = ARM_CPU(cpu_create(cpu_type));
> s->sdram_size = sdram_size;
> s->sram_size = OMAP15XX_SRAM_SIZE;
>
> diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
> index 5821477..3f6076e 100644
> --- a/hw/arm/omap2.c
> +++ b/hw/arm/omap2.c
> @@ -2250,7 +2250,7 @@ static const struct dma_irq_map omap2_dma_irq_map[] = {
>
> struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
> unsigned long sdram_size,
> - const char *core)
> + const char *cpu_type)
> {
> struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1);
> qemu_irq dma_irqs[4];
> @@ -2261,7 +2261,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
>
> /* Core */
> s->mpu_model = omap2420;
> - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, core ?: "arm1136-r2"));
> + s->cpu = ARM_CPU(cpu_create(cpu_type));
> s->sdram_size = sdram_size;
> s->sram_size = OMAP242X_SRAM_SIZE;
>
> diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
> index 4535617..9a14270 100644
> --- a/hw/arm/omap_sx1.c
> +++ b/hw/arm/omap_sx1.c
> @@ -36,6 +36,7 @@
> #include "sysemu/block-backend.h"
> #include "sysemu/qtest.h"
> #include "exec/address-spaces.h"
> +#include "cpu.h"
>
> /*****************************************************************************/
> /* Siemens SX1 Cellphone V1 */
> @@ -120,7 +121,7 @@ static void sx1_init(MachineState *machine, const int version)
> }
>
> mpu = omap310_mpu_init(address_space, sx1_binfo.ram_size,
> - machine->cpu_model);
> + machine->cpu_type);
>
> /* External Flash (EMIFS) */
> memory_region_init_ram(flash, NULL, "omap_sx1.flash0-0", flash_size,
> @@ -224,6 +225,7 @@ static void sx1_machine_v2_class_init(ObjectClass *oc, void *data)
> mc->desc = "Siemens SX1 (OMAP310) V2";
> mc->init = sx1_init_v2;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
> }
>
> static const TypeInfo sx1_machine_v2_type = {
> @@ -239,6 +241,7 @@ static void sx1_machine_v1_class_init(ObjectClass *oc, void *data)
> mc->desc = "Siemens SX1 (OMAP310) V1";
> mc->init = sx1_init_v1;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
> }
>
> static const TypeInfo sx1_machine_v1_type = {
> diff --git a/hw/arm/palm.c b/hw/arm/palm.c
> index bf070a2..b8753e2 100644
> --- a/hw/arm/palm.c
> +++ b/hw/arm/palm.c
> @@ -29,6 +29,7 @@
> #include "hw/devices.h"
> #include "hw/loader.h"
> #include "exec/address-spaces.h"
> +#include "cpu.h"
>
> static uint32_t static_readb(void *opaque, hwaddr offset)
> {
> @@ -195,7 +196,6 @@ static struct arm_boot_info palmte_binfo = {
>
> static void palmte_init(MachineState *machine)
> {
> - const char *cpu_model = machine->cpu_model;
> const char *kernel_filename = machine->kernel_filename;
> const char *kernel_cmdline = machine->kernel_cmdline;
> const char *initrd_filename = machine->initrd_filename;
> @@ -211,7 +211,7 @@ static void palmte_init(MachineState *machine)
> MemoryRegion *flash = g_new(MemoryRegion, 1);
> MemoryRegion *cs = g_new(MemoryRegion, 4);
>
> - mpu = omap310_mpu_init(address_space_mem, sdram_size, cpu_model);
> + mpu = omap310_mpu_init(address_space_mem, sdram_size, machine->cpu_type);
>
> /* External Flash (EMIFS) */
> memory_region_init_ram(flash, NULL, "palmte.flash", flash_size,
> @@ -275,6 +275,7 @@ static void palmte_machine_init(MachineClass *mc)
> mc->desc = "Palm Tungsten|E aka. Cheetah PDA (OMAP310)";
> mc->init = palmte_init;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
> }
>
> DEFINE_MACHINE("cheetah", palmte_machine_init)
> diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
> index c16657d..cf07234 100644
> --- a/hw/arm/pxa2xx.c
> +++ b/hw/arm/pxa2xx.c
> @@ -2052,21 +2052,19 @@ static void pxa2xx_reset(void *opaque, int line, int level)
>
> /* Initialise a PXA270 integrated chip (ARM based core). */
> PXA2xxState *pxa270_init(MemoryRegion *address_space,
> - unsigned int sdram_size, const char *revision)
> + unsigned int sdram_size, const char *cpu_type)
> {
> PXA2xxState *s;
> int i;
> DriveInfo *dinfo;
> s = g_new0(PXA2xxState, 1);
>
> - if (revision && strncmp(revision, "pxa27", 5)) {
> + if (strncmp(cpu_type, "pxa27", 5)) {
> fprintf(stderr, "Machine requires a PXA27x processor.\n");
> exit(1);
> }
> - if (!revision)
> - revision = "pxa270";
>
> - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, revision));
> + s->cpu = ARM_CPU(cpu_create(cpu_type));
> s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0);
>
> /* SDRAM & Internal Memory Storage */
> @@ -2192,7 +2190,7 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
>
> s = g_new0(PXA2xxState, 1);
>
> - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, "pxa255"));
> + s->cpu = ARM_CPU(cpu_create(ARM_CPU_TYPE_NAME("pxa255")));
> s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0);
>
> /* SDRAM & Internal Memory Storage */
> diff --git a/hw/arm/realview.c b/hw/arm/realview.c
> index f3a49b6..87cd1e5 100644
> --- a/hw/arm/realview.c
> +++ b/hw/arm/realview.c
> @@ -57,7 +57,6 @@ static void realview_init(MachineState *machine,
> {
> ARMCPU *cpu = NULL;
> CPUARMState *env;
> - ObjectClass *cpu_oc;
> MemoryRegion *sysmem = get_system_memory();
> MemoryRegion *ram_lo;
> MemoryRegion *ram_hi = g_new(MemoryRegion, 1);
> @@ -98,14 +97,8 @@ static void realview_init(MachineState *machine,
> break;
> }
>
> - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, machine->cpu_model);
> - if (!cpu_oc) {
> - fprintf(stderr, "Unable to find CPU definition\n");
> - exit(1);
> - }
> -
> for (n = 0; n < smp_cpus; n++) {
> - Object *cpuobj = object_new(object_class_get_name(cpu_oc));
> + Object *cpuobj = object_new(machine->cpu_type);
>
> /* By default A9,A15 and ARM1176 CPUs have EL3 enabled. This board
> * does not currently support EL3 so the CPU EL3 property is disabled
> @@ -361,33 +354,21 @@ static void realview_init(MachineState *machine,
>
> static void realview_eb_init(MachineState *machine)
> {
> - if (!machine->cpu_model) {
> - machine->cpu_model = "arm926";
> - }
> realview_init(machine, BOARD_EB);
> }
>
> static void realview_eb_mpcore_init(MachineState *machine)
> {
> - if (!machine->cpu_model) {
> - machine->cpu_model = "arm11mpcore";
> - }
> realview_init(machine, BOARD_EB_MPCORE);
> }
>
> static void realview_pb_a8_init(MachineState *machine)
> {
> - if (!machine->cpu_model) {
> - machine->cpu_model = "cortex-a8";
> - }
> realview_init(machine, BOARD_PB_A8);
> }
>
> static void realview_pbx_a9_init(MachineState *machine)
> {
> - if (!machine->cpu_model) {
> - machine->cpu_model = "cortex-a9";
> - }
> realview_init(machine, BOARD_PBX_A9);
> }
>
> @@ -399,6 +380,7 @@ static void realview_eb_class_init(ObjectClass *oc, void *data)
> mc->init = realview_eb_init;
> mc->block_default_type = IF_SCSI;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
> }
>
> static const TypeInfo realview_eb_type = {
> @@ -416,6 +398,7 @@ static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data)
> mc->block_default_type = IF_SCSI;
> mc->max_cpus = 4;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm11mpcore");
> }
>
> static const TypeInfo realview_eb_mpcore_type = {
> @@ -431,6 +414,7 @@ static void realview_pb_a8_class_init(ObjectClass *oc, void *data)
> mc->desc = "ARM RealView Platform Baseboard for Cortex-A8";
> mc->init = realview_pb_a8_init;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a8");
> }
>
> static const TypeInfo realview_pb_a8_type = {
> @@ -447,6 +431,7 @@ static void realview_pbx_a9_class_init(ObjectClass *oc, void *data)
> mc->init = realview_pbx_a9_init;
> mc->max_cpus = 4;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
> }
>
> static const TypeInfo realview_pbx_a9_type = {
> diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
> index 6406421..feccdb0 100644
> --- a/hw/arm/spitz.c
> +++ b/hw/arm/spitz.c
> @@ -30,6 +30,7 @@
> #include "hw/sysbus.h"
> #include "exec/address-spaces.h"
> #include "sysemu/sysemu.h"
> +#include "cpu.h"
>
> #undef REG_FMT
> #define REG_FMT "0x%02lx"
> @@ -909,13 +910,10 @@ static void spitz_common_init(MachineState *machine,
> DeviceState *scp0, *scp1 = NULL;
> MemoryRegion *address_space_mem = get_system_memory();
> MemoryRegion *rom = g_new(MemoryRegion, 1);
> - const char *cpu_model = machine->cpu_model;
> -
> - if (!cpu_model)
> - cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0";
>
> /* Setup CPU & memory */
> - mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size, cpu_model);
> + mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size,
> + machine->cpu_type);
>
> sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
>
> @@ -984,6 +982,7 @@ static void akitapda_class_init(ObjectClass *oc, void *data)
> mc->desc = "Sharp SL-C1000 (Akita) PDA (PXA270)";
> mc->init = akita_init;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
> }
>
> static const TypeInfo akitapda_type = {
> @@ -1000,6 +999,7 @@ static void spitzpda_class_init(ObjectClass *oc, void *data)
> mc->init = spitz_init;
> mc->block_default_type = IF_IDE;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
> }
>
> static const TypeInfo spitzpda_type = {
> @@ -1016,6 +1016,7 @@ static void borzoipda_class_init(ObjectClass *oc, void *data)
> mc->init = borzoi_init;
> mc->block_default_type = IF_IDE;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
> }
>
> static const TypeInfo borzoipda_type = {
> @@ -1032,6 +1033,7 @@ static void terrierpda_class_init(ObjectClass *oc, void *data)
> mc->init = terrier_init;
> mc->block_default_type = IF_IDE;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5");
> }
>
> static const TypeInfo terrierpda_type = {
> diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
> index b3aad23..de7c0fc 100644
> --- a/hw/arm/stellaris.c
> +++ b/hw/arm/stellaris.c
> @@ -22,6 +22,7 @@
> #include "sysemu/sysemu.h"
> #include "hw/char/pl011.h"
> #include "hw/misc/unimp.h"
> +#include "cpu.h"
>
> #define GPIO_A 0
> #define GPIO_B 1
> @@ -1225,8 +1226,7 @@ static stellaris_board_info stellaris_boards[] = {
> }
> };
>
> -static void stellaris_init(const char *kernel_filename, const char *cpu_model,
> - stellaris_board_info *board)
> +static void stellaris_init(MachineState *ms, stellaris_board_info *board)
> {
> static const int uart_irq[] = {5, 6, 33, 34};
> static const int timer_irq[] = {19, 21, 23, 35};
> @@ -1298,7 +1298,7 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
> memory_region_add_subregion(system_memory, 0x20000000, sram);
>
> nvic = armv7m_init(system_memory, flash_size, NUM_IRQ_LINES,
> - kernel_filename, cpu_model);
> + ms->kernel_filename, ms->cpu_type);
>
> qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0,
> qemu_allocate_irq(&do_sys_reset, NULL, 0));
> @@ -1435,16 +1435,12 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
> /* FIXME: Figure out how to generate these from stellaris_boards. */
> static void lm3s811evb_init(MachineState *machine)
> {
> - const char *cpu_model = machine->cpu_model;
> - const char *kernel_filename = machine->kernel_filename;
> - stellaris_init(kernel_filename, cpu_model, &stellaris_boards[0]);
> + stellaris_init(machine, &stellaris_boards[0]);
> }
>
> static void lm3s6965evb_init(MachineState *machine)
> {
> - const char *cpu_model = machine->cpu_model;
> - const char *kernel_filename = machine->kernel_filename;
> - stellaris_init(kernel_filename, cpu_model, &stellaris_boards[1]);
> + stellaris_init(machine, &stellaris_boards[1]);
> }
>
> static void lm3s811evb_class_init(ObjectClass *oc, void *data)
> @@ -1454,6 +1450,7 @@ static void lm3s811evb_class_init(ObjectClass *oc, void *data)
> mc->desc = "Stellaris LM3S811EVB";
> mc->init = lm3s811evb_init;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
> }
>
> static const TypeInfo lm3s811evb_type = {
> @@ -1469,6 +1466,7 @@ static void lm3s6965evb_class_init(ObjectClass *oc, void *data)
> mc->desc = "Stellaris LM3S6965EVB";
> mc->init = lm3s6965evb_init;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
> }
>
> static const TypeInfo lm3s6965evb_type = {
> diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
> index f61e735..1cd6374 100644
> --- a/hw/arm/stm32f205_soc.c
> +++ b/hw/arm/stm32f205_soc.c
> @@ -112,7 +112,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
>
> armv7m = DEVICE(&s->armv7m);
> qdev_prop_set_uint32(armv7m, "num-irq", 96);
> - qdev_prop_set_string(armv7m, "cpu-model", s->cpu_model);
> + qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
> object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
> "memory", &error_abort);
> object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
> @@ -200,7 +200,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
> }
>
> static Property stm32f205_soc_properties[] = {
> - DEFINE_PROP_STRING("cpu-model", STM32F205State, cpu_model),
> + DEFINE_PROP_STRING("cpu-type", STM32F205State, cpu_type),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
> index c1145dd..3d1a231 100644
> --- a/hw/arm/strongarm.c
> +++ b/hw/arm/strongarm.c
> @@ -1581,23 +1581,19 @@ static const TypeInfo strongarm_ssp_info = {
>
> /* Main CPU functions */
> StrongARMState *sa1110_init(MemoryRegion *sysmem,
> - unsigned int sdram_size, const char *rev)
> + unsigned int sdram_size, const char *cpu_type)
> {
> StrongARMState *s;
> int i;
>
> s = g_new0(StrongARMState, 1);
>
> - if (!rev) {
> - rev = "sa1110-b5";
> - }
> -
> - if (strncmp(rev, "sa1110", 6)) {
> + if (strncmp(cpu_type, "sa1110", 6)) {
> error_report("Machine requires a SA1110 processor.");
> exit(1);
> }
>
> - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, rev));
> + s->cpu = ARM_CPU(cpu_create(cpu_type));
>
> memory_region_allocate_system_memory(&s->sdram, NULL, "strongarm.sdram",
> sdram_size);
> diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
> index 1134cf7..0447963 100644
> --- a/hw/arm/tosa.c
> +++ b/hw/arm/tosa.c
> @@ -219,7 +219,6 @@ static struct arm_boot_info tosa_binfo = {
>
> static void tosa_init(MachineState *machine)
> {
> - const char *cpu_model = machine->cpu_model;
> const char *kernel_filename = machine->kernel_filename;
> const char *kernel_cmdline = machine->kernel_cmdline;
> const char *initrd_filename = machine->initrd_filename;
> @@ -229,9 +228,6 @@ static void tosa_init(MachineState *machine)
> TC6393xbState *tmio;
> DeviceState *scp0, *scp1;
>
> - if (!cpu_model)
> - cpu_model = "pxa255";
> -
> mpu = pxa255_init(address_space_mem, tosa_binfo.ram_size);
>
> memory_region_init_ram(rom, NULL, "tosa.rom", TOSA_ROM, &error_fatal);
> diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
> index 76664e4..418792c 100644
> --- a/hw/arm/versatilepb.c
> +++ b/hw/arm/versatilepb.c
> @@ -181,7 +181,6 @@ static struct arm_boot_info versatile_binfo;
>
> static void versatile_init(MachineState *machine, int board_id)
> {
> - ObjectClass *cpu_oc;
> Object *cpuobj;
> ARMCPU *cpu;
> MemoryRegion *sysmem = get_system_memory();
> @@ -207,17 +206,7 @@ static void versatile_init(MachineState *machine, int board_id)
> exit(1);
> }
>
> - if (!machine->cpu_model) {
> - machine->cpu_model = "arm926";
> - }
> -
> - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, machine->cpu_model);
> - if (!cpu_oc) {
> - fprintf(stderr, "Unable to find CPU definition\n");
> - exit(1);
> - }
> -
> - cpuobj = object_new(object_class_get_name(cpu_oc));
> + cpuobj = object_new(machine->cpu_type);
>
> /* By default ARM1176 CPUs have EL3 enabled. This board does not
> * currently support EL3 so the CPU EL3 property is disabled before
> @@ -404,6 +393,7 @@ static void versatilepb_class_init(ObjectClass *oc, void *data)
> mc->init = vpb_init;
> mc->block_default_type = IF_SCSI;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
> }
>
> static const TypeInfo versatilepb_type = {
> @@ -420,6 +410,7 @@ static void versatileab_class_init(ObjectClass *oc, void *data)
> mc->init = vab_init;
> mc->block_default_type = IF_SCSI;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
> }
>
> static const TypeInfo versatileab_type = {
> diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
> index e3acab6..2e5f670 100644
> --- a/hw/arm/vexpress.c
> +++ b/hw/arm/vexpress.c
> @@ -186,7 +186,7 @@ typedef struct {
>
> typedef void DBoardInitFn(const VexpressMachineState *machine,
> ram_addr_t ram_size,
> - const char *cpu_model,
> + const char *cpu_type,
> qemu_irq *pic);
>
> struct VEDBoardInfo {
> @@ -202,22 +202,16 @@ struct VEDBoardInfo {
> DBoardInitFn *init;
> };
>
> -static void init_cpus(const char *cpu_model, const char *privdev,
> +static void init_cpus(const char *cpu_type, const char *privdev,
> hwaddr periphbase, qemu_irq *pic, bool secure)
> {
> - ObjectClass *cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
> DeviceState *dev;
> SysBusDevice *busdev;
> int n;
>
> - if (!cpu_oc) {
> - fprintf(stderr, "Unable to find CPU definition\n");
> - exit(1);
> - }
> -
> /* Create the actual CPUs */
> for (n = 0; n < smp_cpus; n++) {
> - Object *cpuobj = object_new(object_class_get_name(cpu_oc));
> + Object *cpuobj = object_new(cpu_type);
>
> if (!secure) {
> object_property_set_bool(cpuobj, false, "has_el3", NULL);
> @@ -262,7 +256,7 @@ static void init_cpus(const char *cpu_model, const char *privdev,
>
> static void a9_daughterboard_init(const VexpressMachineState *vms,
> ram_addr_t ram_size,
> - const char *cpu_model,
> + const char *cpu_type,
> qemu_irq *pic)
> {
> MemoryRegion *sysmem = get_system_memory();
> @@ -270,10 +264,6 @@ static void a9_daughterboard_init(const VexpressMachineState *vms,
> MemoryRegion *lowram = g_new(MemoryRegion, 1);
> ram_addr_t low_ram_size;
>
> - if (!cpu_model) {
> - cpu_model = "cortex-a9";
> - }
> -
> if (ram_size > 0x40000000) {
> /* 1GB is the maximum the address space permits */
> fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM\n");
> @@ -295,7 +285,7 @@ static void a9_daughterboard_init(const VexpressMachineState *vms,
> memory_region_add_subregion(sysmem, 0x60000000, ram);
>
> /* 0x1e000000 A9MPCore (SCU) private memory region */
> - init_cpus(cpu_model, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, vms->secure);
> + init_cpus(cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, vms->secure);
>
> /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
>
> @@ -351,17 +341,13 @@ static VEDBoardInfo a9_daughterboard = {
>
> static void a15_daughterboard_init(const VexpressMachineState *vms,
> ram_addr_t ram_size,
> - const char *cpu_model,
> + const char *cpu_type,
> qemu_irq *pic)
> {
> MemoryRegion *sysmem = get_system_memory();
> MemoryRegion *ram = g_new(MemoryRegion, 1);
> MemoryRegion *sram = g_new(MemoryRegion, 1);
>
> - if (!cpu_model) {
> - cpu_model = "cortex-a15";
> - }
> -
> {
> /* We have to use a separate 64 bit variable here to avoid the gcc
> * "comparison is always false due to limited range of data type"
> @@ -380,7 +366,7 @@ static void a15_daughterboard_init(const VexpressMachineState *vms,
> memory_region_add_subregion(sysmem, 0x80000000, ram);
>
> /* 0x2c000000 A15MPCore private memory region (GIC) */
> - init_cpus(cpu_model, TYPE_A15MPCORE_PRIV, 0x2c000000, pic, vms->secure);
> + init_cpus(cpu_type, TYPE_A15MPCORE_PRIV, 0x2c000000, pic, vms->secure);
>
> /* A15 daughterboard peripherals: */
>
> @@ -560,7 +546,7 @@ static void vexpress_common_init(MachineState *machine)
> const hwaddr *map = daughterboard->motherboard_map;
> int i;
>
> - daughterboard->init(vms, machine->ram_size, machine->cpu_model, pic);
> + daughterboard->init(vms, machine->ram_size, machine->cpu_type, pic);
>
> /*
> * If a bios file was provided, attempt to map it into memory
> @@ -761,6 +747,7 @@ static void vexpress_a9_class_init(ObjectClass *oc, void *data)
> VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
>
> mc->desc = "ARM Versatile Express for Cortex-A9";
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
>
> vmc->daughterboard = &a9_daughterboard;
> }
> @@ -771,6 +758,7 @@ static void vexpress_a15_class_init(ObjectClass *oc, void *data)
> VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
>
> mc->desc = "ARM Versatile Express for Cortex-A15";
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
>
> vmc->daughterboard = &a15_daughterboard;
> }
> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> index fe96557..fe26e99 100644
> --- a/hw/arm/virt.c
> +++ b/hw/arm/virt.c
> @@ -163,13 +163,13 @@ static const int a15irqmap[] = {
> };
>
> static const char *valid_cpus[] = {
> - "cortex-a15",
> - "cortex-a53",
> - "cortex-a57",
> - "host",
> + ARM_CPU_TYPE_NAME("cortex-a15"),
> + ARM_CPU_TYPE_NAME("cortex-a53"),
> + ARM_CPU_TYPE_NAME("cortex-a57"),
> + ARM_CPU_TYPE_NAME("host"),
> };
>
> -static bool cpuname_valid(const char *cpu)
> +static bool cpu_type_valid(const char *cpu)
> {
> int i;
>
> @@ -1258,18 +1258,8 @@ static void machvirt_init(MachineState *machine)
> MemoryRegion *secure_sysmem = NULL;
> int n, virt_max_cpus;
> MemoryRegion *ram = g_new(MemoryRegion, 1);
> - const char *cpu_model = machine->cpu_model;
> - char **cpustr;
> - ObjectClass *oc;
> - const char *typename;
> - CPUClass *cc;
> - Error *err = NULL;
> bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0);
>
> - if (!cpu_model) {
> - cpu_model = "cortex-a15";
> - }
> -
> /* We can probe only here because during property set
> * KVM is not available yet
> */
> @@ -1286,11 +1276,8 @@ static void machvirt_init(MachineState *machine)
> }
> }
>
> - /* Separate the actual CPU model name from any appended features */
> - cpustr = g_strsplit(cpu_model, ",", 2);
> -
> - if (!cpuname_valid(cpustr[0])) {
> - error_report("mach-virt: CPU %s not supported", cpustr[0]);
> + if (!cpu_type_valid(machine->cpu_type)) {
> + error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
> exit(1);
> }
>
> @@ -1360,22 +1347,6 @@ static void machvirt_init(MachineState *machine)
>
> create_fdt(vms);
>
> - oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);
> - if (!oc) {
> - error_report("Unable to find CPU definition");
> - exit(1);
> - }
> - typename = object_class_get_name(oc);
> -
> - /* convert -smp CPU options specified by the user into global props */
> - cc = CPU_CLASS(oc);
> - cc->parse_features(typename, cpustr[1], &err);
> - g_strfreev(cpustr);
> - if (err) {
> - error_report_err(err);
> - exit(1);
> - }
> -
> possible_cpus = mc->possible_cpu_arch_ids(machine);
> for (n = 0; n < possible_cpus->len; n++) {
> Object *cpuobj;
> @@ -1385,7 +1356,7 @@ static void machvirt_init(MachineState *machine)
> break;
> }
>
> - cpuobj = object_new(typename);
> + cpuobj = object_new(machine->cpu_type);
> object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id,
> "mp-affinity", NULL);
>
> @@ -1630,6 +1601,7 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
> mc->minimum_page_bits = 12;
> mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
> mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
> }
>
> static const TypeInfo virt_machine_info = {
> diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
> index 3759cf8..1836a4e 100644
> --- a/hw/arm/xilinx_zynq.c
> +++ b/hw/arm/xilinx_zynq.c
> @@ -158,11 +158,9 @@ static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
> static void zynq_init(MachineState *machine)
> {
> ram_addr_t ram_size = machine->ram_size;
> - const char *cpu_model = machine->cpu_model;
> const char *kernel_filename = machine->kernel_filename;
> const char *kernel_cmdline = machine->kernel_cmdline;
> const char *initrd_filename = machine->initrd_filename;
> - ObjectClass *cpu_oc;
> ARMCPU *cpu;
> MemoryRegion *address_space_mem = get_system_memory();
> MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
> @@ -174,12 +172,7 @@ static void zynq_init(MachineState *machine)
> qemu_irq pic[64];
> int n;
>
> - if (!cpu_model) {
> - cpu_model = "cortex-a9";
> - }
> - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
> -
> - cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc)));
> + cpu = ARM_CPU(object_new(machine->cpu_type));
>
> /* By default A9 CPUs have EL3 enabled. This board does not
> * currently support EL3 so the CPU EL3 property is disabled before
> @@ -327,6 +320,7 @@ static void zynq_machine_init(MachineClass *mc)
> mc->max_cpus = 1;
> mc->no_sdcard = 1;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
> }
>
> DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init)
> diff --git a/hw/arm/z2.c b/hw/arm/z2.c
> index 417bc1a..60561c7 100644
> --- a/hw/arm/z2.c
> +++ b/hw/arm/z2.c
> @@ -26,6 +26,7 @@
> #include "audio/audio.h"
> #include "exec/address-spaces.h"
> #include "sysemu/qtest.h"
> +#include "cpu.h"
>
> #ifdef DEBUG_Z2
> #define DPRINTF(fmt, ...) \
> @@ -296,7 +297,6 @@ static const TypeInfo aer915_info = {
>
> static void z2_init(MachineState *machine)
> {
> - const char *cpu_model = machine->cpu_model;
> const char *kernel_filename = machine->kernel_filename;
> const char *kernel_cmdline = machine->kernel_cmdline;
> const char *initrd_filename = machine->initrd_filename;
> @@ -309,12 +309,8 @@ static void z2_init(MachineState *machine)
> I2CBus *bus;
> DeviceState *wm;
>
> - if (!cpu_model) {
> - cpu_model = "pxa270-c5";
> - }
> -
> /* Setup CPU & memory */
> - mpu = pxa270_init(address_space_mem, z2_binfo.ram_size, cpu_model);
> + mpu = pxa270_init(address_space_mem, z2_binfo.ram_size, machine->cpu_type);
>
> #ifdef TARGET_WORDS_BIGENDIAN
> be = 1;
> @@ -371,6 +367,7 @@ static void z2_machine_init(MachineClass *mc)
> mc->desc = "Zipit Z2 (PXA27x)";
> mc->init = z2_init;
> mc->ignore_memory_transaction_failures = true;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5");
> }
>
> DEFINE_MACHINE("z2", z2_machine_init)
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index a1acce3..ff7ff28 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -905,7 +905,7 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
> }
>
> cpuname = g_strsplit(cpu_model, ",", 1);
> - typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]);
> + typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpuname[0]);
> oc = object_class_by_name(typename);
> g_strfreev(cpuname);
> g_free(typename);
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Qemu-devel] [PATCH v2 3/5] vl.c: convert cpu_model to cpu type and set of global properties before machine_init()
2017-09-13 16:04 ` [Qemu-devel] [PATCH v2 3/5] vl.c: convert cpu_model to cpu type and set of global properties before machine_init() Igor Mammedov
@ 2017-09-14 18:19 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-09-14 18:19 UTC (permalink / raw)
To: Igor Mammedov, qemu-devel
On 09/13/2017 01:04 PM, Igor Mammedov wrote:
> All machines that support user specified cpu_model either call
> cpu_generic_init() or cpu_class_by_name()/CPUClass::parse_features
> to parse feature string and to get CPU type to create.
>
> Which leads to code duplication and hard-codding default CPU model
> within machine_foo_init() code. Which makes it impossible to
> get CPU type before machine_init() is run.
>
> So instead of setting default CPUs models and doing parsing in
> target specific machine_foo_init() in various ways, provide
> a generic data driven cpu_model parsing before machine_init()
> is called.
>
> in follow up per target patches, it will allow to:
> * define default CPU type in consistent/generic manner
> per machine type and drop custom code that fallbacks
> to default if cpu_model is NULL
> * drop custom features parsing in targets and do it
> in centralized way.
> * for cases of
> cpu_generic_init(TYPE_BASE/DEFAULT_CPU, "some_cpu")
> replace it with
> cpu_create(machine->cpu_type) || cpu_create(TYPE_FOO)
> depending if CPU type is user settable or not.
> not doing useless parsing and clearly documenting where
> CPU model is user settable or fixed one.
>
> Patch allows machine subclasses to define default CPU type
> per machine class at class_init() time and if that is set
> generic code will parse cpu_model into a MachineState::cpu_type
> which will be used to create CPUs for that machine instance
> and allows gradual per board conversion.
>
> Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> Target specific changes will split into separate per target/machine
> patches to make changes reviewable.
> ---
> include/hw/boards.h | 6 ++++++
> vl.c | 10 ++++++++++
> 2 files changed, 16 insertions(+)
>
> diff --git a/include/hw/boards.h b/include/hw/boards.h
> index 7f044d1..6b67ada 100644
> --- a/include/hw/boards.h
> +++ b/include/hw/boards.h
> @@ -125,6 +125,10 @@ typedef struct {
> * Caller is responsible for freeing returned list.
> * @has_hotpluggable_cpus:
> * If true, board supports CPUs creation with -device/device_add.
> + * @default_cpu_type:
> + * specifies default CPU_TYPE, which will be used for parsing target
> + * specific features and for creating CPUs if CPU name wasn't provided
> + * explicitly at CLI
> * @minimum_page_bits:
> * If non-zero, the board promises never to create a CPU with a page size
> * smaller than this, so QEMU can use a more efficient larger page
> @@ -177,6 +181,7 @@ struct MachineClass {
> GArray *compat_props;
> const char *hw_version;
> ram_addr_t default_ram_size;
> + const char *default_cpu_type;
> bool option_rom_has_mr;
> bool rom_file_has_mr;
> int minimum_page_bits;
> @@ -231,6 +236,7 @@ struct MachineState {
> char *kernel_cmdline;
> char *initrd_filename;
> const char *cpu_model;
> + const char *cpu_type;
> AccelState *accelerator;
> CPUArchIdList *possible_cpus;
> };
> diff --git a/vl.c b/vl.c
> index fb1f05b..034180f 100644
> --- a/vl.c
> +++ b/vl.c
> @@ -4636,6 +4636,16 @@ int main(int argc, char **argv, char **envp)
> current_machine->boot_order = boot_order;
> current_machine->cpu_model = cpu_model;
>
> +
> + /* parse features once if machine provides default cpu_type */
> + if (machine_class->default_cpu_type) {
> + current_machine->cpu_type = machine_class->default_cpu_type;
> + if (cpu_model) {
> + current_machine->cpu_type =
> + cpu_parse_cpu_model(machine_class->default_cpu_type, cpu_model);
> + }
> + }
> +
> machine_run_board_init(current_machine);
>
> realtime_init();
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Qemu-devel] [PATCH v2 5/5] arm: drop intermediate cpu_model -> cpu type parsing and use cpu type directly
2017-09-14 7:50 ` Igor Mammedov
@ 2017-09-14 22:09 ` Alistair Francis
0 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2017-09-14 22:09 UTC (permalink / raw)
To: Igor Mammedov
Cc: Philippe Mathieu-Daudé, qemu-arm, qemu-devel@nongnu.org Developers
On Thu, Sep 14, 2017 at 12:50 AM, Igor Mammedov <imammedo@redhat.com> wrote:
> On Thu, 14 Sep 2017 00:47:20 -0300
> Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
>> Hi Igor,
>>
>> awesome clean refactor!
> Thanks,
>
> there is more patches on this topic for other targets to post
> but it's waiting on 1-3/5 to land in master so it would be
> easier for maintainers to verify/test them without fishing out
> dependencies from mail list.
>
> hopefully everything will land in 2.11 so we won't have to deal
> with cpu_model anywhere except of one place vl.c.
>
>> just 1 comment inlined.
>>
>> On 09/13/2017 01:04 PM, Igor Mammedov wrote:
>> > there are 2 use cases to deal with:
>> > 1: fixed CPU models per board/soc
>> > 2: boards with user configurable cpu_model and fallback to
>> > default cpu_model if user hasn't specified one explicitly
>> >
>> > For the 1st
>> > drop intermediate cpu_model parsing and use const cpu type
>> > directly, which replaces:
>> > typename = object_class_get_name(
>> > cpu_class_by_name(TYPE_ARM_CPU, cpu_model))
>> > object_new(typename)
>> > with
>> > object_new(FOO_CPU_TYPE_NAME)
>> > or
>> > cpu_generic_init(BASE_CPU_TYPE, "my cpu model")
>> > with
>> > cpu_create(FOO_CPU_TYPE_NAME)
>> >
>> > as result 1st use case doesn't have to invoke not necessary
>> > translation and not needed code is removed.
>> >
>> > For the 2nd
>> > 1: set default cpu type with MachineClass::default_cpu_type and
>> > 2: use generic cpu_model parsing that done before machine_init()
>> > is run and:
>> > 2.1: drop custom cpu_model parsing where pattern is:
>> > typename = object_class_get_name(
>> > cpu_class_by_name(TYPE_ARM_CPU, cpu_model))
>> > [parse_features(typename, cpu_model, &err) ]
>> >
>> > 2.2: or replace cpu_generic_init() which does what
>> > 2.1 does + create_cpu(typename) with just
>> > create_cpu(machine->cpu_type)
>> > as result cpu_name -> cpu_type translation is done using
>> > generic machine code one including parsing optional features
>> > if supported/present (removes a bunch of duplicated cpu_model
>> > parsing code) and default cpu type is defined in an uniform way
>> > within machine_class_init callbacks instead of adhoc places
>> > in boadr's machine_init code.
>> >
>> > Signed-off-by: Igor Mammedov <imammedo@redhat.com>
>> > Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
>> > ---
>> > v2:
>> > - fix merge conflicts with ignore_memory_transaction_failures
>> > - fix couple merge conflicts where SoC type string where replaced by type macro
>> > - keep plain prefix string in: strncmp(cpu_type, "pxa27", 5)
>> > - s/"%s" ARM_CPU_TYPE_SUFFIX/ARM_CPU_TYPE_NAME("%s")/
>> > ---
> [...]
>
>> > diff --git a/hw/arm/virt.c b/hw/arm/virt.c
>> > index fe96557..fe26e99 100644
>> > --- a/hw/arm/virt.c
>> > +++ b/hw/arm/virt.c
>> > @@ -163,13 +163,13 @@ static const int a15irqmap[] = {
>> > };
>> >
>> > static const char *valid_cpus[] = {
>> > - "cortex-a15",
>> > - "cortex-a53",
>> > - "cortex-a57",
>> > - "host",
>> > + ARM_CPU_TYPE_NAME("cortex-a15"),
>> > + ARM_CPU_TYPE_NAME("cortex-a53"),
>> > + ARM_CPU_TYPE_NAME("cortex-a57"),
>> > + ARM_CPU_TYPE_NAME("host"),
>> > };
>> >
>> > -static bool cpuname_valid(const char *cpu)
>> > +static bool cpu_type_valid(const char *cpu)
>> > {
>> > int i;
>>
>> I'd just change this by:
>>
>> static bool cpuname_valid(const char *cpu)
>> {
>> static const char *valid_cpus[] = {
>> ARM_CPU_TYPE_NAME("cortex-a15"),
>> ARM_CPU_TYPE_NAME("cortex-a53"),
>> ARM_CPU_TYPE_NAME("cortex-a57"),
>> };
>> int i;
>>
>> for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
>> if (strcmp(cpu, valid_cpus[i]) == 0) {
>> return true;
>> }
>> }
>
>> return kvm_enabled() && !strcmp(cpu, ARM_CPU_TYPE_NAME("host");
> here is one more case to consider for valid_cpus refactoring,
> CCing Alistair.
Thanks, I have a few comments I need to look at for this. I'm going to
hold off until this series lands though.
Thanks,
Alistair
>
>> }
>>
>> Anyway this can be a later patch.
> this check might be removed or superseded by generic valid_cpus work
> that Alistair is working on, anyways it should be part of that work
> as change is not directly related to this series.
>
>
> [...]
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Qemu-devel] [PATCH v2 0/5] generalize parsing of cpu_model (x86/arm)
2017-09-13 16:04 [Qemu-devel] [PATCH v2 0/5] generalize parsing of cpu_model (x86/arm) Igor Mammedov
` (4 preceding siblings ...)
2017-09-13 16:04 ` [Qemu-devel] [PATCH v2 5/5] arm: drop intermediate cpu_model -> cpu type parsing and use cpu type directly Igor Mammedov
@ 2017-09-15 15:03 ` Igor Mammedov
2017-09-18 16:42 ` Igor Mammedov
5 siblings, 1 reply; 17+ messages in thread
From: Igor Mammedov @ 2017-09-15 15:03 UTC (permalink / raw)
To: qemu-devel
On Wed, 13 Sep 2017 18:04:52 +0200
Igor Mammedov <imammedo@redhat.com> wrote:
> Changelog since v1:
> * fix merge conflicts with ignore_memory_transaction_failures
> * fix couple merge conflicts where SoC type string where replaced by type macro
> * keep plain prefix string in: strncmp(cpu_type, "pxa27", 5)
> * s/"%s" ARM_CPU_TYPE_SUFFIX/ARM_CPU_TYPE_NAME("%s")/
> * drop not needed assert
> * instead of checking error/reporting/exiting explicitly
> use error_fatal which will do all of it for us
> * squash in "cpu: rename cpu_parse_features() to cpu_parse_cpu_model()"
>
>
> Issue 1:
> Some callers call CPUClass->parse_features manually to convert
> '-cpu cpufoo,featurestr' string to cpu type and featurestr
> into a set of global properties and then do controlled
> cpu creation with setting properties and completing it with realize.
> That's a lot of code duplication as they all are practically
> reimplement the same parsing logic.
>
> Some use cpu_generic_init() instead which does the same parsing
> along with creation/realizing cpu within one wrapper.
>
> And some trying to switch to controlled cpu creation,
> implement object_new()/set properties/realize steps
> but forget feature parsing logic witch leads to 'bugs'
> commit (00909b585 hw/arm/integratorcp: Support specifying features via -cpu)
>
> Issue 2:
> Default cpu model selection logic is spread over all board's
> machine_init() fuctions but it's basicallyi hardcodes default
> cpu model string in init function.
>
> if (!cpu_model) {
> cpu_model = "some cpu model string";
> }
>
> and written in different ways.
> it forces machine_init callbacks to parse cpu_model string
> either by using cpu_generic_init() or by manually calling
> cpu_class_by_name()/CPUClass::parse_features to perform
> name to cpu type translation.
>
> This series moves -cpu option parsing to generic machine code
> that removes some of code duplication and makes cpus creation
> process more generic/simple:
>
> * unify default (fallback) cpu type handling by replacing
> hardcoded cpu_model strings with cpu type directly in
>
> machine_foo_class_init() {
> MachineClass::default_cpu_type = BOARD_DEFAULT_CPU_TYPE
> }
>
> which allows to generalize move cpu model parsing instead of
> parsing it in each board.
>
> * make generic machine vl.c parse cpu_model into properties/cpu_type
> and let boards use cpu_type without any cpu_model prasing.
> Generic parsing will kick in only if board advertises its support
> by setting MachineClass::default_cpu_type to a cpu type.
>
> PS:
> I intend make tree-wide conversion but as one series it's too many patches,
> so I'm splitting out it into an intial series that implements generic
> part and several patchsets that will do per target conversion.
>
> As part of initial series x86 and ARM targets conversion is included
> to showcase generalization usage. Per target conversions are done
> as 1 patch per target, it might be too much for targets that have lots
> of boards (ARM) so let me know if you'd like to split it on per board
> basis (then I'll respin it as separate series on top of generic patches)
>
> github tree for testing:
> https://github.com/imammedo/qemu.git default_machine_cpu_type_PC_ARM_v2
>
Hi Eduardo,
Could you merge it via machine tree?
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Qemu-devel] [PATCH v2 0/5] generalize parsing of cpu_model (x86/arm)
2017-09-15 15:03 ` [Qemu-devel] [PATCH v2 0/5] generalize parsing of cpu_model (x86/arm) Igor Mammedov
@ 2017-09-18 16:42 ` Igor Mammedov
2017-09-19 12:11 ` Eduardo Habkost
0 siblings, 1 reply; 17+ messages in thread
From: Igor Mammedov @ 2017-09-18 16:42 UTC (permalink / raw)
To: qemu-devel; +Cc: Eduardo Habkost, peter.maydell, Subbaraya Sundeep
On Fri, 15 Sep 2017 17:03:26 +0200
Igor Mammedov <imammedo@redhat.com> wrote:
[...]
> >
> Hi Eduardo,
>
> Could you merge it via machine tree?
Forgot to actually CC Eduardo,
Just noticed a patch (1) on list adding a new soc that would break,
due to armv7 dropping cpu-model property in 5/5.
It would be better to merge this series asap so that people
could rebase their work on cpu-type based approach, instead of
continuing copy-past old cpu-model based code.
1)
[Qemu devel v9 PATCH 4/5] msf2: Add Smartfusion2 SoC
CCing Subbaraya so he could amend patch to use cpu-type instead of cpu-model.
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH] !fixup arm: missed comment update
2017-09-13 16:04 ` [Qemu-devel] [PATCH v2 5/5] arm: drop intermediate cpu_model -> cpu type parsing and use cpu type directly Igor Mammedov
2017-09-14 3:47 ` Philippe Mathieu-Daudé
2017-09-14 17:57 ` Alistair Francis
@ 2017-09-18 21:53 ` Philippe Mathieu-Daudé
2 siblings, 0 replies; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-09-18 21:53 UTC (permalink / raw)
To: Igor Mammedov, Eduardo Habkost
Cc: Philippe Mathieu-Daudé, qemu-devel, Peter Maydell, qemu-arm
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
Based-on: 1505318697-77161-6-git-send-email-imammedo@redhat.com
include/hw/arm/armv7m.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
index 68cb30d611..9ad316c76e 100644
--- a/include/hw/arm/armv7m.h
+++ b/include/hw/arm/armv7m.h
@@ -35,7 +35,7 @@ typedef struct {
/* ARMv7M container object.
* + Unnamed GPIO input lines: external IRQ lines for the NVIC
* + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ
- * + Property "cpu-model": CPU model to instantiate
+ * + Property "cpu-type": CPU type to instantiate
* + Property "num-irq": number of external IRQ lines
* + Property "memory": MemoryRegion defining the physical address space
* that CPU accesses see. (The NVIC, bitbanding and other CPU-internal
--
2.14.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [Qemu-devel] [PATCH v2 0/5] generalize parsing of cpu_model (x86/arm)
2017-09-18 16:42 ` Igor Mammedov
@ 2017-09-19 12:11 ` Eduardo Habkost
2017-09-19 12:46 ` Igor Mammedov
2017-09-19 12:56 ` Philippe Mathieu-Daudé
0 siblings, 2 replies; 17+ messages in thread
From: Eduardo Habkost @ 2017-09-19 12:11 UTC (permalink / raw)
To: Igor Mammedov; +Cc: qemu-devel, peter.maydell, Subbaraya Sundeep
On Mon, Sep 18, 2017 at 06:42:13PM +0200, Igor Mammedov wrote:
> On Fri, 15 Sep 2017 17:03:26 +0200
> Igor Mammedov <imammedo@redhat.com> wrote:
>
> [...]
> > >
> > Hi Eduardo,
> >
> > Could you merge it via machine tree?
> Forgot to actually CC Eduardo,
>
> Just noticed a patch (1) on list adding a new soc that would break,
> due to armv7 dropping cpu-model property in 5/5.
> It would be better to merge this series asap so that people
> could rebase their work on cpu-type based approach, instead of
> continuing copy-past old cpu-model based code.
>
> 1)
> [Qemu devel v9 PATCH 4/5] msf2: Add Smartfusion2 SoC
>
> CCing Subbaraya so he could amend patch to use cpu-type instead of cpu-model.
Queued on machine-next:
https://github.com/ehabkost/qemu.git machine-next
--
Eduardo
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Qemu-devel] [PATCH v2 0/5] generalize parsing of cpu_model (x86/arm)
2017-09-19 12:11 ` Eduardo Habkost
@ 2017-09-19 12:46 ` Igor Mammedov
2017-09-19 12:56 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 17+ messages in thread
From: Igor Mammedov @ 2017-09-19 12:46 UTC (permalink / raw)
To: Eduardo Habkost; +Cc: peter.maydell, qemu-devel, Subbaraya Sundeep
On Tue, 19 Sep 2017 09:11:25 -0300
Eduardo Habkost <ehabkost@redhat.com> wrote:
> On Mon, Sep 18, 2017 at 06:42:13PM +0200, Igor Mammedov wrote:
> > On Fri, 15 Sep 2017 17:03:26 +0200
> > Igor Mammedov <imammedo@redhat.com> wrote:
> >
> > [...]
> > > >
> > > Hi Eduardo,
> > >
> > > Could you merge it via machine tree?
> > Forgot to actually CC Eduardo,
> >
> > Just noticed a patch (1) on list adding a new soc that would break,
> > due to armv7 dropping cpu-model property in 5/5.
> > It would be better to merge this series asap so that people
> > could rebase their work on cpu-type based approach, instead of
> > continuing copy-past old cpu-model based code.
> >
> > 1)
> > [Qemu devel v9 PATCH 4/5] msf2: Add Smartfusion2 SoC
> >
> > CCing Subbaraya so he could amend patch to use cpu-type instead of cpu-model.
>
> Queued on machine-next:
>
> https://github.com/ehabkost/qemu.git machine-next
>
Thanks!
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Qemu-devel] [PATCH v2 0/5] generalize parsing of cpu_model (x86/arm)
2017-09-19 12:11 ` Eduardo Habkost
2017-09-19 12:46 ` Igor Mammedov
@ 2017-09-19 12:56 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-09-19 12:56 UTC (permalink / raw)
To: Eduardo Habkost, Igor Mammedov
Cc: peter.maydell, qemu-devel, Subbaraya Sundeep
On 09/19/2017 09:11 AM, Eduardo Habkost wrote:
>> Igor Mammedov <imammedo@redhat.com> wrote:
[...]
>>> Could you merge it via machine tree?
[...]
>
> Queued on machine-next:
Thanks Eduardo for applying the !fixup :)
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2017-09-19 12:56 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-09-13 16:04 [Qemu-devel] [PATCH v2 0/5] generalize parsing of cpu_model (x86/arm) Igor Mammedov
2017-09-13 16:04 ` [Qemu-devel] [PATCH v2 1/5] qom: cpus: split cpu_generic_init() on feature parsing and cpu creation parts Igor Mammedov
2017-09-13 16:04 ` [Qemu-devel] [PATCH v2 2/5] cpu: make cpu_generic_init() abort QEMU on error Igor Mammedov
2017-09-13 16:04 ` [Qemu-devel] [PATCH v2 3/5] vl.c: convert cpu_model to cpu type and set of global properties before machine_init() Igor Mammedov
2017-09-14 18:19 ` Philippe Mathieu-Daudé
2017-09-13 16:04 ` [Qemu-devel] [PATCH v2 4/5] pc: use generic cpu_model parsing Igor Mammedov
2017-09-13 16:04 ` [Qemu-devel] [PATCH v2 5/5] arm: drop intermediate cpu_model -> cpu type parsing and use cpu type directly Igor Mammedov
2017-09-14 3:47 ` Philippe Mathieu-Daudé
2017-09-14 7:50 ` Igor Mammedov
2017-09-14 22:09 ` Alistair Francis
2017-09-14 17:57 ` Alistair Francis
2017-09-18 21:53 ` [Qemu-devel] [PATCH] !fixup arm: missed comment update Philippe Mathieu-Daudé
2017-09-15 15:03 ` [Qemu-devel] [PATCH v2 0/5] generalize parsing of cpu_model (x86/arm) Igor Mammedov
2017-09-18 16:42 ` Igor Mammedov
2017-09-19 12:11 ` Eduardo Habkost
2017-09-19 12:46 ` Igor Mammedov
2017-09-19 12:56 ` Philippe Mathieu-Daudé
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