* [PATCH 1/5] drm/i915/cnl: extract cnl_dvfs_{pre, post}_change
2017-09-26 19:17 [PATCH 0/5] Introduce DVFS Rodrigo Vivi
@ 2017-09-26 19:17 ` Rodrigo Vivi
2017-09-26 19:17 ` [PATCH 2/5] drm/i915/cnl: Expose DVFS change functions Rodrigo Vivi
` (9 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Rodrigo Vivi @ 2017-09-26 19:17 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Rodrigo Vivi
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
These functions even have their own page in our spec,
so extract them from cnl_set_cdclk().
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_cdclk.c | 33 +++++++++++++++++++++++----------
1 file changed, 23 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 87fc42b19336..a7f3e4615a44 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1510,12 +1510,8 @@ static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
dev_priv->cdclk.hw.vco = vco;
}
-static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *cdclk_state)
+static int cnl_dvfs_pre_change(struct drm_i915_private *dev_priv)
{
- int cdclk = cdclk_state->cdclk;
- int vco = cdclk_state->vco;
- u32 val, divider, pcu_ack;
int ret;
mutex_lock(&dev_priv->rps.hw_lock);
@@ -1524,11 +1520,30 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
SKL_CDCLK_READY_FOR_CHANGE,
SKL_CDCLK_READY_FOR_CHANGE, 3);
mutex_unlock(&dev_priv->rps.hw_lock);
- if (ret) {
+
+ if (ret)
DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
ret);
+
+ return ret;
+}
+
+static void cnl_dvfs_post_change(struct drm_i915_private *dev_priv, int level)
+{
+ mutex_lock(&dev_priv->rps.hw_lock);
+ sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, level);
+ mutex_unlock(&dev_priv->rps.hw_lock);
+}
+
+static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_state *cdclk_state)
+{
+ int cdclk = cdclk_state->cdclk;
+ int vco = cdclk_state->vco;
+ u32 val, divider, pcu_ack;
+
+ if (!cnl_dvfs_pre_change(dev_priv))
return;
- }
/* cdclk = vco / 2 / div{1,2} */
switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
@@ -1575,9 +1590,7 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
I915_WRITE(CDCLK_CTL, val);
/* inform PCU of the change */
- mutex_lock(&dev_priv->rps.hw_lock);
- sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
- mutex_unlock(&dev_priv->rps.hw_lock);
+ cnl_dvfs_post_change(dev_priv, pcu_ack);
intel_update_cdclk(dev_priv);
}
--
2.13.5
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^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 2/5] drm/i915/cnl: Expose DVFS change functions
2017-09-26 19:17 [PATCH 0/5] Introduce DVFS Rodrigo Vivi
2017-09-26 19:17 ` [PATCH 1/5] drm/i915/cnl: extract cnl_dvfs_{pre, post}_change Rodrigo Vivi
@ 2017-09-26 19:17 ` Rodrigo Vivi
2017-09-26 19:17 ` [PATCH 3/5] drm/i915/cnl: DVFS for PLL enabling Rodrigo Vivi
` (8 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Rodrigo Vivi @ 2017-09-26 19:17 UTC (permalink / raw)
To: intel-gfx; +Cc: Kahola, Rodrigo Vivi
From: "Kahola, Mika" <mika.kahola@intel.com>
DVFS computation needs cnl_dvfs_{pre,post}_change() functions to be exposed.
These functions will be used when computing DVFS levels in intel_dpll_mgr.c
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Kahola, Mika <mika.kahola@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_cdclk.c | 4 ++--
drivers/gpu/drm/i915/intel_drv.h | 2 ++
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index a7f3e4615a44..86ef4d0add70 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1510,7 +1510,7 @@ static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
dev_priv->cdclk.hw.vco = vco;
}
-static int cnl_dvfs_pre_change(struct drm_i915_private *dev_priv)
+int cnl_dvfs_pre_change(struct drm_i915_private *dev_priv)
{
int ret;
@@ -1528,7 +1528,7 @@ static int cnl_dvfs_pre_change(struct drm_i915_private *dev_priv)
return ret;
}
-static void cnl_dvfs_post_change(struct drm_i915_private *dev_priv, int level)
+void cnl_dvfs_post_change(struct drm_i915_private *dev_priv, int level)
{
mutex_lock(&dev_priv->rps.hw_lock);
sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, level);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0cab667fff57..f9d7b48584d3 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1322,6 +1322,8 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv);
void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
void cnl_init_cdclk(struct drm_i915_private *dev_priv);
void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
+int cnl_dvfs_pre_change(struct drm_i915_private *dev_priv);
+void cnl_dvfs_post_change(struct drm_i915_private *dev_priv, int level);
void bxt_init_cdclk(struct drm_i915_private *dev_priv);
void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
--
2.13.5
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^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 3/5] drm/i915/cnl: DVFS for PLL enabling
2017-09-26 19:17 [PATCH 0/5] Introduce DVFS Rodrigo Vivi
2017-09-26 19:17 ` [PATCH 1/5] drm/i915/cnl: extract cnl_dvfs_{pre, post}_change Rodrigo Vivi
2017-09-26 19:17 ` [PATCH 2/5] drm/i915/cnl: Expose DVFS change functions Rodrigo Vivi
@ 2017-09-26 19:17 ` Rodrigo Vivi
2017-09-26 19:17 ` [PATCH 4/5] drm/i915/cnl: DVFS for PLL disabling Rodrigo Vivi
` (7 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Rodrigo Vivi @ 2017-09-26 19:17 UTC (permalink / raw)
To: intel-gfx; +Cc: Kahola, Paulo Zanoni, Rodrigo Vivi
From: "Kahola, Mika" <mika.kahola@intel.com>
Display Voltage and Frequency Switching (DVFS) is used to adjust the
display voltage to match the display clock frequencies. If voltage is
set too low, it will break functionality. If voltage is set too high,
it will waste power. Voltage level is selected based on CD clock and
DDI clock.
The sequence before frequency change is the following and it requests
the power controller to raise voltage to maximum
- Ensure any previous GT Driver Mailbox transaction is complete.
- Write GT Driver Mailbox Data Low = 0x3.
- Write GT Driver Mailbox Data High = 0x0.
- Write GT Driver Mailbox Interface = 0x80000007.
- Poll GT Driver Mailbox Interface for Run/Busy indication cleared (bit 31 = 0).
- Read GT Driver Mailbox Data Low, if bit 0 is 0x1, continue, else restart the sequence.
Timeout after 3ms
The sequence after frequency change is the following and it requests
the port controller to raise voltage to the requested level.
- Write GT Driver Mailbox Data Low
* For level 0, write 0x0
* For level 1, write 0x1
* For level 2, write 0x2
* For level 3, write 0x3
- Write GT Driver Mailbox Data High = 0x0.
- Write GT Driver Mailbox Interface = 0x80000007.
For Cannonlake, the level 3 is not used and it aliases to level 2.
v2: reuse Paulo's work on cdclk. This patch depends on Paulo's patch
[PATCH 02/12] drm/i915/cnl: extract cnl_dvfs_{pre,post}_change
v3: (By Rodrigo): Remove duplicated commend and fix typo on Paulo's name.
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Kahola, Mika <mika.kahola@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 57 ++++++++++++++++++++++++++++++-----
1 file changed, 49 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index a2a3d93d67bd..9927df6294da 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1966,10 +1966,48 @@ static const struct intel_dpll_mgr bxt_pll_mgr = {
.dump_hw_state = bxt_dump_hw_state,
};
+static int cnl_get_port_clock(uint32_t val)
+{
+ if (val & DPLL_CFGCR0_LINK_RATE_810)
+ return 2*81000;
+ else if (val & DPLL_CFGCR0_LINK_RATE_1350)
+ return 2*135000;
+ else if (val & DPLL_CFGCR0_LINK_RATE_2700)
+ return 2*270000;
+ else if (val & DPLL_CFGCR0_LINK_RATE_1620)
+ return 2*162000;
+ else if (val & DPLL_CFGCR0_LINK_RATE_1080)
+ return 2*108000;
+ else if (val & DPLL_CFGCR0_LINK_RATE_2160)
+ return 2*216000;
+ else if (val & DPLL_CFGCR0_LINK_RATE_3240)
+ return 2*324000;
+ else if (val & DPLL_CFGCR0_LINK_RATE_4050)
+ return 2*405000;
+
+ return -EINVAL;
+}
+
+static int cnl_get_dvfs_level(int cdclk, int portclk)
+{
+ if (portclk == -EINVAL)
+ return 2;
+
+ if (cdclk == 168000 && portclk < 594000)
+ return 0;
+ else if (cdclk == 336000 && portclk < 594000)
+ return 1;
+ else
+ return 2;
+}
+
static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
uint32_t val;
+ int ret;
+ int level;
+ int cdclk, portclk;
/* 1. Enable DPLL power in DPLL_ENABLE. */
val = I915_READ(CNL_DPLL_ENABLE(pll->id));
@@ -2006,11 +2044,9 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
/*
* 5. If the frequency will result in a change to the voltage
* requirement, follow the Display Voltage Frequency Switching
- * Sequence Before Frequency Change
- *
- * FIXME: (DVFS) is used to adjust the display voltage to match the
- * display clock frequencies
+ * (DVFS) Sequence Before Frequency Change
*/
+ ret = cnl_dvfs_pre_change(dev_priv);
/* 6. Enable DPLL in DPLL_ENABLE. */
val = I915_READ(CNL_DPLL_ENABLE(pll->id));
@@ -2028,11 +2064,16 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
/*
* 8. If the frequency will result in a change to the voltage
* requirement, follow the Display Voltage Frequency Switching
- * Sequence After Frequency Change
- *
- * FIXME: (DVFS) is used to adjust the display voltage to match the
- * display clock frequencies
+ * (DVFS) Sequence After Frequency Change
*/
+ if (ret == 0) {
+ val = pll->state.hw_state.cfgcr0;
+ cdclk = dev_priv->cdclk.hw.cdclk;
+ portclk = cnl_get_port_clock(val);
+
+ level = cnl_get_dvfs_level(cdclk, portclk);
+ cnl_dvfs_post_change(dev_priv, level);
+ }
/*
* 9. turn on the clock for the DDI and map the DPLL to the DDI
--
2.13.5
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^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 4/5] drm/i915/cnl: DVFS for PLL disabling
2017-09-26 19:17 [PATCH 0/5] Introduce DVFS Rodrigo Vivi
` (2 preceding siblings ...)
2017-09-26 19:17 ` [PATCH 3/5] drm/i915/cnl: DVFS for PLL enabling Rodrigo Vivi
@ 2017-09-26 19:17 ` Rodrigo Vivi
2017-09-26 19:17 ` [PATCH 5/5] drm/i915: Extend DVFS function back to Skylake Rodrigo Vivi
` (6 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Rodrigo Vivi @ 2017-09-26 19:17 UTC (permalink / raw)
To: intel-gfx; +Cc: Kahola, Paulo Zanoni, Rodrigo Vivi
From: "Kahola, Mika" <mika.kahola@intel.com>
Display Voltage and Frequency Switching (DVFS) is used to adjust the
display voltage to match the display clock frequencies. To save power the
voltage is set to minimum when disabling PLL.
The sequence before frequency change is the following and it requests
the power controller to raise voltage to maximum
- Ensure any previous GT Driver Mailbox transaction is complete.
- Write GT Driver Mailbox Data Low = 0x3.
- Write GT Driver Mailbox Data High = 0x0.
- Write GT Driver Mailbox Interface = 0x80000007.
- Poll GT Driver Mailbox Interface for Run/Busy indication cleared (bit 31 = 0).
- Read GT Driver Mailbox Data Low, if bit 0 is 0x1, continue, else restart the sequence.
Timeout after 3ms
The sequence after frequency change is the following and it requests
the port controller to lower voltage to the minimum.
- Write GT Driver Mailbox Data Low = 0x0
- Write GT Driver Mailbox Data High = 0x0.
- Write GT Driver Mailbox Interface = 0x80000007.
v2: reuse Paulo's work on cdclk. This patch depends on Paulo's patch
[PATCH 02/12] drm/i915/cnl: extract cnl_dvfs_{pre,post}_change
v3: (By Rodrigo): Fix typo on Paulo's name.
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Kahola, Mika <mika.kahola@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 9927df6294da..cc288534dcc6 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2085,6 +2085,7 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
uint32_t val;
+ int ret;
/*
* 1. Configure DPCLKA_CFGCR0 to turn off the clock for the DDI.
@@ -2094,11 +2095,9 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
/*
* 2. If the frequency will result in a change to the voltage
* requirement, follow the Display Voltage Frequency Switching
- * Sequence Before Frequency Change
- *
- * FIXME: (DVFS) is used to adjust the display voltage to match the
- * display clock frequencies
+ * (DVFS) Sequence Before Frequency Change
*/
+ ret = cnl_dvfs_pre_change(dev_priv);
/* 3. Disable DPLL through DPLL_ENABLE. */
val = I915_READ(CNL_DPLL_ENABLE(pll->id));
@@ -2116,11 +2115,10 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
/*
* 5. If the frequency will result in a change to the voltage
* requirement, follow the Display Voltage Frequency Switching
- * Sequence After Frequency Change
- *
- * FIXME: (DVFS) is used to adjust the display voltage to match the
- * display clock frequencies
+ * (DVFS) Sequence After Frequency Change
*/
+ if (ret == 0)
+ cnl_dvfs_post_change(dev_priv, 0);
/* 6. Disable DPLL power in DPLL_ENABLE. */
val = I915_READ(CNL_DPLL_ENABLE(pll->id));
--
2.13.5
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^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 5/5] drm/i915: Extend DVFS function back to Skylake.
2017-09-26 19:17 [PATCH 0/5] Introduce DVFS Rodrigo Vivi
` (3 preceding siblings ...)
2017-09-26 19:17 ` [PATCH 4/5] drm/i915/cnl: DVFS for PLL disabling Rodrigo Vivi
@ 2017-09-26 19:17 ` Rodrigo Vivi
2017-09-26 19:40 ` ✓ Fi.CI.BAT: success for Introduce DVFS Patchwork
` (5 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Rodrigo Vivi @ 2017-09-26 19:17 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Rodrigo Vivi
Although SKL Spec doesn't explicit call this sequence
as DVFS, that is exactly what it is.
So let's remove a bit of code duplication and re-use
CNL functions.
No functional change.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_cdclk.c | 25 ++++++-------------------
drivers/gpu/drm/i915/intel_dpll_mgr.c | 8 ++++----
drivers/gpu/drm/i915/intel_drv.h | 4 ++--
3 files changed, 12 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 86ef4d0add70..d6befabd6ed5 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -924,21 +924,10 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
int cdclk = cdclk_state->cdclk;
int vco = cdclk_state->vco;
u32 freq_select, pcu_ack;
- int ret;
WARN_ON((cdclk == 24000) != (vco == 0));
- mutex_lock(&dev_priv->rps.hw_lock);
- ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
- SKL_CDCLK_PREPARE_FOR_CHANGE,
- SKL_CDCLK_READY_FOR_CHANGE,
- SKL_CDCLK_READY_FOR_CHANGE, 3);
- mutex_unlock(&dev_priv->rps.hw_lock);
- if (ret) {
- DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
- ret);
- return;
- }
+ skl_dvfs_pre_change(dev_priv);
/* set CDCLK_CTL */
switch (cdclk) {
@@ -975,9 +964,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
POSTING_READ(CDCLK_CTL);
/* inform PCU of the change */
- mutex_lock(&dev_priv->rps.hw_lock);
- sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
- mutex_unlock(&dev_priv->rps.hw_lock);
+ skl_dvfs_post_change(dev_priv, pcu_ack);
intel_update_cdclk(dev_priv);
}
@@ -1510,7 +1497,7 @@ static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
dev_priv->cdclk.hw.vco = vco;
}
-int cnl_dvfs_pre_change(struct drm_i915_private *dev_priv)
+int skl_dvfs_pre_change(struct drm_i915_private *dev_priv)
{
int ret;
@@ -1528,7 +1515,7 @@ int cnl_dvfs_pre_change(struct drm_i915_private *dev_priv)
return ret;
}
-void cnl_dvfs_post_change(struct drm_i915_private *dev_priv, int level)
+void skl_dvfs_post_change(struct drm_i915_private *dev_priv, int level)
{
mutex_lock(&dev_priv->rps.hw_lock);
sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, level);
@@ -1542,7 +1529,7 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
int vco = cdclk_state->vco;
u32 val, divider, pcu_ack;
- if (!cnl_dvfs_pre_change(dev_priv))
+ if (!skl_dvfs_pre_change(dev_priv))
return;
/* cdclk = vco / 2 / div{1,2} */
@@ -1590,7 +1577,7 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
I915_WRITE(CDCLK_CTL, val);
/* inform PCU of the change */
- cnl_dvfs_post_change(dev_priv, pcu_ack);
+ skl_dvfs_post_change(dev_priv, pcu_ack);
intel_update_cdclk(dev_priv);
}
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index cc288534dcc6..c08ca8f03e90 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2046,7 +2046,7 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
* requirement, follow the Display Voltage Frequency Switching
* (DVFS) Sequence Before Frequency Change
*/
- ret = cnl_dvfs_pre_change(dev_priv);
+ ret = skl_dvfs_pre_change(dev_priv);
/* 6. Enable DPLL in DPLL_ENABLE. */
val = I915_READ(CNL_DPLL_ENABLE(pll->id));
@@ -2072,7 +2072,7 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
portclk = cnl_get_port_clock(val);
level = cnl_get_dvfs_level(cdclk, portclk);
- cnl_dvfs_post_change(dev_priv, level);
+ skl_dvfs_post_change(dev_priv, level);
}
/*
@@ -2097,7 +2097,7 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
* requirement, follow the Display Voltage Frequency Switching
* (DVFS) Sequence Before Frequency Change
*/
- ret = cnl_dvfs_pre_change(dev_priv);
+ ret = skl_dvfs_pre_change(dev_priv);
/* 3. Disable DPLL through DPLL_ENABLE. */
val = I915_READ(CNL_DPLL_ENABLE(pll->id));
@@ -2118,7 +2118,7 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
* (DVFS) Sequence After Frequency Change
*/
if (ret == 0)
- cnl_dvfs_post_change(dev_priv, 0);
+ skl_dvfs_post_change(dev_priv, 0);
/* 6. Disable DPLL power in DPLL_ENABLE. */
val = I915_READ(CNL_DPLL_ENABLE(pll->id));
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f9d7b48584d3..688843bd7f68 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1320,10 +1320,10 @@ void intel_audio_deinit(struct drm_i915_private *dev_priv);
int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
void skl_init_cdclk(struct drm_i915_private *dev_priv);
void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
+int skl_dvfs_pre_change(struct drm_i915_private *dev_priv);
+void skl_dvfs_post_change(struct drm_i915_private *dev_priv, int level);
void cnl_init_cdclk(struct drm_i915_private *dev_priv);
void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
-int cnl_dvfs_pre_change(struct drm_i915_private *dev_priv);
-void cnl_dvfs_post_change(struct drm_i915_private *dev_priv, int level);
void bxt_init_cdclk(struct drm_i915_private *dev_priv);
void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
--
2.13.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread* ✓ Fi.CI.BAT: success for Introduce DVFS.
2017-09-26 19:17 [PATCH 0/5] Introduce DVFS Rodrigo Vivi
` (4 preceding siblings ...)
2017-09-26 19:17 ` [PATCH 5/5] drm/i915: Extend DVFS function back to Skylake Rodrigo Vivi
@ 2017-09-26 19:40 ` Patchwork
2017-09-27 4:38 ` ✓ Fi.CI.IGT: " Patchwork
` (4 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2017-09-26 19:40 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: Introduce DVFS.
URL : https://patchwork.freedesktop.org/series/30922/
State : success
== Summary ==
Series 30922v1 Introduce DVFS.
https://patchwork.freedesktop.org/api/1.0/series/30922/revisions/1/mbox/
Test drv_module_reload:
Subgroup basic-reload-inject:
pass -> DMESG-WARN (fi-glk-1) fdo#102777
fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:443s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:480s
fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:421s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:538s
fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:279s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:503s
fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:505s
fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:497s
fi-cfl-s total:289 pass:222 dwarn:35 dfail:0 fail:0 skip:32 time:539s
fi-cnl-y total:289 pass:208 dwarn:12 dfail:31 fail:6 skip:31 time:652s
fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:424s
fi-glk-1 total:289 pass:259 dwarn:1 dfail:0 fail:0 skip:29 time:569s
fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:427s
fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:406s
fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:440s
fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:491s
fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:465s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:478s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:578s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:592s
fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:547s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:455s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:761s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:495s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:480s
fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:571s
fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:421s
c4c623d58e38d49e692dc9141250b35e39170e6b drm-tip: 2017y-09m-26d-16h-37m-12s UTC integration manifest
6dd2e3d2f1dc drm/i915: Extend DVFS function back to Skylake.
0b6ee028eacd drm/i915/cnl: DVFS for PLL disabling
d53bc8bce9dc drm/i915/cnl: DVFS for PLL enabling
5f4344381ec4 drm/i915/cnl: Expose DVFS change functions
efb033fbb119 drm/i915/cnl: extract cnl_dvfs_{pre, post}_change
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5823/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* ✓ Fi.CI.IGT: success for Introduce DVFS.
2017-09-26 19:17 [PATCH 0/5] Introduce DVFS Rodrigo Vivi
` (5 preceding siblings ...)
2017-09-26 19:40 ` ✓ Fi.CI.BAT: success for Introduce DVFS Patchwork
@ 2017-09-27 4:38 ` Patchwork
2017-09-28 21:46 ` ✓ Fi.CI.BAT: " Patchwork
` (3 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2017-09-27 4:38 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: Introduce DVFS.
URL : https://patchwork.freedesktop.org/series/30922/
State : success
== Summary ==
Test kms_setmode:
Subgroup basic:
fail -> PASS (shard-hsw) fdo#99912
Test kms_flip:
Subgroup flip-vs-expired-vblank:
fail -> PASS (shard-hsw) fdo#102367
Subgroup plain-flip-ts-check-interruptible:
fail -> PASS (shard-hsw)
Test perf:
Subgroup polling:
pass -> FAIL (shard-hsw) fdo#102252
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102367 https://bugs.freedesktop.org/show_bug.cgi?id=102367
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
shard-hsw total:2429 pass:1335 dwarn:1 dfail:0 fail:10 skip:1083 time:9986s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5823/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* ✓ Fi.CI.BAT: success for Introduce DVFS.
2017-09-26 19:17 [PATCH 0/5] Introduce DVFS Rodrigo Vivi
` (6 preceding siblings ...)
2017-09-27 4:38 ` ✓ Fi.CI.IGT: " Patchwork
@ 2017-09-28 21:46 ` Patchwork
2017-09-29 0:06 ` ✗ Fi.CI.IGT: failure " Patchwork
` (2 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2017-09-28 21:46 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: Introduce DVFS.
URL : https://patchwork.freedesktop.org/series/30922/
State : success
== Summary ==
Series 30922v1 Introduce DVFS.
https://patchwork.freedesktop.org/api/1.0/series/30922/revisions/1/mbox/
Test chamelium:
Subgroup dp-crc-fast:
fail -> PASS (fi-kbl-7500u) fdo#102514
Test drv_module_reload:
Subgroup basic-reload:
pass -> DMESG-WARN (fi-glk-1) fdo#102777 +1
fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514
fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:441s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:473s
fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:416s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:513s
fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:278s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:500s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:514s
fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:491s
fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:486s
fi-cfl-s total:289 pass:256 dwarn:1 dfail:0 fail:0 skip:32 time:566s
fi-cnl-y total:289 pass:210 dwarn:12 dfail:31 fail:2 skip:33 time:624s
fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:412s
fi-glk-1 total:289 pass:259 dwarn:1 dfail:0 fail:0 skip:29 time:568s
fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:426s
fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:403s
fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:429s
fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:488s
fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:471s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:477s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:577s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:585s
fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:544s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:452s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:754s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:489s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:474s
fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:561s
fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:418s
0369ecdbb55495dd4671ad33d375f37d0707b629 drm-tip: 2017y-09m-28d-20h-01m-55s UTC integration manifest
ac06c12d8d06 drm/i915: Extend DVFS function back to Skylake.
451034bed2be drm/i915/cnl: DVFS for PLL disabling
6446bda2c77d drm/i915/cnl: DVFS for PLL enabling
2484dcc7c187 drm/i915/cnl: Expose DVFS change functions
07076582a9a9 drm/i915/cnl: extract cnl_dvfs_{pre, post}_change
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5853/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* ✗ Fi.CI.IGT: failure for Introduce DVFS.
2017-09-26 19:17 [PATCH 0/5] Introduce DVFS Rodrigo Vivi
` (7 preceding siblings ...)
2017-09-28 21:46 ` ✓ Fi.CI.BAT: " Patchwork
@ 2017-09-29 0:06 ` Patchwork
2017-09-29 10:35 ` ✓ Fi.CI.BAT: success " Patchwork
2017-09-29 11:39 ` ✗ Fi.CI.BAT: failure " Patchwork
10 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2017-09-29 0:06 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: Introduce DVFS.
URL : https://patchwork.freedesktop.org/series/30922/
State : failure
== Summary ==
Test perf:
Subgroup blocking:
fail -> PASS (shard-hsw) fdo#102252
Test gem_exec_schedule:
Subgroup preempt-self-vebox:
skip -> INCOMPLETE (shard-hsw)
Test kms_setmode:
Subgroup basic:
pass -> FAIL (shard-hsw) fdo#99912
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
shard-hsw total:2429 pass:1311 dwarn:4 dfail:0 fail:10 skip:1055 time:9896s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5853/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* ✓ Fi.CI.BAT: success for Introduce DVFS.
2017-09-26 19:17 [PATCH 0/5] Introduce DVFS Rodrigo Vivi
` (8 preceding siblings ...)
2017-09-29 0:06 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2017-09-29 10:35 ` Patchwork
2017-09-29 11:39 ` ✗ Fi.CI.BAT: failure " Patchwork
10 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2017-09-29 10:35 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: Introduce DVFS.
URL : https://patchwork.freedesktop.org/series/30922/
State : success
== Summary ==
Series 30922v1 Introduce DVFS.
https://patchwork.freedesktop.org/api/1.0/series/30922/revisions/1/mbox/
Test drv_module_reload:
Subgroup basic-reload-inject:
pass -> DMESG-WARN (fi-glk-1) fdo#102777
fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:443s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:480s
fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:421s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:538s
fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:279s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:503s
fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:505s
fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:497s
fi-cfl-s total:289 pass:222 dwarn:35 dfail:0 fail:0 skip:32 time:539s
fi-cnl-y total:289 pass:208 dwarn:12 dfail:31 fail:6 skip:31 time:652s
fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:424s
fi-glk-1 total:289 pass:259 dwarn:1 dfail:0 fail:0 skip:29 time:569s
fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:427s
fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:406s
fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:440s
fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:491s
fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:465s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:478s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:578s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:592s
fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:547s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:455s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:761s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:495s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:480s
fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:571s
fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:421s
c4c623d58e38d49e692dc9141250b35e39170e6b drm-tip: 2017y-09m-26d-16h-37m-12s UTC integration manifest
6dd2e3d2f1dc drm/i915: Extend DVFS function back to Skylake.
0b6ee028eacd drm/i915/cnl: DVFS for PLL disabling
d53bc8bce9dc drm/i915/cnl: DVFS for PLL enabling
5f4344381ec4 drm/i915/cnl: Expose DVFS change functions
efb033fbb119 drm/i915/cnl: extract cnl_dvfs_{pre, post}_change
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5823/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* ✗ Fi.CI.BAT: failure for Introduce DVFS.
2017-09-26 19:17 [PATCH 0/5] Introduce DVFS Rodrigo Vivi
` (9 preceding siblings ...)
2017-09-29 10:35 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2017-09-29 11:39 ` Patchwork
10 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2017-09-29 11:39 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: Introduce DVFS.
URL : https://patchwork.freedesktop.org/series/30922/
State : failure
== Summary ==
Series 30922v1 Introduce DVFS.
https://patchwork.freedesktop.org/api/1.0/series/30922/revisions/1/mbox/
Test gem_exec_suspend:
Subgroup basic-s3:
pass -> DMESG-WARN (fi-cnl-y) fdo#103036
Subgroup basic-s4-devices:
pass -> DMESG-WARN (fi-cnl-y)
Test gem_flink_basic:
Subgroup bad-flink:
pass -> DMESG-WARN (fi-cnl-y)
Subgroup bad-open:
pass -> DMESG-WARN (fi-cnl-y)
Subgroup basic:
pass -> DMESG-WARN (fi-cnl-y)
Test kms_busy:
Subgroup basic-flip-a:
pass -> DMESG-FAIL (fi-cnl-y)
Subgroup basic-flip-b:
pass -> DMESG-FAIL (fi-cnl-y)
Subgroup basic-flip-c:
pass -> DMESG-FAIL (fi-cnl-y)
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass -> DMESG-FAIL (fi-cnl-y)
Subgroup basic-busy-flip-before-cursor-legacy:
pass -> DMESG-FAIL (fi-cnl-y)
Subgroup basic-flip-after-cursor-atomic:
pass -> DMESG-FAIL (fi-cnl-y)
Subgroup basic-flip-after-cursor-legacy:
pass -> DMESG-FAIL (fi-cnl-y)
Subgroup basic-flip-after-cursor-varying-size:
pass -> DMESG-FAIL (fi-cnl-y)
Subgroup basic-flip-before-cursor-atomic:
pass -> DMESG-FAIL (fi-cnl-y)
Subgroup basic-flip-before-cursor-legacy:
pass -> DMESG-FAIL (fi-cnl-y)
Subgroup basic-flip-before-cursor-varying-size:
pass -> DMESG-FAIL (fi-cnl-y)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
pass -> SKIP (fi-cnl-y)
Subgroup basic-flip-vs-modeset:
pass -> SKIP (fi-cnl-y)
Subgroup basic-flip-vs-wf_vblank:
pass -> SKIP (fi-cnl-y)
Subgroup basic-plain-flip:
pass -> SKIP (fi-cnl-y)
Test kms_frontbuffer_tracking:
Subgroup basic:
pass -> SKIP (fi-cnl-y)
Test kms_pipe_crc_basic:
Subgroup bad-nb-words-1:
pass -> DMESG-WARN (fi-cnl-y)
Subgroup bad-nb-words-3:
pass -> DMESG-WARN (fi-cnl-y)
Subgroup bad-pipe:
pass -> DMESG-WARN (fi-cnl-y)
Subgroup bad-source:
pass -> DMESG-WARN (fi-cnl-y)
Subgroup hang-read-crc-pipe-a:
pass -> DMESG-FAIL (fi-cnl-y)
Subgroup hang-read-crc-pipe-b:
pass -> DMESG-FAIL (fi-cnl-y)
Subgroup hang-read-crc-pipe-c:
pass -> DMESG-FAIL (fi-cnl-y)
Subgroup nonblocking-crc-pipe-a:
pass -> DMESG-FAIL (fi-cnl-y)
Subgroup nonblocking-crc-pipe-a-frame-sequence:
pass -> DMESG-FAIL (fi-cnl-y)
Subgroup nonblocking-crc-pipe-b:
pass -> DMESG-FAIL (fi-cnl-y)
Subgroup nonblocking-crc-pipe-b-frame-sequence:
pass -> DMESG-FAIL (fi-cnl-y)
Subgroup nonblocking-crc-pipe-c:
pass -> DMESG-FAIL (fi-cnl-y)
Subgroup nonblocking-crc-pipe-c-frame-sequence:
pass -> DMESG-FAIL (fi-cnl-y)
Subgroup read-crc-pipe-a:
pass -> DMESG-FAIL (fi-cnl-y)
Subgroup read-crc-pipe-a-frame-sequence:
pass -> DMESG-FAIL (fi-cnl-y)
Subgroup read-crc-pipe-b:
pass -> DMESG-FAIL (fi-cnl-y)
Subgroup read-crc-pipe-b-frame-sequence:
pass -> DMESG-FAIL (fi-cnl-y)
Subgroup read-crc-pipe-c:
pass -> DMESG-FAIL (fi-cnl-y)
Subgroup read-crc-pipe-c-frame-sequence:
pass -> DMESG-FAIL (fi-cnl-y)
Subgroup suspend-read-crc-pipe-a:
pass -> DMESG-FAIL (fi-cnl-y)
Subgroup suspend-read-crc-pipe-b:
pass -> DMESG-FAIL (fi-cnl-y)
Subgroup suspend-read-crc-pipe-c:
pass -> DMESG-FAIL (fi-cnl-y)
Test kms_psr_sink_crc:
Subgroup psr_basic:
pass -> DMESG-FAIL (fi-cnl-y)
Test kms_setmode:
WARNING: Long output truncated
c4c623d58e38d49e692dc9141250b35e39170e6b drm-tip: 2017y-09m-26d-16h-37m-12s UTC integration manifest
6dd2e3d2f1dc drm/i915: Extend DVFS function back to Skylake.
0b6ee028eacd drm/i915/cnl: DVFS for PLL disabling
d53bc8bce9dc drm/i915/cnl: DVFS for PLL enabling
5f4344381ec4 drm/i915/cnl: Expose DVFS change functions
efb033fbb119 drm/i915/cnl: extract cnl_dvfs_{pre, post}_change
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5823/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread