* [PATCH] drm/i915: Fix DDI PHY init if it was already on
@ 2017-10-02 13:53 Imre Deak
2017-10-02 14:17 ` ✓ Fi.CI.BAT: success for " Patchwork
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Imre Deak @ 2017-10-02 13:53 UTC (permalink / raw)
To: intel-gfx
The common lane power down flag of a DPIO PHY has a funky semantic:
after the initial enabling of the PHY (so from a disabled state) this
flag will be clear. It will be set only after the PHY will be used for
the first time (for instance due to enabling the corresponding pipe) and
then become unused (due to disabling the pipe). During the initial PHY
enablement we don't know which of the above phases we are in, so move
the check for the flag where this is known, the HW readout code. This is
where the rest of lane power down status checks are done anyway.
This fixes at least a problem on GLK where after module reloading, the
common lane power down flag of PHY1 is set, but the PHY is actually
powered-on and properly set up. The GRC readout code for other PHYs will
hence think that PHY1 is not powered initially and disable it after the
GRC readout. This will cause the AUX power well related to PHY1 to get
disabled in a stuck state, timing out when we try to enable it later.
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Fixes: e93da0a0137b ("drm/i915/bxt: Sanitiy check the PHY lane power down status")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102777
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 3 ++-
drivers/gpu/drm/i915/intel_dpio_phy.c | 20 --------------------
2 files changed, 2 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 93cbbcbbc193..65f4b6786791 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1713,7 +1713,8 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
out:
if (ret && IS_GEN9_LP(dev_priv)) {
tmp = I915_READ(BXT_PHY_CTL(port));
- if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK |
+ if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
+ BXT_PHY_LANE_POWERDOWN_ACK |
BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
DRM_ERROR("Port %c enabled but PHY powered down? "
"(PHY_CTL %08x)\n", port_name(port), tmp);
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index 09b670929786..de38d014ed39 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -208,12 +208,6 @@ static const struct bxt_ddi_phy_info glk_ddi_phy_info[] = {
},
};
-static u32 bxt_phy_port_mask(const struct bxt_ddi_phy_info *phy_info)
-{
- return (phy_info->dual_channel * BIT(phy_info->channel[DPIO_CH1].port)) |
- BIT(phy_info->channel[DPIO_CH0].port);
-}
-
static const struct bxt_ddi_phy_info *
bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count)
{
@@ -313,7 +307,6 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
enum dpio_phy phy)
{
const struct bxt_ddi_phy_info *phy_info;
- enum port port;
phy_info = bxt_get_phy_info(dev_priv, phy);
@@ -335,19 +328,6 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
return false;
}
- for_each_port_masked(port, bxt_phy_port_mask(phy_info)) {
- u32 tmp = I915_READ(BXT_PHY_CTL(port));
-
- if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) {
- DRM_DEBUG_DRIVER("DDI PHY %d powered, but common lane "
- "for port %c powered down "
- "(PHY_CTL %08x)\n",
- phy, port_name(port), tmp);
-
- return false;
- }
- }
-
return true;
}
--
2.13.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Fix DDI PHY init if it was already on
2017-10-02 13:53 [PATCH] drm/i915: Fix DDI PHY init if it was already on Imre Deak
@ 2017-10-02 14:17 ` Patchwork
2017-10-03 9:14 ` Imre Deak
2017-10-02 15:12 ` ✓ Fi.CI.IGT: " Patchwork
2017-10-02 20:09 ` [PATCH] " Rodrigo Vivi
2 siblings, 1 reply; 6+ messages in thread
From: Patchwork @ 2017-10-02 14:17 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Fix DDI PHY init if it was already on
URL : https://patchwork.freedesktop.org/series/31265/
State : success
== Summary ==
Series 31265v1 drm/i915: Fix DDI PHY init if it was already on
https://patchwork.freedesktop.org/api/1.0/series/31265/revisions/1/mbox/
Test chamelium:
Subgroup hdmi-crc-fast:
pass -> DMESG-WARN (fi-skl-6700k) fdo#103019
Test drv_module_reload:
Subgroup basic-reload:
dmesg-warn -> PASS (fi-glk-1) fdo#102777 +2
fdo#103019 https://bugs.freedesktop.org/show_bug.cgi?id=103019
fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:459s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:476s
fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:393s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:578s
fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:289s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:537s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:542s
fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:549s
fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:528s
fi-cfl-s total:289 pass:256 dwarn:1 dfail:0 fail:0 skip:32 time:565s
fi-cnl-y total:289 pass:261 dwarn:1 dfail:0 fail:0 skip:27 time:636s
fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:442s
fi-glk-1 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:592s
fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:438s
fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:424s
fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:470s
fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:511s
fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:483s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:508s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:583s
fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:501s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:592s
fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:654s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:482s
fi-skl-6700k total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:533s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:529s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:475s
fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:585s
fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:437s
2f14e319a2fd0125bcb06b00095afa6cab5134bd drm-tip: 2017y-10m-02d-09h-23m-23s UTC integration manifest
2ae7aaa119a9 drm/i915: Fix DDI PHY init if it was already on
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5869/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915: Fix DDI PHY init if it was already on
2017-10-02 13:53 [PATCH] drm/i915: Fix DDI PHY init if it was already on Imre Deak
2017-10-02 14:17 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2017-10-02 15:12 ` Patchwork
2017-10-02 20:09 ` [PATCH] " Rodrigo Vivi
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2017-10-02 15:12 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Fix DDI PHY init if it was already on
URL : https://patchwork.freedesktop.org/series/31265/
State : success
== Summary ==
Test perf:
Subgroup blocking:
fail -> PASS (shard-hsw) fdo#102252 +1
Test kms_flip:
Subgroup plain-flip-fb-recreate-interruptible:
pass -> FAIL (shard-hsw) fdo#100368
Test prime_self_import:
Subgroup reimport-vs-gem_close-race:
fail -> PASS (shard-hsw) fdo#102655
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102655 https://bugs.freedesktop.org/show_bug.cgi?id=102655
shard-hsw total:2429 pass:1332 dwarn:5 dfail:0 fail:9 skip:1083 time:10107s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5869/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915: Fix DDI PHY init if it was already on
2017-10-02 13:53 [PATCH] drm/i915: Fix DDI PHY init if it was already on Imre Deak
2017-10-02 14:17 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-10-02 15:12 ` ✓ Fi.CI.IGT: " Patchwork
@ 2017-10-02 20:09 ` Rodrigo Vivi
2017-10-03 8:29 ` Imre Deak
2 siblings, 1 reply; 6+ messages in thread
From: Rodrigo Vivi @ 2017-10-02 20:09 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Mon, Oct 02, 2017 at 01:53:07PM +0000, Imre Deak wrote:
> The common lane power down flag of a DPIO PHY has a funky semantic:
> after the initial enabling of the PHY (so from a disabled state) this
> flag will be clear. It will be set only after the PHY will be used for
> the first time (for instance due to enabling the corresponding pipe) and
> then become unused (due to disabling the pipe). During the initial PHY
> enablement we don't know which of the above phases we are in, so move
> the check for the flag where this is known, the HW readout code. This is
> where the rest of lane power down status checks are done anyway.
This makes sense. I just wonder why at first place we were doing that
extra check to see if that was disabled.
I couldn't find anything on spec to justify the previous use of it and
new one is consistent with bit 9 that is very similar, so:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> This fixes at least a problem on GLK where after module reloading, the
> common lane power down flag of PHY1 is set, but the PHY is actually
> powered-on and properly set up. The GRC readout code for other PHYs will
> hence think that PHY1 is not powered initially and disable it after the
> GRC readout. This will cause the AUX power well related to PHY1 to get
> disabled in a stuck state, timing out when we try to enable it later.
>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Fixes: e93da0a0137b ("drm/i915/bxt: Sanitiy check the PHY lane power down status")
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102777
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 3 ++-
> drivers/gpu/drm/i915/intel_dpio_phy.c | 20 --------------------
> 2 files changed, 2 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 93cbbcbbc193..65f4b6786791 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1713,7 +1713,8 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
> out:
> if (ret && IS_GEN9_LP(dev_priv)) {
> tmp = I915_READ(BXT_PHY_CTL(port));
> - if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK |
> + if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
> + BXT_PHY_LANE_POWERDOWN_ACK |
> BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
> DRM_ERROR("Port %c enabled but PHY powered down? "
> "(PHY_CTL %08x)\n", port_name(port), tmp);
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index 09b670929786..de38d014ed39 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -208,12 +208,6 @@ static const struct bxt_ddi_phy_info glk_ddi_phy_info[] = {
> },
> };
>
> -static u32 bxt_phy_port_mask(const struct bxt_ddi_phy_info *phy_info)
> -{
> - return (phy_info->dual_channel * BIT(phy_info->channel[DPIO_CH1].port)) |
> - BIT(phy_info->channel[DPIO_CH0].port);
> -}
> -
> static const struct bxt_ddi_phy_info *
> bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count)
> {
> @@ -313,7 +307,6 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
> enum dpio_phy phy)
> {
> const struct bxt_ddi_phy_info *phy_info;
> - enum port port;
>
> phy_info = bxt_get_phy_info(dev_priv, phy);
>
> @@ -335,19 +328,6 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
> return false;
> }
>
> - for_each_port_masked(port, bxt_phy_port_mask(phy_info)) {
> - u32 tmp = I915_READ(BXT_PHY_CTL(port));
> -
> - if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) {
> - DRM_DEBUG_DRIVER("DDI PHY %d powered, but common lane "
> - "for port %c powered down "
> - "(PHY_CTL %08x)\n",
> - phy, port_name(port), tmp);
> -
> - return false;
> - }
> - }
> -
> return true;
> }
>
> --
> 2.13.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915: Fix DDI PHY init if it was already on
2017-10-02 20:09 ` [PATCH] " Rodrigo Vivi
@ 2017-10-03 8:29 ` Imre Deak
0 siblings, 0 replies; 6+ messages in thread
From: Imre Deak @ 2017-10-03 8:29 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Mon, Oct 02, 2017 at 01:09:57PM -0700, Rodrigo Vivi wrote:
> On Mon, Oct 02, 2017 at 01:53:07PM +0000, Imre Deak wrote:
> > The common lane power down flag of a DPIO PHY has a funky semantic:
> > after the initial enabling of the PHY (so from a disabled state) this
> > flag will be clear. It will be set only after the PHY will be used for
> > the first time (for instance due to enabling the corresponding pipe) and
> > then become unused (due to disabling the pipe). During the initial PHY
> > enablement we don't know which of the above phases we are in, so move
> > the check for the flag where this is known, the HW readout code. This is
> > where the rest of lane power down status checks are done anyway.
>
> This makes sense. I just wonder why at first place we were doing that
> extra check to see if that was disabled.
> I couldn't find anything on spec to justify the previous use of it and
> new one is consistent with bit 9 that is very similar, so:
Originally it wasn't clear when - or if at all - the flag gets set to
indicate that the common lane is powered down, this isn't explained in
Bspec or anywhere else either. It's just after testing things now more
that it became clear how it behaves as I wrote above. The original check
was based on the fact that after the initial enabling the flag is clear
indicating the common lane is powered, although it isn't used at that
moment (which is rather illogical). This check just didn't take into
account the cases where the PHY is already on during driver loading and
the corresponding pipe went through an enable->disable cycle (like
during driver reloading).
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Thanks.
> >
> > This fixes at least a problem on GLK where after module reloading, the
> > common lane power down flag of PHY1 is set, but the PHY is actually
> > powered-on and properly set up. The GRC readout code for other PHYs will
> > hence think that PHY1 is not powered initially and disable it after the
> > GRC readout. This will cause the AUX power well related to PHY1 to get
> > disabled in a stuck state, timing out when we try to enable it later.
> >
> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > Fixes: e93da0a0137b ("drm/i915/bxt: Sanitiy check the PHY lane power down status")
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102777
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_ddi.c | 3 ++-
> > drivers/gpu/drm/i915/intel_dpio_phy.c | 20 --------------------
> > 2 files changed, 2 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index 93cbbcbbc193..65f4b6786791 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -1713,7 +1713,8 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
> > out:
> > if (ret && IS_GEN9_LP(dev_priv)) {
> > tmp = I915_READ(BXT_PHY_CTL(port));
> > - if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK |
> > + if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
> > + BXT_PHY_LANE_POWERDOWN_ACK |
> > BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
> > DRM_ERROR("Port %c enabled but PHY powered down? "
> > "(PHY_CTL %08x)\n", port_name(port), tmp);
> > diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> > index 09b670929786..de38d014ed39 100644
> > --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> > +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> > @@ -208,12 +208,6 @@ static const struct bxt_ddi_phy_info glk_ddi_phy_info[] = {
> > },
> > };
> >
> > -static u32 bxt_phy_port_mask(const struct bxt_ddi_phy_info *phy_info)
> > -{
> > - return (phy_info->dual_channel * BIT(phy_info->channel[DPIO_CH1].port)) |
> > - BIT(phy_info->channel[DPIO_CH0].port);
> > -}
> > -
> > static const struct bxt_ddi_phy_info *
> > bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count)
> > {
> > @@ -313,7 +307,6 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
> > enum dpio_phy phy)
> > {
> > const struct bxt_ddi_phy_info *phy_info;
> > - enum port port;
> >
> > phy_info = bxt_get_phy_info(dev_priv, phy);
> >
> > @@ -335,19 +328,6 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
> > return false;
> > }
> >
> > - for_each_port_masked(port, bxt_phy_port_mask(phy_info)) {
> > - u32 tmp = I915_READ(BXT_PHY_CTL(port));
> > -
> > - if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) {
> > - DRM_DEBUG_DRIVER("DDI PHY %d powered, but common lane "
> > - "for port %c powered down "
> > - "(PHY_CTL %08x)\n",
> > - phy, port_name(port), tmp);
> > -
> > - return false;
> > - }
> > - }
> > -
> > return true;
> > }
> >
> > --
> > 2.13.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: ✓ Fi.CI.BAT: success for drm/i915: Fix DDI PHY init if it was already on
2017-10-02 14:17 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2017-10-03 9:14 ` Imre Deak
0 siblings, 0 replies; 6+ messages in thread
From: Imre Deak @ 2017-10-03 9:14 UTC (permalink / raw)
To: intel-gfx, Rodrigo Vivi
On Mon, Oct 02, 2017 at 02:17:37PM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Fix DDI PHY init if it was already on
> URL : https://patchwork.freedesktop.org/series/31265/
> State : success
Thanks for the review, pushed it to -dinq.
>
> == Summary ==
>
> Series 31265v1 drm/i915: Fix DDI PHY init if it was already on
> https://patchwork.freedesktop.org/api/1.0/series/31265/revisions/1/mbox/
>
> Test chamelium:
> Subgroup hdmi-crc-fast:
> pass -> DMESG-WARN (fi-skl-6700k) fdo#103019
> Test drv_module_reload:
> Subgroup basic-reload:
> dmesg-warn -> PASS (fi-glk-1) fdo#102777 +2
>
> fdo#103019 https://bugs.freedesktop.org/show_bug.cgi?id=103019
> fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777
>
> fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:459s
> fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:476s
> fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:393s
> fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:578s
> fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:289s
> fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:537s
> fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:542s
> fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:549s
> fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:528s
> fi-cfl-s total:289 pass:256 dwarn:1 dfail:0 fail:0 skip:32 time:565s
> fi-cnl-y total:289 pass:261 dwarn:1 dfail:0 fail:0 skip:27 time:636s
> fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:442s
> fi-glk-1 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:592s
> fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:438s
> fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:424s
> fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:470s
> fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:511s
> fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:483s
> fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:508s
> fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:583s
> fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:501s
> fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:592s
> fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:654s
> fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:482s
> fi-skl-6700k total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:533s
> fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:529s
> fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:475s
> fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:585s
> fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:437s
>
> 2f14e319a2fd0125bcb06b00095afa6cab5134bd drm-tip: 2017y-10m-02d-09h-23m-23s UTC integration manifest
> 2ae7aaa119a9 drm/i915: Fix DDI PHY init if it was already on
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5869/
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^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2017-10-03 9:14 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-10-02 13:53 [PATCH] drm/i915: Fix DDI PHY init if it was already on Imre Deak
2017-10-02 14:17 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-10-03 9:14 ` Imre Deak
2017-10-02 15:12 ` ✓ Fi.CI.IGT: " Patchwork
2017-10-02 20:09 ` [PATCH] " Rodrigo Vivi
2017-10-03 8:29 ` Imre Deak
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