From: Bjorn Andersson <bjorn.andersson@linaro.org> To: Timur Tabi <timur@codeaurora.org> Cc: Linus Walleij <linus.walleij@linaro.org>, andy.gross@linaro.org, david.brown@linaro.org, anjiandi@codeaurora.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org Subject: Re: [PATCH 1/2] [v5] pinctrl: qcom: disable GPIO groups with no pins Date: Mon, 2 Oct 2017 10:44:14 -0700 [thread overview] Message-ID: <20171002174414.GL1165@minitux> (raw) In-Reply-To: <1504798409-32041-2-git-send-email-timur@codeaurora.org> On Thu 07 Sep 08:33 PDT 2017, Timur Tabi wrote: Sorry for the slow response, I finally met with Linus last week to discuss this. > diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c [..] > @@ -825,13 +897,39 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) > chip->owner = THIS_MODULE; > chip->of_node = pctrl->dev->of_node; > > + /* If the GPIO map is sparse, then we need to disable specific IRQs */ > + chip->irq_need_valid_mask = pctrl->soc->sparse; > + > ret = gpiochip_add_data(&pctrl->chip, pctrl); > if (ret) { > dev_err(pctrl->dev, "Failed register gpiochip\n"); > return ret; > } > > - ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio); > + /* > + * If irq_need_valid_mask is true, then gpiochip_add_data() will > + * initialize irq_valid_mask to all 1s. We need to clear all the > + * GPIOs that are unavailable, and we need to find each block > + * of consecutive available GPIOs are add them as pin ranges. > + */ > + if (chip->irq_need_valid_mask) { > + for (i = 0; i < ngpio; i++) > + if (!groups[i].npins) > + clear_bit(i, pctrl->chip.irq_valid_mask); > + > + while ((count = msm_gpio_get_next_range(pctrl, &start))) { > + ret = gpiochip_add_pin_range(&pctrl->chip, > + dev_name(pctrl->dev), > + start, start, count); > + if (ret) > + break; > + start += count; I do not fancy the idea of specifying a bitmap of valid irq pins and then having the driver register the pin-ranges in-between. If we provide a bitmap of validity to the core it should support using this for the pins as well. (Which I believe is what Linus answered in the discussion following patch 0/2) > + } > + } else { > + ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), > + 0, 0, ngpio); > + } > + Regards, Bjorn
WARNING: multiple messages have this Message-ID (diff)
From: bjorn.andersson@linaro.org (Bjorn Andersson) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/2] [v5] pinctrl: qcom: disable GPIO groups with no pins Date: Mon, 2 Oct 2017 10:44:14 -0700 [thread overview] Message-ID: <20171002174414.GL1165@minitux> (raw) In-Reply-To: <1504798409-32041-2-git-send-email-timur@codeaurora.org> On Thu 07 Sep 08:33 PDT 2017, Timur Tabi wrote: Sorry for the slow response, I finally met with Linus last week to discuss this. > diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c [..] > @@ -825,13 +897,39 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) > chip->owner = THIS_MODULE; > chip->of_node = pctrl->dev->of_node; > > + /* If the GPIO map is sparse, then we need to disable specific IRQs */ > + chip->irq_need_valid_mask = pctrl->soc->sparse; > + > ret = gpiochip_add_data(&pctrl->chip, pctrl); > if (ret) { > dev_err(pctrl->dev, "Failed register gpiochip\n"); > return ret; > } > > - ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio); > + /* > + * If irq_need_valid_mask is true, then gpiochip_add_data() will > + * initialize irq_valid_mask to all 1s. We need to clear all the > + * GPIOs that are unavailable, and we need to find each block > + * of consecutive available GPIOs are add them as pin ranges. > + */ > + if (chip->irq_need_valid_mask) { > + for (i = 0; i < ngpio; i++) > + if (!groups[i].npins) > + clear_bit(i, pctrl->chip.irq_valid_mask); > + > + while ((count = msm_gpio_get_next_range(pctrl, &start))) { > + ret = gpiochip_add_pin_range(&pctrl->chip, > + dev_name(pctrl->dev), > + start, start, count); > + if (ret) > + break; > + start += count; I do not fancy the idea of specifying a bitmap of valid irq pins and then having the driver register the pin-ranges in-between. If we provide a bitmap of validity to the core it should support using this for the pins as well. (Which I believe is what Linus answered in the discussion following patch 0/2) > + } > + } else { > + ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), > + 0, 0, ngpio); > + } > + Regards, Bjorn
next prev parent reply other threads:[~2017-10-02 17:44 UTC|newest] Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-09-07 15:33 [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs Timur Tabi 2017-09-07 15:33 ` Timur Tabi 2017-09-07 15:33 ` [PATCH 1/2] [v5] pinctrl: qcom: disable GPIO groups with no pins Timur Tabi 2017-09-07 15:33 ` Timur Tabi 2017-10-02 17:44 ` Bjorn Andersson [this message] 2017-10-02 17:44 ` Bjorn Andersson 2017-10-02 20:47 ` Timur Tabi 2017-10-02 20:47 ` Timur Tabi 2017-10-07 11:07 ` Linus Walleij 2017-10-07 11:07 ` Linus Walleij 2017-10-13 23:35 ` Timur Tabi 2017-10-13 23:35 ` Timur Tabi 2017-10-19 22:44 ` Timur Tabi 2017-10-19 22:44 ` Timur Tabi 2017-10-16 8:01 ` Thierry Reding 2017-10-16 8:01 ` Thierry Reding 2017-10-16 13:52 ` Timur Tabi 2017-10-16 13:52 ` Timur Tabi 2017-09-07 15:33 ` [PATCH 2/2] [v3] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002 Timur Tabi 2017-09-07 15:33 ` Timur Tabi 2017-09-08 12:50 ` [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs Linus Walleij 2017-09-08 12:50 ` Linus Walleij 2017-09-13 17:09 ` Timur Tabi 2017-09-13 17:09 ` Timur Tabi 2017-09-19 7:04 ` Stephen Boyd 2017-09-19 7:04 ` Stephen Boyd 2017-09-19 8:15 ` Linus Walleij 2017-09-19 8:15 ` Linus Walleij 2017-09-19 12:32 ` Timur Tabi 2017-09-19 12:32 ` Timur Tabi 2017-09-20 11:43 ` Linus Walleij 2017-09-20 11:43 ` Linus Walleij 2017-09-20 13:04 ` Timur Tabi 2017-09-20 13:04 ` Timur Tabi 2017-09-21 12:08 ` Linus Walleij 2017-09-21 12:08 ` Linus Walleij 2017-09-21 12:12 ` Timur Tabi 2017-09-21 12:12 ` Timur Tabi 2017-09-22 13:29 ` Linus Walleij 2017-09-22 13:29 ` Linus Walleij 2017-09-22 13:37 ` Timur Tabi 2017-09-22 13:37 ` Timur Tabi 2017-10-03 22:03 ` Stephen Boyd 2017-10-03 22:03 ` Stephen Boyd 2017-10-03 22:12 ` Timur Tabi 2017-10-03 22:12 ` Timur Tabi 2017-10-04 21:50 ` Stephen Boyd 2017-10-04 21:50 ` Stephen Boyd 2017-10-04 22:41 ` Timur Tabi 2017-10-04 22:41 ` Timur Tabi 2017-10-05 21:30 ` Stephen Boyd 2017-10-05 21:30 ` Stephen Boyd 2017-10-11 7:51 ` Linus Walleij 2017-10-11 7:51 ` Linus Walleij 2017-10-12 7:39 ` Stephen Boyd 2017-10-12 7:39 ` Stephen Boyd 2017-10-14 22:43 ` Linus Walleij 2017-10-14 22:43 ` Linus Walleij 2017-10-16 13:42 ` Timur Tabi 2017-10-16 13:42 ` Timur Tabi 2017-10-13 23:26 ` Timur Tabi 2017-10-13 23:26 ` Timur Tabi 2017-10-15 20:18 ` Thierry Reding 2017-10-15 20:18 ` Thierry Reding 2017-10-15 21:09 ` Timur Tabi 2017-10-15 21:09 ` Timur Tabi 2017-10-02 16:02 ` Timur Tabi 2017-10-02 16:02 ` Timur Tabi
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